WO2017124762A1 - 电子器件的开关控制装置、方法和电子器件 - Google Patents

电子器件的开关控制装置、方法和电子器件 Download PDF

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Publication number
WO2017124762A1
WO2017124762A1 PCT/CN2016/098545 CN2016098545W WO2017124762A1 WO 2017124762 A1 WO2017124762 A1 WO 2017124762A1 CN 2016098545 W CN2016098545 W CN 2016098545W WO 2017124762 A1 WO2017124762 A1 WO 2017124762A1
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WIPO (PCT)
Prior art keywords
electronic device
level
logic level
input
switching
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PCT/CN2016/098545
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English (en)
French (fr)
Inventor
林琳
孙伟
陈丽莉
陈忠君
李牧冰
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/525,925 priority Critical patent/US10230371B2/en
Publication of WO2017124762A1 publication Critical patent/WO2017124762A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0072—Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load

Definitions

  • the present disclosure relates to the technical field of switch control of electronic devices, and more particularly to a switch control device, method and electronic device for an electronic device.
  • the level conversion circuit 11 converts the high level VC1 whose maximum amplitude is 3.3V output from the logic controller 12 into a high level VC2 whose maximum amplitude is 5.5V, and then VC2. Output to the high level input Singal of the electronic device 10 to turn on the electronic device 10.
  • the logic controller 12 outputs a low level, the electronic device 10 is turned off.
  • the ground terminal GND of the electronic device 10 is grounded, and the ground terminal is denoted as Gnd.
  • the level conversion circuit can only generate a maximum level of 5.5V, and some electronic devices have a high level for turning on greater than 5.5V, so the level conversion circuit cannot be successfully turned on. These electronic devices.
  • the main object of the present disclosure is to provide a switch control device, method and electronic device for an electronic device to solve some or all of the above problems.
  • a switch control apparatus for an electronic device, the electronic device comprising a ground terminal and a high level input terminal, the switch control device comprising:
  • a high level output unit coupled to the high level input and configured to output a high level having a predetermined amplitude to the high level input; the predetermined amplitude being greater than a predetermined voltage;
  • a logic level output unit configured to output a logic level
  • a switching unit whose control terminal is input to the logic level, a first terminal connected to the ground terminal, a second terminal input to a low level, and configured to be used when the logic level is in a first state Connecting the first end to the second end to turn on the electronic device, and when the logic level is in the second state, the first end is not connected to the second end to close The electronic device.
  • the high level output unit is configured to output a high level having a different predetermined amplitude to the high level input terminal in a time division manner.
  • the switching unit comprises: a switching transistor whose gate is input to the logic level, a first pole is connected to the ground, and a second pole is input to a low level.
  • the switching transistor comprises a switching transistor; a base thereof is input to the logic level, a first pole is connected to the ground, and a second pole is input to a low level.
  • the switching transistor comprises a switching MOS transistor; a gate thereof is input to the logic level, a first pole is connected to the ground, and a second pole is input to a low level.
  • the switching transistor comprises a switching TFT; a gate thereof is input to the logic level, a first pole is connected to the ground, and a second pole is input to a low level.
  • the switching MOS transistor is an N-channel enhancement type MOS transistor or a P-channel depletion MOS transistor
  • the logic level when the logic level is in the first state, the logic level is a high level.
  • the logic level is low when the logic level is in the second state.
  • the switching transistor is a P-channel enhancement transistor or an N-channel depletion transistor
  • the logic level when the logic level is in the first state, the logic level is a low level, when When the logic level is in the second state, the logic level is a high level.
  • a switch control method for an electronic device comprising:
  • the high level output unit outputs a high level of a predetermined amplitude to a high level input terminal of the electronic device; the predetermined amplitude value is greater than a predetermined voltage;
  • the logic level output unit outputs a logic level
  • the switching unit When the logic level is in the first state, the switching unit causes a low level to be input to the ground of the electronic device to turn on the electronic device; when the logic level is in the second state, the switch The unit suspends the ground of the electronic device to turn off the electronic device.
  • the step of outputting the high level output unit to the high level input end of the electronic device to the high level of the predetermined amplitude comprises:
  • the high level output unit outputs a high level having a different predetermined amplitude to the high level input terminal in a time division manner.
  • the switching unit includes a switching transistor; and wherein when the logic level is in the first state, the switching unit controls a low level to be input to a ground of the electronic device, when the logic level is at In the two states, the step of controlling the grounding end of the electronic device to be suspended by the switching unit includes:
  • the switching transistor turns on the electronic device when the logic level is a first level a connection between the ground terminal of the device and the low level input terminal, and when the logic level is the second level, the switching transistor is disconnected between the ground terminal and the low level input terminal of the electronic device Connected such that the ground of the electronic device is suspended.
  • an electronic device comprising a ground terminal and a high level input, wherein the electronic device is configured to be controlled by any of the switch control devices described above.
  • FIG. 1 is a structural view of a switch control device of a conventional electronic device
  • FIG. 2 is a structural diagram of a switch control device of an electronic device according to the present disclosure
  • FIG. 3A is a configuration diagram of a first embodiment of a switch control device of an electronic device according to the present disclosure
  • 3B is a configuration diagram of a second embodiment of a switch control device of an electronic device according to the present disclosure.
  • 3C is a configuration diagram of a third embodiment of a switch control device of an electronic device according to the present disclosure.
  • 3D is a configuration diagram of a fourth embodiment of a switch control device of an electronic device according to the present disclosure.
  • FIG. 4A is a configuration diagram of a fifth embodiment of a switch control device of an electronic device according to the present disclosure.
  • 4B is a configuration diagram of a sixth embodiment of a switch control device of an electronic device according to the present disclosure.
  • 4C is a configuration diagram of a seventh embodiment of a switch control device of an electronic device according to the present disclosure.
  • 4D is a configuration diagram of an eighth embodiment of a switch control device of an electronic device according to the present disclosure.
  • FIG. 5 is a flow chart of a switch control method of an electronic device in accordance with the present disclosure.
  • FIG. 2 is a structural diagram of a switch control device of an electronic device according to the present disclosure. As shown in FIG. 2, the switching control device of the electronic device is used for switching control of the electronic device 20, and the electronic device 20 includes a ground GND and a high-level input Signal.
  • the switch control device includes:
  • a high level output unit 21 connected to the high level input signal and configured to output a high level VCC having a predetermined amplitude to the high level input signal; the predetermined amplitude is greater than a predetermined Voltage;
  • a logic level output unit 22 for outputting a logic level LS
  • the switching unit 23 has its control terminal Ctrl input to the logic level, the first terminal D1 is connected to the ground GND, the second terminal D2 is input with a low level VSS, and is configured to be used for the logic
  • the first end D1 is communicated with the second end D2 to turn on the electronic device 20, and when the logic level is in the second state, the first end D1 is made Not communicating with the second end D2 to turn off the electronic device 20.
  • the switch control device outputs a high level VCC to the high level input signal of the electronic device through the high level output unit 21.
  • the amplitude of the high level VCC can be greater than the maximum high voltage that the existing level shifter can convert, such as 5.5V, and the switching control device passes the switching unit 23 at the logic level LS.
  • the ground GND of the control electronics is input to the low level VSS.
  • GND can be grounded, in which case the potential difference between the high-level input signal of the electronic device and the ground GND is VCC.
  • the switch control device provided by the embodiment of the present disclosure can smoothly turn on the electronic device.
  • the switching unit 23 controls the ground terminal GND of the electronic device not to be input to the low level VSS, so that the ground terminal GND of the electronic device is suspended, thereby causing the high-level input signal of the electronic device to be There is no potential difference between the ground terminals GND, so the electronics are not turned on.
  • the high-level output unit 21 may be configured to output a high level having a different predetermined amplitude to the high-level input signal to time-division to meet the power supply requirements of the electronic device at different times.
  • the time division amplitude of VCC can be 6V, 12V, 24V or other voltage values.
  • the switching unit may include: a switching transistor whose gate is input to the logic level, a first pole is connected to the ground, and a second pole is input to a low level;
  • the switching transistor When the logic level is in the first state, the switching transistor is turned on, the electronic device The ground terminal of the device is input low, and when the logic level is in the second state, the switching transistor is turned off, and the ground of the electronic device is suspended.
  • the switching transistor may include a switching transistor; a base thereof is input to the logic level, a first pole is connected to the ground, and a second pole is input to a low level;
  • the switching transistor is turned on when the logic level of the switching transistor is input to a high level, and the switching transistor is turned off when the logic level of the switching transistor is input to a low level.
  • the first pole of the switching transistor can be a collector or an emitter, and correspondingly the second pole of the switching transistor can be an emitter or a collector.
  • the switching transistor may include a switch MOS (Metal-Oxide-semiconductor) tube or a switching TFT (Thin Film Transistor).
  • MOS Metal-Oxide-semiconductor
  • switching TFT Thin Film Transistor
  • the gate of the switching transistor is input to the logic level, the first pole is connected to the ground, the second pole is input to a low level; when the logic level is in the first state
  • the switching MOS transistor or the switching TFT is turned on, the ground terminal of the electronic device is input with a low level, and when the logic level is in the second state, the switching MOS transistor or the switching TFT is turned off. The ground of the electronic device is input low.
  • the first pole of the switching transistor can be a source or a drain
  • the second pole of the switching transistor can be a drain or a source
  • the on and off speeds of the switching MOS transistor and the switching TFT are fast, especially when the switching transistor adopts a switching MOS transistor, the on and off speeds thereof can satisfy an electronic device suitable for a high speed display device. .
  • the switching transistor includes a switching MOS transistor or a switching TFT
  • the switching transistor is an N-type transistor, when the logic level is in the first state, the logic level is a high level, when When the logic level is in the second state, the logic level is a low level; if the switching transistor is a P-type transistor, when the logic level is in the first state, the logic level is Low level, the logic level is high when the logic level is in the second state.
  • the electronic device includes, but is not limited to, an industrial camera or a radio frequency switch, and may be other electronic devices that control the switch by a pulse control signal.
  • the logic level output unit may be a logic level controller.
  • a logic level controller for example, an FPGA (Field-Programmable Gate Array), a DSP (Digital Signal Processor), an ARM microprocessor or a single chip microcomputer, but is not limited thereto, the logic level output unit can be any A device that can output a logic level.
  • the electronic device is an industrial camera 30, and the high-level input terminal of the industrial camera 30 is a trigger interface Trigger of the industrial camera, which is high.
  • the level of the high level output by the level output unit (not shown in FIG. 3A) is 6V.
  • the switching unit adopts a switching MOS transistor M1, and M1 is an N-channel enhancement type MOS transistor; a gate G of M1 is connected to a logic level output end of the logic level controller 31, and a drain D of the M1 and the industrial camera The ground terminal GND of 30 is connected, and the source S of M1 is connected to the ground Gnd.
  • the logic level controller 31 When the logic level controller 31 outputs a logic "1", that is, when the logic level output from the logic level controller 31 is at a high level, M1 is turned on.
  • the ground terminal GND of the industrial camera 30 is grounded, and the potential difference between the interface Trigger and GND is 6V.
  • the trigger level received is 6V, which meets the requirements of industrial cameras for signal levels, enabling the triggering of industrial cameras.
  • the electronic device is an industrial camera 30, and the high-level input terminal of the industrial camera 30 is a trigger interface Trigger of the industrial camera, which is high.
  • the level of the high level output by the level output unit (not shown in FIG. 3B) is 6V.
  • the switching unit adopts a switching MOS transistor M1, and M1 is a P-channel depletion MOS transistor; a gate G of M1 is connected to a logic level output terminal of the logic level controller 31, and a drain D of the M1 and the industry The ground terminal GND of the camera 30 is connected, and the source S of M1 is connected to the ground Gnd.
  • the logic level controller 31 When the logic level controller 31 outputs a logic "1", that is, when the logic level output from the logic level controller 31 is at a high level, M1 is turned on.
  • the ground terminal GND of the industrial camera 30 is grounded, and the potential difference between the interface Trigger and GND is 6V.
  • the received trigger level has an amplitude of 6V, which satisfies the requirements of industrial cameras for signal levels, thus enabling the triggering function of industrial cameras.
  • the electronic device is an industrial camera 30, and the high-level input terminal of the industrial camera 30 is a trigger interface Trigger of the industrial camera, which is high.
  • the level of the high level output by the level output unit (not shown in FIG. 3C) is 6V.
  • the switching unit adopts a switching MOS transistor M1, and M1 is an N-channel depletion MOS transistor; a gate G of M1 is connected to a logic level output end of the logic level controller 31, and a drain D of the M1 and the industry The ground terminal GND of the camera 30 is connected, and the source S of M1 is connected to the ground Gnd.
  • the logic level controller 31 When the logic level controller 31 outputs a logic "0", that is, when the logic level output from the logic level controller 31 is a low level, M1 is turned on.
  • the ground terminal GND of the industrial camera 30 is grounded, and the potential difference between the interface Trigger and GND is 6V.
  • the received trigger level has an amplitude of 6V, which satisfies the requirements of industrial cameras for signal levels, thus enabling the triggering function of industrial cameras.
  • the electronic device is an industrial camera 30, and the high-level input terminal of the industrial camera 30 is a trigger interface Trigger of the industrial camera, which is high.
  • the level of the high level output by the level output unit (not shown in FIG. 3D) is 6V.
  • the switching unit adopts a switching MOS transistor M1, and M1 is a P-channel enhancement type MOS transistor; a gate G of M1 is connected to a logic level output end of the logic level controller 31, and a drain D of the M1 and the industrial camera The ground terminal GND of 30 is connected, and the source S of M1 is connected to the ground Gnd.
  • the logic level controller 31 When the logic level controller 31 outputs a logic "0", that is, when the logic level output from the logic level controller 31 is a low level, M1 is turned on.
  • the ground terminal GND of the industrial camera 30 is grounded, and the potential difference between the interface Trigger and GND is 6V.
  • the trigger level received is 6V, which satisfies the requirements of industrial cameras for signal levels, thus enabling the triggering function of industrial cameras.
  • the electronic device is the RF switch 40
  • the high-level input terminal of the RF switch 40 is the high-level terminal VCC of the RF switch 40.
  • the amplitude of the high level output by the high level output unit (not shown in FIG. 4A) is 12V.
  • the switch unit adopts a switch MOS transistor M1, and M1 is an N-channel enhancement type MOS transistor; a gate G of M1 is connected to a logic level output end of the logic level controller 41, a drain D of the M1 and the RF switch The ground terminal GND of 40 is connected, and the source S of M1 is connected to the ground Gnd.
  • the logic level controller 41 When the logic level controller 41 outputs a logic "1", that is, when the logic level outputted by the logic level controller 41 is at a high level, M1 is turned on.
  • the ground terminal GND of the RF switch 40 is grounded, and the potential difference between VCC and GND is 6V.
  • the trigger level received by the RF switch is a high level of 6V, which satisfies the requirements of the RF switch on the signal level, thereby realizing the trigger function of the RF switch.
  • the electronic device is the RF switch 40, and the high-level input terminal of the RF switch 40, that is, the high-level terminal VCC of the RF switch 40.
  • the amplitude of the high level output by the high level output unit (not shown in FIG. 4B) is 12V.
  • the switching unit adopts a switching MOS transistor M1, and M1 is a P-channel depletion MOS transistor; a gate G of M1 is connected to a logic level output end of the logic level controller 41, and a drain D of the M1 and the radio frequency The ground terminal GND of the switch 40 is connected, and the source S of the M1 is connected to the ground Gnd.
  • the logic level controller 41 When the logic level controller 41 outputs a logic "1", that is, when the logic level outputted by the logic level controller 41 is at a high level, M1 is turned on.
  • the ground terminal GND of the RF switch 40 is grounded, and the potential difference between VCC and GND is 6V.
  • the amplitude of the trigger level received is 6V, which satisfies the requirements of the RF switch on the signal level, thereby realizing the trigger function of the RF switch.
  • the logic level controller 41 When the logic level controller 41 outputs a logic "0", that is, when the logic level output by the logic level controller is low, M1 is turned off. At this time, the grounding end GND of the RF switch 40 is suspended, and there is no potential difference between VCC and GND. For the RF switch, the received trigger level is low level, which cannot meet the trigger requirement.
  • the electronic device is the RF switch 40, and the high-level input terminal of the RF switch 40, that is, the high-level terminal VCC of the RF switch 40.
  • the amplitude of the high level output by the high level output unit (not shown in FIG. 4A) is 12V.
  • the switching unit adopts a switching MOS transistor M1, and M1 is an N-channel depletion MOS transistor; a gate G of M1 is connected to a logic level output end of the logic level controller 41, and a drain D of the M1 and the RF The ground terminal GND of the switch 40 is connected, and the source S of the M1 is connected to the ground Gnd.
  • the logic level controller 41 When the logic level controller 41 outputs a logic "0", that is, when the logic level output from the logic level controller 41 is a low level, M1 is turned on.
  • the ground terminal GND of the RF switch 40 is grounded, and the potential difference between VCC and GND is 6V.
  • the amplitude of the trigger level received is 6V, which satisfies the requirements of the RF switch on the signal level, thereby realizing the trigger function of the RF switch.
  • the logic level controller 41 When the logic level controller 41 outputs a logic "1", that is, when the logic level output by the logic level controller is high, M1 is turned off. At this time, the grounding end GND of the RF switch 40 is suspended, and there is no potential difference between VCC and GND. For the RF switch, the received trigger level is low level, which cannot meet the trigger requirement.
  • the electronic device is the RF switch 40, and the high-level input terminal of the RF switch 40, that is, the high-level terminal VCC of the RF switch 40.
  • the amplitude of the high level output by the high level output unit (not shown in FIG. 4D) is 12V.
  • the switch unit adopts a switch MOS transistor M1, and M1 is a P-channel enhancement type MOS transistor; the gate G of M1 is connected to a logic level output end of the logic level controller 41, and the drain D of the M1 and the RF switch The ground terminal GND of 40 is connected, and the source S of M1 is connected to the ground Gnd.
  • the logic level controller 41 When the logic level controller 41 outputs a logic "0", that is, when the logic level output from the logic level controller 41 is a low level, M1 is turned on.
  • the ground terminal GND of the RF switch 40 is grounded, and the potential difference between VCC and GND is 6V.
  • the amplitude of the trigger level received is 6V, which satisfies the requirements of the RF switch on the signal level, thereby realizing the trigger function of the RF switch.
  • FIG. 5 illustrates a switching control method of an electronic device for performing switching control of an electronic device according to an embodiment of the present disclosure.
  • the electronic device includes a ground terminal and a high level input terminal.
  • the switch control method includes:
  • the high-level output unit outputs a high level of a predetermined amplitude to a high-level input end of the electronic device, the predetermined amplitude being greater than a predetermined voltage;
  • the switching unit when the logic level is in the first state, the switching unit causes a low level to be input to the ground of the electronic device to turn on the electronic device; when the logic level is in the second state, The switching unit suspends a ground terminal of the electronic device to turn off the electronic device.
  • the switch control method provided by the embodiment of the present disclosure outputs a high level to a high level input terminal of the electronic device through a high level output unit.
  • the amplitude of the high level may be greater than the maximum high voltage that the existing level converter can convert, such as 5.5V; and the switching control method provided by the embodiment of the present disclosure is
  • the logic level is in the first state
  • the ground of the electronic device is input to a low level, for example, the ground of the electronic device can be grounded.
  • the turn-on voltage of the electronic device is greater than the maximum high voltage that the existing level shifter can output, so that the electronic device can be smoothly turned on.
  • the switching unit causes the ground of the electronic device not to be input to a low level, so that the ground of the electronic device is suspended, so that there is no potential difference between the high-level input terminal and the ground of the electronic device. Therefore, the electronic device cannot be turned on.
  • the step of outputting the high level output unit to the high level input end of the electronic device to the high level of the predetermined amplitude comprises:
  • the high level output unit outputs a high level having a different predetermined amplitude to the high level input terminal in a time division manner.
  • the switching unit may include a switching transistor; and when the logic level is in the first state, the switching unit causes a low level to be input to a ground of the electronic device when the logic level is at In the second state, the step of the switch unit floating the ground end of the electronic device includes:
  • the switching transistor turns on a connection between a ground terminal of the electronic device and a low level input when the logic level is a first level, when the logic level is a second level, The switching transistor disconnects the ground between the ground and the low level input of the electronic device such that the ground of the electronic device is suspended.
  • An electronic device provided by an embodiment of the present disclosure includes a ground terminal and a high level input terminal, the electronic device being configured to be controlled by the above-described switch control device.

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Abstract

一种电子器件的开关控制装置、方法和电子器件。所述电子器件（20）的开关控制装置包括：高电平输出单元（21），其与所述高电平输入端连接并且被配置用于向所述高电平输入端输出具有预定幅值的高电平；所述预定幅值大于预定电压；逻辑电平输出单元（22），其被配置用于输出逻辑电平；以及开关单元（23），其控制端被输入所述逻辑电平，第一端与所述接地端连接，第二端被输入低电平，并且其被配置用于当所述逻辑电平处于第一状态时使所述第一端与所述第二端连接，以开启所述电子器件（20），以及当所述逻辑电平处于第二状态时使所述第一端不与所述第二端连接，以关闭所述电子器件（20）。

Description

电子器件的开关控制装置、方法和电子器件 技术领域
本公开涉及电子器件的开关控制的技术领域，尤其涉及一种电子器件的开关控制装置、方法和电子器件。
背景技术
传统地，如图1所示，由电平转换电路11将逻辑控制器12输出的最大幅值为3.3V的高电平VC1转换为最大幅值为5.5V的高电平VC2，然后将VC2输出至电子器件10的高电平输入端Singal，以打开该电子器件10。当该逻辑控制器12输出的是低电平时，电子器件10关闭。在图1中，电子器件10的接地端GND接地，地端标示为Gnd。但是，所述电平转换电路最大只能生成幅值为5.5V的高电平，而有些电子器件的用于开启的高电平是大于5.5V的，因此所述电平转换电路不能成功开启这些电子器件。
发明内容
本公开的主要目的在于提供一种电子器件的开关控制装置、方法和电子器件，以解决上述部分或全部问题。
根据本公开的第一方面，提供了一种电子器件的开关控制装置，所述电子器件包括接地端和高电平输入端，所述开关控制装置包括：
高电平输出单元，其与所述高电平输入端连接并且被配置用于向所述高电平输入端输出具有预定幅值的高电平；所述预定幅值大于预定电压；
逻辑电平输出单元，其被配置用于输出逻辑电平；以及，
开关单元，其控制端被输入所述逻辑电平，第一端与所述接地端连接，第二端被输入低电平，并且其被配置用于当所述逻辑电平处于第一状态时使所述第一端与所述第二端连接，以开启所述电子器件，以及当所述逻辑电平处于第二状态时使所述第一端不与所述第二端连接，以关闭所述电子器件。
可选地，所述高电平输出单元被配置用于分时向所述高电平输入端输出具有不同的预定幅值的高电平。
可选地，所述开关单元包括：开关晶体管，其控制极被输入所述逻辑电平，第一极与所述接地端连接，第二极被输入低电平。
可选地，所述开关晶体管包括开关三极管；其基极被输入所述逻辑电平，第一极与所述接地端连接，第二极被输入低电平。
可选地，所述开关晶体管包括开关MOS管；其栅极被输入所述逻辑电平，第一极与所述接地端连接，第二极被输入低电平。
可选地，所述开关晶体管包括开关TFT；其栅极被输入所述逻辑电平，第一极与所述接地端连接，第二极被输入低电平。
可选地，如果所述开关MOS管为N沟道增强型MOS管或P沟道耗尽型MOS管，则当所述逻辑电平处于第一状态时，所述逻辑电平为高电平，当所述逻辑电平处于第二状态时，所述逻辑电平为低电平。
可选地，如果所述开关晶体管为P沟道增强型晶体管或N沟道耗尽型晶体管时，则当所述逻辑电平处于第一状态时，所述逻辑电平为低电平，当所述逻辑电平处于第二状态时，所述逻辑电平为高电平。
根据本公开的第二方面，还提供了一种电子器件的开关控制方法，所述电子器件包括接地端和高电平输入端，所述开关控制方法包括：
高电平输出单元向电子器件的高电平输入端输出预定幅值的高电平；所述预定幅值大于预定电压；
逻辑电平输出单元输出逻辑电平；
当所述逻辑电平处于第一状态时，开关单元使低电平被输入所述电子器件的接地端，以打开所述电子器件；当所述逻辑电平处于第二状态时，所述开关单元使所述电子器件的接地端悬空，以关闭所述电子器件。
可选地，所述高电平输出单元向电子器件的高电平输入端输出预定幅值的高电平的步骤包括：
所述高电平输出单元分时向所述高电平输入端输出具有不同的预定幅值的高电平。
可选地，所述开关单元包括开关晶体管；并且其中当所述逻辑电平处于第一状态时，开关单元控制低电平被输入所述电子器件的接地端，当所述逻辑电平处于第二状态时，所述开关单元控制所述电子器件的接地端悬空的步骤包括：
当所述逻辑电平为第一电平时，所述开关晶体管导通所述电子器 件的接地端与低电平输入端之间的连接，以及当所述逻辑电平为第二电平时，所述开关晶体管断开所述电子器件的接地端与低电平输入端之间的连接，以使得所述电子器件的接地端悬空。
根据本公开的第三方面，还提供了一种电子器件，包括接地端和高电平输入端，其中，所述电子器件被配置成由上述的任一开关控制装置进行控制。
附图说明
图1是传统电子器件的开关控制装置的结构图；
图2是根据本公开的电子器件的开关控制装置的结构图；
图3A是根据本公开的电子器件的开关控制装置的第一实施例的结构图；
图3B是根据本公开的电子器件的开关控制装置的第二实施例的结构图；
图3C是根据本公开的电子器件的开关控制装置的第三实施例的结构图；
图3D是根据本公开的电子器件的开关控制装置的第四实施例的结构图；
图4A是根据本公开的电子器件的开关控制装置的第五实施例的结构图；
图4B是根据本公开的电子器件的开关控制装置的第六实施例的结构图；
图4C是根据本公开的电子器件的开关控制装置的第七实施例的结构图；
图4D是根据本公开的电子器件的开关控制装置的第八实施例的结构图；
图5是根据本公开的电子器件的开关控制方法的流程图。
具体实施方式
下面将结合附图，对本公开的实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。
图2是根据本公开的电子器件的开关控制装置的结构图。如图2所示，所述电子器件的开关控制装置用于对电子器件20进行开关控制，所述电子器件20包括接地端GND和高电平输入端Signal。
所述开关控制装置包括：
高电平输出单元21，其与所述高电平输入端Signal连接并被配置用于向所述高电平输入端Signal输出具有预定幅值的高电平VCC；所述预定幅值大于预定电压；
逻辑电平输出单元22，其用于输出逻辑电平LS；以及
开关单元23，其控制端Ctrl被输入所述逻辑电平，第一端D1与所述接地端GND连接，第二端D2被输入低电平VSS，并其被配置用于当所述逻辑电平LS处于第一状态时使所述第一端D1与所述第二端D2连通，以开启所述电子器件20，以及当所述逻辑电平处于第二状态时使所述第一端D1与所述第二端D2不连通，以关闭所述电子器件20。
所述开关控制装置通过高电平输出单元21向电子器件的高电平输入端Signal输出高电平VCC。与传统技术相比，该高电平VCC的幅值可以大于现有的电平转换器能够转换出的最大高电压，例如5.5V，并且所述开关控制装置通过开关单元23在逻辑电平LS处于第一状态时控制电子器件的接地端GND被输入低电平VSS。例如，此时GND可以接地，在这种情况下电子器件的高电平输入端Signal与接地端GND之间的电势差即为VCC。即使该电子器件的开启电压大于现有的电平转换器能够转换出的最大电压，本公开的实施例提供的开关控制装置也可以顺利开启所述电子器件。当逻辑电平LS处于第二状态时，开关单元23控制电子器件的接地端GND不被输入低电平VSS，使得电子器件的接地端GND悬空，从而使得电子器件的高电平输入端Signal与接地端GND之间没有电势差，因此电子器件不开启。
可选地，所述高电平输出单元21可以用于分时向所述高电平输入端Signal输出具有不同的预定幅值的高电平，以满足不同时间电子器件的供电需要。例如，在图2所示的实施例中，VCC的分时幅值可以为6V、12V、24V或其他的电压值。
所述开关单元可以包括：开关晶体管，其控制极被输入所述逻辑电平，第一极与所述接地端连接，第二极被输入低电平；
当所述逻辑电平处于第一状态时，所述开关晶体管导通，电子器 件的接地端被输入低电平，并且当所述逻辑电平处于第二状态时，所述开关晶体管断开，电子器件的接地端被悬空。
所述开关晶体管可以包括开关三极管；其基极被输入所述逻辑电平，第一极与所述接地端连接，第二极被输入低电平；
当所述开关三极管被输入的逻辑电平为高电平时，所述开关三极管导通，并且当所述开关三极管被输入的逻辑电平为低电平时，所述开关三极管断开。
在实践中，所述开关三极管的第一极可以为集电极或发射极，相应地所述开关三极管的第二极可以为发射极或集电极。
可选地，所述开关晶体管可以包括开关MOS(Metal-Oxide-semiconductor，金属-氧化物-半导体场效应晶体管)管或开关TFT(Thin Film Transistor，薄膜晶体管)。在这种情况下，所述开关晶体管的栅极被输入所述逻辑电平，第一极与所述接地端连接，第二极被输入低电平；当所述逻辑电平处于第一状态时，所述开关MOS管或所述开关TFT导通，电子器件的接地端被输入低电平，当所述逻辑电平处于第二状态时，所述开关MOS管或所述开关TFT断开，电子器件的接地端被输入低电平。
在实践中，所述开关三极管的第一极可以为源极或漏极，相应地所述开关三极管的第二极可以为漏极或源极。
所述开关MOS管和所述开关TFT的导通和关断速度很快，尤其是当所述开关晶体管采用开关MOS管时，其导通和关断速度可以满足适用于高速显示装置的电子器件。
在所述开关晶体管包括开关MOS管或开关TFT的情况下，如果所述开关晶体管为N型晶体管，则当所述逻辑电平处于第一状态时，所述逻辑电平为高电平，当所述逻辑电平处于第二状态时，所述逻辑电平为低电平；如果所述开关晶体管为P型晶体管，则当所述逻辑电平处于第一状态时，所述逻辑电平为低电平，当所述逻辑电平处于第二状态时，所述逻辑电平为高电平。
下面说明本公开提供的电子器件的开关控制装置。在以下的实施例中，所述电子器件包括但并不限于工业相机或射频开关，也可以为其他的由脉冲控制信号控制开关的电子器件。
在以下的实施例中，逻辑电平输出单元可以为逻辑电平控制器， 例如FPGA(Field-Programmable Gate Array，现场可编程门阵列)、DSP(Digital Signal Processor，数字信号处理器)、ARM微处理器或单片机，但是并不限于此，该逻辑电平输出单元可以为任何可以输出逻辑电平的器件。
如图3A所示，在本公开提供的电子器件的开关控制装置的第一实施例中，电子器件为工业相机30，工业相机30的高电平输入端为工业相机的触发接口Trigger，由高电平输出单元(图3A中未示)输出的高电平的幅值为6V。
所述开关单元采用开关MOS管M1，M1为N沟道增强型MOS管；M1的栅极G与逻辑电平控制器31的逻辑电平输出端连接，M1的漏极D与所述工业相机30的接地端GND连接，M1的源极S连接地Gnd。
当逻辑电平控制器31输出逻辑“1”时，即逻辑电平控制器31输出的逻辑电平为高电平时，M1导通。工业相机30的接地端GND接地，此时接口Trigger与GND之间的电势差为6V。对工业相机来说接收到的触发电平的幅值为6V，满足工业相机对信号电平的要求，从而实现工业相机的触发功能。
当逻辑电平控制器31输出逻辑“0”时，即逻辑电平控制器输出的逻辑电平为低电平时，M1断开。此时，工业相机30的接地端GND悬空，则接口Trigger与GND之间不存在电势差。对于工业相机来说接收到的触发电平为低电平，不能满足触发要求。
如图3B所示，在本公开提供的电子器件的开关控制装置的第二实施例中，电子器件为工业相机30，工业相机30的高电平输入端为工业相机的触发接口Trigger，由高电平输出单元(图3B中未示)输出的高电平的幅值为6V。
所述开关单元采用开关MOS管M1，M1为P沟道耗尽型MOS管；M1的栅极G与逻辑电平控制器31的逻辑电平输出端连接，M1的漏极D与所述工业相机30的接地端GND连接，M1的源极S连接地Gnd。
当逻辑电平控制器31输出逻辑“1”时，即逻辑电平控制器31输出的逻辑电平为高电平时，M1导通。工业相机30的接地端GND接地，此时接口Trigger与GND之间的电势差为6V。对工业相机来说，接收到的触发电平的幅值为6V，满足工业相机对信号电平的要求，从而实现了工业相机的触发功能。
当逻辑电平控制器31输出逻辑“0”时，即逻辑电平控制器输出的逻辑电平为低电平时，M1断开。此时，工业相机30的接地端GND悬空，因此接口Trigger与GND之间不存在电势差。对于工业相机来说接收到的触发电平为低电平，不能满足触发要求。
如图3C所示，在本公开提供的电子器件的开关控制装置的第三实施例中，电子器件为工业相机30，工业相机30的高电平输入端为工业相机的触发接口Trigger，由高电平输出单元(图3C中未示)输出的高电平的幅值为6V。
所述开关单元采用开关MOS管M1，M1为N沟道耗尽型MOS管；M1的栅极G与逻辑电平控制器31的逻辑电平输出端连接，M1的漏极D与所述工业相机30的接地端GND连接，M1的源极S连接地Gnd。
当逻辑电平控制器31输出逻辑“0”时，即逻辑电平控制器31输出的逻辑电平为低电平时，M1导通。工业相机30的接地端GND接地，此时接口Trigger与GND之间的电势差为6V。对工业相机来说，接收到的触发电平的幅值为6V，满足工业相机对信号电平的要求，从而实现了工业相机的触发功能。
当逻辑电平控制器31输出逻辑“1”时，即逻辑电平控制器输出的逻辑电平为高电平时，M1断开。此时，工业相机30的接地端GND悬空，因此接口Trigger与GND之间不存在电势差。对于工业相机来说接收到的触发电平为低电平，不能满足触发要求。
如图3D所示，在本公开提供的电子器件的开关控制装置的第四实施例中，电子器件为工业相机30，工业相机30的高电平输入端为工业相机的触发接口Trigger，由高电平输出单元(图3D中未示)输出的高电平的幅值为6V。
所述开关单元采用开关MOS管M1，M1为P沟道增强型MOS管；M1的栅极G与逻辑电平控制器31的逻辑电平输出端连接，M1的漏极D与所述工业相机30的接地端GND连接，M1的源极S连接地Gnd。
当逻辑电平控制器31输出逻辑“0”时，即逻辑电平控制器31输出的逻辑电平为低电平时，M1导通。工业相机30的接地端GND接地，此时接口Trigger与GND之间的电势差为6V。对工业相机来说接收到的触发电平的幅值为6V，满足工业相机对信号电平的要求，从而实现了工业相机的触发功能。
当逻辑电平控制器31输出逻辑“1”时，即逻辑电平控制器输出的逻辑电平为高电平时，M1断开。此时，工业相机30的接地端GND悬空，接口Trigger与GND之间不存在电势差。对于工业相机来说接收到的触发电平为低电平，不能满足触发要求。
如图4A所示，在本公开提供的电子器件的开关控制装置的第五实施例中，电子器件为射频开关40，射频开关40的高电平输入端为射频开关40的高电平端VCC，由高电平输出单元(图4A中未示)输出的高电平的幅值为12V。
所述开关单元采用开关MOS管M1，M1为N沟道增强型MOS管；M1的栅极G与逻辑电平控制器41的逻辑电平输出端连接，M1的漏极D与所述射频开关40的接地端GND连接，M1的源极S连接地Gnd。
当逻辑电平控制器41输出逻辑“1”时，即逻辑电平控制器41输出的逻辑电平为高电平时，M1导通。射频开关40的接地端GND接地，此时VCC与GND之间的电势差为6V。对射频开关来说接收到的触发电平是幅值为6V的高电平，满足射频开关对信号电平的要求，从而实现了射频开关的触发功能。
当逻辑电平控制器41输出逻辑“0”时，即逻辑电平控制器输出的逻辑电平为低电平时，M1断开。此时，射频开关40的接地端GND悬空，VCC与GND之间不存在电势差。对于射频开关来说接收到的触发电平为低电平，不能满足触发要求。
如图4B所示，在本公开提供的电子器件的开关控制装置的第六实施例中，电子器件为射频开关40，射频开关40的高电平输入端也即射频开关40的高电平端VCC，由高电平输出单元(图4B中未示)输出的高电平的幅值为12V。
所述开关单元采用开关MOS管M1，M1为P沟道耗尽型MOS管；M1的栅极G与逻辑电平控制器41的逻辑电平输出端连接，M1的漏极D与所述射频开关40的接地端GND连接，M1的源极S连接地Gnd。
当逻辑电平控制器41输出逻辑“1”时，即逻辑电平控制器41输出的逻辑电平为高电平时，M1导通。射频开关40的接地端GND接地，此时VCC与GND之间的电势差为6V。对射频开关来说接收到的触发电平的幅值为6V，满足射频开关对信号电平的要求，从而实现了射频开关的触发功能。
当逻辑电平控制器41输出逻辑“0”时，即逻辑电平控制器输出的逻辑电平为低电平时，M1断开。此时，射频开关40的接地端GND悬空，VCC与GND之间不存在电势差，对于射频开关来说接收到的触发电平为低电平，不能满足触发要求。
如图4C所示，在本公开提供的电子器件的开关控制装置的第七实施例中，电子器件为射频开关40，射频开关40的高电平输入端也即射频开关40的高电平端VCC，由高电平输出单元(图4A中未示)输出的高电平的幅值为12V。
所述开关单元采用开关MOS管M1，M1为N沟道耗尽型MOS管；M1的栅极G与逻辑电平控制器41的逻辑电平输出端连接，M1的漏极D与所述射频开关40的接地端GND连接，M1的源极S连接地Gnd。
当逻辑电平控制器41输出逻辑“0”时，即逻辑电平控制器41输出的逻辑电平为低电平时，M1导通。射频开关40的接地端GND接地，此时VCC与GND之间的电势差为6V。对射频开关来说接收到的触发电平的幅值为6V，满足射频开关对信号电平的要求，从而实现了射频开关的触发功能。
当逻辑电平控制器41输出逻辑“1”时，即逻辑电平控制器输出的逻辑电平为高电平时，M1断开。此时，射频开关40的接地端GND悬空，VCC与GND之间不存在电势差，对于射频开关来说接收到的触发电平为低电平，不能满足触发要求。
如图4D所示，在本公开提供的电子器件的开关控制装置的第八实施例中，电子器件为射频开关40，射频开关40的高电平输入端也即射频开关40的高电平端VCC，由高电平输出单元(图4D中未示)输出的高电平的幅值为12V。
所述开关单元采用开关MOS管M1，M1为P沟道增强型MOS管；M1的栅极G与逻辑电平控制器41的逻辑电平输出端连接，M1的漏极D与所述射频开关40的接地端GND连接，M1的源极S连接地Gnd。
当逻辑电平控制器41输出逻辑“0”时，即逻辑电平控制器41输出的逻辑电平为低电平时，M1导通。射频开关40的接地端GND接地，此时VCC与GND之间的电势差为6V。对射频开关来说接收到的触发电平的幅值为6V，满足射频开关对信号电平的要求，从而实现了射频开关的触发功能。
当逻辑电平控制器41输出逻辑“1”时，即逻辑电平控制器输出的逻辑电平为高电平时，M1断开。此时，射频开关40的接地端GND悬空，VCC与GND之间不存在电势差。对于射频开关来说接收到的触发电平为低电平，不能满足触发要求。
图5示出根据本公开的实施例所述的电子器件的开关控制方法，其用于对电子器件进行开关控制。所述电子器件包括接地端和高电平输入端。所述开关控制方法包括：
S1：高电平输出单元向电子器件的高电平输入端输出预定幅值的高电平，所述预定幅值大于预定电压；
S2：逻辑电平输出单元输出逻辑电平；
S3：当所述逻辑电平处于第一状态时，开关单元使低电平被输入到所述电子器件的接地端，以打开所述电子器件；当所述逻辑电平处于第二状态时，所述开关单元使所述电子器件的接地端悬空，以关闭所述电子器件。
本公开的实施例提供的开关控制方法通过高电平输出单元向电子器件的高电平输入端输出高电平。与现有技术相比，该高电平的幅值可以大于现有的电平转换器能够转换出的最大高电压，例如5.5V；并且本公开的实施例提供的开关控制方法通过开关单元在逻辑电平处于第一状态时使电子器件的接地端被输入低电平，例如此时该电子器件的接地端可以接地。在这种情况下，该电子器件的开启电压大于现有的电平转换器能够输出的最大高电压，从而可以顺利开启所述电子器件。当逻辑电平处于第二状态时，开关单元使电子器件的接地端不被输入低电平，使得电子器件的接地端悬空，从而使得电子器件的高电平输入端与接地端之间没有电势差，因此电子器件不能开启。
可选地，所述高电平输出单元向电子器件的高电平输入端输出预定幅值的高电平的步骤包括：
所述高电平输出单元分时向所述高电平输入端输出具有不同的预定幅值的高电平。
可选地，所述开关单元可以包括开关晶体管；并且当所述逻辑电平处于第一状态时，开关单元使低电平被输入到所述电子器件的接地端，当所述逻辑电平处于第二状态时，所述开关单元使所述电子器件的接地端悬空的步骤包括：
当所述逻辑电平为第一电平时，所述开关晶体管导通所述电子器件的接地端与低电平输入端之间的连接，当所述逻辑电平为第二电平时，所述开关晶体管断开所述电子器件的接地端与低电平输入端之间的连接，以使得所述电子器件的接地端悬空。
本公开的实施例提供的电子器件包括接地端和高电平输入端，所述电子器件被配置成由上述的开关控制装置进行控制。
以上是本公开的可选实施方式。应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和变化，这些改进和变化也应视为在本发明的保护范围内。

Claims (12)

  1. 一种电子器件的开关控制装置，所述电子器件包括接地端和高电平输入端，所述开关控制装置包括：
    高电平输出单元，其与所述高电平输入端连接并且被配置用于向所述高电平输入端输出具有预定幅值的高电平；所述预定幅值大于预定电压；
    逻辑电平输出单元，其被配置用于输出逻辑电平；以及，
    开关单元，其控制端被输入所述逻辑电平，第一端与所述接地端连接，第二端被输入低电平，并且其被配置用于：当所述逻辑电平处于第一状态时使所述第一端与所述第二端连接，以开启所述电子器件，以及当所述逻辑电平处于第二状态时使所述第一端不与所述第二端连接，以关闭所述电子器件。
  2. 如权利要求1所述的电子器件的开关控制装置，其中，所述高电平输出单元被配置用于分时向所述高电平输入端输出具有不同的预定幅值的高电平。
  3. 如权利要求1或2所述的电子器件的开关控制装置，其中，所述开关单元包括：开关晶体管，其控制极被输入所述逻辑电平，第一极与所述接地端连接，第二极被输入低电平。
  4. 如权利要求3所述的电子器件的开关控制装置，其中，所述开关晶体管包括开关三极管；其基极被输入所述逻辑电平，第一极与所述接地端连接，第二极被输入低电平。
  5. 如权利要求3包括所述的电子器件的开关控制装置，其中，所述开关晶体管包括开关MOS管；其栅极被输入所述逻辑电平，第一极与所述接地端连接，第二极被输入低电平。
  6. 如权利要求3包括所述的电子器件的开关控制装置，其中，所述开关晶体管包括开关TFT；其栅极被输入所述逻辑电平，第一极与所述接地端连接，第二极被输入低电平。
  7. 如权利要求5所述的电子器件的开关控制装置，其中，如果所述开关MOS管为N沟道增强型MOS管或P沟道耗尽型MOS管，则当所述逻辑电平处于第一状态时，所述逻辑电平为高电平，以及当所述逻辑电平处于第二状态时，所述逻辑电平为低电平。
  8. 如权利要求5所述的电子器件的开关控制装置，其中如果所述开关晶体管为P沟道增强型晶体管或N沟道耗尽型晶体管时，则当所述逻辑电平处于第一状态时，所述逻辑电平为低电平，以及当所述逻辑电平处于第二状态时，所述逻辑电平为高电平。
  9. 一种电子器件的开关控制方法，所述电子器件包括接地端和高电平输入端，所述开关控制方法包括：
    高电平输出单元向电子器件的高电平输入端输出预定幅值的高电平；所述预定幅值大于预定电压；
    逻辑电平输出单元输出逻辑电平；
    当所述逻辑电平处于第一状态时，开关单元使低电平被输入所述电子器件的接地端，以打开所述电子器件；当所述逻辑电平处于第二状态时，所述开关单元使所述电子器件的接地端悬空，以关闭所述电子器件。
  10. 如权利要求9所述的电子器件的开关控制方法，其中，所述高电平输出单元向电子器件的高电平输入端输出预定幅值的高电平的步骤包括：
    所述高电平输出单元分时向所述高电平输入端输出具有不同的预定幅值的高电平。
  11. 如权利要求9或10所述的电子器件的开关控制方法，其中，所述开关单元包括开关晶体管；并且其中当所述逻辑电平处于第一状态时，开关单元控制低电平被输入所述电子器件的接地端，当所述逻辑电平处于第二状态时，所述开关单元控制所述电子器件的接地端悬空的步骤包括：
    当所述逻辑电平为第一电平时，所述开关晶体管导通所述电子器件的接地端与低电平输入端之间的连接，以及当所述逻辑电平为第二电平时，所述开关晶体管断开所述电子器件的接地端与低电平输入端之间的连接，以使得所述电子器件的接地端悬空。
  12. 一种电子器件，包括接地端和高电平输入端，其中，所述电子器件被配置成由如权利要求1至8中任一权利要求所述的开关控制装置进行控制。
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