WO2017122284A1 - Substrate with built-in component and method for manufacturing substrate with built-in component - Google Patents

Substrate with built-in component and method for manufacturing substrate with built-in component Download PDF

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Publication number
WO2017122284A1
WO2017122284A1 PCT/JP2016/050745 JP2016050745W WO2017122284A1 WO 2017122284 A1 WO2017122284 A1 WO 2017122284A1 JP 2016050745 W JP2016050745 W JP 2016050745W WO 2017122284 A1 WO2017122284 A1 WO 2017122284A1
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Prior art keywords
copper
component
terminal
connection portion
copper terminal
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PCT/JP2016/050745
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French (fr)
Japanese (ja)
Inventor
松本　徹
琢哉 長谷川
健太朗 青木
Original Assignee
株式会社メイコー
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Application filed by 株式会社メイコー filed Critical 株式会社メイコー
Priority to CN201680075962.0A priority Critical patent/CN108464061A/en
Priority to PCT/JP2016/050745 priority patent/WO2017122284A1/en
Priority to JP2017561097A priority patent/JP6839099B2/en
Priority to KR1020187018394A priority patent/KR20180103859A/en
Priority to TW105137089A priority patent/TW201725946A/en
Publication of WO2017122284A1 publication Critical patent/WO2017122284A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes

Definitions

  • the present invention relates to a component-embedded substrate having a built-in electric / electronic component having electrodes made of copper on the front and back surfaces, and a manufacturing method thereof.
  • Patent Documents 1 and 2 disclose a component built-in substrate and a manufacturing method thereof.
  • a field effect transistor MOSFET: Metal-Oxide-Semiconductor-Field-Effect-Transistor
  • MOSFET Metal-Oxide-Semiconductor-Field-Effect-Transistor
  • the thermal conductivity is only 100 to 150 W / m ⁇ K, which is a fraction of the thermal conductivity of the metal.
  • the built-in semiconductor chip can be dissipated.
  • the vias when filling the vias with conductors, if the via holes are arranged at a narrow pitch, it becomes difficult to reliably fill the via holes, and the surface of the via conductors becomes concave, which is required for a component-embedded substrate. Heat dissipation and current capacity path cannot be secured. Therefore, it becomes difficult to arrange the via conductors at a narrow pitch, and it becomes difficult to ensure a high current capacity while providing high heat dissipation.
  • the present invention has been made in view of such a problem, and an object of the present invention is to provide a component-embedded substrate that can ensure a relatively high current capacity while having a relatively high heat dissipation property, and It is in providing the manufacturing method.
  • a component-embedded substrate of the present invention includes an insulating layer containing an insulating resin material, a first copper terminal on a first surface, and a second copper on a second surface opposite to the first surface.
  • the formed second outer layer wiring pattern, the first copper terminal and the first outer layer wiring pattern, the first copper connection part for electrically connecting the first copper terminal and the first outer layer wiring pattern, the second copper terminal and the second outer layer wiring pattern A first copper terminal, the first copper connection, and a connection surface located along a surface shape of the first copper terminal, and the second copper connection.
  • the terminal, the second copper connection portion, and the connection surface are located along the surface shape of the second copper terminal. That.
  • a method for manufacturing a component-embedded board includes an IC including a first copper terminal on a first surface and a second copper terminal on a second surface opposite to the first surface.
  • a method of manufacturing a component-embedded substrate that incorporates a component wherein a first copper terminal is brought into contact with a support member, and a mounting step of mounting the IC component on the support member, and an insulating resin material so as to cover the IC component
  • a first outer layer wiring pattern forming step formed on one surface, and the second copper contact A second outer layer wiring pattern forming step of forming
  • a relatively high current capacity can be ensured while having a relatively high heat dissipation.
  • FIG. 1 to FIG. 4 are schematic cross-sectional views in each manufacturing process of the method for manufacturing the component-embedded substrate according to the first embodiment.
  • 5 and 6 are partially enlarged plan views showing the positional relationship between the IC component, the copper terminal, and the via when each terminal of the built-in IC component is viewed in plan, and
  • FIG. 5 is the first copper terminal.
  • FIG. 6 is a partially enlarged plan view of the second copper terminal (upper side in FIG. 4).
  • FIG. 8 and 9 are partially enlarged plan views showing the positional relationship between the IC component, the copper terminal, and the copper connection portion when each terminal of the built-in IC component is viewed in plan.
  • FIG. FIG. 9 shows a partially enlarged plan view on the copper terminal side (lower side in FIG. 7), and FIG. 9 shows a partially enlarged plan view on the second copper terminal side (upper side in FIG. 7).
  • a support member 3 in which an insulating adhesive 2 is applied on a support plate 1 is prepared, and an IC component 4 which is a built-in electronic / electrical component is also prepared (preparation process).
  • the support plate 1 a support plate having a degree of rigidity required under process conditions is used.
  • the support plate 1 is made of a metal plate such as a rigid SUS (stainless steel) plate or an aluminum plate with a copper foil (conductive material) attached thereto. A member provided may be used.
  • the adhesive 2 may be a general epoxy adhesive, for example, or may be applied by a dispenser or printing.
  • the IC component 4 is a general MOSFET, and one first copper terminal 4b made of copper is disposed on the first surface 4a side, and three second copper electrodes are made on the second surface 4c side.
  • a copper terminal 4d is provided.
  • the first copper terminal 4 b functions as the drain terminal of the IC component 4 and is disposed on the entire first surface 4 a of the IC component 4.
  • the second copper terminal 4d functions as a source terminal or a gate terminal of the IC component 4, and is partially disposed with respect to the second surface 4c of the IC component 4 (that is, the second surface 4c is a partial portion). Exposed).
  • the number of the first copper terminals 4b and the second copper terminals 4d is not limited, and can be changed as appropriate according to the electrical characteristics required for the component-embedded substrate (that is, the type of the embedded IC component 4).
  • a mounting process for mounting the IC component 4 on the adhesive 2 is performed. More specifically, the first copper disposed on the first surface 4a side of the IC component 4 with respect to the adhesive 2 constituting the support member 3 using a surface mounter (chip mounter) having a suction nozzle. The mounting process is performed so that the terminals 4b come into contact with each other. That is, the first copper terminal 4 b is disposed at a position close to the adhesive 2, and the second copper terminal 4 d is disposed at a position away from the adhesive 2.
  • an insulating layer forming step for forming an insulating layer 5 in which the IC component 4 is embedded is performed. More specifically, a prepreg 6, a resin body 7 with a wiring pattern, a prepreg 8, and a sandwiching plate (support plate) 9 are laid up on the support member 3 on which the IC component 4 is mounted, and this is heated under vacuum. While pressing. This press is performed using, for example, a vacuum press machine.
  • the resin body 7 with a wiring pattern includes a resin substrate 7a made of an insulating resin material, and a wiring pattern 7b formed on the front and back surfaces of the resin substrate 7a.
  • the wiring pattern 7b is also formed so as to cover the side surface 7d exposed by the through hole 7c, and the wiring pattern 7b formed on the front side of the resin base 7a and the wiring formed on the back side of the resin base 7a.
  • the pattern 7b is electrically connected.
  • the sandwiching plate 9 is made of a metal foil made of SUS (stainless steel), aluminum, or the like, which is rigid, like the support plate 1, or a copper foil.
  • the prepreg 6 and the resin base 7a are previously formed with a through hole into which the IC component 4 can be inserted, and the layup is performed so that the IC component 4 is inserted into the through hole.
  • the prepreg 6, the resin base 7 a, and the prepreg 8 are integrated and the insulating layer 5 in which the IC component 4 is embedded is formed by heating and pressing in the vacuum described above. Further, at the same time that the IC component 4 is embedded by the insulating layer 5, the wiring pattern 7 b is also embedded in the insulating layer 5, and the internal wiring pattern of the component built-in substrate is formed. In addition, the through-hole 7c of the resin body 7 with a wiring pattern is filled with the insulating resin material which comprises the prepregs 6 and 8 by the heating and press process in said vacuum.
  • each via for example, by irradiating a CO 2 laser to a via forming portion, a member at a CO 2 laser irradiated portion may be removed, and a via having a desired shape may be formed.
  • the present invention is not limited to the CO 2 laser, and for example, a high frequency laser such as UV-YAG or excimer may be used.
  • each via may be formed by plasma etching or chemical etching. Note that the support plate 1 and the holding plate 9 may be removed before the CO 2 laser irradiation.
  • the first via 11 is disposed along the planar shape of the first copper terminal 4b, and the opening dimension of the first via 11 is slightly smaller than the planar dimension of the first copper terminal 4b. ing. That is, the opening shape of the first via 11 is similar to the planar shape of the first copper terminal 4 b, and most of the first copper terminal 4 b is exposed by the first via 11.
  • the first via 11 preferably exposes about 50% or more of the area of the main surface of the first copper terminal 4b (that is, the surface located on the side opposite to the IC component 4 side), more preferably 80%. % Or more, particularly preferably 90% or more.
  • each of the third vias 13 is disposed along the planar shape of each of the second copper terminals 4 d to which each via reaches, and each opening dimension of the third via 13 is the first dimension. It is slightly smaller than the respective plane dimensions of the two copper terminals 4d. That is, each opening shape of the third via 13 is similar to the planar shape of the second copper terminal 4d to which each via reaches, and most of the second copper terminal 4d is exposed by the third via 13. As in the case of the first via 11, each third via 13 is about 50% or more of the area of the main surface of the second copper terminal 4 d (that is, the surface located on the side opposite to the IC component 4 side). Is preferably exposed, more preferably 80% or more, and particularly preferably 90% or more.
  • the reason for adjusting the shapes and dimensions of the first via 11 and the third via 13 in this way is that the planar dimensions of the conductive via that fills the first via 11 and the third via 13 are the same as those of the IC component 4. This is to ensure the same level as the planar dimensions of each copper terminal. The reason why the conductive via is made as large as possible will be described later.
  • first copper terminal 4b and the second copper terminal 4d are further subjected to a soft etching process to remove oxides and organic substances on the exposed surfaces of the first copper terminal 4b and the second copper terminal 4d exposed by the via formation. Is preferred. Thereby, the surface of fresh copper will be exposed, adhesiveness with the copper which precipitates in subsequent plating processing will increase, and electrical connection reliability will improve as a result.
  • each via is filled with copper, and a first conductive via (first copper connection portion) 15, a second conductive via 16, and a third conductive via (second copper connection) made of copper.
  • Part 17 and the fourth conductive via 18 are formed. More specifically, first, the support plate 1 and the sandwiching plate 9 are removed, and then desmearing and half-etching treatment is performed on each via as necessary, followed by plating treatment such as chemical copper plating and electrolytic copper plating. As a result, copper is deposited in each via, and the first conductive via 15, the second conductive via 16, the third conductive via 17, and the fourth conductive via 18, which are filled vias filled with the copper, are formed. Will be.
  • the first conductive via 15 fills the first via 11 and reaches the first copper terminal 4b
  • the second conductive via 16 fills the second via 12 and reaches the wiring pattern 7b
  • the via 17 fills the third via 13 and reaches the second copper terminal 4d
  • the fourth conductive via 18 fills the fourth via 14 and reaches the wiring pattern 7b.
  • the first copper wiring layer 21 is formed on the surface of the prepreg 6 constituting the insulating layer 5
  • the second copper wiring layer 22 is formed on the surface of the prepreg 8 constituting the insulating layer 5. Is formed.
  • the first conductive via 15 fills the first via 11, as shown in FIG. 8, the first conductive via 15 is disposed along the planar shape of the first copper terminal 4b, and the first conductive via 15 is provided.
  • the planar dimension of 15 is slightly smaller than the planar dimension of the first copper terminal 4b. That is, the planar dimension of the first conductive via 15 is similar to the planar shape of the first copper terminal 4b.
  • the connection surface between the first copper terminal 4b and the first conductive via 15 is positioned along the planar shape of the first copper terminal 4b. Then, by adjusting the exposure ratio of the first copper terminal 4b by the first via 11 as described above, the coverage of the first conductive via 15 with respect to the first copper terminal 4b is about 50% or more, more preferably. 80% or more, particularly preferably 90% or more.
  • each of the third conductive vias 17 fills the third via 13, as shown in FIG. 9, each of the third conductive vias 17 is arranged along each planar shape of the second copper terminal 4d to be connected. It is installed.
  • Each planar dimension of the third conductive via 17 is slightly smaller than each planar dimension of the second copper terminal 4d to be connected. That is, the planar dimensions of the third conductive vias 17 are similar to the planar shapes of the second copper terminals 4d to be connected. In other words, the connection surface between the second copper terminal 4d and the third conductive via 17 is located along the planar shape of the second copper terminal 4d.
  • the coverage of the third conductive via 17 with respect to the second copper terminal 4d becomes about 50% or more, more preferably. 80% or more, particularly preferably 90% or more.
  • the heat generated in the IC component 4 can be efficiently radiated, and the IC component 4 is deteriorated.
  • the reliability of the component-embedded substrate itself can be improved.
  • the on-resistance of the IC component 4 can be reduced by improving the heat dissipation.
  • a higher current capacity can be ensured, and a component-embedded substrate having characteristics superior in the allowable current value can be realized.
  • the first copper connection portion (first conductive via 15) forming step that is, the first conductive via 15) electrically connected to the first copper terminal 4b (ie, the first step).
  • the copper connection portion forming step) and the formation step of the second copper connection portion (third conductive via 17) electrically connected to the second copper terminal 4d (ie, the second copper connection portion forming step) are completed.
  • the first outer layer wiring pattern 23 is formed by patterning the first copper wiring layer 21 located on the first surface 5a of the insulating layer 5 (first outer layer wiring pattern forming step). Then, the second copper wiring layer 22 located on the second surface 5b of the insulating layer 5 is patterned to form the second outer layer wiring pattern 24 (second outer layer wiring pattern forming step). For example, the first outer wiring pattern 23 and the second outer wiring pattern 24 are formed by etching the first copper wiring layer 21 and the second copper wiring layer 22 using a known photolithography technique.
  • the formation of the component-embedded substrate 30 as shown in FIG. 10 is completed.
  • the plurality of component-embedded substrates 30 are manufactured as one substrate, and after the formation of the plurality of component-embedded substrates 30, the one substrate is cut and finally A plurality of component-embedded substrates 30 are manufactured simultaneously.
  • the component-embedded substrate 30 is formed on the insulating layer 5 containing an insulating resin material, the IC component 4 embedded in the insulating layer 5, and the first surface 5a of the insulating layer 5.
  • the first outer layer wiring pattern 23, the second outer layer wiring pattern 24 formed on the second surface 5b of the insulating layer 5, and the first copper terminal 4b of the IC component 4 and the first outer layer wiring pattern 23 are electrically connected.
  • the first conductive via 15 and the third conductive via 17 that electrically connects the second copper terminal 4 d of the IC component 4 and the second outer layer wiring pattern 24 are provided.
  • each of the first conductive via 15 and the third conductive via 17 is located along the surface shape of the copper terminal of the IC component 4 to be connected, and has a planar dimension equivalent to (slightly smaller than) the copper terminal. Therefore, the heat generated in the IC component 4 can be radiated well and a relatively high current capacity can be secured.
  • a structure that can dissipate heat through a conductive via made of copper without using a conductive adhesive or solder having a relatively low thermal conductivity Therefore, heat dissipation can be improved as described above.
  • a relatively large conductive via corresponding to each copper terminal of the IC component 4 is formed without providing a plurality of relatively small conductive vias, it is possible to further improve heat dissipation and secure a higher current capacity. Will be realized.
  • the second copper terminal 4d is a drain terminal and is formed on the entire first surface 4a of the IC component 4, and the first conductive via 15 is further formed.
  • the second copper terminal 4d serving as the source terminal or the gate terminal has a relatively small dimension (terminal area) with respect to the second surface 4c.
  • FIG. and the conductive via according to the present invention can be formed for different IC components 4 'as shown in FIG.
  • the component-embedded substrate 30 ′ shown in FIGS. 11 and 12 will be described below as a modified example according to the first embodiment.
  • FIG. 11 is a schematic cross-sectional view of a component-embedded substrate 30 ′ according to a modified example
  • FIG. 12 shows an IC component 4 ′, each copper terminal, and each conductive via in the component-embedded substrate 30 ′ according to the modified example. It is the elements on larger scale which show the positional relationship of these.
  • symbol is attached
  • the component-embedded substrate 30 ′ is formed on the insulating layer 5 containing an insulating resin material, the IC component 4 ′ embedded in the insulating layer 5, and the first surface 5 a of the insulating layer 5.
  • the first outer layer wiring pattern 23, the second outer layer wiring pattern 24 formed on the second surface 5b of the insulating layer 5, the first copper terminal 4b 'of the IC component 4' and the first outer layer wiring pattern 23 are electrically connected.
  • a third conductive via 17 ′ for electrically connecting the second copper terminal 4 d ′ of the IC component 4 ′ and the second outer layer wiring pattern 24.
  • one of the two first copper terminals 4b ' functions as a source terminal, the other functions as a gate terminal, and the second copper terminal 4d' functions as a drain terminal. That is, in the present modified example, the number and shape of the first copper terminal 4b ′ and the second copper terminal 4d ′ are different while the direction of the IC component 4 ′ is reversed as compared with the first embodiment. .
  • each of the first conductive vias 15 ′ has a surface shape of the first copper terminal 4b ′ (source terminal or drain terminal) of the IC component 4 ′ to be connected. And has a planar dimension equivalent to (slightly smaller than) each of the first copper terminals 4b ′.
  • the third conductive via 17 ′ follows the surface shape of the second copper terminal 4 d ′ (gate terminal) of the IC component 4 ′ to be connected. And has a planar dimension equivalent to (slightly smaller than) each of the second copper terminals 4d ′. Therefore, also in this modification, the heat generated in the IC component 4 ′ can be radiated well and a relatively high current capacity can be secured.
  • a single copper connection portion is connected to one copper terminal of the IC component 4.
  • the coverage of the copper connection portion described above can be satisfied. You may connect a some copper connection part with respect to one copper terminal. That is, you may form a copper connection part from several copper connection members. Further, the number of IC components 4 embedded in the component-embedded substrate 30 is not limited to one and may be plural.
  • FIGS. 13 to 18 are schematic cross-sectional views in each manufacturing process of the method for manufacturing the component-embedded substrate according to the second embodiment.
  • a support member 103 that is an insulating adhesive sheet is prepared, and an IC component 104 that is a built-in electronic / electrical component is also prepared (preparation step).
  • the support member 103 is a general adhesive sheet, and one that can be easily peeled off from the IC component 104, copper, and insulating resin material in a process described later.
  • the IC component 104 has one first copper terminal 104b made of copper on the first surface 104a side, and two second copper terminals 104d made of copper on the second surface 104c side.
  • the first copper terminal 104 b functions as the drain terminal of the IC component 104 and is disposed on the entire first surface 104 a of the IC component 104.
  • one of the second copper terminals 104d functions as a source terminal, the other functions as a gate terminal, and each terminal is partially disposed on the second surface 104c of the IC component 104 (that is, The second surface 104c is partially exposed).
  • a mounting step of mounting the first copper foil 107 on which the IC component 104 and desired through holes 105 and 106 are formed on the support member 103 is performed. More specifically, using a surface mounter (chip mounter) having a suction nozzle, the support member 103 is fixed so that the first copper terminal 104b disposed on the first surface 104a side of the IC component 104 is in contact with the support member 103. Then, the first copper foil 107 is attached to the support member 103 so that the IC component 104 is inserted into the through hole 106 of the first copper foil 107.
  • the first copper foil 107 may be fixed to the support member 103 first, and then the IC component 104 may be fixed to the support member 103 while being inserted into the through hole 106.
  • the through-hole 106 in which the IC component 104 is disposed is filled with an insulating resin material and cured to form a resin body 108.
  • the IC component 104 is embedded in the resin body 108.
  • the support member 103 is peeled off, and the prepreg 109 and the second copper foil 110 are placed on the side opposite to one end where the support member 103 is disposed (that is, the second surface 104c side).
  • press while heating under vacuum. This press is performed using, for example, a vacuum press machine.
  • each via for example, by irradiating a CO 2 laser to a via forming portion, a member at a CO 2 laser irradiated portion may be removed, and a via having a desired shape may be formed.
  • a high frequency laser such as UV-YAG or excimer may be used.
  • each via may be formed by plasma etching or chemical etching.
  • each of the first vias 112 is disposed along the planar shape of each of the second copper terminals 104d to which each via reaches, similarly to the third via 13 of the first embodiment.
  • Each opening dimension is slightly smaller than each planar dimension of the second copper terminal 104d.
  • each opening shape of the first via 112 is similar to the planar shape of the second copper terminal 104d to which each via reaches, and most of the second copper terminal 104d is exposed by the first via 112.
  • each first via 112 has an area of about 50 of the main surface of the second copper terminal 104d (that is, the surface located on the side opposite to the IC component 104 side). % Or more is preferably exposed, more preferably 80% or more, and particularly preferably 90% or more.
  • the reason for adjusting the shape and size of the first via 112 in this manner is that, as in the first embodiment, the planar size of the conductive via that fills the first via 112 is changed to the second copper of the IC component 104. This is to ensure the same size as the planar dimension of the terminal 104d.
  • a desmear process is performed to remove the resin remaining in the via formation.
  • the second copper terminal 104d is further subjected to a soft etching process to remove oxides and organic substances on the exposed surface of the second copper terminal 104d exposed by the via formation. Thereby, the surface of fresh copper will be exposed, adhesiveness with the copper which precipitates in subsequent plating processing will increase, and electrical connection reliability will improve as a result.
  • a first conductive via 114 filling the first via 112 and a second conductive via 115 filling the second via 113 by performing a plating process such as chemical copper plating or electrolytic copper plating
  • a first copper wiring layer 116 located on the first surface 111a side of the insulating layer 111 and electrically connected to the first copper terminal 104b and the first copper foil 107, and a second copper wiring covering the second copper foil 110 Layer 117 is formed.
  • the portion covering the entire surface of the first copper terminal 104b electrically connects the portion covering the region other than the first copper terminal 104b and the first copper terminal 104b. Functions as the first copper connection part 116a.
  • the 1st copper connection part 116a is arrange
  • the first conductive via 114 fills the first via 112
  • the first conductive via 114 is arranged along the planar shape of the second copper terminal 104d, and the first conductive via 114 is provided.
  • the planar dimension of 114 is slightly smaller than the planar dimension of the second copper terminal 104d. That is, the planar dimension of the first conductive via 114 is similar to the planar shape of the second copper terminal 104d. In other words, the connection surface between the second copper terminal 104d and the first conductive via 114 is positioned along the planar shape of the second copper terminal 104d.
  • the coverage ratio of the first conductive via 114 to the second copper terminal 104d becomes about 50% or more, more preferably. 80% or more, particularly preferably 90% or more.
  • the size and shape of the first conductive via 114 connected to the second copper terminal 104d of the IC component 104 are adjusted to increase the size, and the first copper connection portion 116a connected to the first copper terminal 104b is formed.
  • the heat generated in the IC component 104 can be efficiently dissipated, and the deterioration of the IC component 104 and the reliability of the component-embedded substrate itself can be improved.
  • the on-resistance of the IC component 104 can be reduced by improving the heat dissipation.
  • by increasing the size of the first conductive via 114 and the first copper connection portion 116a a higher current capacity can be ensured, and a component-embedded substrate having superior characteristics in the allowable current value can be realized.
  • the first copper connection part 116a formation process that is, the first copper connection
  • the connecting portion forming step and the forming step of the second copper connecting portion first conductive via 114) electrically connected to the second copper terminal 104d (that is, the second copper connecting portion forming step) are completed.
  • the first copper wiring layer 116 located on the first surface 111a side of the insulating layer 111 is patterned to form a first outer layer wiring pattern 123 (first outer layer wiring pattern forming step).
  • Patterning is performed on the second copper wiring layer 117 and the second copper foil 110 located on the second surface 111b of the insulating layer 111 to form a second outer layer wiring pattern 124 (second outer layer wiring pattern forming step).
  • the first copper wiring layer 116, the second copper wiring layer 117, and the second copper foil 110 are etched using a known photolithography technique so that the first outer layer wiring pattern 123 and the second outer layer wiring pattern are etched.
  • 124 is formed.
  • the formation of the component built-in substrate 130 as shown in FIG. 18 is completed.
  • the plurality of component-embedded substrates 130 are manufactured as one substrate, and after the formation of the plurality of component-embedded substrates 130 is completed, the one substrate And finally, a plurality of component-embedded boards 130 are manufactured simultaneously.
  • the size and shape of the first conductive via 114 connected to the second copper terminal 104d of the IC component 104 are adjusted and the size is increased, and the first conductive via 114 is connected to the first copper terminal 104b. Since the first copper connection portion 116a is adjusted to the same plane size as the first copper terminal 104b, the heat generated in the IC component 104 can be efficiently radiated, and the deterioration of the IC component 104 and the built-in component The reliability of the substrate itself can be further improved. In addition, the on-resistance of the IC component 104 can be reduced by improving the heat dissipation. Furthermore, by increasing the size of the first conductive via 114 and the first copper connection portion 116a, a higher current capacity can be ensured, and a component-embedded substrate having superior characteristics in the allowable current value can be realized.
  • the component-embedded substrate according to the first embodiment of the present invention includes an insulating layer containing an insulating resin material, a first copper terminal on the first surface, and a second copper terminal on the second surface opposite to the first surface.
  • the second outer layer wiring pattern, the first copper terminal and the first outer layer wiring pattern are electrically connected, and the second copper terminal and the second outer layer wiring pattern are electrically connected.
  • a first copper terminal, the first copper connection and the connection surface are located along a surface shape of the first copper terminal, and the second copper terminal.
  • the said 2nd copper connection part and a connection surface are located along the surface shape of the said 2nd copper terminal.
  • both the first copper connection portion and the second copper connection portion are located along the surface shape of the copper terminal of the IC component to be connected.
  • the heat generated can be radiated satisfactorily and a relatively high current capacity can be secured.
  • the component-embedded substrate employs a structure that can dissipate heat through a connection made of copper without using a conductive adhesive or solder having a relatively low thermal conductivity. The improvement of performance is realized.
  • relatively large first copper connection portions and second copper connection portions corresponding to the respective copper terminals of the IC component are formed without providing a plurality of relatively small connection portions (conduction vias), the connection is further improved. Thus, the improvement of the heat dissipation and the securing of a higher current capacity are realized.
  • the component-embedded substrate according to the second embodiment of the present invention is the first embodiment described above, wherein the first copper connection portion covers the first copper terminal, and the second copper connection connects to the second copper terminal.
  • the coverage of the part is 50% or more.
  • either the first copper terminal or the second copper terminal is formed on the entire surface of the IC component. It is a drain terminal.
  • a component-embedded substrate according to a fourth embodiment of the present invention is the component-embedded substrate according to any one of the first to third embodiments described above, wherein the first copper connection portion and the second copper connection portion are configured from a single connection member. It is that you are. Thereby, the heat dissipation in the component built-in substrate is further improved, and a higher current capacity can be easily secured.
  • the first copper connection portion and the second copper connection portion are constituted by a plurality of connection members. That is. As a result, it is possible to easily ensure a higher current capacity while improving the heat dissipation in the component-embedded substrate. Furthermore, the first copper connection portion and the second copper are adapted to correspond to the copper terminals of various IC components. It becomes possible to arrange the connecting portion.
  • a method of manufacturing a component-embedded substrate including an IC component including a first copper terminal on a first surface and a second copper terminal on a second surface opposite to the first surface.
  • a method of manufacturing a component-embedded substrate comprising: mounting a step of bringing a first copper terminal into contact with a support member and mounting the IC component on the support member; and laminating an insulating resin material so as to cover the IC component.
  • the first copper terminal and the A 1st copper connection part and a connection surface are located along the surface shape of the said 1st copper terminal, and in the said 2nd copper connection part formation process, the said 2nd copper terminal, the said 2nd copper connection part, and a connection surface are used. It is located along the surface shape of the second copper terminal.
  • both the first copper connection portion and the second copper connection portion are located along the surface shape of the copper terminal of the IC component to be connected. It is possible to manufacture a component-embedded substrate that can radiate heat generated in an IC component well and can ensure a relatively high current capacity. This is because a conductive adhesive or solder having a relatively low thermal conductivity is not used, so that heat can be efficiently radiated through the connection portion made of copper.
  • the manufacturing method of the component built-in substrate according to the seventh embodiment of the present invention is the above-described sixth embodiment, wherein the first copper connection portion forming step and the second copper connection portion forming step are configured to The coverage of the first copper connection portion and the coverage of the second copper connection portion with respect to the second copper terminal are 50% or more.
  • the electrical connection by the relatively large first copper connection portion and the second copper connection portion corresponding to each copper terminal of the IC component is ensured without providing a plurality of relatively small connection portions (conduction vias). Therefore, further improvement in heat dissipation and securing of a higher current capacity can be realized.
  • the method for manufacturing a component-embedded substrate according to the eighth embodiment of the present invention is the same as the sixth or seventh embodiment described above, in the first copper connection portion forming step and the second copper connection portion forming step. Forming the first copper connection and the second copper connection from a member. Thereby, the heat dissipation in the component built-in substrate is further improved, and a higher current capacity can be easily secured.
  • the component-embedded substrate manufacturing method is the above-described sixth or seventh embodiment, wherein the first copper connection portion forming step and the second copper connection portion forming step include a plurality of connection members. Forming the first copper connection and the second copper connection. As a result, it is possible to easily ensure a higher current capacity while improving the heat dissipation in the component-embedded substrate. Furthermore, the first copper connection portion and the second copper are adapted to correspond to the copper terminals of various IC components. It becomes possible to arrange the connecting portion.
  • Support plate Adhesive 3
  • Support member 4 IC component 4a 1st surface 4b 1st copper terminal 4c 2nd surface 4d 2nd copper terminal 5 Insulating layer 5a 1st surface 5b 2nd surface 6
  • Prepreg 7 Resin body with wiring pattern 7a Resin base 7b Wiring pattern 7c Through hole 7d Side 8
  • Nipping plate (support plate) 11 First via 12 Second via 13 Third via 14 Fourth via 15 First conductive via (first copper connection) 16 Second conductive via 17 Third conductive via (second copper connecting portion) 18 Fourth conductive via 21 First copper wiring layer 22 Second copper wiring layer 23 First outer layer wiring pattern 24 Second outer layer wiring pattern 30 Component-embedded substrate

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Abstract

The present invention has: an insulating layer (5) containing an insulating resin material; an IC component (4), which is provided with a first copper terminal (4b) on a first surface, and a second copper terminal (4d) on a second surface on the reverse side of the first surface, and which is embedded in the insulating layer; a first outer layer wiring pattern (23) formed on the first surface of the insulating layer; a second outer layer wiring pattern (24) formed on the second surface of the insulating layer, said second surface being on the reverse side of the first surface; a first copper connection section (15) that electrically connects the first copper terminal and the first outer layer wiring pattern to each other; and a second copper connection section (17) that electrically connects the second copper terminal and the second outer layer wiring pattern to each other. The first copper terminal, the first copper connection section, and a connection surface are positioned conforming to the surface shape of the first copper terminal, and the second copper terminal, the second copper connection section, and the connection surface are positioned conforming to the surface shape of the second copper terminal.

Description

部品内蔵基板及び部品内蔵基板の製造方法Component built-in substrate and method for manufacturing component built-in substrate
　本発明は、表裏面に銅からなる電極を有する電気・電子部品を内蔵した部品内蔵基板、及びその製造方法に関する。 The present invention relates to a component-embedded substrate having a built-in electric / electronic component having electrodes made of copper on the front and back surfaces, and a manufacturing method thereof.
　従来から、各種の電気・電子機器の小型化、薄型化、軽量化、及び多機能化を図るための研究開発が行われてきている。特に、携帯電話、ノートパソコン、デジタルカメラ等の民生品では、多機能化を図りつつも小型化、薄型化、及び軽量化が強く求められている。また、各種の電気・電子機器においては、伝送信号の高周波化及び高速化も図られており、これに伴う信号ノイズの増大を防止することも要求されている。 Conventionally, research and development has been conducted to reduce the size, thickness, weight, and functionality of various electrical and electronic devices. In particular, consumer products such as mobile phones, notebook computers, and digital cameras are strongly required to be smaller, thinner, and lighter while being multi-functional. Further, in various electric / electronic devices, transmission signals have been increased in frequency and speed, and it is also required to prevent an increase in signal noise associated therewith.
　このような要求を実現するために、電気・電子機器に組み込まれる回路基板として、従来は基板表面に実装されていた各種の電気・電子部品を基板の絶縁層である絶縁基材内に内蔵した構造を備える部品内蔵基板や、当該部品内蔵基板を積層してなる部品内蔵多層回路基板の研究開発及び製造が従来から行われてきている。例えば、特許文献１及び２に、部品内蔵基板及びその製造方法が開示されている。 In order to realize such demands, various electric / electronic components that have been mounted on the substrate surface as a circuit board to be incorporated in electric / electronic devices are built in an insulating base material that is an insulating layer of the substrate. Research and development and manufacture of a component-embedded substrate having a structure and a component-embedded multilayer circuit board formed by laminating the component-embedded substrate have been conventionally performed. For example, Patent Documents 1 and 2 disclose a component built-in substrate and a manufacturing method thereof.
特開２００６－４９７６２号公報JP 2006-49762 A 特開２０１３－２２９５４８号公報JP 2013-229548 A
　しかしながら、特許文献１に開示されている部品内蔵基板においては、その製造プロセスの関係から、内蔵される金属酸化膜半導体の電界効果型トランジスタ（ＭＯＳＦＥＴ：Metal-Oxide-Semiconductor Field-Effect Transistor）等の半導体部品の一端の全面が接着剤によって覆われているため、当該半導体部品において生じる熱を十分に放熱することができない問題がある。これは、当該接着剤に高い熱伝導性ペースト剤を使用したとしても、その熱伝導率は１００～１５０Ｗ／ｍ・Ｋにとどまり、金属の熱伝導率の数分の１となるためである。 However, in the component-embedded substrate disclosed in Patent Document 1, a field effect transistor (MOSFET: Metal-Oxide-Semiconductor-Field-Effect-Transistor) of a built-in metal oxide semiconductor is used because of its manufacturing process. Since the entire surface of one end of the semiconductor component is covered with the adhesive, there is a problem that heat generated in the semiconductor component cannot be sufficiently radiated. This is because even if a high thermal conductive paste is used for the adhesive, the thermal conductivity is only 100 to 150 W / m · K, which is a fraction of the thermal conductivity of the metal.
　また、特許文献２に開示されている部品内蔵基板においては、半導体チップの裏面側に対して複数のビア導体が接続されているため、内蔵された半導体チップの放熱を行うことができる。しかしながら、ビアに導体を充填する際に、ビアホールが狭ピッチで配設されていると、当該ビアホールを確実に充填することが困難となり、ビア導体の表面が凹でしまい、部品内蔵基板に要求される放熱性及び電流容量経路を確保することができなくなる。従って、ビア導体を狭ピッチで配設することが困難となり、高い放熱性を備えつつも高い電流容量を確保することが困難になる。 Further, in the component-embedded substrate disclosed in Patent Document 2, since the plurality of via conductors are connected to the back surface side of the semiconductor chip, the built-in semiconductor chip can be dissipated. However, when filling the vias with conductors, if the via holes are arranged at a narrow pitch, it becomes difficult to reliably fill the via holes, and the surface of the via conductors becomes concave, which is required for a component-embedded substrate. Heat dissipation and current capacity path cannot be secured. Therefore, it becomes difficult to arrange the via conductors at a narrow pitch, and it becomes difficult to ensure a high current capacity while providing high heat dissipation.
　本発明はこのような課題に鑑みてなされたものであり、その目的とするところは、比較的に高い放熱性を備えつつも比較的に高い電流容量を確保することができる部品内蔵基板、及びその製造方法を提供することにある。 The present invention has been made in view of such a problem, and an object of the present invention is to provide a component-embedded substrate that can ensure a relatively high current capacity while having a relatively high heat dissipation property, and It is in providing the manufacturing method.
　上記目的を達成するため、本発明の部品内蔵基板は、絶縁樹脂材料を含む絶縁層と、第１表面に第１銅端子、及び前記第１表面とは反対側の第２表面に第２銅端子を備えるとともに、前記絶縁層に埋設されたＩＣ部品と、前記絶縁層の第１表面に形成された第１外層配線パターンと、前記絶縁層の第１表面とは反対側の第２表面に形成された第２外層配線パターンと、前記第１銅端子と前記第１外層配線パターンとを電気的に接続する第１銅接続部と、前記第２銅端子と前記第２外層配線パターンとを電気的に接続する第２銅接続部と、を有し、前記第１銅端子と前記第１銅接続部と接続面は前記第１銅端子の表面形状に沿って位置し、前記第２銅端子と前記第２銅接続部と接続面は前記第２銅端子の表面形状に沿って位置していることである。 In order to achieve the above object, a component-embedded substrate of the present invention includes an insulating layer containing an insulating resin material, a first copper terminal on a first surface, and a second copper on a second surface opposite to the first surface. An IC component embedded in the insulating layer; a first outer layer wiring pattern formed on the first surface of the insulating layer; and a second surface opposite to the first surface of the insulating layer. The formed second outer layer wiring pattern, the first copper terminal and the first outer layer wiring pattern, the first copper connection part for electrically connecting the first copper terminal and the first outer layer wiring pattern, the second copper terminal and the second outer layer wiring pattern A first copper terminal, the first copper connection, and a connection surface located along a surface shape of the first copper terminal, and the second copper connection. The terminal, the second copper connection portion, and the connection surface are located along the surface shape of the second copper terminal. That.
　また、上記目的を達成するため、本発明の部品内蔵基板の製造方法は、第１表面に第１銅端子、及び前記第１表面とは反対側の第２表面に第２銅端子を備えるＩＣ部品を内蔵する部品内蔵基板の製造方法であって、第１銅端子を支持部材に接触させ、前記ＩＣ部品を前記支持部材上に搭載する搭載工程と、前記ＩＣ部品を覆うように絶縁樹脂材料を積層し、前記ＩＣ部品を埋設する絶縁層を形成する絶縁層形成工程と、前記第１銅端子に電気的に接続する第１銅接続部を形成する第１銅接続部形成工程と、前記第２銅端子に電気的に接続する第２銅接続部を形成する第２銅接続部形成工程と、前記第１銅接続部に電気的に接続する第１外層配線パターンを前記絶縁層の第１表面上に形成する第１外層配線パターン形成工程と、前記第２銅接続部に電気的に接続する第２外層配線パターンを前記絶縁層の第２表面上に形成する第２外層配線パターン形成工程と、を有し、前記第１銅接続部形成工程においては、前記第１銅端子と前記第１銅接続部と接続面を前記第１銅端子の表面形状に沿って位置し、前記第２銅接続部形成工程においては、前記第２銅端子と前記第２銅接続部と接続面を前記第２銅端子の表面形状に沿って位置することである。 In order to achieve the above object, a method for manufacturing a component-embedded board according to the present invention includes an IC including a first copper terminal on a first surface and a second copper terminal on a second surface opposite to the first surface. A method of manufacturing a component-embedded substrate that incorporates a component, wherein a first copper terminal is brought into contact with a support member, and a mounting step of mounting the IC component on the support member, and an insulating resin material so as to cover the IC component An insulating layer forming step of forming an insulating layer for embedding the IC component, a first copper connecting portion forming step of forming a first copper connecting portion electrically connected to the first copper terminal, A second copper connecting portion forming step of forming a second copper connecting portion electrically connected to the second copper terminal, and a first outer layer wiring pattern electrically connecting to the first copper connecting portion; A first outer layer wiring pattern forming step formed on one surface, and the second copper contact A second outer layer wiring pattern forming step of forming a second outer layer wiring pattern electrically connected to the portion on the second surface of the insulating layer, and in the first copper connection portion forming step, 1 copper terminal, the 1st copper connection part, and a connection surface are located along the surface shape of the 1st copper terminal, and in the 2nd copper connection part formation process, the 2nd copper terminal and the 2nd copper connection A part and a connection surface are located along the surface shape of the second copper terminal.
　本発明に係る部品内蔵基板においては、比較的に高い放熱性を備えつつも比較的に高い電流容量を確保することができる。また、本発明に係る部品内蔵基板の製造方法においては、比較的に高い放熱性を備えつつも比較的に高い電流容量を確保することができる部品内蔵基板を製造することができる。 In the component-embedded substrate according to the present invention, a relatively high current capacity can be ensured while having a relatively high heat dissipation. Moreover, in the method for manufacturing a component built-in substrate according to the present invention, it is possible to manufacture a component built-in substrate that can ensure a relatively high current capacity while having a relatively high heat dissipation property.
本発明の実施例１に係る部品内蔵基板の製造方法の各製造工程における概略断面図である。It is a schematic sectional drawing in each manufacturing process of the manufacturing method of the component built-in board which concerns on Example 1 of this invention. 本発明の実施例１に係る部品内蔵基板の製造方法の各製造工程における概略断面図である。It is a schematic sectional drawing in each manufacturing process of the manufacturing method of the component built-in board which concerns on Example 1 of this invention. 本発明の実施例１に係る部品内蔵基板の製造方法の各製造工程における概略断面図である。It is a schematic sectional drawing in each manufacturing process of the manufacturing method of the component built-in board which concerns on Example 1 of this invention. 本発明の実施例１に係る部品内蔵基板の製造方法の各製造工程における概略断面図である。It is a schematic sectional drawing in each manufacturing process of the manufacturing method of the component built-in board which concerns on Example 1 of this invention. 本発明の実施例に係る部品内蔵基板におけるＩＣ部品、銅端子、及びビアの位置関係を示す部分拡大平面図である。It is a partial enlarged plan view which shows the positional relationship of IC components, a copper terminal, and a via in the component built-in substrate according to the embodiment of the present invention. 本発明の実施例に係る部品内蔵基板におけるＩＣ部品、銅端子、及びビアの位置関係を示す部分拡大平面図である。It is a partial enlarged plan view which shows the positional relationship of IC components, a copper terminal, and a via in the component built-in substrate according to the embodiment of the present invention. 本発明の実施例１に係る部品内蔵基板の製造方法の各製造工程における概略断面図である。It is a schematic sectional drawing in each manufacturing process of the manufacturing method of the component built-in board which concerns on Example 1 of this invention. 本発明の実施例に係る部品内蔵基板におけるＩＣ部品、銅端子、及び銅接続部の位置関係を示す部分拡大平面図である。It is a partial enlarged plan view which shows the positional relationship of the IC component in the component built-in board | substrate which concerns on the Example of this invention, a copper terminal, and a copper connection part. 本発明の実施例に係る部品内蔵基板におけるＩＣ部品、銅端子、及び銅接続部の位置関係を示す部分拡大平面図である。It is a partial enlarged plan view which shows the positional relationship of the IC component in the component built-in substrate based on the Example of this invention, a copper terminal, and a copper connection part. 本発明の実施例１に係る部品内蔵基板の製造方法の各製造工程における概略断面図である。It is a schematic sectional drawing in each manufacturing process of the manufacturing method of the component built-in board which concerns on Example 1 of this invention. 本発明の実施例１の変形例に係る部品内蔵基板の概略断面図である。It is a schematic sectional drawing of the component built-in board | substrate which concerns on the modification of Example 1 of this invention. 本発明の実施例１の変形例に係る部品内蔵基板におけるＩＣ部品、銅端子、及び銅接続部の位置関係を示す部分拡大平面図である。It is a partial enlarged plan view which shows the positional relationship of the IC component in the component built-in board | substrate which concerns on the modification of Example 1 of this invention, a copper terminal, and a copper connection part. 本発明の実施例２に係る部品内蔵基板の製造方法の各製造工程における概略断面図である。It is a schematic sectional drawing in each manufacturing process of the manufacturing method of the component built-in board which concerns on Example 2 of this invention. 本発明の実施例２に係る部品内蔵基板の製造方法の各製造工程における概略断面図である。It is a schematic sectional drawing in each manufacturing process of the manufacturing method of the component built-in board which concerns on Example 2 of this invention. 本発明の実施例２に係る部品内蔵基板の製造方法の各製造工程における概略断面図である。It is a schematic sectional drawing in each manufacturing process of the manufacturing method of the component built-in board which concerns on Example 2 of this invention. 本発明の実施例２に係る部品内蔵基板の製造方法の各製造工程における概略断面図である。It is a schematic sectional drawing in each manufacturing process of the manufacturing method of the component built-in board which concerns on Example 2 of this invention. 本発明の実施例２に係る部品内蔵基板の製造方法の各製造工程における概略断面図である。It is a schematic sectional drawing in each manufacturing process of the manufacturing method of the component built-in board which concerns on Example 2 of this invention. 本発明の実施例２に係る部品内蔵基板の製造方法の各製造工程における概略断面図である。It is a schematic sectional drawing in each manufacturing process of the manufacturing method of the component built-in board which concerns on Example 2 of this invention.
　以下、図面を参照し、本発明の実施の形態について、各実施例に基づき詳細に説明する。なお、本発明は以下に説明する内容に限定されるものではなく、その要旨を変更しない範囲において任意に変更して実施することが可能である。また、各実施例の説明に用いる図面は、いずれも本発明による部品内蔵基板及びその構成部材を模式的に示すものであって、理解を深めるべく部分的な強調、拡大、縮小、または省略などを行っており、部品内蔵基板及びその構成部材の縮尺や形状等を正確に表すものとはなっていない場合がある。更に、各実施例で用いる様々な数値は、いずれも一例を示すものであり、必要に応じて様々に変更することが可能である。 Hereinafter, embodiments of the present invention will be described in detail based on each example with reference to the drawings. In addition, this invention is not limited to the content demonstrated below, In the range which does not change the summary, it can change arbitrarily and can implement. The drawings used for explaining each embodiment schematically show the component-embedded substrate and its constituent members according to the present invention, and are partly emphasized, enlarged, reduced, omitted, etc. for better understanding. In some cases, the scale does not accurately represent the scale and shape of the component-embedded substrate and its constituent members. Furthermore, the various numerical values used in each embodiment are merely examples, and can be variously changed as necessary.
＜実施例１＞
　以下において、本発明の実施例１に係る部品内蔵基板の製造方法及び完成した部品内蔵基板について、図１乃至図８を参照して詳細に説明する。ここで、図１乃至図４、図７及び図１０は、本実施例１に係る部品内蔵基板の製造方法の各製造工程における概略断面図である。また、図５及び図６は、内蔵されたＩＣ部品の各端子を平面視した場合におけるＩＣ部品、銅端子、及びビアの位置関係を示す部分拡大平面図であり、図５が第１銅端子側（図４における下側）の部分拡大平面図、図６が第２銅端子側（図４における上側）の部分拡大平面図を示す。更に、図８及び図９は、内蔵されたＩＣ部品の各端子を平面視した場合におけるＩＣ部品、銅端子、及び銅接続部の位置関係を示す部分拡大平面図であり、図８が第１銅端子側（図７における下側）の部分拡大平面図、図９が第２銅端子側（図７における上側）の部分拡大平面図を示す。 <Example 1>
Hereinafter, a method for manufacturing a component-embedded substrate and a completed component-embedded substrate according to Embodiment 1 of the present invention will be described in detail with reference to FIGS. Here, FIG. 1 to FIG. 4, FIG. 7 and FIG. 10 are schematic cross-sectional views in each manufacturing process of the method for manufacturing the component-embedded substrate according to the first embodiment. 5 and 6 are partially enlarged plan views showing the positional relationship between the IC component, the copper terminal, and the via when each terminal of the built-in IC component is viewed in plan, and FIG. 5 is the first copper terminal. FIG. 6 is a partially enlarged plan view of the second copper terminal (upper side in FIG. 4). 8 and 9 are partially enlarged plan views showing the positional relationship between the IC component, the copper terminal, and the copper connection portion when each terminal of the built-in IC component is viewed in plan. FIG. FIG. 9 shows a partially enlarged plan view on the copper terminal side (lower side in FIG. 7), and FIG. 9 shows a partially enlarged plan view on the second copper terminal side (upper side in FIG. 7).
　先ず、支持板１上に絶縁性の接着剤２が塗布された支持部材３を準備するとともに、内蔵される電子・電気部品であるＩＣ部品４も準備する（準備工程）。ここで、支持板１としては、プロセス条件にて必要とされる程度の剛性を有するものが用いられる。本実施例１において、支持板１には剛性のあるＳＵＳ（ステンレス）板又はアルミ板等の金属板の表面に銅箔（導電材）を貼り付けたものを用いたが、その他の導電性を備える部材を用いてもよい。また、接着剤２には、例えば一般的なエポキシ接着剤を用いてもよく、ディスペンサーや印刷等によって塗布してもよい。 First, a support member 3 in which an insulating adhesive 2 is applied on a support plate 1 is prepared, and an IC component 4 which is a built-in electronic / electrical component is also prepared (preparation process). Here, as the support plate 1, a support plate having a degree of rigidity required under process conditions is used. In the first embodiment, the support plate 1 is made of a metal plate such as a rigid SUS (stainless steel) plate or an aluminum plate with a copper foil (conductive material) attached thereto. A member provided may be used. The adhesive 2 may be a general epoxy adhesive, for example, or may be applied by a dispenser or printing.
　更に、ＩＣ部品４は、一般的なＭＯＳＦＥＴであり、その第１表面４ａ側に銅からなる１つの第１銅端子４ｂが配設され、その第２表面４ｃ側に銅からなる３つの第２銅端子４ｄが配設されている。特に、本実施例１においては、第１銅端子４ｂがＩＣ部品４のドレイン端子として機能し、ＩＣ部品４の第１表面４ａの全面に配設されている。一方、第２銅端子４ｄは、ＩＣ部品４のソース端子又はゲート端子として機能し、ＩＣ部品４の第２表面４ｃに対して部分的に配設されている（すなわち、第２表面４ｃは部分的に露出している）。なお、第１銅端子４ｂ及び第２銅端子４ｄの数量は限定されず、部品内蔵基板に要求される電気的特性（すなわち、埋設されるＩＣ部品４の種類）に応じて適宜変更される。 Further, the IC component 4 is a general MOSFET, and one first copper terminal 4b made of copper is disposed on the first surface 4a side, and three second copper electrodes are made on the second surface 4c side. A copper terminal 4d is provided. In particular, in the first embodiment, the first copper terminal 4 b functions as the drain terminal of the IC component 4 and is disposed on the entire first surface 4 a of the IC component 4. On the other hand, the second copper terminal 4d functions as a source terminal or a gate terminal of the IC component 4, and is partially disposed with respect to the second surface 4c of the IC component 4 (that is, the second surface 4c is a partial portion). Exposed). The number of the first copper terminals 4b and the second copper terminals 4d is not limited, and can be changed as appropriate according to the electrical characteristics required for the component-embedded substrate (that is, the type of the embedded IC component 4).
　次に、図１に示すように、ＩＣ部品４を接着剤２上に搭載する搭載工程が行われる。より具体的には、吸引ノズルを備える表面実装機（チップマウンタ）を用い、支持部材３を構成する接着剤２に対して、ＩＣ部品４の第１表面４ａ側に配設された第１銅端子４ｂが接触するように当該搭載工程を行う。すなわち、第１銅端子４ｂが接着剤２に近接する位置に配置され、第２銅端子４ｄが接着剤２から離間する位置に配置されることになる。 Next, as shown in FIG. 1, a mounting process for mounting the IC component 4 on the adhesive 2 is performed. More specifically, the first copper disposed on the first surface 4a side of the IC component 4 with respect to the adhesive 2 constituting the support member 3 using a surface mounter (chip mounter) having a suction nozzle. The mounting process is performed so that the terminals 4b come into contact with each other. That is, the first copper terminal 4 b is disposed at a position close to the adhesive 2, and the second copper terminal 4 d is disposed at a position away from the adhesive 2.
　次に、図２及び図３に示すように、ＩＣ部品４を埋設する絶縁層５を形成する絶縁層形成工程を行う。より具体的には、ＩＣ部品４が搭載された支持部材３上に、プリプレグ６、配線パターン付樹脂体７、プリプレグ８、挟持板（支持板）９をレイアップし、これを真空下で加熱しながらプレスする。このプレスは、例えば真空加圧式のプレス機を用いて行われる。ここで、配線パターン付樹脂体７は、絶縁樹脂材料からなる樹脂基体７ａ、及び樹脂基体７ａの表裏面に形成された配線パターン７ｂから構成されている。そして、配線パターン７ｂは、貫通孔７ｃによって露出した側面７ｄを被覆するようにも形成され、樹脂基体７ａの表面側に形成された配線パターン７ｂと、樹脂基体７ａの裏面側に形成された配線パターン７ｂとが電気的に接続されている。また、挟持板９には、支持板１と同様に剛性のあるＳＵＳ（ステンレス）またはアルミ等からなる金属箔に銅箔（導電材）を張り付けたもの、または銅箔が用いられる。更に、プリプレグ６及び樹脂基体７ａには、ＩＣ部品４を挿入することができる貫通孔があらかじめ形成されており、ＩＣ部品４が当該貫通孔に挿入されるように当該レイアップが行われる。 Next, as shown in FIGS. 2 and 3, an insulating layer forming step for forming an insulating layer 5 in which the IC component 4 is embedded is performed. More specifically, a prepreg 6, a resin body 7 with a wiring pattern, a prepreg 8, and a sandwiching plate (support plate) 9 are laid up on the support member 3 on which the IC component 4 is mounted, and this is heated under vacuum. While pressing. This press is performed using, for example, a vacuum press machine. Here, the resin body 7 with a wiring pattern includes a resin substrate 7a made of an insulating resin material, and a wiring pattern 7b formed on the front and back surfaces of the resin substrate 7a. The wiring pattern 7b is also formed so as to cover the side surface 7d exposed by the through hole 7c, and the wiring pattern 7b formed on the front side of the resin base 7a and the wiring formed on the back side of the resin base 7a. The pattern 7b is electrically connected. In addition, the sandwiching plate 9 is made of a metal foil made of SUS (stainless steel), aluminum, or the like, which is rigid, like the support plate 1, or a copper foil. Furthermore, the prepreg 6 and the resin base 7a are previously formed with a through hole into which the IC component 4 can be inserted, and the layup is performed so that the IC component 4 is inserted into the through hole.
　上記の真空下における加熱及びプレス処理により、図３に示すように、プリプレグ６、樹脂基体７ａ、プリプレグ８が一体化され、ＩＣ部品４を埋設する絶縁層５が形成されることになる。また、当該絶縁層５によってＩＣ部品４が埋設されると同時に、配線パターン７ｂも絶縁層５内に埋設され、部品内蔵基板の内部配線パターンが形成されることになる。なお、上記の真空下における加熱及びプレス処理により、配線パターン付樹脂体７の貫通孔７ｃはプリプレグ６、８を構成する絶縁樹脂材料によって充填されることになる。 As shown in FIG. 3, the prepreg 6, the resin base 7 a, and the prepreg 8 are integrated and the insulating layer 5 in which the IC component 4 is embedded is formed by heating and pressing in the vacuum described above. Further, at the same time that the IC component 4 is embedded by the insulating layer 5, the wiring pattern 7 b is also embedded in the insulating layer 5, and the internal wiring pattern of the component built-in substrate is formed. In addition, the through-hole 7c of the resin body 7 with a wiring pattern is filled with the insulating resin material which comprises the prepregs 6 and 8 by the heating and press process in said vacuum.
　次に、図４に示すように、支持板１及び接着剤２を貫通しＩＣ部品４の第１銅端子４ｂに到達する第１ビア１１、支持板１及び絶縁層５（プリプレグ６からなる部分）を貫通して配線パターン７ｂに到達する第２ビア１２、挟持板９及び絶縁層５（プリプレグ８からなる部分）を貫通しＩＣ部品４の第２銅端子４ｄに到達する第３ビア１３、挟持板９及び絶縁層５（プリプレグ８からなる部分）を貫通して配線パターン７ｂに到達する第４ビア１４を形成する。各ビアの形成方法としては、例えばＣＯ２レーザをビア形成箇所に照射することにより、ＣＯ２レーザの照射部分の部材が除去され、所望の形状のビアが形成されてもよい。なお、ＣＯ２レーザに限られることがなく、例えば、ＵＶ－ＹＡＧやエキシマ等の高周波レーザを用いてもよい。また、プラズマエッチング又はケミカルエッチングによって各ビアを形成してもよい。なお、ＣＯ２レーザの照射前に、支持板１及び挟持板９を除去してもよい。 Next, as shown in FIG. 4, the first via 11, the support plate 1 and the insulating layer 5 (part consisting of the prepreg 6) that penetrates the support plate 1 and the adhesive 2 and reaches the first copper terminal 4 b of the IC component 4. ) Through the second via 12 that reaches the wiring pattern 7b, the third via 13 that reaches the second copper terminal 4d of the IC component 4 through the sandwiching plate 9 and the insulating layer 5 (part consisting of the prepreg 8), A fourth via 14 is formed so as to penetrate the sandwiching plate 9 and the insulating layer 5 (part consisting of the prepreg 8) and reach the wiring pattern 7b. As a method for forming each via, for example, by irradiating a CO 2 laser to a via forming portion, a member at a CO 2 laser irradiated portion may be removed, and a via having a desired shape may be formed. Note that the present invention is not limited to the CO 2 laser, and for example, a high frequency laser such as UV-YAG or excimer may be used. Further, each via may be formed by plasma etching or chemical etching. Note that the support plate 1 and the holding plate 9 may be removed before the CO 2 laser irradiation.
　また、図５に示すように、第１ビア１１は第１銅端子４ｂの平面形状に沿って配設され、第１ビア１１の開口寸法は第１銅端子４ｂの平面寸法よりも若干小さくなっている。すなわち、第１ビア１１の開口形状は第１銅端子４ｂの平面形状に相似し、第１ビア１１によって第１銅端子４ｂの大部分が露出することになる。例えば、第１ビア１１は、第１銅端子４ｂの主表面（すなわち、ＩＣ部品４側とは反対側に位置する表面）の面積の約５０％以上を露出することが好ましく、より好ましくは８０％以上、特に好ましくは９０％以上となる。 Further, as shown in FIG. 5, the first via 11 is disposed along the planar shape of the first copper terminal 4b, and the opening dimension of the first via 11 is slightly smaller than the planar dimension of the first copper terminal 4b. ing. That is, the opening shape of the first via 11 is similar to the planar shape of the first copper terminal 4 b, and most of the first copper terminal 4 b is exposed by the first via 11. For example, the first via 11 preferably exposes about 50% or more of the area of the main surface of the first copper terminal 4b (that is, the surface located on the side opposite to the IC component 4 side), more preferably 80%. % Or more, particularly preferably 90% or more.
　更に、図６に示すように、第３ビア１３のそれぞれは、各ビアが到達する第２銅端子４ｄのそれぞれの平面形状に沿って配設され、第３ビア１３のそれぞれの開口寸法は第２銅端子４ｄのそれぞれの平面寸法よりも若干小さくなっている。すなわち、第３ビア１３のそれぞれの開口形状は、各ビアが到達する第２銅端子４ｄの平面形状に相似し、第３ビア１３によって第２銅端子４ｄの大部分が露出することになる。そして、第１ビア１１の場合と同様に、各第３ビア１３は、第２銅端子４ｄの主表面（すなわち、ＩＣ部品４側とは反対側に位置する表面）の面積の約５０％以上を露出することが好ましく、より好ましくは８０％以上、特に好ましくは９０％以上となる。 Further, as shown in FIG. 6, each of the third vias 13 is disposed along the planar shape of each of the second copper terminals 4 d to which each via reaches, and each opening dimension of the third via 13 is the first dimension. It is slightly smaller than the respective plane dimensions of the two copper terminals 4d. That is, each opening shape of the third via 13 is similar to the planar shape of the second copper terminal 4d to which each via reaches, and most of the second copper terminal 4d is exposed by the third via 13. As in the case of the first via 11, each third via 13 is about 50% or more of the area of the main surface of the second copper terminal 4 d (that is, the surface located on the side opposite to the IC component 4 side). Is preferably exposed, more preferably 80% or more, and particularly preferably 90% or more.
　このように第１ビア１１及び第３ビア１３の形状及び寸法を調整する理由は、第１ビア１１及び第３ビア１３を充填することになる導通ビアの平面状の寸法を、ＩＣ部品４の各銅端子の平面状の寸法と同等程度に確保するためである。なお、当該導通ビアをできる限り大きくする理由については後述するものとする。 The reason for adjusting the shapes and dimensions of the first via 11 and the third via 13 in this way is that the planar dimensions of the conductive via that fills the first via 11 and the third via 13 are the same as those of the IC component 4. This is to ensure the same level as the planar dimensions of each copper terminal. The reason why the conductive via is made as large as possible will be described later.
　各ビアが形成された後、デスミア処理を施し、ビア形成の際に残留している樹脂を除去することが好ましい。また、第１銅端子４ｂ及び第２銅端子４ｄには更にソフトエッチング処理を施し、ビア形成によって露出した第１銅端子４ｂ及び第２銅端子４ｄの露出面の酸化物や有機物を除去することが好ましい。これにより、新鮮な銅の表面が露出することになり、その後のめっき処理において析出する銅との密着性が高まり、結果として電気的な接続信頼性が向上する。 It is preferable that after each via is formed, a desmear process is performed to remove the resin remaining in the via formation. Further, the first copper terminal 4b and the second copper terminal 4d are further subjected to a soft etching process to remove oxides and organic substances on the exposed surfaces of the first copper terminal 4b and the second copper terminal 4d exposed by the via formation. Is preferred. Thereby, the surface of fresh copper will be exposed, adhesiveness with the copper which precipitates in subsequent plating processing will increase, and electrical connection reliability will improve as a result.
　次に、図７に示すように、各ビア内に銅を充填し、銅からなる第１導通ビア（第１銅接続部）１５、第２導通ビア１６、第３導通ビア（第２銅接続部）１７、及び第４導通ビア１８を形成する。より具体的には、先ず支持板１及び挟持板９を除去し、その後に必要に応じて各ビアにデスミアやハーフエッチング処理を施し、続いて化学銅めっきや電気銅めっき等のめっき処理を施すことにより、各ビア内に銅を析出させ、当該銅によって各ビアが充填されたフィルドビアである第１導通ビア１５、第２導通ビア１６、第３導通ビア１７、及び第４導通ビア１８が形成されることになる。ここで、第１導通ビア１５が第１ビア１１を充填して第１銅端子４ｂに到達し、第２導通ビア１６が第２ビア１２を充填して配線パターン７ｂに到達し、第３導通ビア１７が第３ビア１３を充填して第２銅端子４ｄに到達し、第４導通ビア１８が第４ビア１４を充填して配線パターン７ｂに到達している。また、当該銅の析出により、絶縁層５を構成するプリプレグ６側の表面に第１銅配線層２１が形成されるとともに、絶縁層５を構成するプリプレグ８側の表面に第２銅配線層２２が形成される。 Next, as shown in FIG. 7, each via is filled with copper, and a first conductive via (first copper connection portion) 15, a second conductive via 16, and a third conductive via (second copper connection) made of copper. Part) 17 and the fourth conductive via 18 are formed. More specifically, first, the support plate 1 and the sandwiching plate 9 are removed, and then desmearing and half-etching treatment is performed on each via as necessary, followed by plating treatment such as chemical copper plating and electrolytic copper plating. As a result, copper is deposited in each via, and the first conductive via 15, the second conductive via 16, the third conductive via 17, and the fourth conductive via 18, which are filled vias filled with the copper, are formed. Will be. Here, the first conductive via 15 fills the first via 11 and reaches the first copper terminal 4b, the second conductive via 16 fills the second via 12 and reaches the wiring pattern 7b, and the third conductive The via 17 fills the third via 13 and reaches the second copper terminal 4d, and the fourth conductive via 18 fills the fourth via 14 and reaches the wiring pattern 7b. Further, due to the deposition of the copper, the first copper wiring layer 21 is formed on the surface of the prepreg 6 constituting the insulating layer 5, and the second copper wiring layer 22 is formed on the surface of the prepreg 8 constituting the insulating layer 5. Is formed.
　また、第１導通ビア１５は第１ビア１１を充填することから、図８に示すように、第１導通ビア１５は第１銅端子４ｂの平面形状に沿って配設され、第１導通ビア１５の平面寸法は第１銅端子４ｂの平面寸法よりも若干小さくなっている。すなわち、第１導通ビア１５の平面寸法は第１銅端子４ｂの平面形状に相似していることになる。これらのことを換言すると、第１銅端子４ｂと第１導通ビア１５との接続面は、第１銅端子４ｂの平面形状に沿って位置することになる。そして、第１ビア１１による第１銅端子４ｂの露出割合を上述したように調整することにより、第１銅端子４ｂに対する第１導通ビア１５の被覆率は、約５０％以上となり、より好ましくは８０％以上、特に好ましくは９０％以上となる。 Since the first conductive via 15 fills the first via 11, as shown in FIG. 8, the first conductive via 15 is disposed along the planar shape of the first copper terminal 4b, and the first conductive via 15 is provided. The planar dimension of 15 is slightly smaller than the planar dimension of the first copper terminal 4b. That is, the planar dimension of the first conductive via 15 is similar to the planar shape of the first copper terminal 4b. In other words, the connection surface between the first copper terminal 4b and the first conductive via 15 is positioned along the planar shape of the first copper terminal 4b. Then, by adjusting the exposure ratio of the first copper terminal 4b by the first via 11 as described above, the coverage of the first conductive via 15 with respect to the first copper terminal 4b is about 50% or more, more preferably. 80% or more, particularly preferably 90% or more.
　更に、第３導通ビア１７は第３ビア１３を充填することから、図９に示すように、第３導通ビア１７のそれぞれは、接続する第２銅端子４ｄのそれぞれの平面形状に沿って配設されている。そして、第３導通ビア１７のそれぞれの平面寸法は、接続する第２銅端子４ｄのそれぞれの平面寸法よりも若干小さくなっている。すなわち、第３導通ビア１７のそれぞれの平面寸法は、接続する第２銅端子４ｄのそれぞれの平面形状に相似していることになる。これらのことを換言すると、第２銅端子４ｄと第３導通ビア１７との接続面は、第２銅端子４ｄの平面形状に沿って位置することになる。そして、第３ビア１３による第２銅端子４ｄの露出割合を上述したように調整することにより、第２銅端子４ｄに対する第３導通ビア１７の被覆率は、約５０％以上となり、より好ましくは８０％以上、特に好ましくは９０％以上となる。 Further, since the third conductive via 17 fills the third via 13, as shown in FIG. 9, each of the third conductive vias 17 is arranged along each planar shape of the second copper terminal 4d to be connected. It is installed. Each planar dimension of the third conductive via 17 is slightly smaller than each planar dimension of the second copper terminal 4d to be connected. That is, the planar dimensions of the third conductive vias 17 are similar to the planar shapes of the second copper terminals 4d to be connected. In other words, the connection surface between the second copper terminal 4d and the third conductive via 17 is located along the planar shape of the second copper terminal 4d. Then, by adjusting the exposure ratio of the second copper terminal 4d by the third via 13 as described above, the coverage of the third conductive via 17 with respect to the second copper terminal 4d becomes about 50% or more, more preferably. 80% or more, particularly preferably 90% or more.
　このようにＩＣ部品４の各端子に接続される導通ビアの寸法及び形状を調整して大型化することより、ＩＣ部品４にて生じる熱を効率よく放熱することができ、ＩＣ部品４の劣化及び部品内蔵基板自体の信頼性を向上することができる。また、当該放熱性の向上により、ＩＣ部品４のオン抵抗の低下を図ることが可能になる。更に、当該導通ビアの大型化により、より高い電流容量を確保することができ、許容電流値において優位な特性を備える部品内蔵基板を実現することができる。 Thus, by adjusting the size and shape of the conductive via connected to each terminal of the IC component 4 and increasing the size, the heat generated in the IC component 4 can be efficiently radiated, and the IC component 4 is deteriorated. In addition, the reliability of the component-embedded substrate itself can be improved. In addition, the on-resistance of the IC component 4 can be reduced by improving the heat dissipation. Furthermore, by increasing the size of the conductive via, a higher current capacity can be ensured, and a component-embedded substrate having characteristics superior in the allowable current value can be realized.
　そして、上述したビアの形成工程及び導通ビアの形成工程を経ることにより、第１銅端子４ｂに電気的に接続する第１銅接続部（第１導通ビア１５）の形成工程（すなわち、第１銅接続部形成工程）、及び第２銅端子４ｄに電気的に接続する第２銅接続部（第３導通ビア１７）の形成工程（すなわち、第２銅接続部形成工程）が完了する。 Then, through the above-described via formation step and conductive via formation step, the first copper connection portion (first conductive via 15) forming step (that is, the first conductive via 15) electrically connected to the first copper terminal 4b (ie, the first step). The copper connection portion forming step) and the formation step of the second copper connection portion (third conductive via 17) electrically connected to the second copper terminal 4d (ie, the second copper connection portion forming step) are completed.
　次に、図１０に示すように、絶縁層５の第１表面５ａに位置する第１銅配線層２１にパターニングを施して第１外層配線パターン２３を形成し（第１外層配線パターン形成工程）、絶縁層５の第２表面５ｂに位置する第２銅配線層２２にパターニングを施して第２外層配線パターン２４を形成する（第２外層配線パターン形成工程）。例えば、公知のフォトリソグラフィ技術を用いて、第１銅配線層２１及び第２銅配線層２２にエッチング処理を施して、第１外層配線パターン２３及び第２外層配線パターン２４を形成する。 Next, as shown in FIG. 10, the first outer layer wiring pattern 23 is formed by patterning the first copper wiring layer 21 located on the first surface 5a of the insulating layer 5 (first outer layer wiring pattern forming step). Then, the second copper wiring layer 22 located on the second surface 5b of the insulating layer 5 is patterned to form the second outer layer wiring pattern 24 (second outer layer wiring pattern forming step). For example, the first outer wiring pattern 23 and the second outer wiring pattern 24 are formed by etching the first copper wiring layer 21 and the second copper wiring layer 22 using a known photolithography technique.
　以上のような製造工程を経て、図１０に示すような部品内蔵基板３０の形成が完了する。なお、実際の部品内蔵基板３０の製造においては、複数の部品内蔵基板３０が１枚の基板として製造され、複数の部品内蔵基板３０の形成完了後に当該１枚の基板を切断し、最終的に複数の部品内蔵基板３０を同時に製造することになる。 Through the manufacturing process as described above, the formation of the component-embedded substrate 30 as shown in FIG. 10 is completed. In the actual production of the component-embedded substrate 30, the plurality of component-embedded substrates 30 are manufactured as one substrate, and after the formation of the plurality of component-embedded substrates 30, the one substrate is cut and finally A plurality of component-embedded substrates 30 are manufactured simultaneously.
　図１０に示すように、本実施例１に係る部品内蔵基板３０は、絶縁樹脂材料を含む絶縁層５、絶縁層５に埋設されたＩＣ部品４、絶縁層５の第１表面５ａに形成された第１外層配線パターン２３、絶縁層５の第２表面５ｂに形成された第２外層配線パターン２４、ＩＣ部品４の第１銅端子４ｂと第１外層配線パターン２３とを電気的に接続する第１導通ビア１５、及びＩＣ部品４の第２銅端子４ｄと第２外層配線パターン２４とを電気的に接続する第３導通ビア１７を有している。特に、第１導通ビア１５及び第３導通ビア１７のいずれもが、接続するＩＣ部品４の銅端子の表面形状に沿って位置するとともに、当該銅端子と同等（若干小さい）の平面寸法を有しているため、ＩＣ部品４にて生じる熱を良好に放熱するとともに、比較的に高い電流容量を確保することができる。 As shown in FIG. 10, the component-embedded substrate 30 according to the first embodiment is formed on the insulating layer 5 containing an insulating resin material, the IC component 4 embedded in the insulating layer 5, and the first surface 5a of the insulating layer 5. The first outer layer wiring pattern 23, the second outer layer wiring pattern 24 formed on the second surface 5b of the insulating layer 5, and the first copper terminal 4b of the IC component 4 and the first outer layer wiring pattern 23 are electrically connected. The first conductive via 15 and the third conductive via 17 that electrically connects the second copper terminal 4 d of the IC component 4 and the second outer layer wiring pattern 24 are provided. In particular, each of the first conductive via 15 and the third conductive via 17 is located along the surface shape of the copper terminal of the IC component 4 to be connected, and has a planar dimension equivalent to (slightly smaller than) the copper terminal. Therefore, the heat generated in the IC component 4 can be radiated well and a relatively high current capacity can be secured.
　より詳細に、本実施例１に係る部品内蔵基板３０においては、熱伝導性の比較的に低い導電性接着剤又は半田を使用することなく、銅からなる導通ビアを介して熱を放熱できる構造が採用されているため、上記のように放熱性を向上することができる。また、比較的に小さい複数の導通ビアを設けることなく、ＩＣ部品４の各銅端子に対応した比較的に大きな導通ビアを形成するため、更なる放熱性の向上及びより高い電流容量の確保が実現されることになる。 More specifically, in the component-embedded substrate 30 according to the first embodiment, a structure that can dissipate heat through a conductive via made of copper without using a conductive adhesive or solder having a relatively low thermal conductivity. Therefore, heat dissipation can be improved as described above. In addition, since a relatively large conductive via corresponding to each copper terminal of the IC component 4 is formed without providing a plurality of relatively small conductive vias, it is possible to further improve heat dissipation and secure a higher current capacity. Will be realized.
　また、本実施例１に係る部品内蔵基板３０においては、第２銅端子４ｄがドレイン端子であり、且つＩＣ部品４の第１表面４ａの全面に形成されており、更には第１導通ビア１５がＩＣ部品４の第１表面４ａと同等の平面寸法を備えている。このような構造により、部品内蔵基板３０における放熱性がより向上されることになり、より高い電流容量の確保を容易に行えることになる。 In the component-embedded substrate 30 according to the first embodiment, the second copper terminal 4d is a drain terminal and is formed on the entire first surface 4a of the IC component 4, and the first conductive via 15 is further formed. Has a planar dimension equivalent to that of the first surface 4 a of the IC component 4. With such a structure, the heat dissipation in the component-embedded substrate 30 is further improved, and a higher current capacity can be easily secured.
　なお、上記実施例１においては、ソース端子又はゲート端子となる第２銅端子４ｄは、第２表面４ｃに対して比較的に小さい寸法（端子面積）を有していたが、例えば、図１１及び図１２に示すような、異なるＩＣ部品４’に対しても、本発明に係る導通ビアを形成することができる。図１１及び図１２に示されている部品内蔵基板３０’を実施例１に係る変形例として以下に説明する。ここで、図１１は、変形例に係る部品内蔵基板３０’の概略断面図であり、図１２は、変形例に係る部品内蔵基板３０’におけるＩＣ部品４’、各銅端子、及び各導通ビアの位置関係を示す部分拡大平面図である。なお、上記実施例１と同一の構造については、同一の符号を付し、その説明を省略する。 In the first embodiment, the second copper terminal 4d serving as the source terminal or the gate terminal has a relatively small dimension (terminal area) with respect to the second surface 4c. For example, FIG. And the conductive via according to the present invention can be formed for different IC components 4 'as shown in FIG. The component-embedded substrate 30 ′ shown in FIGS. 11 and 12 will be described below as a modified example according to the first embodiment. Here, FIG. 11 is a schematic cross-sectional view of a component-embedded substrate 30 ′ according to a modified example, and FIG. 12 shows an IC component 4 ′, each copper terminal, and each conductive via in the component-embedded substrate 30 ′ according to the modified example. It is the elements on larger scale which show the positional relationship of these. In addition, about the structure same as the said Example 1, the same code | symbol is attached | subjected and the description is abbreviate | omitted.
　図１１及び図１２に示すように、部品内蔵基板３０’は、絶縁樹脂材料を含む絶縁層５、絶縁層５に埋設されたＩＣ部品４’、絶縁層５の第１表面５ａに形成された第１外層配線パターン２３、絶縁層５の第２表面５ｂに形成された第２外層配線パターン２４、ＩＣ部品４’の第１銅端子４ｂ’と第１外層配線パターン２３とを電気的に接続する第１導通ビア１５’、及びＩＣ部品４’の第２銅端子４ｄ’と第２外層配線パターン２４とを電気的に接続する第３導通ビア１７’を有している。本変形例においては、２つの第１銅端子４ｂ’の一方がソース端子として機能し、他方がゲート端子として機能し、第２銅端子４ｄ’がドレイン端子として機能する。すなわち、本変形例においては、上記実施例１と比較して、ＩＣ部品４’の向きが逆になりつつ、第１銅端子４ｂ’及び第２銅端子４ｄ’の数量及び形状が異なっている。 As shown in FIGS. 11 and 12, the component-embedded substrate 30 ′ is formed on the insulating layer 5 containing an insulating resin material, the IC component 4 ′ embedded in the insulating layer 5, and the first surface 5 a of the insulating layer 5. The first outer layer wiring pattern 23, the second outer layer wiring pattern 24 formed on the second surface 5b of the insulating layer 5, the first copper terminal 4b 'of the IC component 4' and the first outer layer wiring pattern 23 are electrically connected. And a third conductive via 17 ′ for electrically connecting the second copper terminal 4 d ′ of the IC component 4 ′ and the second outer layer wiring pattern 24. In this modification, one of the two first copper terminals 4b 'functions as a source terminal, the other functions as a gate terminal, and the second copper terminal 4d' functions as a drain terminal. That is, in the present modified example, the number and shape of the first copper terminal 4b ′ and the second copper terminal 4d ′ are different while the direction of the IC component 4 ′ is reversed as compared with the first embodiment. .
　本変形例の場合であっても、図１２に示すように、第１導通ビア１５’のそれぞれが、接続するＩＣ部品４’の第１銅端子４ｂ’（ソース端子又はドレイン端子）の表面形状に沿って位置するとともに、第１銅端子４ｂ’のそれぞれと同等（若干小さい）の平面寸法を有している。また、図示しないものの、上記実施例の第１導通ビア１５と同様に、第３導通ビア１７’は、接続するＩＣ部品４’の第２銅端子４ｄ’（ゲート端子）の表面形状に沿って位置するとともに、第２銅端子４ｄ’のそれぞれと同等（若干小さい）の平面寸法を有している。従って、本変形例においても、ＩＣ部品４’にて生じる熱を良好に放熱するとともに、比較的に高い電流容量を確保することができる。 Even in the case of this modification, as shown in FIG. 12, each of the first conductive vias 15 ′ has a surface shape of the first copper terminal 4b ′ (source terminal or drain terminal) of the IC component 4 ′ to be connected. And has a planar dimension equivalent to (slightly smaller than) each of the first copper terminals 4b ′. In addition, although not shown, like the first conductive via 15 in the above embodiment, the third conductive via 17 ′ follows the surface shape of the second copper terminal 4 d ′ (gate terminal) of the IC component 4 ′ to be connected. And has a planar dimension equivalent to (slightly smaller than) each of the second copper terminals 4d ′. Therefore, also in this modification, the heat generated in the IC component 4 ′ can be radiated well and a relatively high current capacity can be secured.
　なお、上述した実施例１及び変形例においては、ＩＣ部品４の１つの銅端子に対して単一の銅接続部が接続されていたが、上述した銅接続部の被覆率を満たすことができれば、１つの銅端子に対して複数の銅接続部を接続してもよい。すなわち、複数の銅接続部材から銅接続部形成してもよい。また、部品内蔵基板３０に埋め込まれるＩＣ部品４の数量は１つに限定されることなく、複数であってもよい。 In the first embodiment and the modification described above, a single copper connection portion is connected to one copper terminal of the IC component 4. However, if the coverage of the copper connection portion described above can be satisfied. You may connect a some copper connection part with respect to one copper terminal. That is, you may form a copper connection part from several copper connection members. Further, the number of IC components 4 embedded in the component-embedded substrate 30 is not limited to one and may be plural.
＜実施例２＞
　以下において、実施例１とは異なる製造方法にて本発明に係る部品内蔵基板を製造すること、及び製造される部品内蔵基板について、図１３乃至図１８を参照しつつ実施例２として説明する。ここで、図１３乃至図１８は、本実施例２に係る部品内蔵基板の製造方法の各製造工程における概略断面図である。 <Example 2>
In the following, a component-embedded substrate according to the present invention is manufactured by a manufacturing method different from that of Embodiment 1, and the manufactured component-embedded substrate will be described as Embodiment 2 with reference to FIGS. 13 to 18. Here, FIGS. 13 to 18 are schematic cross-sectional views in each manufacturing process of the method for manufacturing the component-embedded substrate according to the second embodiment.
　先ず、絶縁性の接着シートである支持部材１０３を準備するとともに、内蔵される電子・電気部品であるＩＣ部品１０４も準備する（準備工程）。支持部材１０３は、一般的な接着シートであり、後述する工程においてＩＣ部品１０４、銅、絶縁樹脂材料から容易に剥離することができるものを使用する。 First, a support member 103 that is an insulating adhesive sheet is prepared, and an IC component 104 that is a built-in electronic / electrical component is also prepared (preparation step). The support member 103 is a general adhesive sheet, and one that can be easily peeled off from the IC component 104, copper, and insulating resin material in a process described later.
　更に、ＩＣ部品１０４は、その第１表面１０４ａ側に銅からなる１つの第１銅端子１０４ｂが配設され、その第２表面１０４ｃ側に銅からなる２つの第２銅端子１０４ｄが配設され、また、本実施例２においても、第１銅端子１０４ｂがＩＣ部品１０４のドレイン端子として機能し、ＩＣ部品１０４の第１表面１０４ａの全面に配設されている。一方、第２銅端子１０４ｄの一方がソース端子として機能し、他方がゲート端子して機能し、各端子がＩＣ部品１０４の第２表面１０４ｃに対して部分的に配設されている（すなわち、第２表面１０４ｃは部分的に露出している）。 Further, the IC component 104 has one first copper terminal 104b made of copper on the first surface 104a side, and two second copper terminals 104d made of copper on the second surface 104c side. Also in the second embodiment, the first copper terminal 104 b functions as the drain terminal of the IC component 104 and is disposed on the entire first surface 104 a of the IC component 104. On the other hand, one of the second copper terminals 104d functions as a source terminal, the other functions as a gate terminal, and each terminal is partially disposed on the second surface 104c of the IC component 104 (that is, The second surface 104c is partially exposed).
　次に、図１３に示すように、ＩＣ部品１０４及び所望の貫通孔１０５、１０６が形成された第１銅箔１０７を支持部材１０３上に搭載する搭載工程が行われる。より具体的には、吸引ノズルを備える表面実装機（チップマウンタ）を用い、支持部材１０３に、ＩＣ部品１０４の第１表面１０４ａ側に配設された第１銅端子１０４ｂが接触するように固着し、その後に第１銅箔１０７の貫通孔１０６にＩＣ部品１０４が挿入されるように、第１銅箔１０７を支持部材１０３に貼り付ける。なお、先に第１銅箔１０７を支持部材１０３に固着した後に、ＩＣ部品１０４を貫通孔１０６に挿入しつつ支持部材１０３に固着してもよい。 Next, as shown in FIG. 13, a mounting step of mounting the first copper foil 107 on which the IC component 104 and desired through holes 105 and 106 are formed on the support member 103 is performed. More specifically, using a surface mounter (chip mounter) having a suction nozzle, the support member 103 is fixed so that the first copper terminal 104b disposed on the first surface 104a side of the IC component 104 is in contact with the support member 103. Then, the first copper foil 107 is attached to the support member 103 so that the IC component 104 is inserted into the through hole 106 of the first copper foil 107. The first copper foil 107 may be fixed to the support member 103 first, and then the IC component 104 may be fixed to the support member 103 while being inserted into the through hole 106.
　次に、図１４に示すように、ＩＣ部品１０４が配設されている貫通孔１０６のみに絶縁樹脂材料を充填して硬化し、樹脂体１０８を形成する。これにより、樹脂体１０８内にＩＣ部品１０４が埋設される。その後、図１５に示すように、支持部材１０３を剥離し、支持部材１０３が配設された一端とは反対側（すなわち、第２表面１０４ｃ側）に、プリプレグ１０９及び第２銅箔１１０をレイアップし、これを真空下で加熱しながらプレスする。このプレスは、例えば真空加圧式のプレス機を用いて行われる。これにより、樹脂体１０８及びプリプレグ１０９からなる絶縁層１１１が形成され、ＩＣ部品１０４を埋設する絶縁層１１１の形成工程（絶縁層形成工程）が完了する。 Next, as shown in FIG. 14, only the through-hole 106 in which the IC component 104 is disposed is filled with an insulating resin material and cured to form a resin body 108. As a result, the IC component 104 is embedded in the resin body 108. Thereafter, as shown in FIG. 15, the support member 103 is peeled off, and the prepreg 109 and the second copper foil 110 are placed on the side opposite to one end where the support member 103 is disposed (that is, the second surface 104c side). And press while heating under vacuum. This press is performed using, for example, a vacuum press machine. Thereby, the insulating layer 111 made of the resin body 108 and the prepreg 109 is formed, and the forming process (insulating layer forming process) of the insulating layer 111 in which the IC component 104 is embedded is completed.
　次に、図１６に示すように、第２銅箔１１０、プリプレグ１０９、及び樹脂体１０８を貫通してＩＣ部品１０４の第２銅端子１０４ｄに到達する第１ビア１１２、並びに第２銅箔１１０及びプリプレグ１０９貫通して第１銅箔１０７に到達する第２ビア１１３を形成する。各ビアの形成方法としては、例えばＣＯ２レーザをビア形成箇所に照射することにより、ＣＯ２レーザの照射部分の部材が除去され、所望の形状のビアが形成されてもよい。なお、ＣＯ２レーザに限られることがなく、例えば、ＵＶ－ＹＡＧやエキシマ等の高周波レーザを用いてもよい。また、プラズマエッチング又はケミカルエッチングによって各ビアを形成してもよい。 Next, as shown in FIG. 16, the first via 112 that passes through the second copper foil 110, the prepreg 109, and the resin body 108 and reaches the second copper terminal 104 d of the IC component 104, and the second copper foil 110. Then, a second via 113 penetrating the prepreg 109 and reaching the first copper foil 107 is formed. As a method for forming each via, for example, by irradiating a CO 2 laser to a via forming portion, a member at a CO 2 laser irradiated portion may be removed, and a via having a desired shape may be formed. Note that the present invention is not limited to the CO 2 laser, and for example, a high frequency laser such as UV-YAG or excimer may be used. Further, each via may be formed by plasma etching or chemical etching.
　ここで、第１ビア１１２のそれぞれは、実施例１の第３ビア１３と同様に、各ビアが到達する第２銅端子１０４ｄのそれぞれの平面形状に沿って配設され、第１ビア１１２のそれぞれの開口寸法は第２銅端子１０４ｄのそれぞれの平面寸法よりも若干小さくなっている。すなわち、第１ビア１１２のそれぞれの開口形状は、各ビアが到達する第２銅端子１０４ｄの平面形状に相似し、第１ビア１１２によって第２銅端子１０４ｄの大部分が露出することになる。そして、実施例１の第３ビア１３と同様に、各第１ビア１１２は、第２銅端子１０４ｄの主表面（すなわち、ＩＣ部品１０４側とは反対側に位置する表面）の面積の約５０％以上を露出することが好ましく、より好ましくは８０％以上、特に好ましくは９０％以上となる。 Here, each of the first vias 112 is disposed along the planar shape of each of the second copper terminals 104d to which each via reaches, similarly to the third via 13 of the first embodiment. Each opening dimension is slightly smaller than each planar dimension of the second copper terminal 104d. In other words, each opening shape of the first via 112 is similar to the planar shape of the second copper terminal 104d to which each via reaches, and most of the second copper terminal 104d is exposed by the first via 112. As in the third via 13 of the first embodiment, each first via 112 has an area of about 50 of the main surface of the second copper terminal 104d (that is, the surface located on the side opposite to the IC component 104 side). % Or more is preferably exposed, more preferably 80% or more, and particularly preferably 90% or more.
　このように第１ビア１１２の形状及び寸法を調整する理由は、実施例１と同様に、第１ビア１１２を充填することになる導通ビアの平面状の寸法を、ＩＣ部品１０４の第２銅端子１０４ｄの平面状の寸法と同等程度に確保するためである。 The reason for adjusting the shape and size of the first via 112 in this manner is that, as in the first embodiment, the planar size of the conductive via that fills the first via 112 is changed to the second copper of the IC component 104. This is to ensure the same size as the planar dimension of the terminal 104d.
　各ビアが形成された後、デスミア処理を施し、ビア形成の際に残留している樹脂を除去することが好ましい。また、第２銅端子１０４ｄには更にソフトエッチング処理を施し、ビア形成によって露出した第２銅端子１０４ｄの露出面の酸化物や有機物を除去することが好ましい。これにより、新鮮な銅の表面が露出することになり、その後のめっき処理において析出する銅との密着性が高まり、結果として電気的な接続信頼性が向上する。 It is preferable that after each via is formed, a desmear process is performed to remove the resin remaining in the via formation. Further, it is preferable that the second copper terminal 104d is further subjected to a soft etching process to remove oxides and organic substances on the exposed surface of the second copper terminal 104d exposed by the via formation. Thereby, the surface of fresh copper will be exposed, adhesiveness with the copper which precipitates in subsequent plating processing will increase, and electrical connection reliability will improve as a result.
　次に、図１７に示すように、化学銅めっきや電気銅めっき等のめっき処理を施し、第１ビア１１２を充填する第１導通ビア１１４、第２ビア１１３を充填する第２導通ビア１１５、絶縁層１１１の第１表面１１１ａ側に位置するとともに第１銅端子１０４ｂ及び第１銅箔１０７に電気的に接続した第１銅配線層１１６、及び第２銅箔１１０を被覆する第２銅配線層１１７を形成する。ここで、第１銅配線層１１６は、第１銅端子１０４ｂの表面を全体的に覆う部分が、第１銅端子１０４ｂ以外の領域を被覆する部分と第１銅端子１０４ｂとを電気的に接続する第１銅接続部１１６ａとして機能する。そして、第１銅接続部１１６ａは、第１銅端子１０４ｂの表面を全体的に覆うため、第１銅端子１０４ｂの平面形状に沿って配設されていることになる。 Next, as shown in FIG. 17, a first conductive via 114 filling the first via 112 and a second conductive via 115 filling the second via 113 by performing a plating process such as chemical copper plating or electrolytic copper plating, A first copper wiring layer 116 located on the first surface 111a side of the insulating layer 111 and electrically connected to the first copper terminal 104b and the first copper foil 107, and a second copper wiring covering the second copper foil 110 Layer 117 is formed. Here, in the first copper wiring layer 116, the portion covering the entire surface of the first copper terminal 104b electrically connects the portion covering the region other than the first copper terminal 104b and the first copper terminal 104b. Functions as the first copper connection part 116a. And the 1st copper connection part 116a is arrange | positioned along the planar shape of the 1st copper terminal 104b, in order to cover the surface of the 1st copper terminal 104b entirely.
　また、実施例１と同様に、第１導通ビア１１４は第１ビア１１２を充填することから、第１導通ビア１１４は第２銅端子１０４ｄの平面形状に沿って配設され、第１導通ビア１１４の平面寸法は第２銅端子１０４ｄの平面寸法よりも若干小さくなっている。すなわち、第１導通ビア１１４の平面寸法は第２銅端子１０４ｄの平面形状に相似していることになる。これらのことを換言すると、第２銅端子１０４ｄと第１導通ビア１１４との接続面は、第２銅端子１０４ｄの平面形状に沿って位置することになる。そして、第１ビア１１２による第２銅端子１０４ｄの露出割合を上述したように調整することにより、第２銅端子１０４ｄに対する第１導通ビア１１４の被覆率は、約５０％以上となり、より好ましくは８０％以上、特に好ましくは９０％以上となる。 Similarly to the first embodiment, since the first conductive via 114 fills the first via 112, the first conductive via 114 is arranged along the planar shape of the second copper terminal 104d, and the first conductive via 114 is provided. The planar dimension of 114 is slightly smaller than the planar dimension of the second copper terminal 104d. That is, the planar dimension of the first conductive via 114 is similar to the planar shape of the second copper terminal 104d. In other words, the connection surface between the second copper terminal 104d and the first conductive via 114 is positioned along the planar shape of the second copper terminal 104d. Then, by adjusting the exposure ratio of the second copper terminal 104d by the first via 112 as described above, the coverage ratio of the first conductive via 114 to the second copper terminal 104d becomes about 50% or more, more preferably. 80% or more, particularly preferably 90% or more.
　このようにＩＣ部品１０４の第２銅端子１０４ｄに接続される第１導通ビア１１４の寸法及び形状を調整して大型化するとともに、第１銅端子１０４ｂに接続される第１銅接続部１１６ａを第１銅端子１０４ｂと同一の平面寸法とすることにより、ＩＣ部品１０４にて生じる熱を効率よく放熱することができ、ＩＣ部品１０４の劣化及び部品内蔵基板自体の信頼性を向上することができる。また、当該放熱性の向上により、ＩＣ部品１０４のオン抵抗の低下を図ることが可能になる。更に、当該第１導通ビア１１４及び第１銅接続部１１６ａの大型化により、より高い電流容量を確保することができ、許容電流値において優位な特性を備える部品内蔵基板を実現することができる。 As described above, the size and shape of the first conductive via 114 connected to the second copper terminal 104d of the IC component 104 are adjusted to increase the size, and the first copper connection portion 116a connected to the first copper terminal 104b is formed. By setting the same planar dimensions as the first copper terminal 104b, the heat generated in the IC component 104 can be efficiently dissipated, and the deterioration of the IC component 104 and the reliability of the component-embedded substrate itself can be improved. . In addition, the on-resistance of the IC component 104 can be reduced by improving the heat dissipation. Furthermore, by increasing the size of the first conductive via 114 and the first copper connection portion 116a, a higher current capacity can be ensured, and a component-embedded substrate having superior characteristics in the allowable current value can be realized.
　そして、上述したビアの形成工程、並びに銅配線層及び導通ビアの形成工程を経ることにより、第１銅端子１０４ｂに電気的に接続する第１銅接続部１１６ａの形成工程（すなわち、第１銅接続部形成工程）、及び第２銅端子１０４ｄに電気的に接続する第２銅接続部（第１導通ビア１１４）の形成工程（すなわち、第２銅接続部形成工程）が完了する。 Then, through the above-described via formation process and the copper wiring layer and conductive via formation process, the first copper connection part 116a formation process (that is, the first copper connection) that is electrically connected to the first copper terminal 104b. The connecting portion forming step) and the forming step of the second copper connecting portion (first conductive via 114) electrically connected to the second copper terminal 104d (that is, the second copper connecting portion forming step) are completed.
　次に、図１８に示すように、絶縁層１１１の第１表面１１１ａ側に位置する第１銅配線層１１６にパターニングを施して第１外層配線パターン１２３を形成し（第１外層配線パターン形成工程）、絶縁層１１１の第２表面１１１ｂに位置する第２銅配線層１１７及び第２銅箔１１０にパターニングを施して第２外層配線パターン１２４を形成する（第２外層配線パターン形成工程）。例えば、公知のフォトリソグラフィ技術を用いて、第１銅配線層１１６、第２銅配線層１１７、及び第２銅箔１１０にエッチング処理を施して、第１外層配線パターン１２３及び第２外層配線パターン１２４を形成する。 Next, as shown in FIG. 18, the first copper wiring layer 116 located on the first surface 111a side of the insulating layer 111 is patterned to form a first outer layer wiring pattern 123 (first outer layer wiring pattern forming step). ), Patterning is performed on the second copper wiring layer 117 and the second copper foil 110 located on the second surface 111b of the insulating layer 111 to form a second outer layer wiring pattern 124 (second outer layer wiring pattern forming step). For example, the first copper wiring layer 116, the second copper wiring layer 117, and the second copper foil 110 are etched using a known photolithography technique so that the first outer layer wiring pattern 123 and the second outer layer wiring pattern are etched. 124 is formed.
　以上のような製造工程を経て、図１８に示すような部品内蔵基板１３０の形成が完了する。なお、実際の部品内蔵基板１３０の製造においても、実施例１と同様に、複数の部品内蔵基板１３０が１枚の基板として製造され、複数の部品内蔵基板１３０の形成完了後に当該１枚の基板を切断し、最終的に複数の部品内蔵基板１３０を同時に製造することになる。 Through the manufacturing process as described above, the formation of the component built-in substrate 130 as shown in FIG. 18 is completed. In the actual production of the component-embedded substrate 130, as in the first embodiment, the plurality of component-embedded substrates 130 are manufactured as one substrate, and after the formation of the plurality of component-embedded substrates 130 is completed, the one substrate And finally, a plurality of component-embedded boards 130 are manufactured simultaneously.
　実施例２に係る部品内蔵基板１３０においては、ＩＣ部品１０４の第２銅端子１０４ｄに接続される第１導通ビア１１４の寸法及び形状を調整して大型化され、且つ第１銅端子１０４ｂに接続される第１銅接続部１１６ａを第１銅端子１０４ｂと同一の平面寸法に調整されているため、ＩＣ部品１０４にて生じる熱を効率よく放熱することができ、ＩＣ部品１０４の劣化及び部品内蔵基板自体の信頼性をより一層向上することができる。また、当該放熱性の向上により、ＩＣ部品１０４のオン抵抗の低下を図ることが可能になる。更に、当該第１導通ビア１１４及び第１銅接続部１１６ａの大型化により、より高い電流容量を確保することができ、許容電流値において優位な特性を備える部品内蔵基板を実現することができる。 In the component-embedded substrate 130 according to the second embodiment, the size and shape of the first conductive via 114 connected to the second copper terminal 104d of the IC component 104 are adjusted and the size is increased, and the first conductive via 114 is connected to the first copper terminal 104b. Since the first copper connection portion 116a is adjusted to the same plane size as the first copper terminal 104b, the heat generated in the IC component 104 can be efficiently radiated, and the deterioration of the IC component 104 and the built-in component The reliability of the substrate itself can be further improved. In addition, the on-resistance of the IC component 104 can be reduced by improving the heat dissipation. Furthermore, by increasing the size of the first conductive via 114 and the first copper connection portion 116a, a higher current capacity can be ensured, and a component-embedded substrate having superior characteristics in the allowable current value can be realized.
＜本発明の実施態様＞
　本発明の第１実施態様に係る部品内蔵基板は、絶縁樹脂材料を含む絶縁層と、第１表面に第１銅端子、及び前記第１表面とは反対側の第２表面に第２銅端子を備えるとともに、前記絶縁層に埋設されたＩＣ部品と、前記絶縁層の第１表面に形成された第１外層配線パターンと、前記絶縁層の第１表面とは反対側の第２表面に形成された第２外層配線パターンと、前記第１銅端子と前記第１外層配線パターンとを電気的に接続する第１銅接続部と、前記第２銅端子と前記第２外層配線パターンとを電気的に接続する第２銅接続部と、を有し、前記第１銅端子と前記第１銅接続部と接続面は前記第１銅端子の表面形状に沿って位置し、前記第２銅端子と前記第２銅接続部と接続面は前記第２銅端子の表面形状に沿って位置していることである。 <Embodiment of the present invention>
The component-embedded substrate according to the first embodiment of the present invention includes an insulating layer containing an insulating resin material, a first copper terminal on the first surface, and a second copper terminal on the second surface opposite to the first surface. An IC component embedded in the insulating layer, a first outer layer wiring pattern formed on the first surface of the insulating layer, and a second surface opposite to the first surface of the insulating layer. The second outer layer wiring pattern, the first copper terminal and the first outer layer wiring pattern are electrically connected, and the second copper terminal and the second outer layer wiring pattern are electrically connected. A first copper terminal, the first copper connection and the connection surface are located along a surface shape of the first copper terminal, and the second copper terminal. And the said 2nd copper connection part and a connection surface are located along the surface shape of the said 2nd copper terminal.
　第１実施態様に係る部品内蔵基板においては、第１銅接続部及び第２銅接続部のいずれもが、接続するＩＣ部品の銅端子の表面形状に沿って位置しているため、ＩＣ部品にて生じる熱を良好に放熱するとともに、比較的に高い電流容量を確保することができる。これは、当該部品内蔵基板において、熱伝導性の比較的に低い導電性接着剤又は半田を使用することなく、銅からなる接続部を介して熱を放熱できる構造が採用されているため、放熱性の向上が実現されている。また、比較的に小さい複数の接続部（導通ビア）を設けることなく、ＩＣ部品の各銅端子に対応した比較的に大きな第１銅接続部及び第２銅接続部が形成されるため、更なる放熱性の向上及びより高い電流容量の確保が実現されることになる。 In the component-embedded substrate according to the first embodiment, both the first copper connection portion and the second copper connection portion are located along the surface shape of the copper terminal of the IC component to be connected. The heat generated can be radiated satisfactorily and a relatively high current capacity can be secured. This is because the component-embedded substrate employs a structure that can dissipate heat through a connection made of copper without using a conductive adhesive or solder having a relatively low thermal conductivity. The improvement of performance is realized. In addition, since relatively large first copper connection portions and second copper connection portions corresponding to the respective copper terminals of the IC component are formed without providing a plurality of relatively small connection portions (conduction vias), the connection is further improved. Thus, the improvement of the heat dissipation and the securing of a higher current capacity are realized.
　本発明の第２実施態様に係る部品内蔵基板は、上述した第１実施態様において、前記第１銅端子に対する前記第１銅接続部の被覆率、及び前記第２銅端子に対する前記第２銅接続部の被覆率が５０％以上である。これにより、比較的に小さい複数の接続部（導通ビア）を設けることなく、ＩＣ部品の各銅端子に対応した比較的に大きな第１銅接続部及び第２銅接続部による電気的接続を確保することができるため、更なる放熱性の向上及びより高い電流容量の確保が実現されることになる。 The component-embedded substrate according to the second embodiment of the present invention is the first embodiment described above, wherein the first copper connection portion covers the first copper terminal, and the second copper connection connects to the second copper terminal. The coverage of the part is 50% or more. As a result, the electrical connection by the relatively large first copper connection portion and the second copper connection portion corresponding to each copper terminal of the IC component is ensured without providing a plurality of relatively small connection portions (conduction vias). Therefore, further improvement in heat dissipation and securing of a higher current capacity can be realized.
　本発明の第３実施態様に係る部品内蔵基板は、上述した第１又は第２実施態様において、前記第１銅端子又は前記第２銅端子のいずれか一方が前記ＩＣ部品の表面全体に形成されているドレイン端子である。これにより、部品内蔵基板における放熱性がより向上されることになり、より高い電流容量の確保を容易に行えることになる。 In the component-embedded substrate according to the third embodiment of the present invention, in the first or second embodiment described above, either the first copper terminal or the second copper terminal is formed on the entire surface of the IC component. It is a drain terminal. Thereby, the heat dissipation in the component built-in substrate is further improved, and a higher current capacity can be easily ensured.
　本発明の第４実施態様に係る部品内蔵基板は、上述した第１乃至第３実施態様のいずれかにおいて、前記第１銅接続部及び第２銅接続部が単一の接続部材から構成されていることである。これにより、部品内蔵基板における放熱性がより一層向上されることになり、より高い電流容量の確保を容易に行えることになる。 A component-embedded substrate according to a fourth embodiment of the present invention is the component-embedded substrate according to any one of the first to third embodiments described above, wherein the first copper connection portion and the second copper connection portion are configured from a single connection member. It is that you are. Thereby, the heat dissipation in the component built-in substrate is further improved, and a higher current capacity can be easily secured.
　本発明の第５実施態様に係る部品内蔵基板は、上述した第１乃至第３実施態様のいずれかにおいて、前記第１銅接続部及び第２銅接続部が複数の接続部材から構成されていることである。これにより、部品内蔵基板における放熱性が向上されつつより高い電流容量の確保を容易に行えることになり、更には様々なＩＣ部品の銅端子に対応させて前記第１銅接続部及び第２銅接続部を配置することが可能になる。 In the component-embedded substrate according to the fifth embodiment of the present invention, in any of the first to third embodiments described above, the first copper connection portion and the second copper connection portion are constituted by a plurality of connection members. That is. As a result, it is possible to easily ensure a higher current capacity while improving the heat dissipation in the component-embedded substrate. Furthermore, the first copper connection portion and the second copper are adapted to correspond to the copper terminals of various IC components. It becomes possible to arrange the connecting portion.
　本発明の第６実施態様に係る部品内蔵基板の製造方法は、第１表面に第１銅端子、及び前記第１表面とは反対側の第２表面に第２銅端子を備えるＩＣ部品を内蔵する部品内蔵基板の製造方法であって、第１銅端子を支持部材に接触させ、前記ＩＣ部品を前記支持部材上に搭載する搭載工程と、前記ＩＣ部品を覆うように絶縁樹脂材料を積層し、前記ＩＣ部品を埋設する絶縁層を形成する絶縁層形成工程と、前記第１銅端子に電気的に接続する第１銅接続部を形成する第１銅接続部形成工程と、前記第２銅端子に電気的に接続する第２銅接続部を形成する第２銅接続部形成工程と、前記第１銅接続部に電気的に接続する第１外層配線パターンを前記絶縁層の第１表面上に形成する第１外層配線パターン形成工程と、前記第２銅接続部に電気的に接続する第２外層配線パターンを前記絶縁層の第２表面上に形成する第２外層配線パターン形成工程と、を有し、前記第１銅接続部形成工程においては、前記第１銅端子と前記第１銅接続部と接続面を前記第１銅端子の表面形状に沿って位置し、前記第２銅接続部形成工程においては、前記第２銅端子と前記第２銅接続部と接続面を前記第２銅端子の表面形状に沿って位置することである。 According to a sixth embodiment of the present invention, there is provided a method of manufacturing a component-embedded substrate including an IC component including a first copper terminal on a first surface and a second copper terminal on a second surface opposite to the first surface. A method of manufacturing a component-embedded substrate comprising: mounting a step of bringing a first copper terminal into contact with a support member and mounting the IC component on the support member; and laminating an insulating resin material so as to cover the IC component. An insulating layer forming step of forming an insulating layer in which the IC component is embedded, a first copper connecting portion forming step of forming a first copper connecting portion electrically connected to the first copper terminal, and the second copper Forming a second copper connecting portion for forming a second copper connecting portion electrically connected to the terminal, and a first outer layer wiring pattern electrically connecting to the first copper connecting portion on the first surface of the insulating layer; Forming a first outer layer wiring pattern forming step and electrically connecting the second copper connection portion A second outer layer wiring pattern forming step of forming a second outer layer wiring pattern to be connected on the second surface of the insulating layer. In the first copper connection portion forming step, the first copper terminal and the A 1st copper connection part and a connection surface are located along the surface shape of the said 1st copper terminal, and in the said 2nd copper connection part formation process, the said 2nd copper terminal, the said 2nd copper connection part, and a connection surface are used. It is located along the surface shape of the second copper terminal.
　第６実施態様においも、第１実施態様と同様に、第１銅接続部及び第２銅接続部のいずれもが、接続するＩＣ部品の銅端子の表面形状に沿って位置しているため、ＩＣ部品にて生じる熱を良好に放熱するとともに、比較的に高い電流容量を確保することができる部品内蔵基板を製造することができる。これは、熱伝導性の比較的に低い導電性接着剤又は半田を使用することないため、銅からなる接続部を介して熱を効率よく放熱することができるためである。 In the sixth embodiment, as in the first embodiment, both the first copper connection portion and the second copper connection portion are located along the surface shape of the copper terminal of the IC component to be connected. It is possible to manufacture a component-embedded substrate that can radiate heat generated in an IC component well and can ensure a relatively high current capacity. This is because a conductive adhesive or solder having a relatively low thermal conductivity is not used, so that heat can be efficiently radiated through the connection portion made of copper.
　本発明の第７実施態様に係る部品内蔵基板の製造方法は、上述した第６実施態様において、前記第１銅接続部形成工程及び前記第２銅接続部形成工程では前記第１銅端子に対する前記第１銅接続部の被覆率、及び前記第２銅端子に対する前記第２銅接続部の被覆率を、５０％以上とすることである。これにより、比較的に小さい複数の接続部（導通ビア）を設けることなく、ＩＣ部品の各銅端子に対応した比較的に大きな第１銅接続部及び第２銅接続部による電気的接続を確保することができるため、更なる放熱性の向上及びより高い電流容量の確保が実現されることになる。 The manufacturing method of the component built-in substrate according to the seventh embodiment of the present invention is the above-described sixth embodiment, wherein the first copper connection portion forming step and the second copper connection portion forming step are configured to The coverage of the first copper connection portion and the coverage of the second copper connection portion with respect to the second copper terminal are 50% or more. As a result, the electrical connection by the relatively large first copper connection portion and the second copper connection portion corresponding to each copper terminal of the IC component is ensured without providing a plurality of relatively small connection portions (conduction vias). Therefore, further improvement in heat dissipation and securing of a higher current capacity can be realized.
　本発明の第８実施態様に係る部品内蔵基板の製造方法は、上述した第６又は第７実施態様において、前記第１銅接続部形成工程及び前記第２銅接続部形成工程では単一の接続部材から前記第１銅接続部及び第２銅接続部を形成することである。これにより、部品内蔵基板における放熱性がより一層向上されることになり、より高い電流容量の確保を容易に行えることになる。 The method for manufacturing a component-embedded substrate according to the eighth embodiment of the present invention is the same as the sixth or seventh embodiment described above, in the first copper connection portion forming step and the second copper connection portion forming step. Forming the first copper connection and the second copper connection from a member. Thereby, the heat dissipation in the component built-in substrate is further improved, and a higher current capacity can be easily secured.
　本発明の第９実施態様に係る部品内蔵基板の製造方法は、上述した第６又は第７実施態様において、前記第１銅接続部形成工程及び前記第２銅接続部形成工程では複数の接続部材から前記第１銅接続部及び第２銅接続部を形成することである。これにより、部品内蔵基板における放熱性が向上されつつより高い電流容量の確保を容易に行えることになり、更には様々なＩＣ部品の銅端子に対応させて前記第１銅接続部及び第２銅接続部を配置することが可能になる。 The component-embedded substrate manufacturing method according to the ninth embodiment of the present invention is the above-described sixth or seventh embodiment, wherein the first copper connection portion forming step and the second copper connection portion forming step include a plurality of connection members. Forming the first copper connection and the second copper connection. As a result, it is possible to easily ensure a higher current capacity while improving the heat dissipation in the component-embedded substrate. Furthermore, the first copper connection portion and the second copper are adapted to correspond to the copper terminals of various IC components. It becomes possible to arrange the connecting portion.
　１　　支持板
　２　　接着剤
　３　　支持部材
　４　　ＩＣ部品
　４ａ　　第１表面
　４ｂ　　第１銅端子
　４ｃ　　第２表面
　４ｄ　　第２銅端子
　５　　絶縁層
　５ａ　　第１表面
　５ｂ　　第２表面
　６　　プリプレグ
　７　　配線パターン付樹脂体
　７ａ　　樹脂基体
　７ｂ　　配線パターン
　７ｃ　　貫通孔
　７ｄ　　側面
　８　　プリプレグ
　９　　挟持板（支持板）
　１１　　第１ビア
　１２　　第２ビア
　１３　　第３ビア
　１４　　第４ビア
　１５　　第１導通ビア（第１銅接続部）
　１６　　第２導通ビア
　１７　　第３導通ビア（第２銅接続部）
　１８　　第４導通ビア
　２１　　第１銅配線層
　２２　　第２銅配線層
　２３　　第１外層配線パターン
　２４　　第２外層配線パターン
　３０　　部品内蔵基板 DESCRIPTION OF SYMBOLS 1 Support plate 2 Adhesive 3 Support member 4 IC component 4a 1st surface 4b 1st copper terminal 4c 2nd surface 4d 2nd copper terminal 5 Insulating layer 5a 1st surface 5b 2nd surface 6 Prepreg 7 Resin body with wiring pattern 7a Resin base 7b Wiring pattern 7c Through hole 7d Side 8 Pre-preg 9 Nipping plate (support plate)
11 First via 12 Second via 13 Third via 14 Fourth via 15 First conductive via (first copper connection)
16 Second conductive via 17 Third conductive via (second copper connecting portion)
18 Fourth conductive via 21 First copper wiring layer 22 Second copper wiring layer 23 First outer layer wiring pattern 24 Second outer layer wiring pattern 30 Component-embedded substrate

Claims (9)

  1. 　絶縁樹脂材料を含む絶縁層と、
    　第１表面に第１銅端子、及び前記第１表面とは反対側の第２表面に第２銅端子を備えるとともに、前記絶縁層に埋設されたＩＣ部品と、
    　前記絶縁層の第１表面に形成された第１外層配線パターンと、
    　前記絶縁層の第１表面とは反対側の第２表面に形成された第２外層配線パターンと、
    　前記第１銅端子と前記第１外層配線パターンとを電気的に接続する第１銅接続部と、
    　前記第２銅端子と前記第２外層配線パターンとを電気的に接続する第２銅接続部と、を有し、
    　前記第１銅端子と前記第１銅接続部と接続面は前記第１銅端子の表面形状に沿って位置し、前記第２銅端子と前記第２銅接続部と接続面は前記第２銅端子の表面形状に沿って位置している部品内蔵基板。     An insulating layer containing an insulating resin material;
    The first copper terminal on the first surface and the second copper terminal on the second surface opposite to the first surface, and an IC component embedded in the insulating layer;
    A first outer layer wiring pattern formed on the first surface of the insulating layer;
    A second outer layer wiring pattern formed on the second surface opposite to the first surface of the insulating layer;
    A first copper connection portion for electrically connecting the first copper terminal and the first outer layer wiring pattern;
    A second copper connection part for electrically connecting the second copper terminal and the second outer layer wiring pattern;
    The first copper terminal, the first copper connection portion, and the connection surface are located along the surface shape of the first copper terminal, and the second copper terminal, the second copper connection portion, and the connection surface are the second copper. A component-embedded board located along the surface shape of the terminal.
  2. 　前記第１銅端子に対する前記第１銅接続部の被覆率、及び前記第２銅端子に対する前記第２銅接続部の被覆率は、５０％以上である請求項１に記載の部品内蔵基板。 The component built-in board according to claim 1, wherein a coverage ratio of the first copper connection portion with respect to the first copper terminal and a coverage ratio of the second copper connection portion with respect to the second copper terminal are 50% or more.
  3. 　前記第１銅端子又は前記第２銅端子のいずれか一方は、前記ＩＣ部品の表面全体に形成されているドレイン端子である請求項１又は２に記載の部品内蔵基板。 3. The component-embedded substrate according to claim 1, wherein one of the first copper terminal and the second copper terminal is a drain terminal formed on the entire surface of the IC component.
  4. 　前記第１銅接続部及び第２銅接続部は、単一の接続部材から構成されている請求項１乃至３のいずれいか１項に記載の部品内蔵基板。 The component-embedded substrate according to any one of claims 1 to 3, wherein the first copper connection portion and the second copper connection portion are configured by a single connection member.
  5. 　前記第１銅接続部及び第２銅接続部は、複数の接続部材から構成されている請求項１乃至３のいずれいか１項に記載の部品内蔵基板。 The component-embedded substrate according to any one of claims 1 to 3, wherein the first copper connection portion and the second copper connection portion are constituted by a plurality of connection members.
  6. 　第１表面に第１銅端子、及び前記第１表面とは反対側の第２表面に第２銅端子を備えるＩＣ部品を内蔵する部品内蔵基板の製造方法であって、
    　第１銅端子を支持部材に接触させ、前記ＩＣ部品を前記支持部材上に搭載する搭載工程と、
    　前記ＩＣ部品を覆うように絶縁樹脂材料を積層し、前記ＩＣ部品を埋設する絶縁層を形成する絶縁層形成工程と、
    　前記第１銅端子に電気的に接続する第１銅接続部を形成する第１銅接続部形成工程と、
    　前記第２銅端子に電気的に接続する第２銅接続部を形成する第２銅接続部形成工程と、
    　前記第１銅接続部に電気的に接続する第１外層配線パターンを前記絶縁層の第１表面上に形成する第１外層配線パターン形成工程と、
    　前記第２銅接続部に電気的に接続する第２外層配線パターンを前記絶縁層の第２表面上に形成する第２外層配線パターン形成工程と、を有し、
    　前記第１銅接続部形成工程においては、前記第１銅端子と前記第１銅接続部と接続面を前記第１銅端子の表面形状に沿って位置し、
    　前記第２銅接続部形成工程においては、前記第２銅端子と前記第２銅接続部と接続面を前記第２銅端子の表面形状に沿って位置する部品内蔵基板の製造方法。     A method for manufacturing a component-embedded substrate including an IC component including a first copper terminal on a first surface and a second copper terminal on a second surface opposite to the first surface,
    A mounting step of bringing the first copper terminal into contact with the support member and mounting the IC component on the support member;
    An insulating layer forming step of laminating an insulating resin material so as to cover the IC component and forming an insulating layer in which the IC component is embedded;
    A first copper connection part forming step of forming a first copper connection part electrically connected to the first copper terminal;
    A second copper connection part forming step of forming a second copper connection part electrically connected to the second copper terminal;
    A first outer layer wiring pattern forming step of forming a first outer layer wiring pattern electrically connected to the first copper connection portion on the first surface of the insulating layer;
    A second outer layer wiring pattern forming step of forming a second outer layer wiring pattern electrically connected to the second copper connection portion on the second surface of the insulating layer,
    In the first copper connection portion forming step, the first copper terminal, the first copper connection portion and the connection surface are positioned along the surface shape of the first copper terminal,
    In the second copper connection portion forming step, the component-embedded substrate manufacturing method wherein the second copper terminal, the second copper connection portion, and the connection surface are positioned along the surface shape of the second copper terminal.
  7. 　前記第１銅接続部形成工程及び前記第２銅接続部形成工程においては、前記第１銅端子に対する前記第１銅接続部の被覆率、及び前記第２銅端子に対する前記第２銅接続部の被覆率を、５０％以上とする請求項６に記載の部品内蔵基板の製造方法。 In the first copper connection portion forming step and the second copper connection portion forming step, the coverage ratio of the first copper connection portion with respect to the first copper terminal, and the second copper connection portion with respect to the second copper terminal. The method for manufacturing a component-embedded board according to claim 6, wherein the coverage is 50% or more.
  8. 　前記第１銅接続部形成工程及び前記第２銅接続部形成工程においては、単一の接続部材から前記第１銅接続部及び第２銅接続部を形成する請求項６又は７に記載の部品内蔵基板の製造方法。 The component according to claim 6 or 7, wherein, in the first copper connection portion forming step and the second copper connection portion forming step, the first copper connection portion and the second copper connection portion are formed from a single connection member. A method for manufacturing a built-in substrate.
  9. 　前記第１銅接続部形成工程及び前記第２銅接続部形成工程においては、複数の接続部材から前記第１銅接続部及び第２銅接続部を形成する請求項６又は７に記載の部品内蔵基板の製造方法。
          The component built-in according to claim 6 or 7, wherein, in the first copper connection portion forming step and the second copper connection portion forming step, the first copper connection portion and the second copper connection portion are formed from a plurality of connection members. A method for manufacturing a substrate.
PCT/JP2016/050745 2016-01-12 2016-01-12 Substrate with built-in component and method for manufacturing substrate with built-in component WO2017122284A1 (en)

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CN201680075962.0A CN108464061A (en) 2016-01-12 2016-01-12 The manufacturing method of including components therein substrate and including components therein substrate
PCT/JP2016/050745 WO2017122284A1 (en) 2016-01-12 2016-01-12 Substrate with built-in component and method for manufacturing substrate with built-in component
JP2017561097A JP6839099B2 (en) 2016-01-12 2016-01-12 Manufacturing method of component-embedded board and component-embedded board
KR1020187018394A KR20180103859A (en) 2016-01-12 2016-01-12 Manufacturing method of internal board and internal board
TW105137089A TW201725946A (en) 2016-01-12 2016-11-14 Substrate with built-in component and method for manufacturing substrate with built-in component

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WO2014162478A1 (en) * 2013-04-01 2014-10-09 株式会社メイコー Component-embedded substrate and manufacturing method for same
JP2015015349A (en) * 2013-07-04 2015-01-22 株式会社ジェイテクト Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014162478A1 (en) * 2013-04-01 2014-10-09 株式会社メイコー Component-embedded substrate and manufacturing method for same
JP2015015349A (en) * 2013-07-04 2015-01-22 株式会社ジェイテクト Semiconductor device

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