WO2017113305A1 - Correction device and method - Google Patents

Abstract

The invention relates to the technical field of digital acquisition. Provided are a correction device and method for resolving the problem that in the prior art, using compensation in an analog domain to perform a time error correction results in low compensation precision and is difficult to satisfy an SFDR requirement of an ADC. The correction device comprises: M sample/hold circuits (102); M analog clock circuits (101) connected one-to-one with clock control terminals of the M sample/hold circuits (102) correspondingly; M analog to digital converters (ADCs) (103) connected one-to-one with output terminals of the M sample/hold circuits (102) correspondingly; a multiplexer (MUX) (104) connected to output terminals of the M ADCs (103); a time error digital compensation unit (105) connected to an output terminal of the MUX (104); a time error estimation unit (106) connected to an output terminal of the time error digital compensation unit (105); and an error compensation distribution unit (107) connected to an output terminal of the time error estimation unit (106). The error compensation distribution unit (107) is connected to the time error digital compensation unit (105) and the M sample/hold circuits (102).

Description

Correction device and method Technical field

The present invention relates to the field of digital acquisition technologies, and in particular, to a calibration apparatus and method.

Background technique

Analog to Digital Coverter (ADC) is an important device in digital acquisition systems for extracting useful information from analog signals and digitizing signals. With the continuous development of information electronic technology, various fields have put forward higher and higher requirements for the speed and accuracy of the analog-to-digital converter system. However, due to the fabrication process of the device itself, it is difficult for a single-chip ADC to meet high-speed sampling. At the same time, it maintains high sampling accuracy.

In order to solve this problem, Black & Hodges proposed an ADC (Time-interleaved ADC, TIADC), which is also called multi-channel parallel sampling in 1980. The M-chip ADC is used to form a parallel sampling system. Each sub-channel ADC is fixed at one time. The time interval alternately samples the same input analog signal in parallel, and finally multiplexes the multiplexed data into a total output signal through a data selector (Multiplexer, MUX) at the back end of the system, for example, Figure 1 shows the system block diagram of TIADC. The analog signal X(t) is processed by the M subchannel ADCs respectively, and the digital signals processed by the subchannels are combined into the output signal Y[n] through the MUX, so that the sampling frequency of the entire sampling system is the sampling frequency of each ADC. The sum of the system has doubled the sampling rate and achieved the purpose of high-speed sampling.

However, in the implementation process, due to limitations, differences, and aging of components, non-ideal characteristics of the sampling clock (phase delay, jitter), and transmission delay caused by signal paths, etc. Each subchannel samples the offset of the clock, thereby generating a clock mismatch error. The presence of these mismatch errors causes the output signal spectrum to generate a large amount of spurious components, which seriously affects the signal-to-noise ratio of the sampling system and the spurious-free dynamic range (Spurious) Free Dynamic Range (SFDR) reduces the performance of the entire sampling system. Therefore, in order to improve the overall performance of the TIADC system, it is necessary to The sub-channel is used to correct the time error. The correction of the time error mainly involves the estimation and compensation of the error. The time error compensation is divided into the compensation of the analog domain and the compensation of the digital domain.

Figure 2 is a block diagram of the error compensation of the analog domain. Compared with Figure 1, the part of the time error analog correction including the estimation of the time error and the analog compensation of the time error is added, by the current digital output signal Y[n] The time error estimation of each subchannel is performed, and the estimated value is converted into an analog domain compensation value to adjust the sampling clock control circuit of each subchannel at the next moment, and the sampling clock of each subchannel is compensated, thereby realizing the correction of the time error. However, because the correction accuracy of the analog domain is limited by the circuit compensation accuracy, and the compensation accuracy is strongly related to the circuit complexity, the limitations of the manufacturing process of each channel circuit, the difference and the non-ideal characteristics of the analog device result in the accuracy of the analog compensation cannot be accurate. Control, and in the case of limited power consumption, the complexity of the analog circuit is limited, so the compensation accuracy of the analog domain is low, it is difficult to meet the SFDR requirements of the ADC.

Summary of the invention

Embodiments of the present invention provide a calibration apparatus and method for solving the current error correction method using an analog domain, resulting in low compensation accuracy and difficulty in meeting the SFDR requirement of the ADC.

In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:

In a first aspect, an embodiment of the present invention provides a calibration apparatus, where the apparatus may include: M sample/hold circuits, and M analog clock circuits connected in one-to-one correspondence with clock control ends of the M sample/hold circuits; M analog-to-digital converter ADCs connected in one-to-one correspondence with the output ends of the M sample/hold circuits, a data selector MUX connected to the output ends of the M ADCs, and an output terminal of the MUX a time error digital compensation unit, a time error estimation unit connected to an output end of the time error digital compensation unit, an error compensation distribution unit connected to an output end of the time error estimation unit, the error compensation distribution unit and the The time error digital compensation unit is connected to the M sample/hold circuits; the M is an integer greater than or equal to 2; the M sample/hold circuits and the M ADCs are one-to-one corresponding to form M sub-channels;

The time error estimating unit is configured to acquire M first time error values corresponding to the M subchannels in a first sampling period, and output the M first to the error compensation allocating unit. Time error value

The error compensation allocation unit is configured to process the M first time error values according to a preset compensation strategy, respectively, to obtain M sets of compensation values corresponding to the M first time error values; The value includes: an analog domain compensation value and a digital domain compensation value;

Transmitting, to the M analog clock circuits, the M analog domain compensation values of the M sets of compensation values, and transmitting M digital domain compensation values of the M sets of compensation values to the time error Digital compensation unit;

Any one of the M analog clock circuits, configured to adjust a sampling time of the sample/hold circuit connected to the analog clock circuit in the first sampling period according to the received analog domain compensation value;

Any one of the M sample/hold circuits for sampling the input analog signal according to the adjusted sampling time of the analog clock circuit, and outputting the sampled signal to the ADC;

Any one of the M ADCs, configured to quantize and encode the received sampled signal, and output the processed signal to the MUX;

The MUX is configured to combine the M low-speed signals output by the M ADCs into a high-speed serial output digital signal, and output the digital signal to the time error digital compensation unit;

The time error digital compensation unit is configured to compensate the M digital domain compensation values output by the distribution unit according to the time error, and perform error compensation on the M channel signals in the digital signal one by one, and output the compensated Digital signal.

In this way, the time error estimation unit estimates the time error estimation value of each subchannel and calculates the time error value, and the error compensation distribution unit compensates the time error value for distribution, and allocates a reasonable analog domain compensation value and a digital domain compensation value according to the allocation. The analog domain compensation value and the digital domain compensation value are used for analog domain compensation and digital domain compensation, and the time error of the TIADC is corrected by the hybrid domain compensation method, and does not depend on a single analog or digital domain. Compensation, making full use of the analog domain is suitable for large step size rough correction and the digital domain is suitable for small step size and high precision correction. Organic combination of analog and digital correction can achieve optimal time error with minimum power consumption and resource overhead. Correction effect.

Optionally, in an implementation manner of the first aspect, for any one of the M subchannels, the time error estimation unit is specifically configured to:

Recording a time error estimate of the subchannel and a second time error value in a second sampling period; the second sampling period being a previous sampling period adjacent to the first sampling period;

And obtaining a first time error value of the subchannel according to the time error estimation value and the second time error value.

Specifically, the first time error value corresponding to the subchannel in the first sampling period may be obtained according to the formula Δt _m (k+1)=Δt _m (k)+Δt_esti _m ,

Wherein m takes any value from 1 to M, and Δt _m (k+1) is the first time error value corresponding to the mth subchannel in the first sampling period; Δt _m (k) is before the first sampling period The time error value corresponding to the mth subchannel within the sampling period; Δt_esti _m is the time error estimate of the mth subchannel.

Optionally, in another implementation manner of the first aspect, the first subchannel is the first time error value corresponding to the first subchannel in the M first time error values. Any one of the M sub-channels, the first sub-channel includes a first analog clock circuit and a first ADC; the error compensation distribution unit is specifically configured to:

Determining whether a difference between the first time error value and an analog domain compensation value of the first analog clock circuit in the second sampling period is smaller than an adjustment step of the first analog clock circuit;

And determining, if the difference between the first time error value and the analog domain compensation value of the first analog clock circuit in the second sampling period is smaller than the adjustment step size of the first analog clock circuit, Analog domain compensation value of the first analog clock during a sampling period As an analog domain compensation value of the first analog clock in the first sampling period, and obtaining an analog domain compensation value of the first analog clock according to the first time error value and the first sampling period a digital domain compensation value of the first subchannel in the first sampling period;

If it is determined that the difference between the first time error value and the analog domain compensation value of the first analog clock circuit in the second sampling period is not less than the adjustment step of the first analog clock circuit, according to the first simulation Adjusting step size of the circuit, the correction value, and the analog compensation value of the first analog clock circuit in the second sampling period to obtain an analog domain compensation value of the first analog clock circuit in the first sampling period, and according to The first time error value and the analog domain compensation value of the first analog clock in the first sampling period obtain a digital domain compensation value of the first subchannel in the first sampling period.

Specifically, according to the formula

Obtaining an analog domain compensation value and a digital domain compensation value of the mth subchannel in the k+1th sampling period;

Wherein k is an integer greater than or equal to 0; Δt_Astep _m is an adjustment step of the mth analog clock circuit, α is a correction value of an adjustment step of the mth analog clock circuit, and Δt_a _m (k) is the kth The analog domain compensation value of the mth analog clock circuit in one sampling period, Δt _m (k+1) is the time error value of the mth subchannel in the k+1th sampling period; Δt_a _m (k+1) is the first The analog domain compensation value of the mth analog clock circuit in k+1 sampling periods; Δt_d _m (k+1) is the digital compensation value of the mth subchannel in the k+1th sampling period.

In a second aspect, an embodiment of the present invention provides a calibration method for correcting a time error generated by an alternate analog-to-digital converter TIADC, where the TIADC includes: M sample/hold circuits, and the M sample/hold circuits The clock control terminals are connected to the M analog clock circuits and the M analog-to-digital converter ADCs connected to the output terminals of the M sample/hold circuits in one-to-one correspondence with the output terminals of the M ADCs. Data selection The M is an integer greater than or equal to 2; the M sample/hold circuits and the M ADCs are in one-to-one correspondence to form M sub-channels; the method may include:

Obtaining M first time error values corresponding to the M subchannels in a first sampling period;

And processing the M first time error values according to a preset compensation strategy, and acquiring M sets of compensation values corresponding to the M first time error values; each set of compensation values includes: one analog domain compensation Value and a digital domain compensation value;

Adjusting, according to the M analog domain compensation values of the M sets of compensation values, sampling timings of the M analog clock circuits in the first sampling period, so that the sampling/holding circuit connected to the analog clock circuit is Sampling the input analog signal by the sampling time after the adjustment of the analog clock circuit;

And adjusting, according to the M digital domain compensation values in the M group compensation values, the digital signals output by the M channel subchannels.

In this way, the compensation distribution is performed according to the time error value, the reasonable analog domain compensation value and the digital domain compensation value are allocated, and the analog domain compensation and the digital domain compensation are performed according to the allocated analog domain compensation value and the digital domain compensation value, and the hybrid domain compensation mode is adopted. Correcting the time error of TIADC, independent of single analog or digital domain compensation, making full use of the advantages of analog domain suitable for large step size rough correction and digital domain suitable for small step size high precision correction, organic combination of analog and digital correction, The ability to achieve optimal time error correction with minimal power and resource overhead.

Optionally, in an implementation manner of the second aspect, for any one of the M subchannels, the acquiring a time error value of the subchannel in a first sampling period:

Recording a second time error value of the subchannel and a time error estimation value in a second sampling period; the second sampling period is a previous sampling period adjacent to the first sampling period;

And obtaining a first time error value of the subchannel according to the time error estimation value and the first two time error value.

Optionally, in another implementation manner of the second aspect, for the M a first time error value corresponding to the first sub-channel in a time error value, the first sub-channel is any one of the M sub-channels, and the first sub-channel includes a first analog clock circuit and The first ADC is configured to process the first time error value according to a preset compensation strategy, and acquiring a set of compensation values corresponding to the first time error value specifically includes:

Determining whether a difference between the first time error value and an analog domain compensation value of the first analog clock circuit in the second sampling period is smaller than an adjustment step of the first analog clock circuit;

And determining, if the difference between the first time error value and the analog domain compensation value of the first analog clock circuit in the second sampling period is smaller than the adjustment step size of the first analog clock circuit, An analog domain compensation value of the first analog clock in a sampling period as an analog domain compensation value of the first analog clock in the first sampling period, and according to the first time error value and the first sampling period The analog domain compensation value of the first analog clock is obtained as a digital domain compensation value of the first subchannel in the first sampling period;

If it is determined that the difference between the first time error value and the analog domain compensation value of the first analog clock circuit in the second sampling period is not less than the adjustment step of the first analog clock circuit, according to the first simulation Adjusting step size of the circuit, the correction value, and the analog compensation value of the first analog clock circuit in the second sampling period to obtain an analog domain compensation value of the first analog clock circuit in the first sampling period, and according to The first time error value and the analog domain compensation value of the first analog clock in the first sampling period obtain a digital domain compensation value of the first subchannel in the first sampling period.

Specifically, according to the formula

Obtaining an analog domain compensation value and a digital domain compensation value of the mth subchannel in the k+1th sampling period;

Wherein k is an integer greater than or equal to 0; Δt_Astep _m is an adjustment step of the mth analog clock circuit, and α is a correction value of an adjustment step of the mth analog clock circuit, and Δt_a _m (k) is k The analog domain compensation value of the mth analog clock circuit in one sampling period, Δt _m (k+1) is the time error value of the mth subchannel in the k+1th sampling period; Δt_a _m (k+1) is the first The analog domain compensation value of the mth analog clock circuit in k+1 sampling periods; Δt_d _m (k+1) is the digital compensation value of the mth subchannel in the k+1th sampling period.

As can be seen from the above, an embodiment of the present invention provides a calibration apparatus and method, including: M sample/hold circuits, M analog clock circuits connected in one-to-one correspondence with clock control terminals of the M sample/hold circuits, and Outputs of the M sample/hold circuits are connected to the M analog-to-digital converters ADC, the data selectors MUX connected to the outputs of the M ADCs, and the time connected to the outputs of the MUXs An error digital compensation unit, a time error estimation unit coupled to an output of the time error digital compensation unit, an error compensation distribution unit coupled to an output of the time error estimation unit, the error compensation distribution unit and the time The error digital compensation unit is connected to the M sample/hold circuits; the M is an integer greater than or equal to 2; the M sample/hold circuits and the M ADCs are one-to-one corresponding to the M sub-channels; The error estimating unit estimates the time error value of each subchannel, and the error compensation assigning unit performs compensation allocation according to the time error value, and allocates a reasonable analog domain compensation value and a digital domain compensation value. The analog domain compensation and digital domain compensation are performed according to the assigned analog domain compensation value and the digital domain compensation value. The time error of the TIADC is corrected by the hybrid domain compensation method, and the simulation domain is not dependent on a single analog or digital domain compensation. The step size rough correction and the digital domain are suitable for small step size and high precision correction. The organic combination of analog and digital correction enables the device to achieve optimal time error correction with minimal power consumption and resource overhead.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and can be used by those skilled in the art without creative efforts. Other figures are obtained from these figures.

Figure 1 is a system block diagram of an existing TIADC;

2 is a schematic diagram of a conventional time domain compensation method for correcting TIADC time;

3 is a structural diagram of a calibration apparatus according to an embodiment of the present invention;

FIG. 4 is a flowchart of a calibration method according to an embodiment of the present invention.

detailed description

The core idea of the invention is that the analog domain compensation value and the digital domain compensation value are reasonably allocated according to the estimated time error value, the analog domain error correction is performed by using the analog domain compensation value, and the digital domain error correction is performed by using the digital domain compensation value. Compared with the existing single analog domain or digital domain correction, the invention does not rely on high-precision compensation of analog circuits, and does not require a digital compensation circuit with large resource consumption, and solves the problem that it is difficult to achieve high-precision time error compensation under low power consumption.

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

In the description of the present invention, it is to be understood that the system or element indicated by the terms "first", "second", "another" or the like is a system or component having a function described based on the embodiments, only for the purpose of The invention is not limited by the description, and is not intended to be a limitation of the invention.

FIG. 3 is a structural diagram of a calibration apparatus 10 according to an embodiment of the present invention. As shown in FIG. 3, the calibration apparatus 10 may include: M sample/hold (S/H) circuits, and M analog-to-digital circuits 101 connected to the clock control terminals of the M sample/hold circuits 102, and M analog-to-digital converters (Analog) connected one-to-one with the output terminals of the M sample/hold circuits 102 To Digital Converter, ADC 103), a data selector (MUX) 104 connected to the output of the M ADCs 103, and a time connected to the output of the MUX 104 An error digital compensation unit 105, a time error estimation unit 106 connected to the output of the time error digital compensation unit 105, and an error compensation distribution unit 107 connected to the output of the time error estimation unit 106, the error compensation allocation The unit 107 is connected to the time error digital compensation unit 105 and the M sample/hold circuits 102; the M is an integer greater than or equal to 2; the M sample/hold circuits 102 and the M ADCs 103 are one by one. Corresponding to form M sub-channels.

It should be noted that the time error digital compensation unit 105, the time error estimation unit 106, and the error compensation distribution unit 107 described in FIG. 3 may be integrated into a single correction unit for correcting the time error generated by the existing TIADC. As shown in FIG. 1 , the unit constituting the TIADC is integrated as a calibration device, and the time error generated by the TIADC in the device is corrected. This embodiment of the present invention is not limited thereto. The correction device will be described as an example.

The time error estimating unit 106 is configured to acquire M first time error values that are in one-to-one correspondence with the M sub-channels in a first sampling period, and output the M first to the error compensation allocating unit 107. Time error value.

In the embodiment of the present invention, the M sample/hold circuits 102 alternately sample the input analog signal at equal or non-equal intervals, from the first sample/hold circuit to the Mth sample. The / hold circuit is sampled once for one round of sampling, that is, one round of sampling includes M sampling moments, and after the round of sampling is completed, the next round of sampling is performed in turn, and the first sampling period can be any sampling period, each sampling The period may include a plurality of rounds of samples, each of which is generated by an analog clock circuit 101 for causing the sample/hold circuit 102 connected to the analog clock circuit 101 to sample the input analog signal using the sampling timing generated by the analog clock circuit 101. .

The first time error value may be a value obtained by estimating the time error of the digital signal processed by the sample/hold circuit 102 and the ADC 103 of the subchannel in the current sampling period before the first sampling period.

The error compensation distribution unit 107 is configured to process the M first time error values according to a preset compensation strategy, respectively, to obtain M sets of compensation values corresponding to the M first time error values; each group The compensation value includes: an analog domain compensation value and a Digital domain compensation value;

Transmitting, to the M analog clock circuits 101, the M analog domain compensation values of the M sets of compensation values, and transmitting the M digital domain compensation values of the M sets of compensation values to the time Error digital compensation unit 105.

The compensation strategy is used to properly allocate the analog domain compensation value and the digital domain compensation value, and the execution of the compensation strategy may be set as needed, which is not limited by the embodiment of the present invention.

For example, if the calibration device includes four sub-channels, wherein the sub-channel 1 corresponds to a time error value, and the first group of compensation values is obtained according to the time error value, the analog domain compensation value in the first group of compensation values can be sent to The analog clock circuit 101 in the sub-channel 1 transmits the digital domain compensation value in the first set of compensation values to the time error digital compensation unit 105, and the digital signal outputted by the time error digital compensation unit 105 to the MUX 104 is sub-channel. 1 The error of the processed signal is corrected.

Any one of the M analog clock circuits 101 for adjusting the sampling of the sample/hold circuit 102 connected to the analog clock circuit 101 in the first sampling period according to the received analog domain compensation value time.

Alternatively, the analog clock circuit 101 can use the analog compensation value to change the clock register of the sample/hold circuit 102 to adjust the sampling timing.

Any one of the M sample/hold circuits 102 for sampling the input analog signal according to the adjusted sampling time of the analog clock circuit 101, and outputting the sample to the ADC 103 after sampling signal of.

Optionally, the sample/hold circuit 102 can be configured to receive the input analog signal X(t), sample the value of the analog signal at discrete points by using the adjusted sampling time, and complete the conversion of the continuous time signal to the discrete time signal. .

Any one of the M ADCs 103 is configured to quantize and encode the received sampled signal, and output the processed signal to the MUX 104.

Among them, quantization and coding are prior art, and details are not described herein again.

The MUX 104 is configured to combine the M low-speed signals output by the M ADCs 103 into high-speed serial output digital signals, and compensate the time error digital Element 105 outputs the digital signal.

In the embodiment of the present invention, the M sample/hold circuits 102 alternately sample the input analog signals at equal or non-equal intervals, so that the M subchannels are received by the MUX 104 in one sampling period. The processed digital signals have a sequential order in time. Therefore, combining the M signals output by the M ADCs 103 into a set of digital signals may be: aligning the M signals output by the M ADCs 103 in chronological order.

The time error digital compensation unit 105 is configured to perform error compensation on the M channel signals in the digital signal according to the M digital domain compensation values output by the time error compensation distribution unit 107, and output compensation After the digital signal.

Optionally, the time error digital compensation unit 105 may be configured to calculate M sets of multi-tap digital filter coefficients according to the digital compensation value, and perform convolution operation on the M-channel signals and the obtained multi-tap digital filter coefficients to implement digital Compensation for errors.

Further, for the first time error value of any subchannel, the time error estimating unit 106 may specifically be used to:

Recording a second time error value of the subchannel and a time error estimation value in a second sampling period; the second sampling period is a previous sampling period adjacent to the first sampling period;

And obtaining a first time error value of the subchannel according to the second time error value and the time error estimate.

Specifically, the time error value in the current sampling period can be obtained in an iterative manner according to the time error estimation value in the previous sampling period. For example, the time error estimating unit 106 can be used to:

Obtaining a first time error value corresponding to the subchannel during the first sampling period according to the formula Δt _m (k+1)=Δt _m (k)+Δt_esti _m ,

Wherein m takes any value from 1 to M, and Δt _m (k+1) is the first time error value corresponding to the mth subchannel in the first sampling period; Δt _m (k) is before the first sampling period The time error value corresponding to the mth subchannel within the sampling period; Δt_esti _m is the time error estimate of the mth subchannel.

Further, for the first time error value corresponding to the first subchannel of the M first time error values, the first subchannel is any one of the M subchannels, the first The subchannel includes a first analog clock circuit and a first ADC; the error compensation distribution unit 107 can be used to:

Determining whether a difference between the first time error value and an analog domain compensation value of the first analog clock circuit in the second sampling period is smaller than an adjustment step of the first analog clock circuit; the analog domain compensation value Obtained according to the analog domain compensation value;

And determining, if the difference between the first time error value and the analog domain compensation value of the first analog clock circuit in the second sampling period is smaller than the adjustment step size of the first analog clock circuit, An analog domain compensation value of the first analog clock in a sampling period as an analog domain compensation value of the first analog clock in the first sampling period, and according to the first time error value and the first sampling period The analog domain compensation value of the first analog clock is obtained by the digital domain compensation value of the first subchannel in the first sampling period; that is, according to the formula:

Obtaining the analog domain compensation value and the digital domain compensation value;

Wherein k is an integer greater than or equal to 0; Δt_a _m (k) is an analog domain compensation value of the mth analog clock circuit in the kth sampling period, and Δt _m (k+1) is the k+1th sample The time error value of the mth subchannel in the period; Δt_a _m (k+1) is the analog domain compensation value of the mth analog clock circuit in the k+1th sampling period.

Determining, if the difference between the first time error value and the analog domain compensation value of the first analog clock circuit in the second sampling period is not less than the adjustment of the first analog clock circuit a step size, the first analog clock in the first sampling period is obtained according to an adjustment step size of the first analog circuit, a correction value, and an analog compensation value of the first analog clock circuit in the second sampling period An analog domain compensation value of the circuit, and obtaining the first subchannel in the first sampling period according to the first time error value and an analog domain compensation value of the first analog clock in the first sampling period Digital domain compensation value.

Specifically, when determining that the difference between the first time error value of the mth subchannel and the analog domain compensation value of the mth analog clock circuit in the second sampling period is not less than the adjustment step of the mth analog clock circuit The mth analog clock circuit is configured to control a sampling moment of the mth sample/hold circuit of the mth subchannel, wherein the m takes any one of 1 to M, and the error compensation unit Can be used for:

According to the formula

Obtaining an analog domain compensation value and a digital domain compensation value of the mth subchannel in the k+1th sampling period;

Wherein k is an integer greater than or equal to 0; Δt_Astep _m is the mth adjustment step, α is a correction value of the mth adjustment step, and Δt_a _m (k) is the _mth in the kth sampling period The analog domain compensation value of the analog clock circuit, Δt _m (k+1) is the time error value of the mth subchannel in the k+1th sampling period; Δt_a _m (k+1) is the k+1th sampling period The analog domain compensation value of the mth analog clock circuit; Δt_d _m (k+1) is the digital compensation value of the mth subchannel in the k+1th sampling period.

The correction value may be a fixed preset value, and may be obtained by querying an adjustment step of the analog clock circuit, a correspondence table between the currently obtained time error value and the correction value, which is not limited by the embodiment of the present invention. .

It should be noted that the adjustment step of the analog clock circuit 101 may be set to a fixed value according to the requirement, or may be set to a changed value according to the currently obtained time error value, which is not limited in the embodiment of the present invention.

As can be seen from the above, an embodiment of the present invention provides a calibration apparatus, including: M sample/hold circuits, M analog clock circuits connected in one-to-one correspondence with clock control terminals of the M sample/hold circuits, and M analog-to-digital converter ADCs connected one by one to the output of the M sample/hold circuits, a data selector MUX connected to the output of the M ADCs, and a time error number connected to the output of the MUX a compensation unit, a time error estimation unit connected to an output of the time error digital compensation unit, an error compensation distribution unit connected to an output of the time error estimation unit, the error compensation distribution unit and the time error number a compensation unit is connected to the M sample/hold circuits; the M is an integer greater than or equal to 2; the M sample/hold circuits and the M ADCs are one-to-one corresponding to the M sub-channels; The unit estimation calculates the time error value of each sub-channel, and the error compensation distribution unit compensates the time error value, and allocates a reasonable analog domain compensation value and a digital domain compensation value. The analog domain compensation and digital domain compensation are performed according to the assigned analog domain compensation value and the digital domain compensation value. The time error of the TIADC is corrected by the hybrid domain compensation method, and the simulation domain is not dependent on a single analog or digital domain compensation. The step size rough correction and the digital domain are suitable for small step size and high precision correction. The organic combination of analog and digital correction enables the device to achieve optimal time error correction with minimal power consumption and resource overhead.

For ease of description, the following embodiment 1 shows and describes in detail the process of the data transmission method provided by the present invention, wherein the steps shown may also be performed in a computer system of a set of executable instructions. Moreover, although logical sequences are shown in the figures, in some cases the steps shown or described may be performed in a different order than the ones described herein.

4 is a calibration method for correcting a time error generated by an alternate analog-to-digital converter TIADC, where the TIADC includes: M sample/hold circuits, and the M sample/hold circuits The clock control terminals are connected to the M analog clock circuits and the M analog-to-digital converter ADCs connected to the output terminals of the M sample/hold circuits in one-to-one correspondence with the output terminals of the M ADCs. a data selector MUX; the M is an integer greater than or equal to 2; the M sample/hold circuits Forming M sub-channels corresponding to the M ADCs one by one; the sampling/holding circuit can be used for receiving the input analog signal X(t), and sampling the analog signal at discrete points by using the adjusted sampling time, Completing conversion of the continuous time signal to the discrete time signal; any one of the M ADCs for quantizing and encoding the received sampled signal, and outputting the processed signal to the MUX, An MUX, configured to combine the M low-speed signals output by the M ADCs into a high-speed serial output digital signal, and output the digital signal to the time error digital compensation unit; as shown in FIG. 4, the method Can include:

S101: Obtain M first time error values that are in one-to-one correspondence with the M sub-channels in the first sampling period.

Wherein, in the embodiment of the present invention, the M sample/hold circuits alternately sample the input analog signal at equal or non-equal intervals, from the first sample/hold circuit to the Mth sample/ The holding circuit is sampled once for one round of sampling, that is, one round of sampling includes M sampling moments, and after the round of sampling is completed, the next round of sampling is performed in turn, and the first sampling period may be any sampling period, each sampling period. Multiple rounds of sampling may be included, each sampling instant being generated by an analog clock circuit for causing the sample/hold circuit connected to the analog clock circuit to sample the incoming analog signal using the sampling instants generated by the analog clock circuit.

Further, for the first time error value of any sub-channel, the obtaining the first time error value of the sub-channel in the first sampling period may include:

Recording a second time error value of the subchannel and a time error estimation value in a second sampling period; the second sampling period is a previous sampling period adjacent to the first sampling period;

And obtaining a first time error value of the subchannel according to the second time error value and the time error estimate.

Specifically, the time error value in the current sampling period can be obtained in an iterative manner according to the time error estimation value in the previous sampling period, such as:

Obtaining a first time error value corresponding to the subchannel during the first sampling period according to the formula Δt _m (k+1)=Δt _m (k)+Δt_esti _m ,

Wherein m takes any value from 1 to M, and Δt _m (k+1) is the first time error value corresponding to the mth subchannel in the first sampling period; Δt _m (k) is before the first sampling period The time error value corresponding to the mth subchannel within the sampling period; Δt_esti _m is the time error estimate of the mth subchannel.

S102: processing the M first time error values according to a preset compensation strategy, and acquiring M sets of compensation values corresponding to the M first time error values; each set of compensation values includes: The domain compensation value and a digital domain compensation value.

The compensation strategy is used to properly allocate the analog domain compensation value and the digital domain compensation value, and the execution of the compensation strategy may be set as needed, which is not limited by the embodiment of the present invention.

Optionally, for the first time error value corresponding to the first subchannel of the M first time error values, the first subchannel is any one of the M subchannels, where the a sub-channel includes a first analog clock circuit and a first ADC; the first time error value is processed according to a preset compensation strategy, and acquiring a set of compensation values corresponding to the first time error value specifically includes :

Determining whether a difference between the first time error value and an analog domain compensation value of the first analog clock circuit in the second sampling period is smaller than an adjustment step of the first analog clock circuit; the analog domain compensation value Obtained according to the analog domain compensation value;

And determining, if the difference between the first time error value and the analog domain compensation value of the first analog clock circuit in the second sampling period is smaller than the adjustment step size of the first analog clock circuit, An analog domain compensation value of the first analog clock in a sampling period as an analog domain compensation value of the first analog clock in the first sampling period, and according to the first time error value and the first sampling period The analog domain compensation value of the first analog clock is obtained by the digital domain compensation value of the first subchannel in the first sampling period; that is, according to the formula:

Obtaining the analog domain compensation value and the digital domain compensation value;

Wherein k is an integer greater than or equal to 0; Δt_a _m (k) is an analog domain compensation value of the mth analog clock circuit in the kth sampling period, and Δt _m (k+1) is the k+1th sample The time error value of the mth subchannel in the period; Δt_a _m (k+1) is the analog domain compensation value of the mth analog clock circuit in the k+1th sampling period.

If it is determined that the difference between the first time error value and the analog domain compensation value of the first analog clock circuit in the second sampling period is not less than the adjustment step of the first analog clock circuit, according to the first simulation Adjusting step size of the circuit, the correction value, and the analog compensation value of the first analog clock circuit in the second sampling period to obtain an analog domain compensation value of the first analog clock circuit in the first sampling period, and according to The first time error value and the analog domain compensation value of the first analog clock in the first sampling period obtain a digital domain compensation value of the first subchannel in the first sampling period.

Specifically, when determining that the difference between the first time error value of the mth subchannel and the analog domain compensation value of the mth analog clock circuit in the second sampling period is not less than the adjustment step of the mth analog clock circuit The mth analog clock circuit is configured to control a sampling moment of the mth sample/hold circuit of the mth subchannel, where the m takes any one of 1 to M, according to the preset The compensation strategy is configured to process the first time error value of the mth subchannel, and obtaining a set of compensation values corresponding to the first time error value may include:

According to the formula

Obtaining an analog domain compensation value and a digital domain compensation value of the mth subchannel in the k+1th sampling period;

Wherein k is an integer greater than or equal to 0; Δt_Astep _m is an adjustment step of the mth analog clock circuit, and α is a correction value of an adjustment step of the mth analog clock circuit, and Δt_a _m (k) is k The analog domain compensation value of the mth analog clock circuit in one sampling period, Δt _m (k+1) is the time error value of the mth subchannel in the k+1th sampling period; Δt_a _m (k+1) is the first The analog domain compensation value of the mth analog clock circuit in k+1 sampling periods; Δt_d _m (k+1) is the digital compensation value of the mth subchannel in the k+1th sampling period.

The correction value may be a fixed preset value, and may be obtained by querying an adjustment step of the analog clock circuit, a correspondence table between the currently obtained time error value and the correction value, which is not limited by the embodiment of the present invention. .

It should be noted that the adjustment step of the analog clock circuit may be set to a fixed value according to the requirement, or may be set to a changed value according to the currently obtained time error value, which is not limited in this embodiment of the present invention.

S103: Adjust, according to the M analog domain compensation values of the M sets of compensation values, a sampling time of the M analog clock circuits in the first sampling period, so as to enable a sample/hold circuit connected to the analog clock circuit. The input analog signal is sampled according to the adjusted sampling time of the analog clock circuit.

S104: Perform error compensation on the M digital signals output by adjusting the M subchannels corresponding to the M digital domain compensation values in the M group compensation values, and output the compensated digital signals.

Optionally, the M-group multi-tap digital filter coefficients can be calculated according to the digital compensation value, and the M-channel signals are respectively convoluted with the obtained multi-tap digital filter coefficients to achieve digital error compensation.

As can be seen from the above, the embodiment of the present invention provides a method for correcting M first time error values corresponding to the M sub-channels in a first sampling period; respectively, the M times according to a preset compensation strategy The first time error value is processed to obtain M sets of compensation values corresponding to the M first time error values; each set of compensation values includes: an analog domain compensation value and a digital domain compensation value; The M analog domain compensation values in the group compensation values are correspondingly adjusted to the sampling moments of the M analog clock circuits in the first sampling period, so that the sampling/holding circuit connected to the analog clock circuit is based on The analog clock circuit adjusts the sampling time to sample the input analog signal; and according to the M digital domain compensation values in the M group of compensation values, respectively, error is performed on the M digital signals output by the M subchannels Compensate and output the compensated digital signal. In this way, the time error of the TIADC is corrected by the method of the hybrid domain compensation, and the single analog or digital domain compensation is not relied on, and the advantage of the analog domain for the large step length correction and the digital domain suitable for the small step length high precision correction is fully utilized. Combining analog and digital correction, the device is able to achieve optimal time error correction with minimal power consumption and resource overhead.

The above is only a specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention. It should be covered by the scope of the present invention. Therefore, the scope of the invention should be determined by the scope of the claims.

Claims (10)

1. A calibration apparatus, comprising: M sample/hold circuits, M analog clock circuits connected in one-to-one correspondence with clock control terminals of the M sample/hold circuits, and the M samples/holds The output terminals of the circuit are respectively connected to the M analog-to-digital converter ADCs, the data selector MUX connected to the output ends of the M ADCs, the time error digital compensation unit connected to the output end of the MUX, and the a time error estimating unit connected to an output end of the time error digital compensating unit, an error compensating and distributing unit connected to an output end of the time error estimating unit, the error compensating allocating unit and the time error digital compensating unit and M sampling/holding circuit connections; the M is an integer greater than or equal to 2; the M sampling/holding circuits and the M ADCs are one-to-one corresponding to form M sub-channels;

   The time error estimating unit is configured to calculate M first time error values corresponding to the M subchannels in a first sampling period, and output the M first time errors to the error compensation allocating unit value;

   The error compensation allocation unit is configured to process the M first time error values according to a preset compensation strategy, respectively, to obtain M sets of compensation values corresponding to the M first time error values; The value includes: an analog domain compensation value and a digital domain compensation value;

   Transmitting, to the M analog clock circuits, the M analog domain compensation values of the M sets of compensation values, and transmitting M digital domain compensation values of the M sets of compensation values to the time error Digital compensation unit;

   Any one of the M analog clock circuits, configured to adjust a sampling time of the sample/hold circuit connected to the analog clock circuit in the first sampling period according to the received analog domain compensation value;

   Any one of the M sample/hold circuits for sampling the input analog signal according to the adjusted sampling time of the analog clock circuit, and outputting the sampled signal to the ADC;

   Any one of the M ADCs, configured to quantize and encode the received sampled signal, and output the processed signal to the MUX;

   The MUX is configured to combine the M low-speed signals output by the M ADCs into a high-speed serial output digital signal, and output the digital signal to the time error digital compensation unit;

   The time error digital compensation unit is configured to compensate the M digital domain compensation values output by the distribution unit according to the time error, and perform error compensation on the M channel signals in the digital signal one by one, and output the compensated Digital signal.
2. The calibration apparatus according to claim 1, wherein for any one of the M subchannels, the time error estimating unit is specifically configured to:

   Recording a second time error value of the subchannel and a first time error estimation value in a second sampling period; the second sampling period is a previous sampling period adjacent to the first sampling period;

   And obtaining a first time error value of the subchannel according to the second time error value and the first time error estimate.
3. The calibration apparatus according to claim 1 or 2, wherein, for the first time error value corresponding to the first subchannel among the M first time error values, the first subchannel is the M Any one of the sub-channels, the first sub-channel includes a first analog clock circuit and a first ADC; the error compensation distribution unit is specifically configured to:

   Determining whether a difference between the first time error value and an analog domain compensation value of the first analog clock circuit in the second sampling period is smaller than an adjustment step of the first analog clock circuit; the analog domain compensation value Obtained according to the analog domain compensation value;

   And determining, if the difference between the first time error value and the analog domain compensation value of the first analog clock circuit in the second sampling period is smaller than the adjustment step size of the first analog clock circuit, An analog domain compensation value of the first analog clock in a sampling period as an analog domain compensation value of the first analog clock in the first sampling period, and according to the first time error value and the first sampling period The analog domain compensation value of the first analog clock is obtained as a digital domain compensation value of the first subchannel in the first sampling period;

   Determining, if the difference between the first time error value and the analog domain compensation value of the first analog clock circuit in the second sampling period is not less than the adjustment of the first analog clock circuit a step size, the first analog clock in the first sampling period is obtained according to an adjustment step size of the first analog circuit, a correction value, and an analog compensation value of the first analog clock circuit in the second sampling period An analog domain compensation value of the circuit, and obtaining the first subchannel in the first sampling period according to the first time error value and an analog domain compensation value of the first analog clock in the first sampling period Digital domain compensation value.
4. The correction apparatus according to claim 3, wherein said error compensation distribution unit determines a first time error value of the mth subchannel and an analog domain compensation of an mth analog clock circuit in said second sampling period When the difference of the values is not less than the adjustment step of the mth analog clock circuit, the mth analog clock circuit is configured to control a sampling moment of the mth sample/hold circuit of the mth subchannel, Let m take any value from 1 to M, and the error compensation unit is specifically used to:

   According to the formula

   

   Obtaining an analog domain compensation value and a digital domain compensation value of the mth subchannel in the k+1th sampling period;

   Wherein k is an integer greater than or equal to 0; Δt_Astep _m is an adjustment step of the mth analog clock circuit, and α is a correction value of an adjustment step of the mth analog clock circuit, and Δt_a _m (k) is The analog domain compensation value of the mth analog clock circuit in the kth sampling period, Δt _m (k+1) is the time error value of the mth subchannel in the k+1th sampling period; Δt_a _m (k+ 1) is the analog domain compensation value of the mth analog clock circuit in the k+1th sampling period; Δt_d _m (k+1) is the digital compensation value of the mth subchannel in the k+1th sampling period.
5. A correction device according to claim 4, wherein

   The correction value is a fixed preset value,

   Alternatively, the correction value is obtained by querying an adjustment step of the analog clock circuit, a correspondence table between the currently obtained time error value and the correction value.
6. A correction method for correcting the time produced by the alternate analog-to-digital converter TIADC Error, the TIADC includes: M sample/hold circuits, M analog clock circuits connected in one-to-one correspondence with clock control terminals of the M sample/hold circuits, and outputs of the M sample/hold circuits One-to-one connected M analog-to-digital converter ADCs, data selectors MUX connected to the outputs of the M ADCs; the M is an integer greater than or equal to 2; the M sample/hold circuits and the Each of the M ADCs is composed of M sub-channels; and the method includes:

   Obtaining M first time error values corresponding to the M subchannels in a first sampling period;

   And processing the M first time error values according to a preset compensation strategy, and acquiring M sets of compensation values corresponding to the M first time error values; each set of compensation values includes: one analog domain compensation Value and a digital domain compensation value;

   Adjusting, according to the M analog domain compensation values of the M sets of compensation values, sampling timings of the M analog clock circuits in the first sampling period, so that the sampling/holding circuit connected to the analog clock circuit is Sampling the input analog signal by the sampling time after the adjustment of the analog clock circuit;

   The M digital signals outputted by the M subchannels are correspondingly compensated according to the M digital domain compensation values of the M sets of compensation values, and the compensated digital signals are outputted.
7. The calibration method according to claim 6, wherein for any one of the M subchannels, the obtaining a time error value of the subchannel in a first sampling period:

   Recording a second time error value of the subchannel and a time error estimation value in a second sampling period; the second sampling period is a previous sampling period adjacent to the first sampling period;

   And obtaining a first time error value of the subchannel according to the second time error value and the time error estimate.
8. The calibration method according to claim 6 or 7, wherein the first subchannel is the M for the first time error value corresponding to the first subchannel of the M first time error values Any one of the sub-channels, the first sub-channel The first analog clock circuit and the first ADC are included; the processing the first time error value according to the preset compensation strategy, and acquiring a set of compensation values corresponding to the first time error value specifically includes:

   Determining whether a difference between the first time error value and an analog domain compensation value of the first analog clock circuit in the second sampling period is smaller than an adjustment step of the first analog clock circuit; the analog domain compensation value Obtained according to the analog domain compensation value;

   And determining, if the difference between the first time error value and the analog domain compensation value of the first analog clock circuit in the second sampling period is smaller than the adjustment step size of the first analog clock circuit, An analog domain compensation value of the first analog clock in a sampling period as an analog domain compensation value of the first analog clock in the first sampling period, and according to the first time error value and the first sampling period The analog domain compensation value of the first analog clock is obtained as a digital domain compensation value of the first subchannel in the first sampling period;

   If it is determined that the difference between the first time error value and the analog domain compensation value of the first analog clock circuit in the second sampling period is not less than the adjustment step of the first analog clock circuit, according to the first simulation Adjusting step size of the circuit, the correction value, and the analog compensation value of the first analog clock circuit in the second sampling period to obtain an analog domain compensation value of the first analog clock circuit in the first sampling period, and according to The first time error value and the analog domain compensation value of the first analog clock in the first sampling period obtain a digital domain compensation value of the first subchannel in the first sampling period.
9. The calibration method according to claim 8, wherein the difference between the first time error value of the mth subchannel and the analog domain compensation value of the mth analog clock circuit in the second sampling period is not less than When the adjustment step of the mth analog clock circuit is performed, the mth analog clock circuit is configured to control a sampling moment of the mth sample/hold circuit of the mth subchannel, where the m takes 1 to M The value of the first time error value of the mth sub-channel is processed according to a preset compensation strategy, and the acquiring a set of compensation values corresponding to the first time error value includes:

   According to the formula

   

   Obtaining an analog domain compensation value and a digital domain compensation value of the mth subchannel in the k+1th sampling period;

   Wherein k is an integer greater than or equal to 0; Δt_Astep _m is an adjustment step of the mth analog clock circuit, and α is a correction value of an adjustment step of the mth analog clock circuit, and Δt_a _m (k) is The analog domain compensation value of the mth analog clock circuit in the kth sampling period, Δt _m (k+1) is the time error value of the mth subchannel in the k+1th sampling period; Δt_a _m (k+ 1) is the analog domain compensation value of the mth analog clock circuit in the k+1th sampling period; Δt_d _m (k+1) is the digital compensation value of the mth subchannel in the k+1th sampling period.
10. The correction method according to claim 9, wherein

    The correction value is a fixed preset value,

    Alternatively, the correction value is obtained by querying an adjustment step of the analog clock circuit, a correspondence table between the currently obtained time error value and the correction value.

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