CN117081595A - Signal acquisition system, signal acquisition method and device - Google Patents
Signal acquisition system, signal acquisition method and device Download PDFInfo
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Abstract
The application relates to a signal acquisition system, a signal acquisition method and a signal acquisition device, wherein the method comprises the following steps: after the first target signal is input to the signal acquisition system, determining an amplitude value and a phase value of a second target signal output by each channel based on the processor; determining an amplitude compensation value based on the amplitude of each channel in the plurality of groups of channels and the amplitude of the target channel respectively, and determining a delay compensation value based on the delay corresponding to the phase of each channel in the plurality of groups of channels and the delay corresponding to the phase of the target channel respectively; setting a time interval between the ADCs based on a preset sampling frequency, determining sampling clock differences between the ADCs based on the time interval and a delay compensation value, and calibrating any channel except a target channel in a plurality of groups of channels based on the amplitude compensation value and the sampling clock differences; and inputting the signals to be acquired into each calibrated channel and target channel based on the power divider, and executing signal acquisition operation.
Description
Technical Field
The present application relates to the field of signal acquisition, and in particular, to a signal acquisition system, a signal acquisition method and a signal acquisition device.
Background
The high-speed data acquisition system needs to have extremely high sampling rate, and particularly in the occasion of instantaneous measurement and rapid change, the pulse signal acquisition system has the characteristics of rapid rise, short duration, large dynamic range, single unrepeatable property and the like. To meet these processing requirements, a flexible front-end conditioning module, low noise input, higher gain, and the ability to dynamically change the gain in response to input level changes without affecting performance while still maintaining a wide dynamic range are needed. Therefore, under the condition that the sampling speed and the sampling bit width of an ADC (Analog-to-Digital Converter) are limited, how to realize large dynamic range signal and large bandwidth signal acquisition is lacking in a flexible, economical, safe and reliable method.
Disclosure of Invention
The application provides a signal acquisition system, a signal acquisition method and a signal acquisition device, which are used for solving the problem that the acquisition of a signal with a large dynamic range and a signal with a large bandwidth cannot be realized under the condition that the sampling speed and the sampling bit width of an ADC (analog-to-digital converter) are limited in the prior art.
In a first aspect, the application provides a signal acquisition method based on a signal acquisition system, wherein the signal acquisition system comprises a power divider, a plurality of groups of channels respectively connected with the power divider and a processor connected with the plurality of groups of channels; each group of channels comprises two channels, one channel comprises an amplifying circuit and an ADC, and the other channel comprises a reducing circuit and the ADC; the method comprises the following steps: after a first target signal is input to the signal acquisition system, determining an amplitude value and a phase value of a second target signal output by each channel based on the processor; wherein the amplification factor of the amplifying circuit is consistent with the reduction factor of the reducing circuit; the initial sampling clocks fed back by the processor to the ADCs in the multiple groups of channels are consistent; determining an amplitude compensation value based on the amplitude of each channel in the plurality of groups of channels and the amplitude of the target channel respectively, and determining a delay compensation value based on the delay corresponding to the phase of each channel in the plurality of groups of channels and the delay corresponding to the phase of the target channel respectively; wherein the target channel is any one of the plurality of groups of channels; setting a time interval between the ADCs based on a preset sampling frequency, determining a sampling clock difference between the ADCs based on the time interval and the delay compensation value, and calibrating any channel except the target channel in the multiple groups of channels based on the amplitude compensation value and the sampling clock difference; inputting signals to be acquired into each calibrated channel and the target channel based on the power divider, and executing signal acquisition operation; inputting the signals to be acquired into each calibrated channel and the target channel based on the power divider, and executing the signal acquisition operation comprises the following steps: determining signals corresponding to each group of channels based on a comparison result of the amplitude of the signal to be acquired and a preset amplitude range; and signal splicing is carried out on the signals corresponding to each group of channels according to the sequence of the sampling clock, so that the acquired signals are obtained.
In a second aspect, the present application provides a signal acquisition device based on a signal acquisition system, the method comprising: the first determining module is used for determining the amplitude value and the phase value of the second target signal output by each channel after the first target signal is input to the signal acquisition system; wherein the amplification factor of the amplifying circuit is consistent with the reduction factor of the reducing circuit; the initial sampling clocks fed back by the processor to the ADCs in the multiple groups of channels are consistent; the second determining module is used for determining an amplitude compensation value based on the amplitude of each channel in the plurality of groups of channels and the amplitude of the target channel respectively, and determining a delay compensation value based on the delay corresponding to the phase of each channel in the plurality of groups of channels and the delay corresponding to the phase of the target channel respectively; wherein the target channel is any one of the plurality of groups of channels; the processing module is used for determining the time interval between the ADCs based on a preset sampling frequency, setting sampling clock differences between the ADCs based on the time interval and the delay compensation value, and calibrating any channel except the target channel in the multiple groups of channels based on the amplitude compensation value and the sampling clock differences; the sampling module is used for inputting signals to be acquired into each calibrated channel and the target channel based on the power divider, and executing signal acquisition operation; wherein, the sampling module includes: the determining unit is used for determining the signals corresponding to each group of channels based on the comparison result of the amplitude of the signals to be acquired and the preset amplitude range; and the splicing unit is used for carrying out signal splicing on the signals corresponding to each group of channels according to the sequence of the sampling clock to obtain the acquired signals.
In a third aspect, the application provides a signal acquisition system, which comprises a power divider, a plurality of groups of channels respectively connected with the power divider and a processor connected with the plurality of groups of channels; each group of channels comprises two channels, one channel comprises an amplifying circuit and an ADC, and the other channel comprises a reducing circuit and the ADC; wherein the amplification factor of the amplifying circuit is consistent with the reduction factor of the reducing circuit; the initial sampling clocks fed back by the processor to the ADCs in the multiple groups of channels are consistent; the processor is used for executing the following steps: after a first target signal is input to the signal acquisition system, determining an amplitude value and a phase value of a second target signal output by each channel; wherein the amplification factor of the amplifying circuit is consistent with the reduction factor of the reducing circuit; the initial sampling clocks fed back by the processor to the ADCs in the multiple groups of channels are consistent; determining an amplitude compensation value based on the amplitude of each channel in the plurality of groups of channels and the amplitude of the target channel respectively, and determining a delay compensation value based on the delay corresponding to the phase of each channel in the plurality of groups of channels and the delay corresponding to the phase of the target channel respectively; wherein the target channel is any one of the plurality of groups of channels; setting a time interval between the ADCs based on a preset sampling frequency, determining a sampling clock difference between the ADCs based on the time interval and the delay compensation value, and calibrating any channel except the target channel in the multiple groups of channels based on the amplitude compensation value and the sampling clock difference; inputting signals to be acquired into each calibrated channel and the target channel based on the power divider, and executing signal acquisition operation; inputting the signals to be acquired into each calibrated channel and the target channel based on the power divider, and executing the signal acquisition operation comprises the following steps: determining signals corresponding to each group of channels based on a comparison result of the amplitude of the signal to be acquired and a preset amplitude range; and signal splicing is carried out on the signals corresponding to each group of channels according to the sequence of the sampling clock, so that the acquired signals are obtained.
In a fourth aspect, the present application provides an electronic device, comprising: at least one communication interface; at least one bus connected to the at least one communication interface; at least one processor coupled to the at least one bus; at least one memory coupled to the at least one bus, wherein the processor is configured to perform the signal acquisition method of the first aspect of the present application.
In a fifth aspect, the present application further provides a computer storage medium storing computer executable instructions for performing the signal acquisition method according to the first aspect of the present application.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages: according to the method provided by the embodiment of the application, the signal acquisition system is provided with the plurality of channels, each channel comprises the ADC, after the plurality of channels are calibrated, the signals to be acquired are accurate based on the signals output by the plurality of ADCs after the calibrated channels are input by the power divider, so that the signals output by the plurality of ADCs can be acquired, and even if the current signals to be acquired are signals with a large dynamic range and a large bandwidth, the signals can be acquired by the method in the embodiment of the application under the condition that the sampling speed and the sampling bit width of the existing ADCs are not changed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
In order to more clearly illustrate the embodiments of the application or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.
Fig. 1 is a schematic structural diagram of a signal acquisition system according to an embodiment of the present application;
fig. 2 is a flowchart of a signal acquisition method based on a signal acquisition system according to an embodiment of the present application;
FIG. 3 is a schematic diagram of amplitude compensation of signals provided by an embodiment of the present application;
FIG. 4 is a schematic diagram of delay compensation of signals according to an embodiment of the present application;
FIG. 5 is a schematic diagram of an embodiment of the present application after stacking a plurality of ADCDE sampling signals;
fig. 6 is a schematic structural diagram of a signal acquisition device based on a signal acquisition system according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The following disclosure provides many different embodiments, or examples, for implementing different structures of the application. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
The embodiment of the application provides a signal acquisition system, as shown in figure 1, which comprises a power divider, a plurality of groups of channels respectively connected with the power divider and a processor connected with the plurality of groups of channels; each group of channels comprises two channels, one channel comprises an amplifying circuit and an ADC, and the other channel comprises a shrinking circuit and an ADC.
Based on the signal acquisition system in fig. 1, the embodiment of the application also provides a signal acquisition method based on the signal acquisition system, as shown in fig. 2, the steps of the method include:
step 201, after a first target signal is input to a signal acquisition system, determining an amplitude value and a phase value of a second target signal output by each channel based on a processor; the amplification times of the amplifying circuit are consistent with the reduction times of the reducing circuit; the initial sampling clock fed back by the processor to each ADC in the multiple groups of channels is consistent;
it should be noted that, in the embodiment of the present application, the first target signal may be a sine signal, a cosine signal, or other signals in a specific example. The type of the first target signal may be set according to specific requirements, for example, the first target signal is a sinusoidal signal, and then the output second target signal is also a sinusoidal signal, so that the amplitude value and the phase value of the second target signal need to be determined.
In addition, the signal acquisition system in the embodiment of the present application includes multiple groups of channels, each group of channels includes an amplifying circuit and a reducing circuit, where the amplifying times of all amplifying circuits in the multiple groups of channels on the signal are consistent, for example, D, and the reducing times of all reducing circuits on the signal are also consistent, for example, E.
In this regard, in the embodiment of the present application, the adjustment of the amplification factor of the amplifying circuit and the reduction factor of the reducing circuit to uniform parameters and the adjustment of the sampling clocks fed back by the processor to the ADCs in the multiple groups of channels are to ensure that the same signal can be acquired from different channels, that is, the amplitude Ampi and the phase θi of the signal acquired from the processor are uniform.
Step 202, determining an amplitude compensation value based on the amplitude of each channel in the plurality of groups of channels and the amplitude of the target channel respectively, and determining a delay compensation value based on the delay corresponding to the phase of each channel in the plurality of groups of channels and the delay corresponding to the phase of the target channel respectively; wherein the target channel is any channel in a plurality of groups of channels;
it should be noted that, even after the amplification factor of the amplifying circuit and the reduction factor of the reducing circuit are adjusted to be uniform parameters in the embodiment of the present application, the signals of the channels acquired in the processor may still have differences due to the differences of hardware. Therefore, in the embodiment of the application, any one of the multiple groups of channels is used as a reference channel (target channel), and the amplitude and phase adjustment of other channels are consistent with those of the reference channel, so that the amplitude Ampi and the phase θi of all the channel signals acquired in the processor can be further consistent.
Step 203, determining a time interval between the ADCs based on a preset sampling frequency, determining a sampling clock difference between the ADCs based on the time interval and a delay compensation value, and calibrating any channel except a target channel in the multiple groups of channels based on the amplitude compensation value and the sampling clock difference;
and 204, inputting the signals to be acquired into each calibrated channel and target channel based on the power divider, and executing signal acquisition operation.
It should be noted that, in the embodiment of the present application, the signal to be collected may be set correspondingly according to the requirement, for example, the signal to be collected is a signal with a large dynamic range and a large bandwidth.
Through steps 201 to 204, the signal acquisition system is provided with a plurality of channels, each channel comprises an ADC, after the channels are calibrated, the signals to be acquired are accurate based on the signals output by the ADCs after the calibrated channels are input by the power divider, so that the signals output by the ADCs can be acquired, and even if the current signals to be acquired are large dynamic range and large bandwidth signals, the signals can still be acquired by the method in the embodiment of the application without changing the sampling speed and sampling bit width of the existing ADCs.
In an optional implementation manner of the embodiment of the present application, for the manner of determining the amplitude compensation value based on the amplitude of each channel in the plurality of groups of channels and the amplitude of the target channel in step 202 in the embodiment of the present application, the method further may include: determining the ratio of the amplitude of each channel to the amplitude of the target channel as an amplitude compensation value;
in this regard, in a specific example, if the amplitude compensation value of the signal is to be calculated, the difference in hardware amplitude between the channels is to be known. In the embodiment of the present application, when the parameters of the channels are consistent, the same signal (first target signal) is input, and the received signal (second target signal) is compared and calculated in the processor to obtain an amplitude compensation value, specifically, as shown in fig. 3, after the same signal passes through two channels in the same group of channels, because of the difference of hardware, if the amplitude of the signal of the processor receiving channel 1 (including the channel of the amplifying circuit) is Amp1, the amplitude of the signal of the receiving channel 2 (including the channel of the reducing circuit) is Amp2, in the processor, if the channel 1 is taken as the reference signal, the signal of the channel 1 is not compensated, and in order to make the amplitude of the signal of the channel 2 consistent with the amplitude of the signal of the channel 1, that is, if Amp 4=amp 1, the signal of the channel 2 needs to be multiplied by the amplitude compensation value AC 1/Amp2, and the amplitude of the output signal is consistent with the amplitude of the channel 1.
Further, the calculation of the amplitude may be that when the input calibration signal is a sinusoidal signal, the capability of the received signal may be obtained by using an energy formula, so as to obtain the power of the signal, and finally obtain the amplitude of the received signal. The specific calculation process is as follows: 1) Carrying out Fourier transform on the sampling signal X [ N ] to obtain frequency domain data X [ K ], wherein K is a frequency index value, the range is 0-N-1, and N is the number of sampling points; 2) Amplitude calculation: amplitude information of the sinusoidal signal, i.e., amplitude a of the sinusoidal signal, is extracted from the frequency domain data X k. A=sqrt (X [0] ] 2+x [ N/2] ] 2, wherein sqrt represents a square root operation and; 3) Final amplitude value: dividing the calculated amplitude A by the sampling frequency to obtain the amplitude value of the sinusoidal signal.
In an optional implementation manner of the embodiment of the present application, the method for determining the delay compensation value based on the delay corresponding to each channel phase in the plurality of groups of channels and the delay corresponding to the target channel phase in step 202 in the embodiment of the present application further may include: and determining the difference value between the delay corresponding to each channel phase and the delay corresponding to the target channel phase as a delay compensation value.
In this regard, in a specific example, if the delay compensation value of the signal is to be calculated, the difference of hardware delay between the channels is to be known, specifically by: under the condition that parameters of all channels are consistent, the same signal is input, and the received signal is compared and calculated in a processor to obtain a delay compensation value. Specifically, as shown in fig. 4, taking two channels as an example, after the same signal passes through the two channels, due to the difference of hardware, there are amplitude differences and delay differences, after the amplitude compensation, the amplitudes of the two signals are compensated to a consistent level, and then the delay of the two signals is adjusted to be consistent through precise delay compensation of the signals. As shown in fig. 4, the channel 1 (channel including the amplifying circuit) signal is delayed by a time t with respect to the channel 2 (channel including the reducing circuit), in which case, the delay of the channel 2 data is delayed by t, so that the delay of the channel 1 and channel 2 signals is consistent.
Further, the phase difference is the difference in phase angle between two co-frequency signals. Specifically, the method can be calculated by the following steps: 1) Two sinusoidal signals are provided, x (t) and y (t) respectively, wherein the amplitudes are respectively A1 and A2, the frequencies are respectively f1 and f2, and the phases are respectively theta 1 and theta 2. 2) The two signals are subjected to differential operation to obtain a differential signal z (t) =x (t) -y (t). 3) Fourier transforming the differential signal to obtain a spectrum Z (f) =x (f) ×x (f); wherein X (f) and X× (f) are the Fourier transforms of X (t) and its conjugate function, respectively. 4) Extracting phase information from the spectrum Z (f), that is, calculating a phase difference θ=arctan (Im (Z (f))/Re (Z (f))); by the above way, a phase difference of two sinusoidal signals can be obtained, and thus a corresponding delay difference can be obtained.
In an alternative implementation manner of the embodiment of the present application, for the manner of setting the time interval between the ADCs based on the preset sampling frequency and determining the sampling clock difference between the ADCs based on the time interval and the delay compensation value in the step 203, the method may further include:
step 11, determining the ratio of 1 to a preset sampling frequency as a time interval;
step 12, determining the ADC sampling clock difference in the nth set of channels relative to the ADC in the 1 st set of channels by the following formula:
T=(N-1)τ+θCi
wherein T is sampling clock difference, tau is time interval, thetaCi is delay compensation value, and N is positive integer.
For the above steps 11 and 12, in a specific example, if the signal sampling rate to be achieved is f and the sampling frequency of the ADC chip is fs, the sampling frequency of each ADC chip needs to be respectively different by a time interval τ (τ=1/f), that is, the sampling clock phases of the ADC chips from the 2 nd group to the nth group are sequentially delayed by τ, 2τ, …, (N-1) τ relative to the 1 st group, each ADC converter and its sampling holder collect signals at different moments of the same signal and can meet the sampling frequency f, specifically, as shown in fig. 5, after the phase difference between two adjacent ADC chips is a time interval τ, the signals collected by the corresponding sampling clocks of each sampling signal may be overlapped, and the processed sampling signals are consistent with the original signals.
In an optional implementation manner of the embodiment of the present application, for each channel and the target channel after the calibration of the input signal to be acquired based on the power divider in the step 204, the manner of performing the signal acquisition operation may further include:
step 21, determining signals corresponding to each group of channels based on a comparison result of the amplitude of the signal to be acquired and a preset amplitude range;
and step 22, signal splicing is carried out on the signals corresponding to each group of channels according to the sequence of the sampling clock, and the acquired signals are obtained.
As can be seen from the above steps 21 and 22, in the embodiment of the present application, the signal corresponding to each group of channels may be determined according to the comparison result between the amplitude of the signal to be collected and the preset amplitude range, that is, if the amplitude of the signal to be collected is smaller, the signal corresponding to the channel of the amplifying circuit is taken, if the amplitude of the signal to be collected is larger, the signal corresponding to the reducing circuit is taken, and if the amplitude of the signal to be collected is within the preset range, the two channels need to be fused, so that the complete signal can be obtained. Specifically, for the comparison result of the amplitude of the signal to be acquired and the preset amplitude range in the step 21, the determining the signal corresponding to each group of channels may further include:
Step 31, determining the signals output by the amplifying circuit and the ADC in each group of channels as fusion signals of the group of channels under the condition that the amplitude of the signals to be acquired is smaller than a first preset threshold;
step 32, determining the signals output by the reduction circuit and the ADC in each group of channels as fusion signals of the group of channels under the condition that the amplitude of the signals to be acquired is greater than a second preset threshold;
step 33, determining the sum of the first signal and the second signal of each group of channels as a fusion signal of the group of channels when the amplitude of the signal to be acquired is greater than or equal to a first preset threshold value and less than or equal to a second preset threshold value; the first signal is the ratio result of the signal output by the amplifying circuit and the ADC in the multiple groups of channels and the amplifying multiple of the amplifying circuit, and the second signal is the product result of the signal output by the amplifying circuit and the ADC in the multiple groups of channels and the reducing multiple of the reducing circuit; the first preset threshold is the minimum value in the preset amplitude range, and the second preset threshold is the maximum value in the preset amplitude range.
For the steps 31 to 33, in a specific example with reference to fig. 1, taking the signal to be sampled as a large bandwidth and a large dynamic signal Sig as an example, dividing Sig work into N groups of 2 paths of identical signals, each path of signals being represented by SigNi, where N represents the number of groups and i represents the number of sequences in the groups (i=1 to 2); amplifying the 1 st path of signals of each group by D times through respective amplifying circuits to obtain a signal ASIGN1; the 2 nd path of signals of each group of signals are reduced by E times through respective reduction circuits, and a signal ASIGN2 is obtained; each group of signals and each path of signals are processed by a corresponding ADC chip (the sampling clock of the ADC chip is processed by a processor according to the clock difference obtained during calibration, and then the signals are collected to obtain a discrete signal XSigNIp, wherein P represents the serial number of the sampling point;
And synthesizing each group of signals according to a follow-up rule in a processor to obtain a fused signal RSigNp. Synthesis rule:
if Sig < V1 (V1 corresponds to a first preset threshold), then each group of 1 st signals is taken out, such that rsignp=xsign1. When Sig is smaller than V1, it means that the amplitude of the signal received at this time is smaller, and after the input signal passes through the amplifying circuit, the output signal still does not reach the threshold value V1, and at this time, the first path signal (the signal after passing through the path including the amplifying circuit) is taken, so that the complete signal can be obtained.
If Sig > V2 (V2 corresponds to a second preset threshold), then each group of 2 nd signals is taken out, such that rsignp=xsign2. When Sig > V2, the amplitude of the input signal is larger, the signal still exceeds the threshold after being reduced, and the second path of signal (the signal after the path comprising the reduction circuit) is taken at the moment, so that the complete signal can be obtained.
If V1 < Sig < V2, then each set of 2-way signals is taken out for computation such that RSigNp=XSigN1/D+XSigN2×E. When V1 is less than Sig and less than V2, two paths of signals are required to be fused to obtain a complete signal.
In an alternative implementation manner of the embodiment of the present application, based on the steps 31 to 33, signal splicing is performed on the signals corresponding to each group of channels in the step 22 according to the sequence of sampling clocks, where the obtaining the collected signals includes: and splicing the obtained fusion signals according to the sequence of the sampling clock to obtain the acquired signals.
Taking the examples in the steps 31 to 33 as an example, the acquired fusion signal is rsign P, that is, RSig1P, RSig2P, …, and rsign np performs signal splicing according to the relation of sampling clock phases to complete the acquisition of the large bandwidth and large dynamic signal. In the embodiment of the application, the signal is spliced according to the relation of sampling clock phases to complete the acquisition of large bandwidth and large dynamic signals, for example, RSig1P, RSig2P, … and RsigNP are spliced according to time sequence based on the sampling signals, for example, the signals are obtained by fusion after being sampled according to time sequence, then RSig1P and RSig2P are spliced first, then RSig3P is spliced onto the spliced RSig1P and RSig2P, and the like until the RsigNP is spliced.
Corresponding to fig. 2, the embodiment of the present application further provides a signal acquisition device based on a signal acquisition system, as shown in fig. 6, where the device includes:
a first determining module 602, configured to determine an amplitude value and a phase value of a second target signal output by each channel after inputting the first target signal to the signal acquisition system; the amplification times of the amplifying circuit are consistent with the reduction times of the reducing circuit; the initial sampling clock fed back by the processor to each ADC in the multiple groups of channels is consistent;
A second determining module 604, configured to determine an amplitude compensation value based on the amplitude of each channel in the multiple groups of channels and the amplitude of the target channel, and determine a delay compensation value based on the delay corresponding to each channel phase in the multiple groups of channels and the delay corresponding to the target channel phase; wherein the target channel is any channel in a plurality of groups of channels;
the processing module 606 is configured to set a time interval between the ADCs based on a preset sampling frequency, determine a sampling clock difference between the ADCs based on the time interval and the delay compensation value, and calibrate any channel of the multiple groups of channels except for the target channel based on the amplitude compensation value and the sampling clock difference;
the sampling module 608 is configured to input the signal to be collected into each of the calibrated channels and the target channel based on the power divider, and perform a signal collection operation.
By means of the device, the signal acquisition system is provided with the multiple channels, each channel comprises the ADC, after the multiple channels are calibrated, signals to be acquired are accurately output by the multiple ADCs after the signals to be acquired are input into the calibrated channels based on the power divider, and therefore the signals output by the multiple ADCs can be acquired, and even if the signals to be acquired currently are signals with large dynamic range and large bandwidth, the signals can still be acquired by the mode in the embodiment of the application under the condition that the sampling speed and the sampling bit width of the existing ADCs are not changed.
In an alternative implementation manner of the embodiment of the present application, the acquisition module 608 in the embodiment of the present application may further include: the determining unit is used for determining the signals corresponding to each group of channels based on the comparison result of the amplitude of the signals to be acquired and the preset amplitude range; and the splicing unit is used for carrying out signal splicing on the signals corresponding to each group of channels according to the sequence of the sampling clock to obtain the acquired signals.
In an optional implementation manner of the embodiment of the present application, the determining unit in the embodiment of the present application may further include: the first determining subunit is used for determining the signals output by the amplifying circuit and the ADC in each group of channels as fusion signals of the group of channels under the condition that the amplitude of the signals to be acquired is smaller than a first preset threshold value; the second determining subunit is configured to determine, as a fusion signal of the set of channels, a signal output from each set of channels via the reduction circuit and the ADC, in a case where an amplitude of a signal to be acquired is greater than a second preset threshold; a third determining subunit, configured to determine, when the amplitude of the signal to be acquired is greater than or equal to a first preset threshold and less than or equal to a second preset threshold, a sum of the first signal and the second signal of each group of channels as a fusion signal of the group of channels; the first signal is the ratio result of the signal output by the amplifying circuit and the ADC in the multiple groups of channels and the amplifying multiple of the amplifying circuit, and the second signal is the product result of the signal output by the amplifying circuit and the ADC in the multiple groups of channels and the reducing multiple of the reducing circuit; the first preset threshold is the minimum value in the preset amplitude range, and the second preset threshold is the maximum value in the preset amplitude range.
In an optional implementation manner of the embodiment of the present application, the splicing unit in the embodiment of the present application may further include: and the splicing subunit is used for splicing the obtained fusion signals according to the sequence of the sampling clock to obtain the acquired signals.
In an alternative implementation manner of the embodiment of the present application, the second determining module 604 in the embodiment of the present application may further include: a fourth determination subunit, configured to determine, as an amplitude compensation value, a ratio of an amplitude of each channel to an amplitude of the target channel; and a fifth determining subunit, configured to determine, as a delay compensation value, a difference between the delay corresponding to each channel phase and the delay corresponding to the target channel phase.
In an alternative implementation manner of the embodiment of the present application, the processing module 606 in the embodiment of the present application may further include: a sixth determining subunit, configured to determine a ratio of 1 to a preset sampling frequency as a time interval; a seventh determining subunit for determining a sampling clock difference of the ADC in the nth set of channels relative to the ADC in the 1 st set of channels by:
T=(N-1)τ+θCi
wherein T is sampling clock difference, tau is time interval, thetaCi is delay compensation value, and N is positive integer.
As shown in fig. 7, an embodiment of the present application provides an electronic device including a processor 711, a communication interface 712, a memory 713, and a communication bus 714, wherein the processor 711, the communication interface 712, the memory 713 perform communication with each other through the communication bus 714,
a memory 713 for storing a computer program;
in one embodiment of the present application, the processor 711 is configured to implement the signal acquisition method provided in any of the foregoing method embodiments when executing the program stored in the memory 713, and the functions of the signal acquisition method are similar, and will not be described herein.
The present application also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of a method of providing signal acquisition according to any of the method embodiments described above.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
From the above description of embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus a general purpose hardware platform, or may be implemented by hardware. Based on such understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the related art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform the method described in the respective embodiments or some parts of the embodiments.
It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only, and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "includes," "including," and "having" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order described or illustrated, unless an order of performance is explicitly stated. It should also be appreciated that additional or alternative steps may be used.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. The signal acquisition method based on the signal acquisition system is characterized in that the signal acquisition system comprises a power divider, a plurality of groups of channels respectively connected with the power divider and a processor connected with the plurality of groups of channels; each group of channels comprises two channels, one channel comprises an amplifying circuit and an ADC, and the other channel comprises a reducing circuit and the ADC; the method comprises the following steps:
after a first target signal is input to the signal acquisition system, determining an amplitude value and a phase value of a second target signal output by each channel based on the processor; wherein the amplification factor of the amplifying circuit is consistent with the reduction factor of the reducing circuit; the initial sampling clocks fed back by the processor to the ADCs in the multiple groups of channels are consistent;
Determining an amplitude compensation value based on the amplitude of each channel in the plurality of groups of channels and the amplitude of the target channel respectively, and determining a delay compensation value based on the delay corresponding to the phase of each channel in the plurality of groups of channels and the delay corresponding to the phase of the target channel respectively; wherein the target channel is any one of the plurality of groups of channels;
setting a time interval between the ADCs based on a preset sampling frequency, determining a sampling clock difference between the ADCs based on the time interval and the delay compensation value, and calibrating any channel except the target channel in the multiple groups of channels based on the amplitude compensation value and the sampling clock difference;
inputting signals to be acquired into each calibrated channel and the target channel based on the power divider, and executing signal acquisition operation;
inputting the signals to be acquired into each calibrated channel and the target channel based on the power divider, and executing the signal acquisition operation comprises the following steps: determining signals corresponding to each group of channels based on a comparison result of the amplitude of the signal to be acquired and a preset amplitude range; and signal splicing is carried out on the signals corresponding to each group of channels according to the sequence of the sampling clock, so that the acquired signals are obtained.
2. The method of claim 1, wherein determining the signal corresponding to each set of channels based on the comparison of the amplitude of the signal to be acquired and a preset amplitude range comprises:
under the condition that the amplitude of the signal to be acquired is smaller than a first preset threshold value, determining the signal output by the amplifying circuit and the ADC in each group of channels as a fusion signal of the group of channels;
under the condition that the amplitude of the signal to be acquired is larger than a second preset threshold value, determining the signal output by each group of channels through the reduction circuit and the ADC as a fusion signal of the group of channels;
determining the sum of the first signal and the second signal of each group of channels as a fusion signal of the group of channels under the condition that the amplitude of the signal to be acquired is larger than or equal to the first preset threshold value and smaller than or equal to the second preset threshold value; the first signal is the result of the ratio of the signal output by the amplifying circuit and the ADC to the amplifying power of the amplifying circuit in the multiple groups of channels, and the second signal is the result of the product of the signal output by the amplifying circuit and the ADC and the shrinking power of the shrinking circuit in the multiple groups of channels;
The first preset threshold is the minimum value in the preset amplitude range, and the second preset threshold is the maximum value in the preset amplitude range.
3. The method of claim 2, wherein signal splicing the signals corresponding to each set of channels in the order of sampling clock, to obtain the collected signals comprises:
and splicing the obtained fusion signals according to the sequence of the sampling clock to obtain the acquired signals.
4. The method of claim 1, wherein the step of determining the position of the substrate comprises,
determining an amplitude compensation value based on the amplitude of each of the plurality of sets of channels and the amplitude of the target channel, respectively, includes: determining the ratio of the amplitude of each channel to the amplitude of the target channel as the amplitude compensation value;
determining a delay compensation value based on the delay corresponding to each channel phase in the plurality of groups of channels and the delay corresponding to the target channel phase, respectively, including: and determining the difference value of the delay corresponding to each channel phase and the delay corresponding to the target channel phase as the delay compensation value.
5. The method of claim 1, wherein setting a time interval between ADCs based on a preset sampling frequency and determining a sampling clock difference between ADCs based on the time interval and the delay compensation value comprises:
Determining the ratio of 1 to the preset sampling frequency as the time interval;
the sampling clock difference of the ADC in the nth set of channels relative to the ADC in the 1 st set of channels is determined by the following equation:
T=(N-1)τ+θCi
wherein T is the sampling clock difference, tau is the time interval, thetaCi is the delay compensation value, and N is a positive integer.
6. A signal acquisition device based on a signal acquisition system, for implementing the method as claimed in claims 1-5, said device comprising:
the first determining module is used for determining the amplitude value and the phase value of the second target signal output by each channel after the first target signal is input to the signal acquisition system; wherein the amplification factor of the amplifying circuit is consistent with the reduction factor of the reducing circuit; the initial sampling clocks fed back by the processor to the ADCs in the multiple groups of channels are consistent;
the second determining module is used for determining an amplitude compensation value based on the amplitude of each channel in the plurality of groups of channels and the amplitude of the target channel respectively, and determining a delay compensation value based on the delay corresponding to the phase of each channel in the plurality of groups of channels and the delay corresponding to the phase of the target channel respectively; wherein the target channel is any one of the plurality of groups of channels;
The processing module is used for determining the time interval between the ADCs based on a preset sampling frequency, determining the sampling clock difference between the ADCs based on the time interval and the delay compensation value, and calibrating any channel except the target channel in the multiple groups of channels based on the amplitude compensation value and the sampling clock difference;
the sampling module is used for inputting signals to be acquired into each calibrated channel and the target channel based on the power divider, and executing signal acquisition operation;
wherein, the sampling module includes: the determining unit is used for determining the signals corresponding to each group of channels based on the comparison result of the amplitude of the signals to be acquired and the preset amplitude range; and the splicing unit is used for carrying out signal splicing on the signals corresponding to each group of channels according to the sequence of the sampling clock to obtain the acquired signals.
7. The apparatus according to claim 6, wherein the determining unit includes:
the first determining subunit is used for determining the signals output by the amplifying circuit and the ADC in each group of channels as fusion signals of the group of channels under the condition that the amplitude of the signals to be acquired is smaller than a first preset threshold value;
The second determining subunit is configured to determine, as a fusion signal of the set of channels, a signal output from each set of channels via the reduction circuit and the ADC, in a case where an amplitude of the signal to be acquired is greater than a second preset threshold;
a third determining subunit, configured to determine, when the amplitude of the signal to be acquired is greater than or equal to the first preset threshold and less than or equal to the second preset threshold, a sum of the first signal and the second signal of each group of channels as a fusion signal of the group of channels; the first signal is the result of the ratio of the signal output by the amplifying circuit and the ADC to the amplifying power of the amplifying circuit in the multiple groups of channels, and the second signal is the result of the product of the signal output by the amplifying circuit and the ADC and the shrinking power of the shrinking circuit in the multiple groups of channels;
the first preset threshold is the minimum value in the preset amplitude range, and the second preset threshold is the maximum value in the preset amplitude range.
8. The signal acquisition system is characterized by comprising a power divider, a plurality of groups of channels respectively connected with the power divider and a processor connected with the groups of channels; each group of channels comprises two channels, one channel comprises an amplifying circuit and an ADC, and the other channel comprises a reducing circuit and the ADC;
Wherein the amplification factor of the amplifying circuit is consistent with the reduction factor of the reducing circuit; the initial sampling clocks fed back by the processor to the ADCs in the multiple groups of channels are consistent;
the processor is used for executing the following steps:
after a first target signal is input to the signal acquisition system, determining an amplitude value and a phase value of a second target signal output by each channel; wherein the amplification factor of the amplifying circuit is consistent with the reduction factor of the reducing circuit; the initial sampling clocks fed back by the processor to the ADCs in the multiple groups of channels are consistent;
determining an amplitude compensation value based on the amplitude of each channel in the plurality of groups of channels and the amplitude of the target channel respectively, and determining a delay compensation value based on the delay corresponding to the phase of each channel in the plurality of groups of channels and the delay corresponding to the phase of the target channel respectively; wherein the target channel is any one of the plurality of groups of channels;
setting a time interval between the ADCs based on a preset sampling frequency, determining a sampling clock difference between the ADCs based on the time interval and the delay compensation value, and calibrating any channel except the target channel in the multiple groups of channels based on the amplitude compensation value and the sampling clock difference;
Inputting signals to be acquired into each calibrated channel and the target channel based on the power divider, and executing signal acquisition operation;
inputting the signals to be acquired into each calibrated channel and the target channel based on the power divider, and executing the signal acquisition operation comprises the following steps: determining signals corresponding to each group of channels based on a comparison result of the amplitude of the signal to be acquired and a preset amplitude range; and signal splicing is carried out on the signals corresponding to each group of channels according to the sequence of the sampling clock, so that the acquired signals are obtained.
9. The electronic equipment is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are communicated with each other through the communication bus;
a memory for storing a computer program;
a processor for carrying out the method steps of any one of claims 1-5 when executing a program stored on a memory.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the method according to any of claims 1-5.
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