WO2017113058A1 - 一种基于plb的fpga芯片布线方法 - Google Patents

一种基于plb的fpga芯片布线方法 Download PDF

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Publication number
WO2017113058A1
WO2017113058A1 PCT/CN2015/099208 CN2015099208W WO2017113058A1 WO 2017113058 A1 WO2017113058 A1 WO 2017113058A1 CN 2015099208 W CN2015099208 W CN 2015099208W WO 2017113058 A1 WO2017113058 A1 WO 2017113058A1
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multiplexer
layout
plb
programmable logic
fpga chip
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PCT/CN2015/099208
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English (en)
French (fr)
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宋惠远
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京微雅格（北京）科技有限公司
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Priority to PCT/CN2015/099208 priority Critical patent/WO2017113058A1/zh
Priority to CN201580001648.3A priority patent/CN110313002B/zh
Publication of WO2017113058A1 publication Critical patent/WO2017113058A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors

Definitions

  • the invention relates to the field of integrated circuit design technology in the field of microelectronics, in particular to a PLB-based FPGA chip wiring method.
  • FPGA Field Programmable Gate Array
  • the FPGA design flow includes: design input, debugging, functional simulation, synthesis, place and route, timing simulation, configuration download and other steps.
  • the layout refers to taking out the defined logic and input and output blocks from the map and assigning them to the physical location inside the FPGA. It is often necessary to choose between the optimal speed and the optimal area. Wiring is based on the topology of the layout, using automatic routing software, using routing resources to select the shortest path, try to complete all logical connections.
  • multiplexers are used in many FPGA designs.
  • the multi-stage cascading of multiplexers can form an input crossbar matrix (ixbar) structure, which can realize the logic of selecting and outputting input data, that is, Said to have a unique path between the input and output.
  • ixbar input crossbar matrix
  • the object of the present invention is to provide a PLB-based FPGA chip routing method for prior art defects, which can obtain different configuration modes of multiplexers of various layout modes by analyzing in advance; after the user designs the layout According to the result of the layout, the configuration manner of the multiplexer stored in the call layout result is searched to form the programmable logic block PLB, and then the wiring of the programmable logic block PLB level is performed. This method can shorten the wiring time and reduce the memory occupied by the routing algorithm.
  • the invention provides a PLB-based FPGA chip routing method, the method comprises: analyzing various layout manners of the FPGA chip, separately obtaining configuration rules of the multiplexers in each layout manner; storing the plurality of layout manners Different configuration rules of the multiplexer; after the layout of the FPGA chip, according to the layout result of the FPGA chip netlist, searching and calling the corresponding layout result from the different configuration rules of the multiplexer
  • the multiplexer is configured to configure the multiplexer to form a programmable logic block PLB; then routing is performed at the PLB level of the programmable logic block.
  • the multiplexer configuration law corresponding to the layout result is searched and called from different configuration rules of the multiplexer.
  • the multiplexer is configured to form a programmable logic block PLB.
  • the steps include: a plurality of programmable logic blocks PLB are simultaneously formed, and each of the programmable logic blocks PLB is formed independently.
  • a timing model is established with a programmable logic block PLB as a basic unit, the timing model is a sequential logic behavior using a programmable logic block PLB mode to distinguish different multiplexer mux configuration modes, and using a multi-mode supporting mode
  • the static timing analyzer is used for timing analysis; after the timing analysis is performed using the timing model, the router is optimized based on the results of the timing analysis.
  • the step of performing the routing at the level of the programmable logic block PLB further comprises: when performing the routing of the programmable logic block PLB layer, acquiring a pre-established wiring pattern with the programmable logic block PLB as a basic unit, Then route it.
  • the step of storing different configuration rules of the multiplexers in the plurality of layout modes comprises: different configuration rules of the multiplexers being one input of each multiplexer Corresponding to its unique output; and according to the different configuration rules of the multiplexer, each multiplexer is configured with bits and stores the bit information.
  • the invention designs and layouts in a user by analyzing and obtaining different configurations of multiplexers of various layout modes. After that, according to the result of the layout of the chip net table, the configuration mode of the multiplexer stored and searched for the layout result is searched, thereby shortening the wiring time, reducing the memory occupied by the routing algorithm, and improving the wiring process. effectiveness.
  • FIG. 1 is a schematic diagram of a programmable logic block according to an embodiment of the present invention.
  • FIG. 2 is a schematic flowchart of a method for routing an FPGA chip according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a configuration manner of a multiplexer according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a programmable logic block in a wiring model according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of wiring between programmable logic blocks according to an embodiment of the present invention.
  • the embodiment of the invention provides a PLB-based FPGA chip routing method, which obtains different configuration modes of multiplexers of various layout modes by analyzing in advance; after FPGA chip layout, according to the layout of the FPGA chip net table As a result, the configuration of the multiplexer stored in the call layout result is searched, the number of basic units and the number of nets that the router needs to process is reduced, and then wiring is performed. This method can shorten the wiring time and reduce the memory occupied by the routing algorithm.
  • FIG. 1 is a schematic diagram of a programmable logic block according to an embodiment of the present invention.
  • a programmable logic block (PLB, Programmable Logic Block) includes eight 6-input lookup tables: LUT0, LUT1, LUT2, LUT3, LUT4, LUT5, LUT6, and LUT7.
  • the PLB also includes connection resources between the base unit such as the lookup table LUT, registers, adders, and the like.
  • the multiplexers mux_di0, mux_di1, mux_di2, mux_di3, mux_di4, mux_di5, mux_di6, mux_di8, mux_di9, mux_di10, mux_di11, mux_di12, mux_di13, mux_di14, and mux_di15 are all three-select multiplexers.
  • the multiplexers mux_dy0, mux_dy1, mux_dy2, mux_dy3, mux_dy4, mux_dy5, mux_dy6, and mux_dy7 are all 6-select multiplexers. Other multiplexers are shown in the figure and will not be described here.
  • FIG. 2 is a schematic flowchart of a method for routing an FPGA chip according to an embodiment of the present invention. As shown, the method includes steps S201-S204:
  • Step S201 analyzing various layout manners of the FPGA chip, and separately obtaining configuration rules of the multiplexers in each layout manner;
  • Step S202 storing different configuration rules of the multiplexers in the multiple layout manners
  • the different configuration rules for storing the multiplexers in the different layout manners are different configuration rules of the multiplexer, and one input end of each multiplexer corresponds to the unique one. Outputs; and according to different configuration rules of the multiplexer, each multiplexer is configured with bits and stores the bit information.
  • FIG. 3 is a schematic diagram of a multiplexer configuration manner according to an embodiment of the present invention. As shown in FIG. 3, the multiplexer mux_dy7 of FIG. 1 is taken as an example for description.
  • a 6-to-1 multiplexer is described, but the embodiment of the present invention does not limit the multiplexer which is necessarily a 6-select.
  • the invention is applicable to n-selected multiplexers, where n is an integer greater than one.
  • the six input signals of mux_dy7 are the output signals of register Q15; the carry output signal of adder C7; the sum S7 of adder C7; the x output signal of lookup table LUT7; the output of the shiftout of lookup table LUT6 Signal; output signal of register Q7.
  • the output signals of the multiplexer mux_dy7 are dy[7] and dy_r[7].
  • mux_dy7 selects one signal from the six input signals as the output signal, taking the output signal of Q15 as an example.
  • the output signal of Q15 of mux_dy7 is then marked as 0 or 1 of 1 bit, and the marked bit signal is stored.
  • the implementation of the present invention does not limit such a layout, nor does it limit the selection input signal of the multiplexer mux_dy7 in the embodiment.
  • the output signal of the register Q7 can be selected as an input signal.
  • the results of a large number of different layout methods are analyzed, and the configuration rules of the multiplexers for each different layout result are obtained; different multiplexers of different layout methods are obtained in the experiment.
  • the configuration rules can cover the layout results of all user designs.
  • Step S203 After the FPGA chip performs layout, according to the layout result of the FPGA chip netlist, the multiplexer configuration law corresponding to the layout result is searched and called from different configuration rules of the multiplexer, This configures the multiplexer to form a programmable logic block PLB;
  • Step S204 routing is then performed at the level of the programmable logic block PLB.
  • the layout of the FPGA multiplexer After the layout of the FPGA multiplexer is completed, firstly, a large number of stored layout modes are searched to find a corresponding layout mode, and then the configuration rule of the multiplexer in the corresponding layout mode is found.
  • the FPGA chip lays out the lookup table and the registers. In different layout modes, the lookup table and the register occupy different positions in the PLB.
  • the routing algorithm is no longer needed to search each input port of the mux_dy7, and is directly called from the configuration rule of the pre-stored mux_dy7; That is, directly reading the bit information of the stored mux_dy7 input signal, reading a uniquely determined path between the input and output that has been determined, and forming a programmable logic block PLB, and then performing at the PLB level of the programmable logic block. wiring.
  • the output signal of the mux_dy7 selection Q15 in a certain layout mode is marked as an input signal as 1; after the user finds the layout mode, the selection of the input signal of the mux_dy7 is directly called, and the search is not performed, but directly
  • the output signal of Q15 is input to mux_dy7.
  • the wiring time of a large number of routing algorithms is saved, and the configuration rule of the multiplexer stored in advance is directly called, and the memory occupied by the routing algorithm during operation is also largely reduced.
  • the multiplexer After the user designs the layout, according to the layout result of the FPGA chip netlist, from the multi-path Finding and calling the multiplexer configuration law corresponding to the layout result in different configuration rules of the multiplexer, thereby configuring the multiplexer to form a programmable logic block PLB step into multiple programmable logic blocks
  • the PLBs are formed simultaneously, and each of the programmable logic blocks PLB is formed separately.
  • the configuration rule of the multiplexer corresponding to the layout result stored in advance is directly searched and called; the routing algorithm does not need to be multiplexed for all the multiplexers.
  • the traversal is performed at the input of the device, and the wiring can be directly used by the configuration rule of the multiplexer.
  • the embodiment of the present invention can greatly reduce the number of basic units and the number of network lines that the router needs to process; Save FPGA chip wiring time.
  • the routing step is then performed at the level of the programmable logic block PLB to establish a timing model with a programmable logic block PLB as a basic unit in advance, and the timing model uses a programmable logic block PLB mode to distinguish different
  • the timing behavior of the mux mux configuration mode is used, and the static timing analyzer supporting multi-mode is used for timing analysis; after the timing analysis is performed using the timing model, the router is optimized according to the result of the timing analysis.
  • the output of the eight registers Q0, Q1, Q2, Q3, Q4, Q5, Q6, and Q7 has two modes, one is to directly output the PLB, and the other is the input. Go to the input of the multiplexer.
  • the output of Q7 can be directly output as qx[7], or can be input to mux_dy7 and output via dy[7] or dy_r[7].
  • Each of the eight registers has two output modes; that is, eight parameters, each of which has two cases; these eight parameters constitute a PLB mode.
  • the static timing analyzer refers to calculating the timing behavior of the entire chip according to the timing model of each PLB of the chip, thereby finding the critical path, that is, the longest path; the longest path corresponding to the maximum delay, and then obtaining the chip The highest operating frequency, which is the reciprocal of the maximum delay.
  • the timing model is constructed by using the PLB as a basic unit as a basic unit, and the timing driving can be performed when the PLB layer is completed.
  • the step of performing the routing at the level of the programmable logic block PLB further includes: acquiring a pre-established wiring model with the programmable logic block PLB as a basic unit when performing routing at the PLB level of the programmable logic block, Then route it.
  • the wiring model is a wiring diagram established with the PLB as a basic unit; the timing model is also established with the PLB as a basic unit, but the timing model is a basic unit of the static timing analyzer for timing analysis.
  • the multiplexer configuration law corresponding to the layout result is searched and called to form a programmable logic block PLB; and the timing analysis with the PLB as a basic unit is performed.
  • FIG. 4 is a schematic diagram of a programmable logic block in a wiring model according to an embodiment of the present invention.
  • FIG. 4 it is a schematic diagram of a basic unit in a netlist with a PLB as a basic unit.
  • the entire PLB is used as the unit, and the internal basic logic unit is invisible. Only the input port and output port of the PLB are available; and the input and output ports of the jump carry chain are also included.
  • routing between PLB layers it is equivalent to the internal cassette, and the routing algorithm no longer needs to search the inside of the PLB.
  • FIG. 5 is a schematic diagram of wiring between programmable logic blocks according to an embodiment of the present invention. As shown in FIG. 5, when performing PLB external wiring, a pre-established wiring model using PLB as a basic unit is directly obtained, and then wiring is performed. Direct wiring between PLBs.
  • a wiring model with the PLB as a basic unit is established, and then the wiring is performed.
  • the routing algorithm does not need to search the input and output of the LUT and the Reg inside the PLB, thereby saving a large amount of Time; further shortens the timing of the routing algorithm.
  • the user designs different configurations of the multiplexers by searching and calling different layout modes stored in advance; therefore, the routing algorithm is greatly shortened in the search time, and the routing algorithm is compared with the prior art. The calculations are greatly reduced, which in turn reduces the memory it occupies.
  • the invention analyzes and acquires different configuration modes of the multiplexers of different layout modes, and after the user designs the layout, according to the result of the chip layout, performs configuration for finding and calling the multiplexer stored corresponding to the layout result.
  • the method further shortens the wiring time, and also reduces the memory occupied by the routing algorithm, thereby improving the efficiency of the wiring process.
  • the steps of a method or algorithm described in connection with the embodiments disclosed herein can be implemented in hardware, a software module executed by a processor, or a combination of both.
  • the software module can be placed in random access memory (RAM), memory, read only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or technical field. Any other form of storage medium known.

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Abstract

一种基于PLB的FPGA芯片布线方法，该方法包括：分析FPGA芯片的多种布局方式，分别获取每种布局方式中多路复用器的配置规律（S201）；存储所述多种布局方式中的多路复用器的不同配置规律（S202）；在FPGA芯片进行布局后，根据FPGA芯片网表的布局结果，从所述多路复用器的不同配置规律中查找和调用所述布局结果对应的多路复用器配置规律，由此对多路复用器进行配置，形成可编程逻辑块PLB（S203）；然后在所述可编程逻辑块PLB层面进行布线（S204）。根据芯片多路复用器布局的结果，进行查找和调用该布局结果所对应存储的多路复用器的配置方式，减少布线器所需处理的基本单元数量和线网数量，进而缩短布线的时间，同时也降低布线算法所占用的内存，提高布线流程的效率。

Description

一种基于PLB的FPGA芯片布线方法 技术领域
本发明涉及微电子领域中的集成电路设计技术领域，特别是一种基于PLB的FPGA芯片布线方法。
背景技术
现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)是一种具有丰富硬件资源、强大并行处理能力和灵活可重配置能力的逻辑器件。这些特征使得FPGA在数据处理、通信、网络等很多领域得到了越来越多的广泛应用。
FPGA的设计流程包括：设计输入、调试、功能仿真、综合、布局布线、时序仿真、配置下载等步骤。其中布局是指从映射取出定义的逻辑和输入输出块，并把它们分配到FPGA内部的物理位置，往往需要在速度最优和面积最优之间做出选择。布线是根据布局的拓扑结构，利用自动布线软件，使用布线资源选择时序最短路径，试着完成所有的逻辑连接。
目前，在很多FPGA设计中都使用了多路复用器，多路复用器的多级级联可以形成输入交叉开关矩阵(ixbar)结构，可以实现对输入数据的选择输出的逻辑，也就是说在输入和输出之间具有唯一确定的路径。
在现有技术中，不同的用户设计，都需要对多路复用器进行不同的布线过程；每一次的布线，都需要对多路复用器的输入数据进行选择，然后输出用户想要的逻辑；且只能在以查找表LUT(Lookup table)和寄存器Reg(Register)组成的布线模型的网表中进行布线。每一次布线流程所需要的时间很长；并且布线算法在运行的过程中占有的内存较高。
随着FPGA芯片规模的扩大，要求布线所占用的时间缩短。目前工业界还没有对提高布线的速度和降低布线算法占有的内存提出好的解决办法。
发明内容
本发明的目的是针对现有技术的缺陷，提供了一种基于PLB的FPGA芯片布线方法，该方法通过事先分析获取多种布局方式的多路复用器的不同配置方式；在用户设计布局后，根据布局的结果，查找调用布局结果所对应存储的多路复用器的配置方式，形成可编程逻辑块PLB，然后进行可编程逻辑块PLB层面的布线。该方法能够缩短布线的时间并且降低布线算法所占用的内存。
本发明提供一种基于PLB的FPGA芯片布线方法，该方法包括：分析FPGA芯片的多种布局方式，分别获取每种布局方式中多路复用器的配置规律；存储所述多种布局方式中的多路复用器的不同配置规律；在FPGA芯片进行布局后，根据FPGA芯片网表的布局结果，从所述多路复用器的不同配置规律中查找和调用所述布局结果对应的多路复用器配置规律，由此对多路复用器进行配置，形成可编程逻辑块PLB；然后在所述可编程逻辑块PLB层面进行布线。
优选地，所述在FPGA芯片进行布局后，根据FPGA芯片网表的布局结果，从所述多路复用器的不同配置规律中查找和调用所述布局结果对应的多路复用器配置规律，由此对多路复用器进行配置，形成可编程逻辑块PLB步骤包括：多个可编程逻辑块PLB同时形成，且每一个可编程逻辑块PLB是各自独立的形成。
优选地，建立以可编程逻辑块PLB为基本单位的时序模型，所述时序模型是使用可编程逻辑块PLB模式来区分不同多路复用器mux配置方式的时序行为，并使用支持多模式的静态时序分析器来进行时序分析；使用所述时序模型进行时序分析后，布线器根据时序分析的结果进行优化。
优选地，所述然后在所述可编程逻辑块PLB层面进行布线步骤还包括：当进行可编程逻辑块PLB层进行布线时，获取预先建立的以可编程逻辑块PLB为基本单元的布线模型，然后进行布线。
优选地，所述存储所述多种布局方式中的多路复用器的不同配置规律步骤包括：所述多路复用器的不同配置规律为每一个多路复用器的某一个输入端对应其唯一的输出端；并根据所述多路复用器的不同配置规律，给每一个多路复用器配置比特位，并存储所述比特位信息。
本发明通过分析并获取多种布局方式的多路复用器的不同配置方式，在用户设计布局 后，根据芯片网表布局的结果，进行查找和调用该布局结果所对应存储的多路复用器的配置方式，进而缩短布线的时间，同时也降低布线算法所占用的内存，提高布线流程的效率。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种可编程逻辑块的示意图；
图2为本发明实施例提供的一种FPGA芯片布线方法流程示意图；
图3为本发明实施例提供的一种多路复用器配置方式的示意图；
图4为本发明实施例提供的布线模型中一种可编程逻辑块的示意图；
图5为本发明实施例提供的一种可编程逻辑块之间布线示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。
本发明实施例提供了一种基于PLB的FPGA芯片布线方法，该方法通过事先分析获取多种布局方式的多路复用器的不同配置方式；在FPGA芯片布局后，根据FPGA芯片网表布局的结果，查找调用布局结果所对应存储的多路复用器的配置方式，减少布线器所需处理的基本单元数量和线网数量，然后进行布线。该方法能够缩短布线的时间并且降低布线算法所占用的内存。
现以FPGA芯片架构中CME-C1为例对本发明实施例进行说明，图1为本发明实施例提供的一种可编程逻辑块的示意图。如图1所示一个可编程逻辑块(PLB,Programmable Logic Block)中，包括8个6输入的查找表分别为LUT0、LUT1、LUT2、LUT3、LUT4、LUT5、LUT6、LUT7。其中有4个是带本地存储器的查找表，分别为LUT0、LUT2、LUT4、 LUT6；还包括8个加法器、16个寄存器，寄存器分别为Q0、Q1、Q2、Q3、Q4、Q5、Q6、Q7、Q8、Q9、Q10、Q11、Q12、Q13、Q14、Q15。如图所示，PLB还包括查找表LUT、寄存器、加法器等基本单元之间的连线资源。
如图所示，图中多路复用器mux_bo、mux_b1、mux_b2、mux_b3、mux_b4、mux_b5、mux_b6、mux_b7；多路复用器mux_ca0、mux_ca1、mux_ca2、mux_ca3、mux_ca4、mux_ca5、mux_ca6、mux_ca7；多路复用器mux_di0、mux_di1、mux_di2、mux_di3、mux_di4、mux_di5、mux_di6、mux_di8、mux_di9、mux_di10、mux_di11、mux_di12、mux_di13、mux_di14、mux_di15，都为三选一的多路复用器。PLB在内部布线时，只需要对mux进行布线，因此本发明实施例只讨论多路复用器mux的配置规律。
多路复用器mux_dy0、mux_dy1、mux_dy2、mux_dy3、mux_dy4、mux_dy5、mux_dy6、mux_dy7都为6选一的多路复用器。其它的多路复用器如图所示，在此不再赘述。
现以图1中的多路复用器对本发明实施例进行说明，图2为本发明实施例提供的一种FPGA芯片布线方法流程示意图。如图所示，该方法包括步骤S201-S204：
步骤S201：分析FPGA芯片的多种布局方式，分别获取每种布局方式中多路复用器的配置规律；
步骤S202：存储所述多种布局方式中的多路复用器的不同配置规律；
具体地，所述存储所述不同布局方式中的多路复用器的不同配置规律为所述多路复用器的不同配置规律为每一个多路复用器的某一个输入端对应其唯一的输出端；并根据所述多路复用器的不同配置规律，给每一个多路复用器配置比特位，并存储所述比特位信息。
现以图3为例对此进行详细说明，图3为本发明实施例提供的一种多路复用器配置方式的示意图。如图3所示，以图1中多路复用器mux_dy7为例进行说明。
需要说明的是，本发明实施例是对6选1的多路复用器进行说明，但本发明实施例并不限定一定为6选1的多路复用器。本发明适用于n选1的多路复用器，n为大于1的整数。
如图所示，mux_dy7的6个输入信号分别为寄存器Q15的输出信号；加法器C7的进位输出信号；加法器C7的和数S7；查找表LUT7的x输出信号；查找表LUT6的shiftout的输出信号；寄存器Q7的输出信号。多路复用器mux_dy7的输出信号为dy[7]和dy_r[7]。
在布局布线完成以后，例如mux_dy7的会从6个输入信号选择一个信号作为输出信号，以其选择Q15的输出信号为例。然后将mux_dy7的Q15的输出信号标记为1个比特的0或1，并对标记的比特位信号进行存储。
需要说明的是，本发明实施例只对图1所述的一种布局方式的布线结果中mux_dy7进行说明。但是本发明实施并不限定这种布局方式，也不限定实施例中多路复用器mux_dy7的选择输入信号，例如可以选择寄存器Q7的输出信号做为输入信号。
在实验中会对大量的不同的布局方式的结果进行分析，并获取每种不同的布局结果的多路复用器的配置规律；在实验中的获取的不同布局方式的不同多路复用器的配置规律能够覆盖到所有用户设计的布局结果。
步骤S203：在FPGA芯片进行布局后，根据FPGA芯片网表的布局结果，从所述多路复用器的不同配置规律中查找和调用所述布局结果对应的多路复用器配置规律，由此对多路复用器进行配置，形成可编程逻辑块PLB；
步骤S204：然后在所述可编程逻辑块PLB层面进行布线。
当FPGA多路复用器布局完成之后，首先对存储的大量的布局方式进行查找，找到对应的布局方式，进而找到该对应的布局方式中多路复用器的配置规律。FPGA芯片是对查找表以及寄存器进行布局，不同的布局方式中，查找表和寄存器在PLB中占有的位置不同。
下面对多路复用器的配置方式进行说明，如在进行图3所述的布线时，不再需要布线算法进行搜索mux_dy7的每一个输入端口，直接从事先存储mux_dy7的配置规律中调用；也就是直接读取存储的mux_dy7输入信号的比特位信息，读取已经确定的输入和输出之间具有唯一确定的路径，并形成可编程逻辑块PLB，然后在所述可编程逻辑块PLB层面进行布线。
具体的，就是事先将某个布局方式中mux_dy7选择Q15的输出信号作为输入信号标记为1；用户查找到该布局方式后，直接调用mux_dy7的输入信号的选择，不再进行搜索，而是直接从Q15的输出信号输入到mux_dy7中。进而节省大量的布线算法的布线时间，同时直接调用事先存储的多路复用器的配置规律，布线算法在运行的时候占用的内存也会很大程度上降低。
具体地，所述在用户设计进行布局后，根据FPGA芯片网表的布局结果，从所述多路 复用器的不同配置规律中查找和调用所述布局结果对应的多路复用器配置规律，由此对多路复用器进行配置，形成可编程逻辑块PLB步骤为多个可编程逻辑块PLB同时形成，且每一个可编程逻辑块PLB是各自独立的形成。
本发明实施例中，用户设计布局完成以后，根据布局的结果，通过直接查找和调用事先存储的该布局结果所对应的多路复用器的配置规律；布线算法不需要对所有的多路复用器的输入端进行遍历，可直接利用多路复用器的配置规律进行布线。
需要说明的是，因FPGA芯片的功能越来越强大，PLB的数量也在急剧增加，本发明实施例可以极大的减少布线器所需处理的基本单元数量和线网数量；进而极大的节省FPGA芯片布线时间。
具体地，所述然后在所述可编程逻辑块PLB层面进行布线步骤为事先建立以可编程逻辑块PLB为基本单位的时序模型，所述时序模型是使用可编程逻辑块PLB模式来区分不同多路复用器mux配置方式的时序行为，并使用支持多模式的静态时序分析器来进行时序分析；使用所述时序模型进行时序分析后，布线器根据时序分析的结果进行优化。
下面对此进行说明，如在图1中，8个寄存器Q0、Q1、Q2、Q3、Q4、Q5、Q6、Q7的输出有两种方式，一种是直接输出PLB外，一种是输入到多路复用器的输入端。例如，Q7的输出可以直接输出qx[7],也可以输入到mux_dy7，通过dy[7]或者dy_r[7]输出。这8个寄存器的各有两个输出方式；也就是8个参数，其中每个参数各有两种情况；这8个参数就构成一个PLB模式。
静态时序分析器，是指根据芯片每个PLB的时序模型来计算整个芯片的时序行为，进而找出关键路径，也就是最长的路径；最长的路径所对应最大的延时，然后得到芯片的最高运行频率，也就是最大延时的倒数。
需要说明的是，在FPGA芯片中，找到关键路径后，才能对关键路径进行优化，进而降低延时。故本发明实施例以PLB整体为基本单元构建时序模型，来完成PLB层面进行布线时可以进行时序驱动的布线工作。
具体地，所述然后在所述可编程逻辑块PLB层面进行布线步骤还包括：当进行可编程逻辑块PLB层面进行布线时，获取预先建立的以可编程逻辑块PLB为基本单元的布线模型，然后进行布线。
需要说明的是，布线模型就是以PLB为基本单元建立的布线图；时序模型同样是以PLB为基本单元建立，但时序模型是静态时序分析器做时序分析的基本单元。
用户设计在布局后，查找和调用了所述布局结果对应的多路复用器配置规律，形成可编程逻辑块PLB；进行以PLB为基本单元的时序分析。
图4为本发明实施例提供的布线模型中一种可编程逻辑块的示意图，如图4所示，是在以PLB为基本单元的网表中，基本单元的示意图。如图4所示，在PLB层面以PLB整体为单元，内部的基本逻辑单元都可不见，只有PLB的输入端口和输出端口；还有跳跃进位链的输入和输出端口。在进行PLB层面之间布线时，就相当于内部是暗盒，布线算法不再需要对PLB内部进行搜索。
现以图5对PLB之间的布线进行说明，图5为本发明实施例提供的一种可编程逻辑块之间布线示意图。如图5所示，在进行PLB外部布线的时候，直接获取预先建立的以PLB为基本单元的布线模型，然后进行布线。PLB之间可以直接布线。
现有技术中，在进行PLB之间布线时，是以PLB内部的LUT、Reg作为基本单元建立布线布线。故进行PLB外部与其它PLB之间布线时，布线算法需要对PLB内部的LUT和Reg的输入输出进行搜索，占有大量的时间。
在本发明实施例中，在进行PLB外部布线之间，建立以PLB为基本单元的布线模型，然后进行布线，布线算法不需要对PLB内部的LUT以及Reg的输入输出进行搜索，节省了大量的时间；进一步缩短了布线算法的时间。
本发明实施例中，用户设计通过查找和调用事先存储的不同布局方式的多路复用器的不同配置方式；故布线算法在搜索的时间极大缩短，相对于现有技术而言，布线算法的计算会极大减少，进而降低其占用的内存。
本发明通过分析并获取不同布局方式的多路复用器的不同配置方式，在用户设计布局后，根据芯片布局的结果，进行查找和调用该布局结果所对应存储的多路复用器的配置方式，进而缩短布线的时间，同时也降低布线算法所占用的内存，提高布线流程的效率。
专业人员应该还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。 这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
结合本文中所公开的实施例描述的方法或算法的步骤可以用硬件、处理器执行的软件模块，或者二者的结合来实施。软件模块可以置于随机存储器(RAM)、内存、只读存储器(ROM)、电可编程ROM、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、CD-ROM、或技术领域内所公知的任意其它形式的存储介质中。
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施方式而已，并不用于限定本发明的保护范围，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (5)

  1. 一种基于PLB的FPGA芯片布线方法，其特征在于，所述方法包括：
    分析FPGA芯片的多种布局方式，分别获取每种布局方式中多路复用器的配置规律；
    存储所述多种布局方式中的多路复用器的不同配置规律；
    在FPGA芯片进行布局后，根据FPGA芯片网表的布局结果，从所述多路复用器的不同配置规律中查找和调用所述布局结果对应的多路复用器配置规律，由此对多路复用器进行配置，形成可编程逻辑块PLB；
    然后在所述可编程逻辑块PLB层面进行布线。
  2. 根据权利要求1所述的方法，其特征在于，所述在FPGA芯片进行布局后，根据FPGA芯片网表的布局结果，从所述多路复用器的不同配置规律中查找和调用所述布局结果对应的多路复用器配置规律，由此对多路复用器进行配置，形成可编程逻辑块PLB步骤包括：
    多个可编程逻辑块PLB同时形成，且每一个可编程逻辑块PLB是各自独立的形成。
  3. 根据权利要求1所述的方法，其特征在于，建立以可编程逻辑块PLB为基本单位的时序模型，所述时序模型是使用可编程逻辑块PLB模式来区分不同多路复用器mux配置方式的时序行为，并使用支持多模式的静态时序分析器来进行时序分析；
    使用所述时序模型进行时序分析后，布线器根据时序分析的结果进行优化。
  4. 根据权利要求1所述的方法，其特征在于，所述然后在所述可编程逻辑块PLB层面进行布线步骤还包括：
    当进行可编程逻辑块PLB层进行布线时，获取预先建立的以可编程逻辑块PLB为基本单元的布线模型，然后进行布线。
  5. 根据权利要求1所述的方法，其特征在于，所述存储所述多种布局方式中的多路复用器的不同配置规律步骤包括：
    所述多路复用器的不同配置规律为每一个多路复用器的某一个输入端对应其唯一的输出端；并根据所述多路复用器的不同配置规律，给每一个多路复用器配置比特位，并存储所述比特位信息。
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CN114169283B (zh) * 2021-10-27 2024-04-05 深圳市紫光同创电子有限公司 可编程逻辑器件的延时估算方法、装置、设备及存储介质

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