WO2017111410A1

WO2017111410A1 - Ultra-low power broadband asynchronous binary phase-shift keying demodulator circuit having two pairs of complementary phases aligned by means of sideband comparators using 2nd order sideband filters aligned at 180-degree phase

Info

Publication number: WO2017111410A1
Application number: PCT/KR2016/014871
Authority: WO
Inventors: 피 월커슨벤자민
Original assignee: 피 월커슨벤자민
Priority date: 2015-12-21
Filing date: 2016-12-19
Publication date: 2017-06-29
Also published as: KR101665125B1

Abstract

One embodiment of the present invention relates to a BPSK demodulator circuit, and to an ultra-low power broadband asynchronous BPSK demodulation method enabling two pairs of complementary outputs to be aligned, and to a circuit thereof, the method enabling the alignment of complementary phases of sideband comparators so as to minimize a glitch when a 2nd order sideband filter output is digitized by a comparator, the output having the upper sideband of a BPSK modulated signal suppressed, and said signal is aligned, at a 180-degree phase of a carrier, with a signal having a 2nd order sideband filter output digitized by a comparator, the output having the lower sideband of the BPSK modulated signal suppressed, and thus the method enables increasing circuit stability so as to increase yield when implemented as an integrated circuit.

Description

Ultra-low power wideband asynchronous discrete phase shift demodulation circuit with two pairs of complementary phases by sideband comparators using second-order sideband filters aligned to 180 degrees of phase

The embodiment of the present invention digitizes the output of the secondary sideband filter suppressing the upper sideband of the BPSK modulated signal with a comparator, and digitizes the signal of the secondary sideband filter suppressing the lower sideband with the comparator. Ultra-low power wideband asynchronous BPSK demodulation method by aligning the complementary phases of sideband comparators to minimize the glitches while aligning the carrier phase 180 ^o , aligning the two pairs of complementary outputs to increase the stability of the integrated circuit. And the configuration of the circuit.

Binary Phase Shift Keying (BPSK) modulated signal is a bilateral band signal that suppresses carrier and cannot use carrier signal as its own signal, so it uses synchronous BPSK demodulation method to make carrier by internal oscillator.

The BPSK demodulation has a COSTAS loop as a basic method. The circuit is complicated and the feedback loop including the internal oscillator is used, which consumes a lot of power and limits transmission speed. The asynchronous DPSK demodulation circuit using Analog Integrator and Switched-Capacitor Units consumes a lot of power and complexity due to the internal oscillation circuit and the analog integrator, which increases the area of the chip that contains the circuit and reduces the overall area even if only one error occurs in the packet. There is a problem. In addition, yield reduction occurs due to a difference in characteristics of the CMOS FET according to the semiconductor manufacturing process and a signal distortion problem caused by a comparator input offset.

Regarding the BPSK demodulation circuit, Korean Patent No. 10-0365982 describes a modulation and demodulation circuit device that is stably performed through a synchronization signal generator in a demodulation device. Regarding the PSK demodulation circuit, Korean Patent No. 10-1417593 describes a demodulation method that is performed asynchronously without an internal oscillator.

According to an embodiment of the present invention, in order to solve the problem of transmission speed, circuit complexity, and power consumption in the demodulation method of the existing BPSK modulated signal, the phase difference of the secondary sideband filters is aligned with the phase of the carrier 180 ^° . At the same time, we aim to provide a BPSK demodulation circuit and a method for improving the yield of integrated circuits by increasing jitter by reducing jitter by compensating phase of sideband comparators to minimize glitches of symbol edge signals.

Accordingly, the present invention provides an asynchronous BPSK demodulation circuit and a method for transmitting broadband digital data that are extremely low power and simple in circuit. The output duty cycle of the sideband comparators differs in the characteristics of the CMOS FET and the comparator input offset according to the semiconductor manufacturing process. Due to the problem, the circuit of the lower band comparator and the upper band comparator is complemented with the phased comparator so that the glitches can be minimized.

In one side of the configuration of the BPSK demodulation circuit, the phase difference of the carrier is separated when the BPSK modulated signal is separated into the upper band analog signal and the lower band analog signal by the second high pass filter and the second low pass filter whose cutoff frequency is the carrier frequency. π, or ½ cycle digital signals appear through a pair of sideband differential output comparators, converting the phase of the upper band digital signal into two pairs of positive and partial phase signals, each of which is the opposite phase of the lower band digital signal. The lower band digital signal is output from the lower band digital signals, and the phase difference between the lower band digital signal and the upper band digital signal is aligned with the carrier phase π, that is, 180 ^o . The first symbol edge signal and the lower band portion generated by the difference of the signals in the change portion Since the phase difference between the phase digital signal and the upper band digital signal is aligned to the phase π of the carrier, that is, 180 ^o , the glitches are minimized by overlapping the second symbol edge signal generated by the difference of the signals in the phase change portion. A complementary phase sensing clock generation unit using sideband separation and differential output comparators for generating a complementary phase sensing clock signal; A glitch-free symbol edge signal is generated from the complementary phase detection clock signal through a diglyc filter, and applied to the clock C of the D-flip-flop, and the lower band positive phase digital signal is input to the data D. A data demodulator for demodulating data through a D-flip-flop; And a data clock recovery unit for restoring a data clock using the lower band digital signal and the demodulated data signal.

In another aspect of the configuration of the BPSK demodulation circuit, a phase difference is obtained when the BPSK modulated signal is separated into an upper band analog signal and a lower band analog signal through a second high pass filter and a second low pass filter whose cutoff frequency is a carrier frequency. The digital signals set in phase π, or ½ cycles of, are represented by two pairs of sideband comparators, which convert the phase of the upper band digital signal into two pairs of a positive phase signal and a local phase signal, respectively, which are the opposite phases of the lower band digital signal. The lower band digital signal is output from the lower band digital signals, and the phase difference between the lower band digital signal and the upper band digital signal is aligned with the carrier phase π, that is, 180 ^o . The first symbol edge signal and the lower band portion generated by the difference of the signals in the change portion The digital signal and the upper band in-phase phase difference of the digital signal is reduced glitches By been arranged in a phase π, that is 180 ^o carrier overlapping the second symbol edge signal generated by the difference of the signals in the phase change portion to a minimum A complementary phase detection clock generation unit using sideband separation and two pairs of comparators for generating a complementary phase detection clock signal; A glitch-free symbol edge signal is generated from the complementary phase detection clock signal through a diglyc filter, and applied to the clock C of the D-flip-flop, and the lower band positive phase digital signal is input to the data D. A data demodulator for demodulating data through a D-flip-flop; And a data clock recovery unit for restoring a data clock using the lower band digital signal and the demodulated data signal.

In one side, the complementary phase detection clock generation unit using sideband separation and differential output comparators (2nd Order HPF) for separating the BPSK-modulated differential signal into the sideband signal (2nd Order HPF); A second order low pass filter (2nd Order LPF) for separating the lower band signal; One pair of Sideband Differential Output Comparators, each of which converts the upper and lower bands into digital signals to match the phase with minimal glitch, ie the opposite phase, when aligning the carrier 180 ^° ; Since the phase difference between the lower band positive phase digital signal and the upper band area digital signal is aligned with a 180 ^° phase of a carrier, a first symbol edge is generated by detecting a change in the complementary phase caused by the difference of the digital signals. 1 Exclusive-OR gate; Since the phase difference between the lower sideband digital signal and the upper sideband digital signal is aligned with a phase of 180 ^° of the carrier, a second symbol edge is generated by detecting a portion of the complementary phase caused by the difference of the digital signals. 2 Exclusive-OR gates; And an AND gate for overlapping the first symbol edge signal and the second symbol edge signal to reduce jitter to generate a complementary phase detection clock signal with minimal glitches.

In another aspect, the sideband separation and the complementary phase detection clock generation unit using two pairs of comparators (2nd Order HPF) for separating the BPSK modulated differential signal into an upperband signal; A second order low pass filter (2nd Order LPF) for separating the lower band signal; Two pairs of sideband comparators, each of which converts the upper and lower bands into digital signals so that the glitch is minimized when the carrier is aligned with the phase 180 ^o of the carrier; Since the phase difference between the lower band positive phase digital signal and the upper band area digital signal is aligned with a 180 ^° phase of a carrier, a first symbol edge is generated by detecting a change in the complementary phase caused by the difference of the digital signals. 1 Exclusive-OR gate; Since the phase difference between the lower sideband digital signal and the upper sideband digital signal is aligned with a phase of 180 ^° of the carrier, a second symbol edge is generated by detecting a portion of the complementary phase caused by the difference of the digital signals. 2 Exclusive-OR gates; And an AND gate for overlapping the first symbol edge signal and the second symbol edge signal to reduce jitter to generate a complementary phase detection clock signal with minimal glitches.

In another aspect, the data demodulation unit includes a diglych filter for inputting the complementary phase detection clock signal of which the glitch is minimized; And a D-flip-flop, wherein the lower band digital signal is input to the data (D) input of the D-flip-flop, and a glitch-removed symbol edge signal is input to the clock (C) through the deglitch filter. By demodulating the demodulated data signal can be generated.

In another aspect, the data clock recovery unit may be synchronized by recovering the data clock signal through an exclusive-NOR using the lower band digital signal and the demodulated data signal.

In the BPSK demodulation method, when the BPSK modulated differential signal is separated into an upper band analog signal and a lower band analog signal through a second high pass filter and a second low pass filter having a cutoff frequency of carrier frequency, the phase difference of the carrier is π, That is, digital signals set at ½ cycles are displayed through sideband comparators. The phase of the upper band digital signal is converted into two pairs of a positive phase signal and a partial phase signal, respectively, which are the opposite phases of the lower band digital signal. Among them, a lower band positive phase digital signal is output, and a phase difference between the lower band positive phase digital signal and the upper band digital signal on the upper band portion is aligned to the phase π of the carrier, that is, 180 ^o . And a first symbol edge signal generated by the digital signal on the lower band portion Group the upper band in-phase because the phase differences are aligned to the phase π i.e. 180 ^o of the carrier of the digital signal and a second symbol edge signal generated by the difference of the signals in the phase change portion complementary to reduce to a minimum the glitch being overlapped by the AND gate Generating a complementary phase sensing clock using sideband separation and comparators for generating a phase sensing clock signal; A glitch-free symbol edge signal is generated from the complementary phase detection clock signal through a diglyc circuit and applied to a clock C of a D-flip flop, and the lower band positive phase digital signal is input to the data D. A data demodulating step of demodulating the data via the D-flip-flop; And a data clock recovery step of restoring a data clock through Exclusive-NOR (Exclusive NOR) using the lower band positive phase digital signal and the demodulated data signal. The ultra-low power broadband asynchronous phase shift demodulation method may be provided. have.

According to an embodiment of the present invention, it is possible to provide an asynchronous BPSK demodulation circuit and method thereof, which transmits broadband digital data and is extremely low in power while having a simple circuit.

In addition, it provides a demodulation method that can be applied to high-speed digital communication devices and mobile communication devices that require ultra-low power consumption, and is suitable for implementing a System on Chip (SoC), which is convenient and economical. In addition, the output duty cycle of sideband comparators changes due to the difference in CMOS FET characteristics and the comparator input offset problem according to the semiconductor manufacturing process, and is a complementary circuit in which the phases of the lowerband comparator and the upperband comparator are phased to minimize the glitches. Complement can increase the stability of the circuit to increase the yield.

1 is a circuit diagram for explaining an ultra-low power wideband asynchronous BPSK demodulation circuit configuration using a pair of sideband differential output comparators in one embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining an ultra-low power wideband asynchronous BPSK demodulation circuit configuration using two pairs of sideband comparators according to another embodiment of the present invention.

3 is a pair of sideband comparators in the path of a second symbol edge signal in a BPSK demodulation circuit using two pairs of sideband comparators in another aspect of the present invention; A second Exclusive-OR gate; And a case where the AND gate is excluded, phase detection with a small glitch which is a signal of a transmitter on which a random data is BPSK-modulated to a carrier having a frequency of 32 MHz and a signal appearing during a demodulation process on a receiving side, and a diglitch circuit input. It is a graph showing the signal.

FIG. 4 is a signal and reception side of a transmitter having BPSK modulated random data on a 32 MHz frequency carrier in a BPSK demodulation circuit using a pair of sideband differential output comparators on one side of an embodiment of the present invention. A graph showing the signals appearing in the demodulation process on the side, two pairs of symbol edge signals with reduced glitch which is a diglitch circuit input, and a complementary phase sensing clock signal which minimizes the glitch as an output of the AND gate.

FIG. 5 is a signal and receiving side of a BPSK demodulated circuit in which random data is BPSK-modulated to a carrier of 32 MHz frequency in a BPSK demodulation circuit using two pairs of sideband comparators according to another aspect of the present invention. Figure 2 shows the signals appearing during the demodulation process, two pairs of symbol edge signals with reduced glitch as the diglitch circuit input, and the complementary phase detection clock signal with minimized glitch as the output of the AND gate.

6 is a flowchart illustrating a demodulation scheme performed in an ultra low power broadband asynchronous BPSK demodulation circuit according to an embodiment of the present invention.

[Description of the code]

110: complementary phase detection clock generator using sideband separation and differential output comparators

120: data demodulator

130: data clock recovery unit

210: complementary phase detection clock generator using sideband separation and two pairs of comparators

220: data demodulator

230: data clock recovery unit

310: Complementary phase detection clock generation step using sideband separation and comparators

320: Data demodulation step

330: data clock restoration step

Hereinafter, the configuration and demodulation method of the BPSK demodulation circuit will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram illustrating a configuration of an ultra-low power broadband asynchronous BPSK demodulation circuit using a pair of sideband differential output comparators in one embodiment of the present invention. Referring to the configuration of the circuit as shown in FIG. 1, the BPSK demodulation circuit includes a complementary phase sensing clock generator 110, a data demodulator 120, and a data clock recovery unit 130 using sideband separation and differential output comparators. It may be configured to include).

First, the complementary phase detection clock generator 110 using sideband separation and differential output comparators 110 may include a second order low-pass filter, a first differential output comparator, and a second high pass filter. (2nd order high-pass filter), a second differential output comparator, a first Exclusive-OR gate, a second Exclusive-OR gate, and an AND gate, the signal input to the circuit for demodulation, i.e. When generating BPSK modulated signals by separating the upper band (USB) and the lower band (LSB) into side bands, the side bands are separated through a secondary filter whose cutoff frequency is a carrier frequency. The bands can be separated by a secondary low pass filter (LPF) and the upper bands by a secondary high pass filter (HPF).

Since the lower band signal from the outputs of the second and second filters appears half a period of the carrier later than the upper band signal, the phase difference is 180 ^° without the separate delay circuit. The first symbol by comparing a phase where the glitch is minimized when aligned, that is, a pair of a lower band positive phase signal and an upper band partial phase signal among the lower band digital signals and the upper band digital signals with a first exclusive-OR gate. An edge signal may be generated, and a second symbol edge signal may be generated by comparing signals having different pairs of the lower band region phase signal and the upper band band phase signal with a second exclusive-OR gate to generate a phase for detecting data. The first symbol edge signal, which is a pulse signal generated according to the change, and the second symbol edge signal are overlapped with an AND gate to minimize jitter to generate a complementary phase sensing clock with low glitches, thereby applying power to an integrated circuit. Reduces consumption and stabilizes circuits for higher yields.

Complementary phase-sensing clock signals below the phase π of the carrier are generated at each time point of the modulation signal's phase changes through the Exclusive-OR gates and the AND gates. Since the jitter of about π / 36 caused by the difference between tPLH) and the fall delay (tPHL) was removed by matching the comparator phase, the glitches caused by the jitter, which is about π / 36 phase shift, were mixed. The first symbol edge signal and the second symbol edge signal may be generated, and since the glitches of the symbol edge signals may have little or no overlapping portions, the complementary phase detection clock signal having the minimum glitches may be generated by the AND gate.

As illustrated, the data demodulator 120 may include a diglych filter and a D-Flip-Flop.

In detail, the data demodulator includes a glitch-free symbol edge signal through the Deglitch filter, for example, an analog or digital Deglitch filter, which removes glitches from the complementary phase detection clock signal. The lower band positive phase digital signal is input to the data (D) input of the D-flip-flop, and the symbol edge signal is input to the clock (C). By synchronizing the signals, demodulated data signals through the D-flip-flop may be generated.

The data clock recovery unit 130 may include an Exclusive-NOR gate as shown.

Here, the data clock may be restored by calculating the lower band positive phase digital signal and the demodulated data signal with an exclusive-NOR gate.

FIG. 2 illustrates a circuit diagram for explaining a configuration of an ultra low power broadband asynchronous BPSK demodulation circuit using two pairs of sideband comparators according to another embodiment of the present invention. Referring to the configuration of the circuit as shown in FIG. 2, the BPSK demodulation circuit includes a sideband separation and a complementary phase sensing clock generator 210, a data demodulator 220, and a data clock recovery unit using two pairs of comparators. 230).

First, the complementary phase detection clock generator 210 using sideband separation and two pairs of comparators may include a 2nd order low-pass filter, a first comparator, a second comparator, and a second order. A second pass high pass filter, a third comparator, a fourth comparator, a first Exclusive-OR gate, a second Exclusive-OR gate, and an AND gate, When generating the input signals, that is, the BPSK modulated signals by dividing the upper band (USB) and the lower band (LSB) into side bands, the separation of the side bands causes a secondary filter whose cutoff frequency is the carrier frequency. The lower band can be separated into a secondary low pass filter (LPF) and the upper band can be separated into a secondary high pass filter (HPF).

The lower band signal from the outputs of the second and second filters has half the period of the carrier later than the upper band signal, so that the glitch is minimized when the phase difference is aligned to the carrier phase 180 ^o without a separate delay circuit. The first symbol edge signal may be generated by comparing signals having a pair of the lower band positive phase signal and the upper band area phase signal among the phase, i.e., the lower band digital signals and the upper band digital signals, with a first exclusive-OR gate. The second symbol edge signal may be generated by comparing signals having different pairs of the lower band portion phase signal and the upper band band phase signal with a second exclusive-OR gate, and a pulse signal generated according to a phase change to detect data. Complementary phase detection with less glitches by minimizing jitter by overlapping the first symbol edge signal and the second symbol edge signal with an AND gate. By allowing the generation Luck, to stabilize the circuit to reduce the power consumption when applied to integrated circuit nopyige yield.

As illustrated, the data demodulator 220 may include a diglych filter and a D-flip-flop.

As illustrated, the data clock recovery unit 230 may include an Exclusive-NOR gate.

3 is a pair of sideband comparators in the path of a second symbol edge signal in a BPSK demodulation circuit using two pairs of sideband comparators in another aspect of the present invention; A second Exclusive-OR gate; And a random data signal having a 32 Mbps transmission rate, a signal at the transmitting side BPSK modulated with a 32 MHz frequency carrier, and signals appearing at a receiving side BPSK demodulation process except for the AND gate. One graph.

Referring to the graph from the top to the bottom, the graph (a) shows an embodiment of a random data signal to be modulated at the transmitting side, and the graph (b) shows a phase shift modulation measured at the transmitting side. The signal is shown, and graph (c) shows the BPSK signal of which the band is limited through the receiving side resonant circuit.

In addition, graph (d) shows a positive phase signal passing through the 2nd order LPF, and graph (e) shows a partial phase signal passing through the 2nd order high pass filter (2nd Order HPF). The graph (f) shows the positive phase digital signal of the second order low pass filter, and the graph (g) shows the digital signal on the part of the second order high pass filter.

In addition, graph (h) is a signal including a small glitch obtained by calculating a lower band positive phase digital signal and an upper band band digital signal using an exclusive-OR gate, and graph (i) shows a signal passing through a diglitch filter. The symbol edge signal is shown. And, graph (j) shows the demodulated data signal through the D-flip flop, and finally graph (k) shows the recovered data clock signal.

4 is a BPSK demodulation circuit using a pair of sideband differential output comparators on one side of an embodiment of the present invention, wherein a random data signal having a 32 Mbps transmission rate and a random data signal at a 32 MHz frequency carrier are shown in FIG. BPSK modulated signal is a graph showing the signal appearing during the BPSK demodulation process on the receiving side.

Also, graph (d) shows the positive phase signal passing through the 2nd Order LPF and graph (e) shows the positive phase signal passing through the 2nd Order High Pass Filter (2nd Order HPF). The phase-phase digital signal of the second-order lowpass filter is shown in graph (f), the portion-phase digital signal is shown in graph (h), and the portion-phase digital signal of the second-order highpass filter is plotted (g ) And the positive phase digital signal is shown in the graph (i).

In addition, graph (j) shows a first symbol edge signal including a small glitch obtained by calculating a lower band positive phase digital signal and an upper band band digital signal with a first exclusive-OR gate. ) Shows a second symbol edge signal containing less glitches, the lower band region digital signal and the upper band positive phase digital signal being calculated with a second exclusive-OR gate, and graph (l) shows the glitches with an AND gate. The minimized complementary phase detection clock signal is shown.

And, the graph (m) shows the symbol edge signal passing through the deglitch filter, the graph (n) shows the demodulated data signal through the D-flip flop, and finally the graph (o) shows the restored data clock. The signal is shown.

5 is a BPSK demodulation circuit using two pairs of sideband comparators according to another embodiment of the present invention, in which a random data signal having a 32 Mbps transmission rate and the random data as a carrier having a 32 MHz frequency are shown in FIG. It is a graph showing the signals of the modulated transmitter and the signals appearing in the BPSK demodulation process of the receiver.

The glitch of the graph (l) shown in FIG. 4 and FIG. 5 shown as an embodiment of the present invention is less than the glitches of the graph (h) shown in FIG. 3, and the symbol edge signal shown in the graph (m) shown in FIG. Since the pulse width of the circuit is improved, the circuit is improved to show a stable characteristic, and the pulse width of the symbol edge signal shown in the graph (m) shown in FIG. 4 becomes larger, so that the circuit is markedly improved to show a more stable characteristic.

Each signal shown is generally represented as a clean signal, and it can be seen that the demodulated signal is demodulated to a clear signal. Such a technique is a 0.18 占 퐉 technique, and can be realized, for example, at a high speed operation of 2 Gbps or more, and is a demodulation method capable of operating even beyond that.

FIG. 6 is a flowchart illustrating a demodulation scheme performed in an ultra low power broadband asynchronous BPSK demodulation circuit according to an embodiment of the present invention. Each step is performed through the configuration of the BPSK demodulation circuit described with reference to FIG. 1. Can be.

In step 310, the BPSK modulated signal is separated into an upper band and a lower band and converted into a digital signal, respectively, wherein the upper band analog signal and the lower band analog signal are cut through the secondary HPF and the secondary LPF, which are cutoff frequencies. When the signals are separated into phases, the digital signals set by the phase π, ½ cycle, of the carrier appear through sideband comparators. The phases of the upper and lower phase signals are respectively reversed from those of the lower band signal. Converted into two pairs, the lower band digital signal can be directly output. Generating a first symbol edge signal having a low glitch through a first Exclusive-OR gate, the signals having a pair of the lower band positive phase digital signal and the upper band local digital signal having a phase difference aligned with a phase 180 ^o of a carrier; A second symbol edge signal with less glitch is generated through a second Exclusive-OR gate through a second Exclusive-OR gate, where a pair of a lower band digital signal and a higher band digital signal on which the phase difference is aligned with the phase 180 ^o of the carrier are paired. The first symbol edge signal and the second symbol edge signal overlap each other by an AND gate, thereby generating a complementary phase sensing clock signal having minimal glitch.

In operation 320, a symbol edge signal from which unnecessary glitches are removed from the complementary phase detection clock signal may be generated from the complementary phase detection clock signal, and the signals output in operation 310 may be generated. The lower band positive phase digital signal may be input to the data D, and the data may be demodulated through the D-Flip-Flop input of the symbol edge signal to the clock C.

Finally, in step 330, the data clock may be restored through an exclusive-NOR gate using a lower band positive phase digital signal and the data demodulated in step 320 among the signals output in step 310.

Through this embodiment of the present invention, it is possible to provide an asynchronous BPSK demodulation circuit and a method thereof, which transmit broadband digital data and have a very low power and a simple circuit. In addition, it can be used for digital communication of devices requiring ultra-low power consumption, provides a demodulation method that can be applied to mobile communication devices, and is suitable for implementing a System on Chip (SoC), which is very convenient and economical.

The asynchronous BPSK demodulation method according to the embodiment may be implemented in the form of program instructions that may be executed by various computer means, and may be recorded in a computer readable medium. The computer readable medium may include a data structure, a data file, a program instruction, or the like in combination or singly. The program instructions recorded on the media may be those specially designed and constructed for the purposes of the embodiments, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of computer-readable recording media include magnetic media such as floppy disks, hard disks and magnetic tape, optical media such as DVDs and CD-ROMs, and magnetic disks such as floppy disks. Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as RAM, ROM, flash memory, and the like. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

Although the embodiments have been described by the limited embodiments and the drawings as described above, various modifications and variations are possible to those skilled in the art from the above description. For example, the described techniques may be performed in a different order than the described method, and / or components of the described systems, structures, devices, circuits, etc. may be combined or combined in a different form than the described method, or other components. Or even if replaced or replaced by equivalents, an appropriate result can be achieved.

Therefore, other implementations, other embodiments, and equivalents to the claims are within the scope of the claims that follow.

Claims

In an ultra-low power wideband asynchronous BPSK demodulation circuit configuration in which two pairs of complementary phases are matched by a pair of sideband differential output comparators using secondary sideband filters aligned with a phase of 180 degrees,

The BPSK modulated differential signal is a secondary filter whose carrier frequency is the carrier frequency, and the analog signals obtained by separating the lower band and the upper band are digitized into a positive phase signal and a partial phase signal through differential output comparators, respectively. Complementary phase detection clock with the smallest glitches to be used as a clock for data demodulation, using two pairs of complementary phases that minimize jitter when the lower-band digital signal and the upper-band digital signal are aligned with the carrier phase 180 o . A complementary phase sensing clock generator using sideband separation and differential output comparators to generate a signal;

A data demodulator for generating a symbol edge signal having no glitches from the complementary phase detection clock signal, and demodulating data by synchronizing the lower band digital signal with the falling edge of the symbol edge signal; And

A data clock recovery unit for restoring a data clock using the lower band positive phase digital signal and the demodulated data signal;

Including,

Complementary phase detection clock generation unit using the sideband separation and differential output comparators,

A second order low pass filter (2nd Order LPF), wherein a cutoff frequency for separating the modulated differential signal into a lower band is a carrier frequency;

A first differential output comparator for converting the lower band analog signal separated by the second LPF into digital signals on the positive phase and the partial phase;

A second-order high pass filter (2nd Order HPF), wherein a cutoff frequency for separating the modulated differential signal into an upper band is a carrier frequency;

A second differential output comparator for converting the upper band analog signal separated by the secondary HPF into digital signals on the positive phase and the partial phase;

A first Exclusive-OR gate configured to generate a first symbol edge signal in which a phase difference between the lower band positive phase digital signal and the upper band part digital signal is aligned with a 180 ° phase of a carrier;

A second Exclusive-OR gate configured to generate a second symbol edge signal in which a phase difference between a lower band portion digital signal and an upper side band positive phase digital signal is aligned with a phase 180 ° of a carrier; And

An AND gate for generating a complementary phase detection clock signal having a smaller glitch by overlapping the first symbol edge signal and the second symbol edge signal.

Including,

The data demodulation unit,

A glitch cancellation circuit for generating a symbol edge signal from which the glitch of the complementary phase detection clock signal is removed, that is, an analog or digital deglitch filter for removing glitch; And

D-Flip-Flop with the symbol edge signal as the clock and the lower band positive phase digital signal as the D input

Including,

The data clock recovery unit,

Exclusive-NOR gate comparing the lower band positive phase digital signal and the demodulated data signal

Including,

When the phases of the lower band digital signal and the upper band digital signal are aligned with the carrier phase 180 o , a phase in which the glitch is minimized, that is, the lower band is a positive phase and the upper band is a portion of the digital signals, the lower band, Partial and upper bands are the opposite pairs of digital signals that are positive phases, respectively, in opposite phases, so that the two digital signals are compared between the symbol edge and the symbol edge at the same rising edge and the same falling edge, respectively, so that less jitter is compared. Reducing the power consumption by reducing the glitch by generating the first symbol edge signal and the second symbol edge signal;

Since the first symbol edge signal and the second symbol edge signal are overlapped with each other, the glitch is minimized to generate a complementary phase sensing clock signal, thereby reducing the glitches, and the difference between the characteristics of the CMOS FET and the comparator input offset according to the semiconductor manufacturing process. To improve the yield by increasing the stability of the circuit by complementing the change with the complementary circuit; And

Separate delay circuit because the lower band digital signal separated by the secondary LPF and the first differential output comparator is delayed by the half period of the carrier, that is, the phase π than the upper band digital signal separated by the secondary HPF and the second differential output comparator Using two pairs of signals whose phase difference is aligned with the phase 180 o of the carrier. To facilitate data demodulation in a very low power asynchronous manner by reliably generating a symbol-edge signal with little glitches in the complementary phase detection clock signal resulting from the difference between the upper and lower band digital signals.

An ultra low power broadband asynchronous discrete phase shift demodulation circuit.
The method of claim 1,

The complementary phase detection clock generation unit using the sideband separation and differential output comparators comprises: a secondary LPF for separating the lower sideband analog signal; A first differential output comparator for digitizing the separated lower band; Secondary HPF for separating the high sideband analog signal; A second differential output comparator for digitizing the separated upper band; A first Exclusive-OR gate generating a first symbol edge signal; A second Exclusive-OR gate generating a second symbol edge signal; And an AND gate for generating a complementary phase detection clock signal having less glitch,

The lower band digital signal obtained by digitizing a lower band analog signal, in which the analog output of the secondary LPF whose carrier frequency is the cutoff frequency, is delayed by a phase π / 2, that is, a quarter period, of the carrier than the BPSK modulated signal by a first differential output comparator. Creates a,

The upper band digital signal in which the analog output of the secondary HPF, whose carrier frequency is the cutoff frequency, is digitized by a second differential output comparator from the upper band analog signal in which the carrier phase is π / 2, that is, 1/4 cycles faster than the BPSK modulated signal. By creating

Generating a first symbol edge signal through a first exclusive-OR gate by aligning the lower band positive phase digital signal and the upper band area digital signal in an inverted phase;

Generating a second symbol edge signal through a second exclusive-OR gate by aligning the lower band digital signal on the lower band portion and the upper band digital signal on the upper phase with an inverted phase;

Outputs a complementary phase detection clock signal and the lower band digital signal of the lower band generated through an AND gate where the first symbol edge signal and the second symbol edge signal overlap;

The phase difference between the secondary LPF output signal and the secondary HPF output signal is constant at the phase π of the carrier from the lower band to the upper band with respect to the carrier frequency to stably find the phase shift point of the BPSK modulated signal;

The phases of the lower band digital signal obtained by digitizing the lower band analog signal by the first differential output comparator and the upper band digital signal obtained by digitizing the upper band analog signal by the second differential output comparator are inverted phases. Reducing power consumption by minimizing glitches by allowing signals to be compared on the same rising edge and the same falling edge, respectively; And

By reducing the glitches by generating a complementary phase detection clock signal in which the first symbol edge signal and the second symbol edge signal overlap, the complementary change in the characteristics of the CMOS FET and the comparator input offset problem according to the semiconductor manufacturing process are complementary. Improve the yield by improving the stability of the circuit by complementary circuit

An ultra low power broadband asynchronous discrete phase shift demodulation circuit.
In an ultra low power broadband asynchronous BPSK demodulation circuit configuration in which two pairs of complementary phases are matched by two pairs of sideband comparators using second-order sideband filters aligned at 180 degrees,

The BPSK modulated differential signal is digitized into lower phase and phase phase signals by digitizing the analog signals that separate the lower band and the upper band into secondary phase filters with the carrier frequency of the cutoff frequency, respectively, through two pairs of comparators. Complementary phase detection with the least glitches to be used as clocks for data demodulation using two pairs of complementary phases that output a signal and minimize jitter when the lower-band digital signal and the upper-band digital signal are aligned with the carrier phase 180 o . A complementary phase detection clock generation unit using sideband separation and two pairs of comparators for generating a clock signal;

A data demodulator for generating a symbol edge signal having no glitches from the complementary phase detection clock signal, and performing data demodulation using the lower band positive phase digital signal and the symbol edge signal; And

A data clock recovery unit for restoring a data clock using the lower band positive phase digital signal and the demodulated data signal;

Including,

Complementary phase detection clock generation unit using the sideband separation and two pairs of comparators,

A second order low pass filter (2nd Order LPF), wherein a cutoff frequency for separating the modulated differential signal into a lower band is a carrier frequency;

A first comparator and a second comparator for converting the lower band analog signal separated by the second LPF into digital signals of a positive phase and a partial phase;

A second-order high pass filter (2nd Order HPF), wherein a cutoff frequency for separating the modulated differential signal into an upper band is a carrier frequency;

A third comparator and a fourth comparator for converting the upper band analog signal separated by the secondary HPF into digital signals on the positive phase and the partial phase;

A first Exclusive-OR gate generating a first symbol edge signal in which a phase difference between the lower band positive phase digital signal and the upper band area digital signal is aligned with a phase 180 ° of a carrier;

A second Exclusive-OR gate configured to generate a second symbol edge signal in which a phase difference between a lower band portion digital signal and an upper side band positive phase digital signal is aligned with a phase 180 ° of a carrier; And

An AND gate for generating a complementary phase detection clock signal having a smaller glitch by overlapping the first symbol edge signal and the second symbol edge signal.

Including,

The data demodulation unit,

A glitch cancellation circuit for generating a symbol edge signal from which the glitch of the complementary phase detection clock signal is removed, that is, an analog or digital deglitch filter for removing glitch; And

D-Flip-Flop with the symbol edge signal as the clock and the lower band positive phase digital signal as the D input

Including,

The data clock recovery unit,

Exclusive-NOR gate comparing the lower band positive phase digital signal and the demodulated data signal

Including,

When the phases of the lower band digital signal and the upper band digital signal are aligned with the carrier phase 180 o , a phase in which the glitch is minimized, that is, the lower band is a positive phase and the upper band is a portion of the digital signals, the lower band, The partial and upper bands are each inverted phases of the other pair of digital signals that are in phase, so that the two digital signals are compared between the symbol edge and the symbol edge at the same rising edge and the same falling edge, respectively, so that the jitter is less compared. Reducing the power consumption by reducing the glitch by generating the first symbol edge signal and the second symbol edge signal;

Since the first symbol edge signal and the second symbol edge signal are overlapped with each other, the glitch is minimized to generate a complementary phase sensing clock signal, thereby reducing the glitches, and the difference between the characteristics of the CMOS FET and the comparator input offset according to the semiconductor manufacturing process. To improve the yield by increasing the stability of the circuit by complementing the change with the complementary circuit; And

Since the lower band digital signal separated by the secondary LPF, the first comparator and the second comparator is delayed by the half period of the carrier, that is, the phase π, than the upper band digital signal separated by the secondary HPF, the third comparator and the fourth comparator It uses two pairs of signals whose phase difference is aligned with the phase 180 o of the carrier without a separate delay circuit. To facilitate data demodulation in a very low power asynchronous manner by reliably generating a symbol edge signal with little glitches in the complementary phase detection clock signal resulting from the difference between the lower band digital signal and the upper band digital signal.

An ultra low power broadband asynchronous discrete phase shift demodulation circuit.
The method of claim 3,

The complementary phase detection clock generation unit using the sideband separation and two pairs of comparators includes a secondary LPF for separating the lower sideband analog signal; A first comparator and a second comparator for digitizing the separated lower band; Secondary HPF for separating the high sideband analog signal; A third comparator and a fourth comparator for digitizing the separated upper band; A first Exclusive-OR gate generating a first symbol edge signal; A second Exclusive-OR gate generating a second symbol edge signal; And an AND gate for generating a complementary phase detection clock signal having less glitch,

The lower band where the analog output of the secondary LPF whose carrier frequency is the cutoff frequency is digitized by a first comparator and a second comparator with a lower band analog signal whose carrier phase is π / 2, i.e., 1/4 period later than the BPSK modulated signal. Generate digital signals,

The upper band, in which the analog output of the secondary HPF, whose carrier frequency is the cutoff frequency, is digitized by a third comparator and a fourth comparator. To generate digital signals,

Generating a first symbol edge signal through a first exclusive-OR gate by aligning the lower band positive phase digital signal and the upper band area digital signal in an inverted phase;

Generating a second symbol edge signal through a second exclusive-OR gate by aligning the lower band digital signal on the lower band portion and the upper band digital signal on the upper phase with an inverted phase;

Outputs a complementary phase detection clock signal and the lower band digital signal of the lower band generated through an AND gate where the first symbol edge signal and the second symbol edge signal overlap;

The phase difference between the secondary LPF output signal and the secondary HPF output signal is constant at the phase π of the carrier from the lower band to the upper band with respect to the carrier frequency to stably find the phase shift point of the BPSK modulated signal;

The phases of the lower band digital signals obtained by digitizing the lower band analog signal by the first comparator and the second comparator and the upper band digital signals which digitized the upper band analog signal by the third comparator and the fourth comparator are inverted in phase. Reducing the jitter by minimizing glitches by allowing the digital signals to be compared at the same rising edge and the same falling edge, respectively, to reduce power consumption; And

By reducing the glitches by generating a complementary phase detection clock signal in which the first symbol edge signal and the second symbol edge signal overlap, the complementary change in the characteristics of the CMOS FET and the comparator input offset problem according to the semiconductor manufacturing process are complementary. Improve the yield by improving the stability of the circuit by complementary circuit

An ultra low power broadband asynchronous discrete phase shift demodulation circuit.
The method according to claim 1 or 3,

The data demodulator comprises a glitch removal circuit and a D-flip flop,

Generating a glitch-free symbol edge signal from the complementary phase detection clock signal including the glitch through the glitch cancellation circuit, that is, an analog or digital deglitch filter,

Demodulating the data synchronized to the falling edge through the D-Flip-Flop inputting the lower band digital signal as the data D and inputting the symbol edge signal to the clock C. that

An ultra low power broadband asynchronous discrete phase shift demodulation circuit.
The method according to claim 1 or 3,

The data clock recovery unit includes an exclusive negative-OR gate.

Using the lower band positive phase digital signal and the demodulated data signal as input to the Exclusive-NOR gate,

Restoring a data clock signal through the output of the Exclusive-NOR gate

An ultra low power broadband asynchronous discrete phase shift demodulation circuit.
In the ultra-low power broadband asynchronous BPSK demodulation method using second-order sideband filters aligned to 180 degrees of phase and aligning sideband comparators,

The BPSK-modulated differential signal is digitized into analogue signals of the lower band and the upper band by the secondary filters whose carrier frequency is the carrier frequency. And generate a complementary phase detection clock signal having the least glitches to be used as a clock for data demodulation by using two pairs of complementary phases in which jitter is minimized when the lower and upper band digital signals are aligned with a carrier phase of 180 ° . Generating a complementary phase sensing clock using sideband separation and comparators;

A data demodulating step of generating a symbol edge signal without glitch from the complementary phase detection clock signal including a glitch, and demodulating data by synchronizing the lower band digital signal with the falling edge of the symbol edge signal; And

Restoring a data clock using the lower band positive phase digital signal and the demodulated data signal;

Including,

Complementary phase detection clock generation step using the sideband separation and comparators,

Separating the modulated differential signal into a lower band by a second order low pass filter having a cutoff frequency of carrier frequency;

Converting the lower band analog signal separated by the secondary LPF into digital signals on the phase and region by a pair of comparators;

Separating the modulated differential signal into an upper band by a second order high pass filter having a cutoff frequency of carrier frequency;

Converting the upper band analog signal separated into the secondary HPF into digital signals on the phase and region by a pair of comparators;

Comparing the lower band digital signal with the upper band digital signal by an exclusive-OR gate;

Generating a first symbol edge signal having a phase difference between a lower band positive phase digital signal and an upper band digital signal on the upper band region by a first Exclusive-OR gate aligned with a phase of 180 ° of a carrier;

A second Exclusive-OR step of the phase of the lower sideband and the upper sideband portion the digital signal in-phase digital signals by the gate generating a second symbol signal edges aligned to the phase of the carrier 180 o; And

Generating a complementary phase detection clock signal having a smaller glitch by overlapping the first symbol edge signal and the second symbol edge signal by an AND gate.

Including,

The data demodulation step,

Generating a symbol edge signal from which the glitch of the complementary phase detection clock signal is removed by a glitch elimination circuit, that is, an analog or digital deglitch filter for eliminating glitch; And

Demodulating the data using the D-flip flop as the clock (C) and the lower band digital signal as the data (D) input.

Including,

Restoring the data clock,

Restoring a data clock by comparing the lower band digital signal and the demodulated data signal by an exclusive-NOR gate;

Including,

When the phases of the lower band digital signal and the upper band digital signal are aligned with the carrier phase 180 o , a phase in which the glitch is minimized, that is, the lower band is a positive phase and the upper band is a portion of the digital signals, the lower band, Partial and upper bands are the opposite pairs of digital signals that are positive phases, respectively, in opposite phases, so that the two digital signals are compared between the symbol edge and the symbol edge at the same rising edge and the same falling edge, respectively, so that less jitter is compared. Reducing the power consumption by reducing the glitch by generating the first symbol edge signal and the second symbol edge signal;

Since the first symbol edge signal and the second symbol edge signal are overlapped with each other, the glitch is minimized to generate a complementary phase sensing clock signal, thereby reducing the glitches, and the difference between the characteristics of the CMOS FET and the comparator input offset according to the semiconductor manufacturing process. To improve the yield by increasing the stability of the circuit by complementing the change with the complementary circuit; And

Separate delay circuit because the lower band digital signal separated by the secondary LPF and the first differential output comparator is delayed by the half period of the carrier, that is, the phase π than the upper band digital signal separated by the secondary HPF and the second differential output comparator Using two pairs of signals whose phase difference is aligned with the phase 180 o of the carrier. To facilitate data demodulation in a very low power asynchronous manner by reliably generating a symbol-edge signal with little glitches in the complementary phase detection clock signal resulting from the difference between the upper and lower band digital signals.

Ultra low power broadband asynchronous discrete phase shift demodulation method.