WO2017101238A1 - 一种保证智能变电站保护跳闸可靠性的装置和方法 - Google Patents

一种保证智能变电站保护跳闸可靠性的装置和方法 Download PDF

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WO2017101238A1
WO2017101238A1 PCT/CN2016/079222 CN2016079222W WO2017101238A1 WO 2017101238 A1 WO2017101238 A1 WO 2017101238A1 CN 2016079222 W CN2016079222 W CN 2016079222W WO 2017101238 A1 WO2017101238 A1 WO 2017101238A1
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fpga
main
cpu
trip
information
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PCT/CN2016/079222
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English (en)
French (fr)
Inventor
许宗光
文继峰
陈勇
李响
李彦
赵玉灿
袁明
周强
李广华
赵天恩
李德文
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南京南瑞继保电气有限公司
南京南瑞继保工程技术有限公司
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Application filed by 南京南瑞继保电气有限公司, 南京南瑞继保工程技术有限公司 filed Critical 南京南瑞继保电气有限公司
Priority to GB1811082.5A priority Critical patent/GB2561129B/en
Priority to MYPI2018000951A priority patent/MY197033A/en
Priority to BR112018012323-4A priority patent/BR112018012323B1/pt
Priority to US16/062,635 priority patent/US10637287B2/en
Priority to RU2018124354A priority patent/RU2690175C1/ru
Priority to AU2016370128A priority patent/AU2016370128B2/en
Publication of WO2017101238A1 publication Critical patent/WO2017101238A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H1/00—Details of emergency protective circuit arrangements
    • H02H1/0061—Details of emergency protective circuit arrangements concerning transmission of signals
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J13/00—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J13/00—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network
    • H02J13/00006—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network characterised by information or instructions transport means between the monitoring, controlling or managing units and monitored, controlled or operated power network element or electrical equipment
    • H02J13/00016—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network characterised by information or instructions transport means between the monitoring, controlling or managing units and monitored, controlled or operated power network element or electrical equipment using a wired telecommunication network or a data transmission bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/22—Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
    • Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
    • Y04S10/00—Systems supporting electrical power generation, transmission or distribution
    • Y04S10/16—Electric power substations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
    • Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
    • Y04S40/00—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them
    • Y04S40/12—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them characterised by data transport means between the monitoring, controlling or managing units and monitored, controlled or operated electrical equipment
    • Y04S40/124—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them characterised by data transport means between the monitoring, controlling or managing units and monitored, controlled or operated electrical equipment using wired telecommunication networks or data transmission busses

Definitions

  • the invention relates to a device and a method for ensuring the reliability of a smart substation protection trip.
  • the digital substation is the development direction of the current substation automation system, especially the promulgation of the international standard (IEC61850) of the substation communication network and system, which provides a standard specification for the construction of digital substation, which greatly promotes the development of digital substation application construction.
  • IEC61850 international standard
  • Ethernet becomes the most important communication medium.
  • the communication network replaces the secondary cable, and the AC module and control module of the traditional protection and control device are eliminated. All the information is transmitted through the process layer network, and the substation is reduced for purchase.
  • the cost of secondary cable and cable laying also greatly simplifies the workload of conventional substations for secondary wiring.
  • the trip protection error of the relay protection device is realized by the start-up plus protection logic.
  • the starting condition and the operating condition of the device are different, and the starting conditions are relatively easy to be satisfied. For example, the voltage and current fluctuations will cause the protection to start. It will not be exported to trip the circuit breaker; the conditions of the protection action are strict.
  • the device will start after the device starts up and meets the protection action logic condition, and the outlet trips the circuit breaker.
  • the relay circuit is blocked to ensure that the device cannot operate the circuit breaker in any unactivated state.
  • the transmission of switching and trip signals is implemented by the Goose service in the IEC61850 standard, which is a hard-wired network data communication method that replaces traditional intelligent electronic devices.
  • the measurement and control and protection device sends a jump command to the intelligent operation box through Goose, and the intelligent operation box performs the switching of the switch according to the received command.
  • the digital substation protection device there is still logic for protection and startup, but eventually it will jump through Ethernet packets after satisfying the software logic.
  • the gate message is sent.
  • digital substation protection devices With the increasing requirements for intelligence, information, and digitization, digital substation protection devices use a large number of integrated circuit devices, they bear the core functions of the system, but as the hardware platform becomes more complex and larger, The usage of integrated devices will increase, and the risk of abnormal operation of the protection device due to some hardware failures will become higher and higher. The failure of the common hardware on the data processing link will cause the protection device to malfunction.
  • the present invention provides an apparatus and method for ensuring the reliability of intelligent substation protection tripping, adopting dual FPGA and dual CPU architecture, and improving the anti-missing capability of the protection device through the data link redundancy check mode, in the hardware device.
  • failures such as single event interference (SEU)
  • SEU single event interference
  • An apparatus for ensuring reliability of a smart substation protection trip comprising: a connected main CPU and a sub CPU, a connected main FPGA and a sub-FPGA, wherein the main FPGA and the sub-FPGA are connected to a physical layer of the protection device, Both the primary CPU and the secondary CPU are associated with the status monitoring data output of the protected device.
  • the main CPU sends the processing result to the main FPGA, and the sub CPU sends the processing result to the sub-FPGA.
  • the sub-FPGA receives the information sent by the sub-CPU and synchronizes the current information with the main FPGA.
  • the main FPGA compares the current trip information obtained from the main CPU with the current trip information obtained from the sub-FPGA. If they are consistent, the main FPGA sends the information received from the main CPU. To the protection device, otherwise, the information received from the main CPU is discarded.
  • Step 1 The main CPU and the sub CPU respectively collect state monitoring data of the protected device, perform protection logic judgment according to the sampled value, and send the result of the protection action to the corresponding FPGA, wherein the main CPU transmits the trip message to the main
  • the FPGA calculates the CRC corresponding to the acquired data and transmits it to the main FPGA; the sub CPU transmits the trip state to the sub-FPGA;
  • Step 2 The primary FPGA and the secondary FPGA perform preprocessing on the received data, wherein the secondary FPGA synchronizes the current information with the primary FPGA; the primary FPGA parses the information received from the primary CPU: if the information does not include the trip information, then the primary The FPGA directly attaches the CRC to the physical layer received from the main CPU to the physical layer of the protection device; if the information includes the trip information, the primary FPGA obtains the current trip information obtained from the main CPU and the current trip information obtained from the secondary FPGA. For consistency comparison, if they are consistent, the primary FPGA directly sends the CRC to the physical layer of the protection device from the tail of the information received from the primary CPU. Otherwise, the information received from the primary CPU is discarded.
  • the hardware device fails, any processing unit will get the wrong trip result, and eventually the trip start information detected by the dual FPGA will be inconsistent, and the trip message will be forbidden to exit, thus abnormal.
  • the effect is controlled within the device.
  • the device anti-missing capability can be significantly enhanced, and the reliability and stability of the system can be improved.
  • FIG. 1 is a structural block diagram of an apparatus for ensuring reliability of a smart substation protection trip
  • FIG. 2 is an information flow diagram of a method for ensuring the reliability of intelligent substation protection tripping according to the present invention.
  • a device for ensuring the reliability of the intelligent substation protection trip comprising a connected main CPU and a sub CPU, a connected main FPGA and a sub-FPGA, and the main FPGA and the sub-FPGA are both physically connected to the protection device (
  • the PHY is connected, and both the main CPU and the sub CPU are connected to the status monitoring data output of the protected device.
  • the hardware architecture adopts dual CPU plus dual FPGA redundancy architecture.
  • the FPGA acts as a coprocessor for network message processing, and the dual CPU receives the same measurement data as the basis for protection logic judgment.
  • the device acts as a protection device supporting the IEC61850 protocol, which monitors the measurement status of the protected device, including switching quantity, voltage, current, phase, etc., and when detecting the failure of the protected device, sends a Goose message through the GOOSE service to issue a trip command. Go to the intelligent operation box and cut off the connection between the protected equipment and the primary system.
  • the main CPU sends the processing result to the primary FPGA, and the secondary CPU sends the processing result to the secondary FPGA.
  • the secondary FPGA receives the information sent by the secondary CPU and synchronizes the current information with the primary FPGA.
  • the main FPGA compares the current trip information obtained from the main CPU with the current trip information obtained from the sub-FPGA. If they are consistent, the main FPGA sends the information received from the main CPU. To the protection device, otherwise, the information received from the main CPU is discarded.
  • the primary FPGA and the secondary FPGA perform one-way communication, and the secondary FPGA sends the message to the primary FPGA in a framing manner and periodically.
  • the communication between the primary and secondary FPGAs generally adopts a high-speed communication interface, and uses framing to communicate and periodically transmit.
  • the physical interface can be any standard interface such as MII, EPPI, SPI, PCIE, RGMII, for example, RGMII (Reduced Gigabit Media Independent) Interface: Simplified Gigabit Media Independent Interface)
  • the interface sends, the data bandwidth is 1Gbps, and all data is less than 1us.
  • Two-way communication between the main FPGA and the physical layer chip of the protection device such as S3MII bidirectional communication interface, one-way communication between the sub-FPGA and the physical layer chip of the protection device, such as S3MII communication interface, physical layer of the secondary FPGA receiving protection device The message sent.
  • Ethernet message link layer CRC Cyclic Redundancy Check Code
  • FPGA Fibre Channel Control Coding
  • the CRC is calculated by the main CPU and then sent through the FPGA. Specifically, when the main CPU sends a message to the main FPGA, the CRC corresponding to the message is simultaneously sent, and the main FPGA sends the process to the Ethernet message.
  • the CRC is sent directly at the end of the frame, and the CRC is no longer calculated by itself and the main FPGA does not change any message content.
  • the main FPGA is only responsible for deciding whether to send or not, and can not change any message content.
  • the content of the message changes, and the receiving side cannot receive the correct message, ensuring that the protection device does not malfunction. ,can have Effectiveness guarantees data integrity.
  • the main FPGA can determine the type of the packets to be sent by parsing the packet format. Sexual verification. If the message does not contain the trip information (that is, the ordinary message), it does not need to be directly sent out by the consistency check.
  • the link trip information list synchronized with the secondary FPGA needs to be compared, when the data of the dual FPGA is simultaneously When the link is allowed to trip, the local frame packet can be sent through the Ethernet. Otherwise, the frame data is discarded.
  • the format of the trip information supports multiple LD devices (Laser disc), and in this example, 16 different trip start signal states are supported.
  • the frame header, frame tail, and check are added, and the specific value of the trip start signal is encoded to ensure that the code value is as irregular as possible, preventing 1 bit misalignment and misjudgment after the overall shift.
  • a method for ensuring the reliability of the intelligent substation protection trip includes the following steps:
  • Step 1 The main CPU and the sub CPU respectively collect state monitoring data of the protected device, perform protection logic judgment according to the sampled value, and send the result of the protection action to the corresponding FPGA, wherein the main CPU transmits the trip message to the main
  • the FPGA calculates the CRC corresponding to the acquired data and transmits it to the main FPGA; the sub CPU transmits the trip state to the sub-FPGA;
  • Step 2 The primary FPGA and the secondary FPGA perform preprocessing on the received data, wherein the secondary FPGA synchronizes the current information with the primary FPGA; the primary FPGA parses the information received from the primary CPU: if the information does not include the trip information, then the primary The FPGA directly attaches the CRC to the physical layer received from the main CPU to the physical layer of the protection device; if the information includes the trip information, the primary FPGA obtains the current trip information obtained from the main CPU and the current trip information obtained from the secondary FPGA. Consistency comparison, if consistent, the main FPGA The CRC is directly attached to the physical layer received from the main CPU to the physical layer of the protection device, otherwise, the information received from the main CPU is discarded.
  • the hardware device fails. Any processing unit that obtains an incorrect trip result will eventually cause the trip start information detected by the dual FPGA to be inconsistent, and the trip message will be prohibited from being exported, thereby controlling the abnormal effect in the device.
  • the device anti-missing capability can be significantly enhanced, and the reliability and stability of the system can be improved.

Abstract

一种保证智能变电站保护跳闸可靠性的装置和方法。其中，装置包括相连的主CPU和副CPU、相连的主FPGA和副FPGA，主FPGA和副FPGA均与保护装置的物理层相连，主CPU和副CPU均与被保护设备的状态监视数据输出端相连：其中，主CPU将处理结果发送给主FPGA，副CPU将处理结果发送给副FPGA，副FPGA接收到副CPU发送的信息后向主FPGA同步当前的信息；当主FPGA接收到跳闸信息时，则主FPGA对从主CPU获得的当前的跳闸信息与从副FPGA获得的当前的跳闸信息进行一致性比较，若一致，则主FPGA将从主CPU接收的信息发送至保护装置，否则，丢弃从主CPU接收的信息。提高保护装置防误能力，在硬件器件、单事件干扰(SEU)等失效情况下，确保装置不会由于未知错误导致一次设备误动作。

Description

一种保证智能变电站保护跳闸可靠性的装置和方法 技术领域
本发明涉及一种保证智能变电站保护跳闸可靠性的装置和方法。
背景技术
数字化变电站是当前变电站自动化系统的发展方向，尤其是变电站通信网络与系统的国际标准(IEC61850)的颁布，为数字化变电站建设提供了标准规范，大大推动了数字化变电站应用建设的发展。数字化变电站中，以太网成为最主要的通信介质，应用通信网络取代二次电缆，取消了传统保护测控装置的交流模块和控制模块，所有信息均通过过程层网络来传输，缩减了变电站用于购买二次电缆和电缆铺设的成本，同时也大幅度简化了传统变电站用于二次接线的工作量。
在传统变电站中,继电保护装置的跳闸防误是采用启动加保护逻辑实现，装置的启动条件和动作条件不同，启动条件比较容易满足，如电压、电流波动等都会造成保护启动，此时装置并不会出口使断路器跳闸；而保护动作的条件比较严格的，当被保护的设备出现故障，在装置先启动、且满足保护动作逻辑条件后，装置才会动作，出口使断路器跳闸。在传统的继电保护装置上是通过继电器回路闭锁的方式保证在未启动的状态下装置任何行为都不能操作断路器。
在智能数字化变电站中，对于开关量和跳闸信号的传输是通过IEC61850标准中的Goose服务实现的，它是一种替代传统智能电子设备之间硬接线的网络数据通讯方式。测控、保护装置通过Goose发出跳合命令到智能操作箱，智能操作箱根据收到的命令执行开关的分合。在数字化变电站保护装置中，仍然存在保护和启动的逻辑，但最终会在满足软件逻辑后通过以太网报文的方式将跳 闸报文发出。
随着智能化、信息化、数字化的要求越来越高，数字化变电站保护装置采用了大量的集成电路器件，他们承担着系统的核心功能，但是随着硬件平台越来越复杂，规模日益庞大，集成器件的使用量随之攀升，保护装置由于某些硬件失效导致工作异常的风险也越来越高，其中的数据处理环节上公共的硬件失效后容易造成保护装置误动作。
同时，随着工艺技术的迅速发展，创新进一步提高了器件在速率、容量和功耗等方面的性能。然而，技术的发展也突出了以前可以忽略的某些效应，例如，单事件干扰(SEU)导致的软误码影响越来越大。虽然通过仔细的IC设计，器件的单位比特的软误码率有所下降，但是每一工艺节点的逻辑容量在不断翻倍，片内SRAM比特数量也随之增长。而在保护装置中采用了大量的基于SRAM工艺的处理器、存储器、FPGA，单事件干扰(SEU)导致的软误码的风险也随之突显出来，该异常的特点在于监测相当困难，往往要等到保护出现不正确动作行为时才能够被发现。
发明内容
针对上述问题，本发明提供一种保证智能变电站保护跳闸可靠性的装置和方法，采用双FPGA和双CPU架构，通过数据链路冗余校验的方式，提高保护装置防误能力，在硬件器件、单事件干扰(SEU)等失效情况下，确保装置不会由于未知错误导致一次设备误动作。
为实现上述技术目的，达到上述技术效果，本发明通过以下技术方案实现：
一种保证智能变电站保护跳闸可靠性的装置，其特征在于，包括相连的主CPU和副CPU、相连的主FPGA和副FPGA，所述主FPGA和副FPGA均与保护装置的物理层相连，所述主CPU和副CPU均与被保护设备的状态监视数据输出端相 连：
其中，主CPU将处理结果发送给主FPGA，副CPU将处理结果发送给副FPGA，副FPGA接收到副CPU发送的信息后向主FPGA同步当前的信息；
当主FPGA接收到跳闸信息时，则主FPGA对从主CPU获得的当前的跳闸信息与从副FPGA获得的当前的跳闸信息进行一致性比较，若一致，则主FPGA将从主CPU接收的信息发送至保护装置，否则，丢弃从主CPU接收的信息。
一种保证智能变电站保护跳闸可靠性的方法，其特征在于，具体包括如下步骤：
步骤1、主CPU和副CPU分别采集被保护设备的状态监视数据,根据采样值进行保护逻辑判断，并将保护动作的结果发送给各自对应的FPGA，其中，主CPU将跳闸报文传送至主FPGA，同时计算采集数据对应的CRC并传送至主FPGA；副CPU将跳闸状态传送至副FPGA；
步骤2、主FPGA和副FPGA对接收到的数据进行预处理，其中，副FPGA向主FPGA同步当前的信息；主FPGA对从主CPU接收的信息进行解析：若信息不包含跳闸信息，则主FPGA直接将CRC附在从主CPU接收的信息尾部发送至保护装置的物理层；若信息包含跳闸信息，则主FPGA对从主CPU获得的当前的跳闸信息与从副FPGA获得的当前的跳闸信息进行一致性比较，若一致，则主FPGA直接将CRC附在从主CPU接收的信息尾部发送至保护装置的物理层，否则，丢弃从主CPU接收的信息。
本发明的有益效果是：
第一、硬件器件失效，任何处理单元得出错误的跳闸结果，最终都会导致双FPGA检测到的跳闸启动信息不一致，跳闸报文会被禁止出口，从而将异常的 影响控制在装置内。
第二、在得出正确的跳闸结果后，若在传输过程中，由于物理信号干扰、SEU问题等引起的报文内容变动，会导致CRC与报文内容不一致，接收方会将报文丢弃，不会导致误跳闸。
第三、通过在数字化变电站保护设备上应用本发明的内容，可以显著增强设备防误能力，提高系统的可靠性以及稳定性。
附图说明
图1是本发明一种保证智能变电站保护跳闸可靠性的装置的结构框图；
图2是本发明一种保证智能变电站保护跳闸可靠性的方法的信息流向图。
具体实施方式
下面结合附图和具体的实施例对本发明技术方案作进一步的详细描述，以使本领域的技术人员可以更好的理解本发明并能予以实施，但所举实施例不作为对本发明的限定。
一种保证智能变电站保护跳闸可靠性的装置，如图1所示，包括相连的主CPU和副CPU、相连的主FPGA和副FPGA，所述主FPGA和副FPGA均与保护装置的物理层(PHY)相连，所述主CPU和副CPU均与被保护设备的状态监视数据输出端相连。硬件架构采用双CPU加双FPGA冗余架构，FPGA作为网络报文处理的协处理器，双CPU接收同一份测量数据作为保护逻辑判断的依据。
装置作为一个支持IEC61850协议的保护装置，其监视被保护设备的测量状态，包括开关量、电压、电流、相位等信息，当检测到被保护设备故障时，通过GOOSE服务发送Goose报文发出跳闸命令到智能操作箱，切断被保护设备和一次系统的联系。
其中，主CPU将处理结果发送给主FPGA，副CPU将处理结果发送给副FPGA， 副FPGA接收到副CPU发送的信息后向主FPGA同步当前的信息。
当主FPGA接收到跳闸信息时，则主FPGA对从主CPU获得的当前的跳闸信息与从副FPGA获得的当前的跳闸信息进行一致性比较，若一致，则主FPGA将从主CPU接收的信息发送至保护装置，否则，丢弃从主CPU接收的信息。
优选，主FPGA和副FPGA之间进行单向通信，副FPGA采用成帧方式、周期的向主FPGA发送消息。主、副FPGA间通讯一般采用高速通讯接口，采用成帧方式进行通讯，周期发送，其物理接口可以是MII、EPPI、SPI、PCIE、RGMII等任意标准接口，比如，采用RGMII(Reduced Gigabit Media Independent Interface：精简吉比特介质独立接口)接口发送，数据带宽为1Gbps，发送完所有数据不足1us。
主FPGA和保护装置的物理层芯片之间进行双向通信，比如S3MII双向通信接口，副FPGA和保护装置的物理层芯片之间进行单向通信，比如S3MII通信接口，副FPGA接收保护装置的物理层发送的消息。
现有设计中，以太网报文链路层CRC(循环冗余校验码)作为以太网数据的标准校验方式，通常由负责网络信息处理的FPGA计算，在发送出口时附在有效报文尾部发出，当接收侧检测到报文内容和CRC不一致的情况，会在数据链路层将数据丢掉，不会解析和执行错误报文的内容。而本发明中，CRC由主CPU计算，然后通过FPGA发出，具体为：主CPU在向主FPGA发送报文时，同时发送报文对应的CRC，主FPGA在发送过程以太网报文时将此CRC直接附在帧尾发出，不再自行计算CRC且主FPGA不改变任何报文内容。这样的话，主FPGA只负责决定是否发送，不能改变任何报文内容，在此期间的任何处理或是异常导致报文内容改变，接收侧都不能接收到正确报文，确保保护装置不会误动作，能有 效保证数据完整性。
一般的，装置发送的报文中只有少部分为跳闸报文，主FPGA接收主CPU发送的报文后，主FPGA能够通过解析报文格式判断待发送报文是何种类型，是否需要进行一致性校验。其中，报文若不包含跳闸信息(即普通报文)则无需一致性校验直接发送出去，对于跳闸报文需要经过与副FPGA同步来的链路跳闸信息列表对比，当双FPGA的数据同时允许本链路跳闸时，本帧报文才能通过以太网发出，否则将本帧数据丢弃。
其中，跳闸信息的格式支持多LD设备(Laser disc)，本实例中支持16个不同的跳闸启动信号状态。同时考虑到防误，添加了帧头、帧尾、校验，并对跳闸启动信号的具体值做了编码，保证编码值尽量无规律，防止1bit错位、整体移位后误判。
相应的，如图2所示，一种保证智能变电站保护跳闸可靠性的方法，具体包括如下步骤：
步骤1、主CPU和副CPU分别采集被保护设备的状态监视数据,根据采样值进行保护逻辑判断，并将保护动作的结果发送给各自对应的FPGA，其中，主CPU将跳闸报文传送至主FPGA，同时计算采集数据对应的CRC并传送至主FPGA；副CPU将跳闸状态传送至副FPGA；
步骤2、主FPGA和副FPGA对接收到的数据进行预处理，其中，副FPGA向主FPGA同步当前的信息；主FPGA对从主CPU接收的信息进行解析：若信息不包含跳闸信息，则主FPGA直接将CRC附在从主CPU接收的信息尾部发送至保护装置的物理层；若信息包含跳闸信息，则主FPGA对从主CPU获得的当前的跳闸信息与从副FPGA获得的当前的跳闸信息进行一致性比较，若一致，则主FPGA 直接将CRC附在从主CPU接收的信息尾部发送至保护装置的物理层，否则，丢弃从主CPU接收的信息。
本发明的有益效果是：
第一、硬件器件失效，任何处理单元得出错误的跳闸结果，最终都会导致双FPGA检测到的跳闸启动信息不一致，跳闸报文会被禁止出口，从而将异常的影响控制在装置内。
第二、在得出正确的跳闸结果后，若在传输过程中，由于物理信号干扰、SEU问题等引起的报文内容变动，会导致CRC与报文内容不一致，接收方会将报文丢弃，不会导致误跳闸。
第三、通过在数字化变电站保护设备上应用本发明的内容，可以显著增强设备防误能力，提高系统的可靠性以及稳定性。
以上仅为本发明的优选实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或者等效流程变换，或者直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (6)

  1. 一种保证智能变电站保护跳闸可靠性的装置，其特征在于，包括相连的主CPU和副CPU、相连的主FPGA和副FPGA，所述主FPGA和副FPGA均与保护装置的物理层相连，所述主CPU和副CPU均与被保护设备的状态监视数据输出端相连：
    其中，主CPU将处理结果发送给主FPGA，副CPU将处理结果发送给副FPGA，副FPGA接收到副CPU发送的信息后向主FPGA同步当前的信息；
    当主FPGA接收到跳闸信息时，则主FPGA对从主CPU获得的当前的跳闸信息与从副FPGA获得的当前的跳闸信息进行一致性比较，若一致，则主FPGA将从主CPU接收的信息发送至保护装置，否则，丢弃从主CPU接收的信息。
  2. 根据权利要求1所述的一种保证智能变电站保护跳闸可靠性的装置，其特征在于，主FPGA和副FPGA之间进行单向通信，副FPGA采用成帧方式、周期的向主FPGA发送消息。
  3. 根据权利要求2所述的一种保证智能变电站保护跳闸可靠性的装置，其特征在于，主FPGA和保护装置的物理层芯片之间进行双向通信，副FPGA和保护装置的物理层芯片之间进行单向通信，副FPGA接收保护装置的物理层发送的消息。
  4. 根据权利要求1所述的一种保证智能变电站保护跳闸可靠性的装置，其特征在于，主CPU在向主FPGA发送报文时，同时发送报文对应的CRC，主FPGA在发送过程以太网报文时将此CRC直接附在帧尾发出，不再自行计算CRC且主FPGA不改变任何报文内容。
  5. 根据权利要求4所述的一种保证智能变电站保护跳闸可靠性的装置，其特征 在于，主FPGA接收主CPU发送的报文后，解析报文格式判断是否包含跳闸信息，若不包含跳闸信息则无需一致性校验直接发送出去。
  6. 一种保证智能变电站保护跳闸可靠性的方法，其特征在于，具体包括如下步骤：
    步骤1、主CPU和副CPU分别采集被保护设备的状态监视数据,根据采样值进行保护逻辑判断，并将保护动作的结果发送给各自对应的FPGA，其中，主CPU将跳闸报文传送至主FPGA，同时计算采集数据对应的CRC并传送至主FPGA；副CPU将跳闸状态传送至副FPGA；
    步骤2、主FPGA和副FPGA对接收到的数据进行预处理，其中，副FPGA向主FPGA同步当前的信息；主FPGA对从主CPU接收的信息进行解析：若信息不包含跳闸信息，则主FPGA直接将CRC附在从主CPU接收的信息尾部发送至保护装置的物理层；若信息包含跳闸信息，则主FPGA对从主CPU获得的当前的跳闸信息与从副FPGA获得的当前的跳闸信息进行一致性比较，若一致，则主FPGA直接将CRC附在从主CPU接收的信息尾部发送至保护装置的物理层，否则，丢弃从主CPU接收的信息。
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