WO2017101202A1 - 一种低电源电压二次变频射频接收前端 - Google Patents

一种低电源电压二次变频射频接收前端 Download PDF

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WO2017101202A1
WO2017101202A1 PCT/CN2016/072750 CN2016072750W WO2017101202A1 WO 2017101202 A1 WO2017101202 A1 WO 2017101202A1 CN 2016072750 W CN2016072750 W CN 2016072750W WO 2017101202 A1 WO2017101202 A1 WO 2017101202A1
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nmos transistor
drain
resistor
gate
source
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French (fr)
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陈超
吴建辉
李红
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Southeast University
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Southeast University
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1441—Balanced arrangements with transistors using field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1458—Double balanced arrangements, i.e. where both input signals are differential
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1466—Passive mixer arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/16—Multiple-frequency-changing
    • H03D7/165—Multiple-frequency-changing at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/0084—Lowering the supply voltage and saving power
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45116—Feedback coupled to the input of the differential amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45288—Differential amplifier with circuit arrangements to enhance the transconductance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45481—Indexing scheme relating to differential amplifiers the CSC comprising only a direct connection to the supply voltage, no other components being present

Definitions

  • the invention relates to a secondary frequency conversion RF receiving front-end circuit for low power supply voltage, and the power supply voltage can be as low as 0.6V.
  • the rapid spread of handheld wireless communication terminal devices places higher demands on the power consumption of the RF receiving module.
  • the two-conversion receiver structure uses two frequency conversion technologies, and has achieved good performance in image suppression and power consumption, and is widely used in low-power RF receiving circuits.
  • the traditional secondary frequency conversion RF front end adopts a combination of active and passive mixing, and performs band pass filtering after the first frequency conversion, and then moves the received signal to the baseband by the second orthogonal frequency conversion.
  • the present invention provides a low power supply voltage secondary frequency conversion radio frequency receiving front end, which utilizes an impedance shifting effect of passive frequency conversion to construct a band pass filtering effect after the first stage mixing. Therefore, the two-stage passive frequency conversion is directly cascaded, and the high conversion gain is ensured, and the image signal is fully suppressed, and the circuit structure is simple and the power consumption is low.
  • a low power supply voltage secondary frequency conversion RF receiving front end comprising a low voltage RF transconductance amplifier, a secondary variable frequency mixing switch pair and a transimpedance amplifier; a secondary frequency conversion mixing switch will be the first frequency conversion unit and the second frequency conversion unit Direct cascading, the second frequency conversion unit moves the low input impedance of the transimpedance amplifier to the intermediate frequency to construct a bandpass filtering function for the RF current; the RF current after the two conversions is converted to the output IF voltage by the transimpedance amplifier.
  • the front end of the invention eliminates the intermediate level buffering and filtering circuit, further reducing power consumption and layout area; the invention achieves sufficient suppression of the image signal while ensuring high conversion gain.
  • the low voltage RF transconductance amplifier includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first PMOS transistor MP1, a second PMOS transistor MP2, a first capacitor C1, and a second capacitor.
  • the gate and the drain of the first NMOS transistor MN1 are shorted, and the source is grounded;
  • the source of the second NMOS transistor MN2 is grounded, the gate is connected to the anode of the fifth resistor R5, the drain is connected to the drain of the first PMOS transistor MP1, and the cathode of the fifth resistor R5 is connected to the drain of the first NMOS transistor MN1;
  • the source of the third NMOS transistor MN3 is grounded, the gate is connected to the anode of the sixth resistor R6, the drain is connected to the drain of the second PMOS transistor MP2, and the cathode of the sixth resistor R6 is connected to the drain of the first NMOS transistor MN1;
  • the source of the first PMOS transistor MP1 is connected to the power source VDD, and the gate is connected to the anode of the first resistor R1;
  • the source of the second PMOS transistor MP2 is connected to the power source VDD, and the gate is connected to the anode of the second resistor R2;
  • the anode of the first capacitor C1 is connected to the drain of the first NMOS transistor MN1, and the cathode is grounded;
  • the anode of the second capacitor C2 is connected to the input voltage positive electrode INP, and the cathode is connected to the gate of the third NMOS transistor MN3;
  • the anode of the third capacitor C3 is connected to the input voltage negative anode INN, and the cathode is connected to the gate of the second NMOS transistor MN2;
  • the anode of the fourth capacitor C4 is connected to the gate of the second NMOS transistor MN2, and the cathode is connected to the gate of the first NMOS transistor MN1;
  • the anode of the fifth capacitor C5 is connected to the gate of the third NMOS transistor MN3, and the cathode is connected to the gate of the second NMOS transistor MN2;
  • the positive pole of the first reference current source I1 is connected to the power supply VDD, and the negative pole is connected to the drain of the first NMOS transistor MN1;
  • the anode of the second reference current source I2 is connected to the anode of the first resistor R1, the cathode of the second resistor R2, the cathode of the third resistor R3, and the cathode of the fourth resistor R4, and the cathode is grounded; the anode of the third resistor R3 is connected to the first PMOS.
  • the pair of secondary frequency conversion mixer switches includes a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a seventh NMOS transistor.
  • the anode of the sixth capacitor C6 is connected to the drain of the first PMOS transistor MP1, and the cathode is connected to the source of the sixth NMOS transistor MN6 and the source of the seventh NMOS transistor MN7;
  • the anode of the seventh capacitor C7 is connected to the drain of the second PMOS transistor MP2, and the cathode is connected to the source of the fourth NMOS transistor MN4 and the source of the fifth NMOS transistor MN5;
  • the anode of the eighth capacitor C8 is connected to the drain of the fifth NMOS transistor MN5 and the drain of the sixth NMOS transistor MN6, and the cathode is connected to the drain of the fourth NMOS transistor MN4 and the drain of the seventh NMOS transistor MN7;
  • the gate of the fourth NMOS transistor MN4 and the gate of the sixth NMOS transistor MN6 are connected to the first local oscillation signal positive electrode LO1+, the gate of the fifth NMOS transistor MN5 and the gate of the seventh NMOS transistor MN7 are connected to the first local oscillation signal negative electrode.
  • the anode of the eighth capacitor C8 is connected to the source of the eighth NMOS transistor MN8 and the source of the ninth NMOS transistor MN9, and the cathode is connected to the source of the fourteenth NMOS transistor MN14 and the source of the fifteenth NMOS transistor MN15; the eighth NMOS
  • the drain of the tube MN8 is shorted to the drain of the fourteenth NMOS transistor MN14, the drain of the ninth NMOS transistor MN9 is shorted to the drain of the fifteenth NMOS transistor MN15, and the gate of the eighth NMOS transistor MN8 and the tenth
  • the gate of the fifth NMOS transistor MN15 is connected to the second Q-channel local oscillator signal positive LO2Q+, the gate of the ninth NMOS transistor MN9 and the gate of the fourteenth NMOS transistor MN14 are connected to the second Q-channel local oscillator signal negative LO2Q-;
  • the anode of the eighth capacitor C8 is connected to the source of the tenth NMOS transistor MN10 and the source of the eleventh NMOS transistor MN11, and the cathode is connected to the source of the twelfth NMOS transistor MN12 and the source of the thirteenth NMOS transistor MN13;
  • the drain of the NMOS transistor MN10 is shorted to the drain of the twelfth NMOS transistor MN12, the drain of the eleventh NMOS transistor MN11 is shorted to the drain of the thirteenth NMOS transistor MN13, and the gate of the tenth NMOS transistor MN10 is
  • the gate of the thirteenth NMOS transistor MN13 is connected to the second I-channel local oscillator signal positive LO2I+, the gate of the eleventh NMOS transistor MN11 and the gate of the twelfth NMOS transistor MN12 are connected to the second I-channel local oscillator signal negative LO2I- .
  • the transimpedance amplifier includes a first transconductance amplifier A1, a second transconductance amplifier A2, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10;
  • the positive input terminal of the first transconductance amplifier A1 is connected to the drain of the tenth NMOS transistor MN10, the negative input terminal is connected to the drain of the thirteenth NMOS transistor MN13, and the positive terminal of the seventh resistor R7 is connected to the positive input of the first transconductance amplifier A1.
  • the negative terminal is connected to the negative output terminal of the first transconductance amplifier A1;
  • the anode of the eighth resistor R8 is connected to the negative input terminal of the first transconductance amplifier A1, and the negative terminal is connected to the positive output terminal of the first transconductance amplifier A1;
  • the positive output terminal of the amplifier A1 is the I output positive OUTIP, and the negative output is the I output negative OUTIN;
  • the positive input terminal of the second transconductance amplifier A2 is connected to the drain of the eighth NMOS transistor MN8, the negative input terminal is connected to the drain of the fifteenth NMOS transistor MN15; the positive terminal of the ninth resistor R9 is connected to the positive input of the second transconductance amplifier A2.
  • the negative terminal is connected to the negative output terminal of the second transconductance amplifier A2; the positive terminal of the tenth resistor R10 is connected to the second cross
  • the negative input terminal of the A2 is connected to the positive output terminal of the second transconductance amplifier A2; the positive output terminal of the second transconductance amplifier A2 is the Q output positive output OUTQP, and the negative output terminal is the Q output negative output OUTQN.
  • the low power supply voltage secondary frequency conversion RF receiving front end provided by the invention can operate at a lower power supply voltage based on the passive frequency conversion mode; the front end first frequency conversion and the second frequency conversion unit are directly cascaded,
  • the quadrature orthogonal passive frequency conversion moves the low input impedance of the transimpedance amplifier to the intermediate frequency to construct a bandpass filtering function for the RF current; compared to the conventional active+active or active+passive secondary In the frequency conversion mode, the invention eliminates the intermediate stage active circuit and the filter circuit, saves power consumption and layout area, and achieves sufficient suppression of the image signal while ensuring high conversion gain.
  • FIG. 1 is a structural diagram of a low power supply voltage secondary frequency conversion radio frequency receiving front end circuit according to the present invention
  • Figure 3 is a graph showing the conversion gain curve at the input image frequency of the present invention.
  • Figure 1 shows a low-supply voltage secondary-frequency RF receiving front-end, including a low-voltage RF transconductance amplifier, a secondary-conversion mixing switch pair, and a transimpedance amplifier.
  • the second-conversion mixing switch will be the first inverter unit.
  • the second frequency conversion unit moves the low input impedance of the transimpedance amplifier to the intermediate frequency to construct a band pass filtering function for the RF current; the RF current through the transimpedance amplifier after the two conversions Convert to output IF voltage.
  • the low voltage RF transconductance amplifier in this case adopts a CMOS structure, and the NMOS transistor and the PMOS transistor simultaneously provide a transconductance, wherein the PMOS transconductance is a self-biased structure.
  • this case adds a fixed current source to the gate of the PMOS transistor, which makes the gate bias voltage lower than the drain voltage, thus releasing more voltage margin. degree.
  • the secondary variable frequency mixing switch is composed of two stages of double balanced local oscillator switches, which is a passive frequency conversion mode.
  • the first stage is a single-path structure, and the second stage is an orthogonal mixing structure.
  • the second stage switch moves the input impedance of the transimpedance amplifier to near the intermediate frequency, and the bandpass frequency response at the intermediate frequency is constructed at the output of the first stage local oscillator switch.
  • the bandpass frequency response is directly shifted by the low frequency response, so a higher Q value is obtained at the output of the first local oscillator switch.
  • an image rejection ratio of 50 dB or more can be achieved.
  • the first stage switch then moves the low impedance at the intermediate frequency to the vicinity of the input RF frequency, constructs a low impedance node at the output of the transconductance stage, and sinks the RF current into the first stage local oscillator stage.
  • the transimpedance amplifier consists of a shunt resistor between the input and output of the fully differential transconductance amplifier and will be downconverted. The post current is converted to an output voltage.
  • the low voltage master-slave structure transconductance amplifier structure employed in the transconductance amplifier structure is a prior patent of the inventor.
  • Figure 1 shows the petroleum structure of the circuit structure of the present case.
  • Figure 2 shows the low-supply voltage secondary frequency conversion RF receiving front-end conversion gain curve for this case.
  • freq represents the input frequency
  • CG represents the conversion gain
  • MO represents the measured value; as can be seen from the figure: at 0.6V low
  • the front-end circuit of this case can achieve a conversion gain of 28dB for an input signal near 1.575GHz.
  • Figure 3 shows the conversion gain curve of the low-supply voltage secondary-frequency RF receiving front-end circuit at the input image frequency of the present case.
  • freq represents the input frequency
  • CG represents the conversion gain
  • MO represents the measured value
  • Output The RF front-end of this case has a conversion gain of -25dB or less for an image signal located near 940MHz, and its equivalent image rejection ratio is 53dB or more.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Amplifiers (AREA)

Abstract

本发明公开了一种低电源电压二次变频射频接收前端，基于无源变频方式，可以工作在更低的电源电压下；该前端第一次变频和第二次变频单元直接级联，第二次正交无源变频将跨阻放大器的低输入阻抗搬移到中间频率，构造出对射频电流的带通滤波功能；两次变频后的射频电流经跨阻放大器转换为输出中频电压。相比于传统的有源+有源或者有源+无源的二次变频方式，本发明省去了中间级有源电路和滤波电路，节约了功耗和版图面积，在保证了高转换增益的同时实现了对镜像信号的充分抑制。

Description

一种低电源电压二次变频射频接收前端 技术领域
本发明涉及一种用于低电源电压场合的二次变频射频接收前端电路，其电源电压可低至0.6V。
背景技术
手持无线通信终端设备的迅速普及对射频接收模块的功耗提出了更高的要求。二次变频接收机结构使用了两次变频技术，在镜像抑制和功耗方面均取得了较好的性能，在低功耗射频接收电路中广泛使用。传统二次变频射频前端多采用有源和无源混频相结合的方式，在第一次变频后进行带通滤波，再由第二次正交变频将接收信号搬移至基带。
近年来，随着工艺尺寸的不断降低以及对低功耗的不断追求。设计人员开始尝试将在近阈值电压条件下射频接收电路的设计方法。对于传统的二次变频射频接收前端而言，当电源电压下降到0.6V以下时，其中的有源混频电路很难获得足够的电压裕度。
发明内容
发明目的：为了克服现有技术中存在的不足，本发明提供一种低电源电压二次变频射频接收前端，利用无源变频的阻抗搬移效果，在第一级混频后构造带通滤波效果，从而将两级无源变频直接级联，在保证了高转换增益的同时实现了对镜像信号的充分抑制，具有电路结构简单和功耗低的特点。
技术方案：为实现上述目的，本发明采用的技术方案为：
一种低电源电压二次变频射频接收前端，包括低电压射频跨导放大器、二次变频混频开关对和跨阻放大器；二次变频混频开关将第一次变频单元和第二次变频单元直接级联，第二次变频单元将跨阻放大器的低输入阻抗搬移到中间频率，构造出对射频电流的带通滤波功能；两次变频后的射频电流经跨阻放大器转换为输出中频电压。本发明的前端取消了中间级缓冲及滤波电路，进一步降低了功耗和版图面积；本发明在保证了高转换增益的同时实现了对镜像信号的充分抑制。
具体的，所述低电压射频跨导放大器包括第一NMOS管MN1、第二NMOS管MN2、第三NMOS管MN3、第一PMOS管MP1、第二PMOS管MP2、第一电容C1、第二电容C2、第三电容C3、第四电容C4、第五电容C5、第一电阻R1、第二电阻R2、第三电阻R3、第四电阻R4、第五电阻R5、第六电阻R6、第一参考电流源I1和第二参考电流源I2；
第一NMOS管MN1的栅极和漏极短接，源极接地；
第二NMOS管MN2的源极接地，栅极接第五电阻R5的正极，漏极接第一PMOS管MP1的漏极；第五电阻R5的负极接第一NMOS管MN1的漏极；
第三NMOS管MN3的源极接地，栅极接第六电阻R6的正极，漏极接第二PMOS管MP2的漏极；第六电阻R6的负极接第一NMOS管MN1的漏极；
第一PMOS管MP1的源极接电源VDD，栅极接第一电阻R1的正极；
第二PMOS管MP2的源极接电源VDD，栅极接第二电阻R2的正极；
第一电容C1的正极接第一NMOS管MN1的漏极，负极接地；
第二电容C2的正极接输入电压正极INP，负极接第三NMOS管MN3的栅极；
第三电容C3的正极接输入电压负极INN，负极接第二NMOS管MN2的栅极；
第四电容C4的正极接第二NMOS管MN2的栅极，负极接第一NMOS管MN1的栅极；
第五电容C5的正极接第三NMOS管MN3的栅极，负极接第二NMOS管MN2的栅极；
第一参考电流源I1的正极接电源VDD，负极接第一NMOS管MN1的漏极；
第二参考电流源I2的正极接第一电阻R1的负极、第二电阻R2的负极、第三电阻R3的负极和第四电阻R4的负极，负极接地；第三电阻R3的正极接第一PMOS管MP1的漏极，第四电阻R4的第二PMOS管MP2的漏极。
具体的，所述二次变频混频开关对包括第六电容C6、第七电容C7、第八电容C8、第四NMOS管MN4、第五NMOS管MN5、第六NMOS管MN6、第七NMOS管MN7、第八NMOS管MN8、第九NMOS管MN9、第十NMOS管MN10、第十一NMOS管MN11、第十二NMOS管MN12、第十三NMOS管MN13、第十四NMOS管MN14和第十五NMOS管MN15；
第六电容C6的正极接第一PMOS管MP1的漏极，负极接第六NMOS管MN6的源极和第七NMOS管MN7的源极；
第七电容C7的正极接第二PMOS管MP2的漏极，负极接第四NMOS管MN4的源极和第五NMOS管MN5的源极；
第八电容C8的正极接第五NMOS管MN5的漏极和第六NMOS管MN6的漏极，负极接第四NMOS管MN4的漏极和第七NMOS管MN7的漏极；
第四NMOS管MN4的栅极和第六NMOS管MN6的栅极接第一本振信号正极LO1+，第五NMOS管MN5的栅极和第七NMOS管MN7的栅极接第一本振信号负极LO1-；
第八电容C8的正极接第八NMOS管MN8的源极和第九NMOS管MN9的源极，负极接第十四NMOS管MN14的源极和第十五NMOS管MN15的源极；第八NMOS管MN8的漏极和第十四NMOS管MN14的漏极短接，第九NMOS管MN9的漏极和第十五NMOS管MN15的漏极短接，第八NMOS管MN8的栅极和第十五NMOS管MN15的栅极接第二Q路本振信号正极LO2Q+，第九NMOS管MN9的栅极和第十四NMOS管MN14的栅极接第二Q路本振信号负极LO2Q-；
第八电容C8的正极接第十NMOS管MN10的源极和第十一NMOS管MN11的源极，负极接第十二NMOS管MN12的源极和第十三NMOS管MN13的源极；第十NMOS管MN10的漏极和第十二NMOS管MN12的漏极短接，第十一NMOS管MN11的漏极和第十三NMOS管MN13的漏极短接，第十NMOS管MN10的栅极和第十三NMOS管MN13的栅极接第二I路本振信号正极LO2I+，第十一NMOS管MN11的栅极和第十二NMOS管MN12的栅极接第二I路本振信号负极LO2I-。
具体的，所述跨阻放大器包括第一跨导放大器A1、第二跨导放大器A2、第七电阻R7、第八电阻R8、第九电阻R9和第十电阻R10；
第一跨导放大器A1的正输入端接第十NMOS管MN10的漏极，负输入端接第十三NMOS管MN13的漏极；第七电阻R7的正极接第一跨导放大器A1的正输入端，负极接第一跨导放大器A1的负输出端；第八电阻R8的正极接第一跨导放大器A1的负输入端，负极接第一跨导放大器A1的正输出端；第一跨导放大器A1的正输出端为I路输出正极OUTIP，负输出端为I路输出负极OUTIN；
第二跨导放大器A2的正输入端接第八NMOS管MN8的漏极，负输入端接第十五NMOS管MN15的漏极；第九电阻R9的正极接第二跨导放大器A2的正输入端，负极接第二跨导放大器A2的负输出端；第十电阻R10的正极接第二跨 导放大器A2的负输入端，负极接第二跨导放大器A2的正输出端；第二跨导放大器A2的正输出端为Q路输出正极OUTQP，负输出端为Q路输出负极OUTQN。
有益效果：本发明提供的低电源电压二次变频射频接收前端，基于无源变频方式，可以工作在更低的电源电压下；该前端第一次变频和第二次变频单元直接级联，第二次正交无源变频将跨阻放大器的低输入阻抗搬移到中间频率，构造出对射频电流的带通滤波功能；相比于传统的有源+有源或者有源+无源的二次变频方式，本发明省去了中间级有源电路和滤波电路，节约了功耗和版图面积，在保证了高转换增益的同时实现了对镜像信号的充分抑制。
附图说明
图1为本发明的低电源电压二次变频射频接收前端电路结构图；
图2为本发明的低电源电压二次变频射频接收前端转换增益曲线；
图3为本发明在输入镜像频率处的转换增益曲线。
具体实施方式
下面结合附图对本发明作更进一步的说明。
如图1所示为一种低电源电压二次变频射频接收前端，包括低电压射频跨导放大器、二次变频混频开关对和跨阻放大器，二次变频混频开关将第一次变频单元和第二次变频单元直接级联，第二次变频单元将跨阻放大器的低输入阻抗搬移到中间频率，构造出对射频电流的带通滤波功能；两次变频后的射频电流经跨阻放大器转换为输出中频电压。
本案中的低电压射频跨导放大器采用CMOS结构，NMOS管和PMOS管同时提供跨导，其中PMOS跨导管为自偏置结构。为了节约电压裕度以适应低电源电压应用场合，本案在PMOS管的栅极增加了一个固定电流源，该电流源使得栅极偏置电压低于漏极电压，从而释放出更多的电压裕度。
二次变频混频开关对由两级双平衡本振开关级联组成，为无源变频方式。第一级为单路结构，第二级为正交混频结构。第二级开关将跨阻放大器的输入阻抗搬移到中间频率附近，在第一级本振开关输出端构造出中间频率处的带通频率响应。该带通频率响应由低频频率响应直接进行频率搬移得出，因此在第一本振开关输出端获得了较高的Q值。最终可实现50dB以上的镜像抑制比。第一级开关再将中间频率处的低阻抗搬移到输入射频频率附近，在跨导级输出端构造低阻抗节点，将射频电流吸收进入第一级本振级。
跨阻放大器由全差分跨导放大器输入和输出端之间跨接电阻构成，将下变频 后的电流转化成输出电压。该跨导放大器结构采用的低电压主从结构跨导放大器结构系本发明人前期专利。
如图1所示为本案的电路结构石油图。图2所示为本案的低电源电压二次变频射频接收前端转换增益曲线，图中，freq表示输入频率，CG表示转换增益，MO表示测量值；从图中可以看出：在0.6V的低电源电压下，本案的前端电路对位于1.575GHz附近的输入信号转换增益可达28dB。图3所示为本案的低电源电压二次变频射频接收前端电路在输入镜像频率处的转换增益曲线，图中，freq表示输入频率，CG表示转换增益，MO表示测量值；从图中可以看出：本案的射频前端对位于940MHz附近的镜像信号的转换增益为-25dB以下，其等效镜像抑制比为53dB以上。
以上所述仅是本发明的优选实施方式，应当指出：对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (4)

  1. 一种低电源电压二次变频射频接收前端，包括低电压射频跨导放大器、二次变频混频开关对和跨阻放大器，其特征在于：二次变频混频开关将第一次变频单元和第二次变频单元直接级联，第二次变频单元将跨阻放大器的低输入阻抗搬移到中间频率，构造出对射频电流的带通滤波功能；两次变频后的射频电流经跨阻放大器转换为输出中频电压。
  2. 根据权力要求1所述的低电源电压二次变频射频接收前端，其特征在于：所述低电压射频跨导放大器包括第一NMOS管MN1、第二NMOS管MN2、第三NMOS管MN3、第一PMOS管MP1、第二PMOS管MP2、第一电容C1、第二电容C2、第三电容C3、第四电容C4、第五电容C5、第一电阻R1、第二电阻R2、第三电阻R3、第四电阻R4、第五电阻R5、第六电阻R6、第一参考电流源I1和第二参考电流源I2；
    第一NMOS管MN1的栅极和漏极短接，源极接地；
    第二NMOS管MN2的源极接地，栅极接第五电阻R5的正极，漏极接第一PMOS管MP1的漏极；第五电阻R5的负极接第一NMOS管MN1的漏极；
    第三NMOS管MN3的源极接地，栅极接第六电阻R6的正极，漏极接第二PMOS管MP2的漏极；第六电阻R6的负极接第一NMOS管MN1的漏极；
    第一PMOS管MP1的源极接电源VDD，栅极接第一电阻R1的正极；
    第二PMOS管MP2的源极接电源VDD，栅极接第二电阻R2的正极；
    第一电容C1的正极接第一NMOS管MN1的漏极，负极接地；
    第二电容C2的正极接输入电压正极INP，负极接第三NMOS管MN3的栅极；
    第三电容C3的正极接输入电压负极INN，负极接第二NMOS管MN2的栅极；
    第四电容C4的正极接第二NMOS管MN2的栅极，负极接第一NMOS管MN1的栅极；
    第五电容C5的正极接第三NMOS管MN3的栅极，负极接第二NMOS管MN2的栅极；
    第一参考电流源I1的正极接电源VDD，负极接第一NMOS管MN1的漏极；
    第二参考电流源I2的正极接第一电阻R1的负极、第二电阻R2的负极、第 三电阻R3的负极和第四电阻R4的负极，负极接地；第三电阻R3的正极接第一PMOS管MP1的漏极，第四电阻R4的第二PMOS管MP2的漏极。
  3. 根据权利要求2所述的低电源电压二次变频射频接收前端，其特征在于：所述二次变频混频开关对包括第六电容C6、第七电容C7、第八电容C8、第四NMOS管MN4、第五NMOS管MN5、第六NMOS管MN6、第七NMOS管MN7、第八NMOS管MN8、第九NMOS管MN9、第十NMOS管MN10、第十一NMOS管MN11、第十二NMOS管MN12、第十三NMOS管MN13、第十四NMOS管MN14和第十五NMOS管MN15；
    第六电容C6的正极接第一PMOS管MP1的漏极，负极接第六NMOS管MN6的源极和第七NMOS管MN7的源极；
    第七电容C7的正极接第二PMOS管MP2的漏极，负极接第四NMOS管MN4的源极和第五NMOS管MN5的源极；
    第八电容C8的正极接第五NMOS管MN5的漏极和第六NMOS管MN6的漏极，负极接第四NMOS管MN4的漏极和第七NMOS管MN7的漏极；
    第四NMOS管MN4的栅极和第六NMOS管MN6的栅极接第一本振信号正极LO1+，第五NMOS管MN5的栅极和第七NMOS管MN7的栅极接第一本振信号负极LO1-；
    第八电容C8的正极接第八NMOS管MN8的源极和第九NMOS管MN9的源极，负极接第十四NMOS管MN14的源极和第十五NMOS管MN15的源极；第八NMOS管MN8的漏极和第十四NMOS管MN14的漏极短接，第九NMOS管MN9的漏极和第十五NMOS管MN15的漏极短接，第八NMOS管MN8的栅极和第十五NMOS管MN15的栅极接第二Q路本振信号正极LO2Q+，第九NMOS管MN9的栅极和第十四NMOS管MN14的栅极接第二Q路本振信号负极LO2Q-；
    第八电容C8的正极接第十NMOS管MN10的源极和第十一NMOS管MN11的源极，负极接第十二NMOS管MN12的源极和第十三NMOS管MN13的源极；第十NMOS管MN10的漏极和第十二NMOS管MN12的漏极短接，第十一NMOS管MN11的漏极和第十三NMOS管MN13的漏极短接，第十NMOS管MN10的栅极和第十三NMOS管MN13的栅极接第二I路本振信号正极LO2I+，第十 一NMOS管MN11的栅极和第十二NMOS管MN12的栅极接第二I路本振信号负极LO2I-。
  4. 根据权利要求3所述的低电源电压二次变频射频接收前端，其特征在于：所述跨阻放大器包括第一跨导放大器A1、第二跨导放大器A2、第七电阻R7、第八电阻R8、第九电阻R9和第十电阻R10；
    第一跨导放大器A1的正输入端接第十NMOS管MN10的漏极，负输入端接第十三NMOS管MN13的漏极；第七电阻R7的正极接第一跨导放大器A1的正输入端，负极接第一跨导放大器A1的负输出端；第八电阻R8的正极接第一跨导放大器A1的负输入端，负极接第一跨导放大器A1的正输出端；第一跨导放大器A1的正输出端为I路输出正极OUTIP，负输出端为I路输出负极OUTIN；
    第二跨导放大器A2的正输入端接第八NMOS管MN8的漏极，负输入端接第十五NMOS管MN15的漏极；第九电阻R9的正极接第二跨导放大器A2的正输入端，负极接第二跨导放大器A2的负输出端；第十电阻R10的正极接第二跨导放大器A2的负输入端，负极接第二跨导放大器A2的正输出端；第二跨导放大器A2的正输出端为Q路输出正极OUTQP，负输出端为Q路输出负极OUTQN。
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