WO2017096633A1

WO2017096633A1 - Uart data processing control method and control device

Info

Publication number: WO2017096633A1
Application number: PCT/CN2015/097488
Authority: WO
Inventors: 刘复鑫; 邹伟
Original assignee: 美的集团股份有限公司
Priority date: 2015-12-09
Filing date: 2015-12-15
Publication date: 2017-06-15
Also published as: CN105577568A

Abstract

Disclosed are a UART data processing control method and control device. The method comprises the following steps: acquiring data frames to be sent and storing the data frames to be sent into a ring buffer; reading a packet header of an i th frame of data to be sent and acquiring data length information in the packet header; transferring the i th frame of data to be sent to a transceiver buffer according to the data length information; and sending, by a sending queue, an address of the transceiver buffer and the data length information to a logic controller so as to send the i th frame of data to be sent. The control method in the embodiment of the present invention can ensure that data is not tampered, and data transmission integrity is better protected without considering the problem of memory allocation and release and without worrying about overflow and memory fragmentation, thereby improving data processing performance of a UART. In addition, the method is simple and convenient.

Description

UART data processing control method and control device

Technical field

The present invention relates to the field of household appliances, and in particular, to a data processing control method and a control device for a UART (Universal Asynchronous Receiver/Transmitter).

Background technique

In the related art, Uart's data processing method is: Uart once read the data directly to the data processing, wherein, if the method is sent by the queue, after the memory of the dynamic malloc, the distribution is received at the place where the queue is received. Memory is released.

However, firstly, if multiple frames of data are received at a time, the processing of the second frame of data may be missed, or the two frames of data may be treated as one frame to make false control; secondly, the memory of malloc and free is too frequent, thereby It is easy to cause memory fragmentation, and does not follow the principle of who distributes who releases, there is a risk of memory leaks, and needs to be improved.

Summary of the invention

The present invention aims to solve at least one of the technical problems in the related art to some extent.

Therefore, an object of the present invention is to provide a data processing control method for a UART, which can improve the data processing performance of the UART, and is simple and convenient.

A second object of the present invention is to provide a data processing control device for a UART.

A third object of the invention is to propose an apparatus.

A fourth object of the present invention is to provide a computer storage medium.

In order to achieve the above object, a data processing control method for a UART is provided according to the first aspect of the present invention, including the steps of: acquiring a data frame to be transmitted, and storing the to-be-sent data frame to a circular buffer; Decoding a header of an ith frame to be transmitted in the circular buffer, and acquiring data length information in the packet header, where i is a positive integer; and the ith frame to be transmitted data is from the loop according to the data length information Transferring to the transceiver buffer in the cache; and sending a queue to send the address of the transceiver buffer and the data length information to the logic controller, so that the logic controller obtains according to the address of the transceiver buffer and the data length information The ith frame is to be sent and sent

The data processing control method of the UART of the embodiment of the present invention, by storing the data frame to be sent to the circular buffer, transfers the data to be sent from the circular buffer to the sending and receiving buffer according to the data length information in the packet header, and the sending queue will send and receive the buffer. The address and data length information is sent to the logic controller to implement data transmission to ensure that the data is not Tampering, better guarantee the integrity of data transmission, and do not need to consider the problem of memory allocation release, do not worry about overflow and memory fragmentation, improve the data processing performance of UART, simple and convenient.

In order to achieve the above object, a data processing control apparatus for a UART according to an embodiment of the second aspect of the present invention includes: an obtaining module, configured to acquire a data frame to be transmitted, and store the to-be-sent data frame to a circular buffer; a reading module, configured to read a header of an ith frame to be sent in the circular buffer, and obtain data length information in the packet header, where i is a positive integer; and a transfer module is configured to use, according to the data length Transmitting, by the information, the ith frame to-be-sent data from the circular buffer to the transceiver buffer; and sending module, configured to send, by the sending queue, the address of the transceiver buffer and the data length information to the logic controller, so that The logic controller acquires and sends the ith frame to be transmitted according to the address of the transceiver buffer and the data length information.

The data processing control apparatus of the UART of the embodiment of the present invention stores the data frame to be transmitted into the circular buffer according to the data length information in the packet header, and transfers the data to be transmitted from the circular buffer to the transceiver buffer according to the data length information in the packet header, and the second transmission queue will send and receive the buffer. The address and data length information is sent to the logic controller to realize the data transmission, to ensure that the data is not tampered, to better ensure the integrity of the data transmission, and to avoid the problem of memory allocation release, without worrying about overflow and memory fragmentation, and improving The data processing performance of the UART is simple and convenient.

The additional aspects and advantages of the invention will be set forth in part in the description which follows.

To achieve the above object, an apparatus of a third aspect of the present invention includes: one or more processors; a memory; one or more programs, the one or more programs being stored in the memory when When one or more processors are executed, the data processing control method of the UART of the first aspect of the present invention is executed.

The device in the embodiment of the present invention stores the data frame to be sent from the circular buffer to the sending and receiving buffer according to the data length information in the packet header by storing the data frame to be sent to the circular buffer, and the sending queue buffers the address and data length of the sending and receiving buffer. The information is sent to the logic controller to realize the data transmission, to ensure that the data is not tampered, to better ensure the integrity of the data transmission, and to avoid the problem of memory allocation release, without worrying about overflow and memory fragmentation, and improving the data processing of the UART. Performance, simple and convenient.

To achieve the above object, a fourth aspect of the present invention provides a nonvolatile computer storage medium storing one or more programs when the one or more programs are executed by a device. The apparatus is caused to perform the data processing control method of the UART of the first aspect of the present invention.

The computer storage medium of the embodiment of the present invention stores the data frame to be sent to the circular buffer according to the data length information in the packet header, and then transfers the data to be sent from the circular buffer to the transceiver buffer according to the data length information in the packet header, and the second sending queue will send and receive the cached address and The data length information is sent to the logic controller to realize the data transmission, to ensure that the data is not tampered, to better ensure the integrity of the data transmission, and to avoid the problem of memory allocation release, without worrying about overflow and memory fragmentation, and improving the UART. Data processing performance is simple and convenient.

DRAWINGS

The above and/or additional aspects and advantages of the present invention will become apparent and readily understood from

1 is a flowchart of a data processing control method of a UART according to an embodiment of the present invention;

2 is a schematic structural diagram of an embodiment of a data processing control apparatus of a UART according to the present invention;

FIG. 3 is a schematic structural diagram of a data processing control apparatus for a UART according to an embodiment of the present invention.

detailed description

The embodiments of the present invention are described in detail below, and the examples of the embodiments are illustrated in the drawings, wherein the same or similar reference numerals are used to refer to the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the drawings are intended to be illustrative of the invention and are not to be construed as limiting.

A data processing control method and a control apparatus for a UART according to an embodiment of the present invention will be described below with reference to the accompanying drawings.

1 is a flow chart of a data processing control method of a UART according to an embodiment of the present invention.

As shown in FIG. 1, the data processing control method of the UART may include the following steps:

S101. Acquire a data frame to be sent, and store the data frame to be sent to a circular buffer.

Wherein, in an embodiment of the invention, the circular buffer and the transceiving buffer may be set in a global area of the memory. Further, in one embodiment of the invention, the circular buffer (ring_buffer) and the transceiving buffer (rx_buffer) may exist in the form of static global variables.

In the embodiment of the present invention, the circular cache and the send/receive cache can be stored in the global area in the form of static global variables, so that the program can be automatically released after the program ends, regardless of the overflow caused by allocation, release, memory fragmentation and the like.

Specifically, in the embodiment of the present invention, two static global variables may be first established: a ring_buffer for storing data received from Uart each time; and an rx_buffer for storing a complete frame of data actually received.

Furthermore, the control method of the embodiment of the present invention does not store the data frame in the heap area of the memory, so that the memory allocation and release are very frequent, and the read data frame to be sent is first stored in the loop buffer. Therefore, there is no need to consider the issue of memory allocation release.

S102. Read a header of the data to be sent in the i-th frame in the circular buffer, and obtain data length information in the packet header, where i is a positive integer.

S103. Transfer the ith frame to-be-sent data from the circular buffer to the transceiver buffer according to the data length information.

For example, first put the data that Uart read to put in the ring_buffer, and then read the frame data information from the fixed position in the ring_buffer (including the frame header and frame length, which is equivalent to the header of the data to be sent and the data length information in it). Finally, the valid frame data is read from the ring_buffer according to the frame data length, and the valid frame data is placed in the rx_buffer. in.

Further, in an embodiment of the present invention, transferring the ith frame to-be-sent data from the circular buffer to the transceiving buffer according to the data length information specifically includes: reading the ith frame to be sent data from the circular buffer according to the data length information And clearing the transceiver buffer; storing the data to be sent in the i-th frame to the transceiver buffer.

Additionally, in one embodiment of the invention, the circular cache automatically releases the oldest occupied cache when the circular cache is full.

That is, in the embodiment of the present invention, the embodiment of the present invention can set the circular cache in the global area of the memory, and the size of the circular buffer can be fixed. Once the circular cache is full, the earliest is automatically released. Occupied memory, thus facilitating memory management.

S104. The sending queue sends the address and data length information of the sending and receiving buffer to the logic controller, so that the logic controller acquires the data to be transmitted of the ith frame according to the address and data length information of the sending and receiving buffer and sends the data.

It can be understood that after the valid frame data is placed in the rx_buffer, the address and data length of the rx_buffer can be packaged and sent to the logic center through the queue. For example, the logic controller can directly process the data according to the length and address for processing.

Specifically, in the embodiment of the present invention, there may be two queues and one mutex, wherein the mutex is used for locking control of the TX data to ensure that the data is not tampered and completely transmitted; one of the queues is a data receiving queue, and the receiving is performed. The outside world gives the serial port the data to be written to the Uart device, and the other queue is the send queue, which is the data that the device data read by the serial port will be sent to the outside world. In addition, the mentioned data, when the process is initialized, will be assigned two static global variables, which are used to store the data sent and received.

In addition, in the specific implementation process, that is, when the actual operation of the queue, just point the pointer to the corresponding address, do not need to consider the memory allocation and free details.

The data processing control method of the UART of the embodiment of the present invention, by storing the data frame to be sent to the circular buffer, transfers the data to be sent from the circular buffer to the sending and receiving buffer according to the data length information in the packet header, and the sending queue will send and receive the buffer. The address and data length information is sent to the logic controller to realize the data transmission, to ensure that the data is not tampered, to better ensure the integrity of the data transmission, and to avoid the problem of memory allocation release, without worrying about overflow and memory fragmentation, and improving The data processing performance of the UART is simple and convenient.

In order to implement the above embodiments, the present invention also provides a data processing control apparatus for a UART.

2 is a block diagram showing the structure of a data processing control apparatus for a UART according to an embodiment of the present invention.

As shown in FIG. 2, the data processing control apparatus 10 of the UART includes an acquisition module 100, a reading module 200, a transfer module 300, and a transmission module 400.

The obtaining module 100 is configured to acquire a data frame to be sent, and store the data frame to be sent to a circular buffer. The reading module 200 is configured to read a header of an ith frame to be sent in the circular buffer, and obtain a data length in the header Information, where i is a positive integer. The transfer module 300 is configured to transfer the ith frame to-be-sent data from the circular buffer to the transceiving buffer according to the data length information. The sending module 400 is configured to send, by the sending queue, the address and data length information of the sending and receiving buffer to the logic controller, so that the logic controller acquires the data to be transmitted of the ith frame according to the address and the data length information of the sending and receiving buffer and sends the data. The control device 10 of the embodiment of the invention can ensure that the data is not falsified, better guarantee the integrity of the data transmission, and does not need to consider the problem of memory allocation release, and does not worry about overflow and memory fragmentation, thereby improving the data processing performance of the UART.

Wherein, in an embodiment of the invention, the circular buffer and the transceiving buffer may be set in a global area of the memory.

Further, in one embodiment of the invention, the circular cache and the send and receive cache may exist in the form of static global variables.

In the embodiment of the present invention, the circular cache and the send/receive cache can store the global area in the form of static global variables, so that the program can be automatically released after the end of the program, regardless of the overflow caused by allocation, release, memory fragmentation and the like.

Further, in an embodiment of the present invention, as shown in FIG. 3, the sending module 400 further includes: a clearing unit 401 and a storage unit 402.

The clearing unit 401 is configured to read the ith frame to be sent data from the circular buffer according to the data length information, and clear the sending and receiving buffer. The storage unit 402 is configured to store the ith frame to be transmitted data to the transceiver buffer.

It should be noted that the foregoing explanation of the embodiment of the data processing control method for the UART is also applicable to the data processing control device of the UART of the embodiment, and details are not described herein again.

The data processing control apparatus of the UART of the embodiment of the present invention stores the data frame to be transmitted into the circular buffer according to the data length information in the packet header, and transfers the data to be transmitted from the circular buffer to the transceiver buffer according to the data length information in the packet header, and the second transmission queue will send and receive the buffer. The address and data length information is sent to the logic controller to implement data transmission, to ensure that the data is not tampered, to better ensure the integrity of the data transmission, and to avoid the problem of memory allocation release, without worrying about overflow And memory fragmentation, improve the data processing performance of the UART, simple and convenient.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " After, "Left", "Right", "Vertical", "Horizontal", "Top", "Bottom", "Inside", "Outside", "Clockwise", "Counterclockwise", "Axial", The orientation or positional relationship of the "radial", "circumferential" and the like is based on the orientation or positional relationship shown in the drawings, and is merely for convenience of description of the present invention and simplified description, and does not indicate or imply the indicated device or component. It must be constructed and operated in a particular orientation, and is not to be construed as limiting the invention.

Moreover, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining "first" or "second" may include at least one of the features, either explicitly or implicitly. In the description of the present invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless specifically defined otherwise.

In the present invention, the terms "installation", "connected", "connected", "fixed" and the like shall be understood broadly, and may be either a fixed connection or a detachable connection, unless explicitly stated and defined otherwise. , or integrated; can be mechanical or electrical connection; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of two elements or the interaction of two elements, unless otherwise specified Limited. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.

In the present invention, the first feature "on" or "under" the second feature may be a direct contact of the first and second features, or the first and second features may be indirectly through an intermediate medium, unless otherwise explicitly stated and defined. contact. Moreover, the first feature "above", "above" and "above" the second feature may be that the first feature is directly above or above the second feature, or merely that the first feature level is higher than the second feature. The first feature "below", "below" and "below" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely that the first feature level is less than the second feature.

In the description of the present specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like means a specific feature described in connection with the embodiment or example. A structure, material or feature is included in at least one embodiment or example of the invention. In the present specification, the schematic representation of the above terms is not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, various embodiments or examples described in the specification, as well as features of various embodiments or examples, may be combined and combined.

Although the embodiments of the present invention have been shown and described, it is understood that the above-described embodiments are illustrative and are not to be construed as limiting the scope of the invention. The embodiments are subject to variations, modifications, substitutions and variations.

Claims

A data processing control method for a universal asynchronous transceiver transmitter UART, comprising the steps of:

Obtaining a data frame to be sent, and storing the to-be-sent data frame to a circular buffer;

Reading a header of the to-be-sent data of the i-th frame in the circular buffer, and acquiring data length information in the packet header, where i is a positive integer;

Transmitting the ith frame to-be-sent data from the circular buffer to a transceiving buffer according to the data length information;

Sending, by the sending queue, the address of the sending and receiving buffer and the data length information to the logic controller, so that the logic controller acquires the data to be sent of the ith frame according to the address of the sending and receiving buffer and the data length information. And send.
The data processing control method of the UART according to claim 1, wherein the circular buffer and the transceiving buffer are set in a global area of the memory.
The data processing control method for a UART according to claim 1 or 2, wherein the circular buffer and the transceiving buffer exist as static global variables.
The data processing control method of the UART according to any one of claims 1 to 3, wherein the transferring the ith frame to-be-sent data from the circular buffer to the transceiver buffer according to the data length information specifically includes :

Reading the ith frame to be sent data from the circular buffer according to the data length information, and clearing the transceiver buffer;

And storing the ith frame to transmit data to the transceiver buffer.
The data processing control method for a UART according to any one of claims 1 to 4, characterized in that, when the circular buffer is full, the circular buffer automatically releases the oldest occupied cache.
A data processing control device for a UART, comprising:

An acquiring module, configured to acquire a data frame to be sent, and store the to-be-sent data frame to a circular buffer;

a reading module, configured to read a header of an ith frame to be sent in the circular buffer, and obtain data length information in the packet header, where i is a positive integer;

a transfer module, configured to transfer the ith frame to-be-sent data from the circular buffer to a transceiver buffer according to the data length information;

a sending module, configured to send, by the sending queue, the address of the sending and receiving buffer and the data length information to a logic controller, so that the logic controller acquires the first according to the address of the sending and receiving buffer and the data length information The i frame is to be sent and sent.
A data processing control apparatus for a universal asynchronous transceiver transmitter UART according to claim 6, wherein said cyclic buffer and said transceiver buffer are disposed in a global area of the memory.
A data processing control apparatus for a universal asynchronous transceiver transmitter UART according to claim 6 or 7, wherein said cyclic buffer and said transceiver buffer exist in the form of static global variables.
The data processing control device of the Universal Asynchronous Receiver Transmitter UART according to any of claims 6-8, wherein the transmitting module further comprises:

a clearing unit, configured to read the ith frame to be sent data from the circular buffer according to the data length information, and clear the transceiver buffer;

And a storage unit, configured to store the ith frame to-be-sent data to the transceiver buffer.
The data processing control apparatus for the universal asynchronous transceiver transmitter UART according to any of claims 6-9, characterized in that, when the circular buffer is full, the circular buffer automatically releases the oldest occupied cache.
An apparatus, comprising:

One or more processors;

Memory

One or more programs, the one or more programs being stored in the memory, and when executed by the one or more processors, performing data processing of the UART according to any one of claims 1-5 Control Method.
A non-volatile computer storage medium, characterized in that the computer storage medium stores one or more programs, when the one or more programs are executed by a device, causing the device to perform as claimed in claim 1. A data processing control method for the UART according to any one of the preceding claims.