CN105577568A - UART data processing control method and control device - Google Patents
UART data processing control method and control device Download PDFInfo
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- CN105577568A CN105577568A CN201510906589.6A CN201510906589A CN105577568A CN 105577568 A CN105577568 A CN 105577568A CN 201510906589 A CN201510906589 A CN 201510906589A CN 105577568 A CN105577568 A CN 105577568A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/62—Queue scheduling characterised by scheduling criteria
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/62—Queue scheduling characterised by scheduling criteria
- H04L47/622—Queue service order
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Abstract
The invention discloses a UART data processing control method and control device. The method comprises the following steps: obtaining data frames to be sent and storing the data frames to be sent to a ring buffer; reading a packet header of the ith frame of data to be sent and obtaining data length information of the packet header; transferring the ith frame of data to be sent to a transceiver buffer according to the data length information; and sending the address and the data length information in the transceiver buffer to a logic controller by a sending queue so as to send the ith frame of data to be sent. The control method can ensure the data is not tampered, so that data sending integrity can be better protected without considering the problem of memory allocation and release and without worrying about overflow and memory fragment, data processing performance of a UART is improved, and the method is simple and convenient.
Description
Technical field
The present invention relates to a kind of household electrical appliance technical field, particularly relate to data processing control method and the control device of a kind of UART (UniversalAsynchronousReceiver/Transmitter, universal asynchronous receiving-transmitting transmitter).
Background technology
In correlation technique, the data processing method of Uart is: Uart read to data be directly given to data processing, wherein, if sent by the mode of queue, then after the internal memory that dynamic malloc goes out, receiving the place of queue to the internal memory release distributed.
But, if first once receive multiframe data, then may miss the process to the second frame data, or two frame data are done as a frame control made mistake; Secondly malloc and free of internal memory is too frequent, thus easily causes memory fragmentation, and does not have whose principle of release whom distributes in accordance with, has the risk of RAM leakage, haves much room for improvement.
Summary of the invention
The present invention is intended to solve one of technical problem in correlation technique at least to a certain extent.
For this reason, one object of the present invention is the data processing control method proposing a kind of UART, and this control method can improve the data processing performance of UART, simple and convenient.
Another object of the present invention is the data processing control device proposing a kind of UART.
For achieving the above object, embodiment proposes the data processing control method of a kind of UART according to a first aspect of the present invention, comprises the following steps: obtain Frame to be sent, and described Frame to be sent is stored to circular buffer; Read the packet header of the i-th frame data to be sent in described circular buffer, and obtain the data length information in described packet header, wherein, i is positive integer; According to described data length information, described i-th frame data to be sent are transferred to transmitting-receiving buffer memory from described circular buffer; And the address of described transmitting-receiving buffer memory and described data length information are sent to logic controller by transmit queue, obtain described i-th frame Data Concurrent to be sent to make described logic controller according to the address of described transmitting-receiving buffer memory and described data length information and send.
The data processing control method of the UART of the embodiment of the present invention, by Frame to be sent is stored to circular buffer, thus according to the data length information in packet header, data to be sent are transferred to transmitting-receiving buffer memory from circular buffer, secondly the address of transmitting-receiving buffer memory and data length information are sent to logic controller by transmit queue, realize the transmission of data, ensure that data are not tampered, ensure the integrality that data send better, and without the need to considering the problem that Memory Allocation discharges, do not worry overflowing and memory fragmentation, improve the data processing performance of UART, simple and convenient.
For achieving the above object, embodiment proposes the data processing control device of a kind of UART according to a second aspect of the present invention, comprising: acquisition module, for obtaining Frame to be sent, and described Frame to be sent is stored to circular buffer; Read module, for reading the packet header of the i-th frame data to be sent in described circular buffer, and obtain the data length information in described packet header, wherein, i is positive integer; Shift module, for being transferred to transmitting-receiving buffer memory by described i-th frame data to be sent according to described data length information from described circular buffer; And sending module, for transmit queue, the address of described transmitting-receiving buffer memory and described data length information are sent to logic controller, obtain described i-th frame Data Concurrent to be sent to make described logic controller according to the address of described transmitting-receiving buffer memory and described data length information and send.
The data processing control device of the UART of the embodiment of the present invention, by Frame to be sent is stored to circular buffer, thus according to the data length information in packet header, data to be sent are transferred to transmitting-receiving buffer memory from circular buffer, secondly the address of transmitting-receiving buffer memory and data length information are sent to logic controller by transmit queue, realize the transmission of data, ensure that data are not tampered, ensure the integrality that data send better, and without the need to considering the problem that Memory Allocation discharges, do not worry overflowing and memory fragmentation, improve the data processing performance of UART, simple and convenient.
Accompanying drawing explanation
Fig. 1 is the flow chart of the data processing control method of UART according to the embodiment of the present invention;
Fig. 2 is the structural representation of the data processing control device embodiment according to UART of the present invention;
Fig. 3 is the structural representation of the data processing control device of UART according to the present invention's specific embodiment.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Be exemplary below by the embodiment be described with reference to the drawings, be intended to for explaining the present invention, and can not limitation of the present invention be interpreted as.
Data processing control method and the control device of the UART of the embodiment of the present invention are described with reference to the accompanying drawings.
Fig. 1 is the flow chart of the data processing control method of UART according to an embodiment of the invention.
As shown in Figure 1, the data processing control method of UART can comprise the following steps:
S101, obtains Frame to be sent, and Frame to be sent is stored to circular buffer.
Wherein, in one embodiment of the invention, circular buffer and transmitting-receiving buffer memory can be arranged on the global area of internal memory.Further, in one embodiment of the invention, circular buffer (ring_buffer) and transmitting-receiving buffer memory (rx_buffer) can exist with static overall variable form.
In an embodiment of the present invention, circular buffer and transmitting-receiving buffer memory can leave global area in static overall variable form, thus can automatically discharge after EP (end of program), need not consider to distribute, discharge the problem such as spilling, memory fragmentation brought.
Particularly, in an embodiment of the present invention, two static overall variable: ring_buffer can first be set up, for depositing the data received from Uart at every turn; And rx_buffer, for depositing the actual frame partial data received.
And then, Frame can not leave among the heap district of internal memory by the control method of the embodiment of the present invention, thus cause random memory all very frequent, but the Frame to be sent read was stored in circular buffer, before this therefore without the need to considering the problem that Memory Allocation discharges.
S102, read the packet header of the i-th frame data to be sent in circular buffer, and obtain the data length information in packet header, wherein, i is positive integer.
I-th frame data to be sent are transferred to transmitting-receiving buffer memory according to data length information by S103 from circular buffer.
For example, first by Uartread to data be placed on ring_buffer, secondly read out frame of data information from fixed position inside ring_buffer and (comprise frame head and frame length, be equivalent to packet header and the data length information wherein of data to be sent), finally read effective frame data according to frame data length from ring_buffer, effective frame data are placed in rx_buffer.
Further, in one embodiment of the invention, according to data length information, the i-th frame data to be sent are transferred to transmitting-receiving buffer memory from circular buffer specifically to comprise: from circular buffer, read the i-th frame data to be sent according to data length information, and empty transmitting-receiving buffer memory; I-th frame data to be sent are stored to transmitting-receiving buffer memory.
In addition, in one embodiment of the invention, when circular buffer is filled with, circular buffer discharges the buffer memory taken the earliest automatically.
That is, in an embodiment of the present invention, circular buffer can be arranged in the global area of internal memory by the embodiment of the present invention, and the size of circular buffer can be fixing, full once store at circular buffer, automatically discharge the internal memory taken the earliest, thus facilitate the management of internal memory.
S104, the address of transmitting-receiving buffer memory and data length information are sent to logic controller by transmit queue, obtain the i-th frame Data Concurrent to be sent send to make logic controller according to the address of transmitting-receiving buffer memory and data length information.
Be understandable that, after effective frame data are placed on rx_buffer, the address of rx_buffer and data length packing can be sent to logic centre by queue, as logic controller, logic centre directly can take out data according to length and address and process.
Specifically, in embodiments of the present invention, can have two queue mutex, wherein, mutex is used for adding lock control to TX data, ensures that data are not tampered, complete transmission; One of them queue is data receiver queue, and receive the external world and be given to the data that serial ports will be written to Uartdevice, another queue is transmit queue, and the devicedata read for serial ports will send to extraneous data.In addition, the data mentioned, when flow process initialization, can distribute two static overall variables, are respectively used to store the data sending and receive.
In addition, in specific implementation process, when namely saying in queue practical operation, only by address corresponding for pointed just, need not need the detailed problem considering Memory Allocation and free.
The data processing control method of the UART of the embodiment of the present invention, by Frame to be sent is stored to circular buffer, thus according to the data length information in packet header, data to be sent are transferred to transmitting-receiving buffer memory from circular buffer, secondly the address of transmitting-receiving buffer memory and data length information are sent to logic controller by transmit queue, realize the transmission of data, ensure that data are not tampered, ensure the integrality that data send better, and without the need to considering the problem that Memory Allocation discharges, do not worry overflowing and memory fragmentation, improve the data processing performance of UART, simple and convenient.
For realizing above-described embodiment, the present invention also proposes the data processing control device of a kind of UART.
Fig. 2 is the structural representation of the data processing control device of UART according to an embodiment of the invention.
As shown in Figure 2, the data processing control device 10 of UART comprises: acquisition module 100, read module 200, shift module 300 and sending module 400.
Wherein, Frame to be sent for obtaining Frame to be sent, and is stored to circular buffer by acquisition module 100.Read module 200 for reading the packet header of the i-th frame data to be sent in circular buffer, and obtains the data length information in packet header, and wherein, i is positive integer.Shift module 300 for being transferred to transmitting-receiving buffer memory according to data length information by the i-th frame data to be sent from circular buffer.The address of transmitting-receiving buffer memory and data length information are sent to logic controller for transmit queue by sending module 400, obtain the i-th frame Data Concurrent to be sent send to make logic controller according to the address of transmitting-receiving buffer memory and data length information.The control device 10 of the embodiment of the present invention can ensure that data are not tampered, and ensures the integrality that data send better, and without the need to considering the problem that Memory Allocation discharges, not worrying overflowing and memory fragmentation, improve the data processing performance of UART.
Wherein, in one embodiment of the invention, circular buffer and transmitting-receiving buffer memory can be arranged on the global area of internal memory.
Further, in one embodiment of the invention, circular buffer and transmitting-receiving buffer memory can exist with static overall variable form.
In an embodiment of the present invention, circular buffer and transmitting-receiving buffer memory can deposit global area with static overall variable form, thus can automatically discharge after EP (end of program), need not consider to distribute, discharge the problem such as spilling, memory fragmentation brought.
Particularly, in an embodiment of the present invention, two static overall variable: ring_buffer can first be set up, for depositing the data received from Uart at every turn; And rx_buffer, for depositing the actual frame partial data received.
And then, Frame can not leave among the heap district of internal memory by the control method of the embodiment of the present invention, thus cause random memory all very frequent, but the Frame to be sent read was stored in circular buffer, before this therefore without the need to considering the problem that Memory Allocation discharges.
Further, in one embodiment of the invention, as shown in Figure 3, sending module 400 also comprises: empty unit 401 and memory cell 402.
Wherein, empty unit 401 for reading the i-th frame data to be sent from circular buffer according to data length information, and empty transmitting-receiving buffer memory.Memory cell 402 is for being stored to transmitting-receiving buffer memory by the i-th frame data to be sent.
In addition, in one embodiment of the invention, when circular buffer is filled with, circular buffer discharges the buffer memory taken the earliest automatically.
That is, in an embodiment of the present invention, circular buffer can be arranged in the global area of internal memory by the embodiment of the present invention, and the size of circular buffer can be fixing, full once store at circular buffer, automatically discharge the internal memory taken the earliest, thus facilitate the management of internal memory.
It should be noted that, the explanation of the aforementioned data processing control method embodiment to UART illustrates and the data processing control device being also applicable to the UART of this embodiment repeats no more herein.
The data processing control device of the UART of the embodiment of the present invention, by Frame to be sent is stored to circular buffer, thus according to the data length information in packet header, data to be sent are transferred to transmitting-receiving buffer memory from circular buffer, secondly the address of transmitting-receiving buffer memory and data length information are sent to logic controller by transmit queue, realize the transmission of data, ensure that data are not tampered, ensure the integrality that data send better, and without the need to considering the problem that Memory Allocation discharges, do not worry overflowing and memory fragmentation, improve the data processing performance of UART, simple and convenient.
In describing the invention, it will be appreciated that, term " " center ", " longitudinal direction ", " transverse direction ", " length ", " width ", " thickness ", " on ", D score, " front ", " afterwards ", " left side ", " right side ", " vertically ", " level ", " top ", " end " " interior ", " outward ", " clockwise ", " counterclockwise ", " axis ", " radial direction ", orientation or the position relationship of the instruction such as " circumference " are based on orientation shown in the drawings or position relationship, only the present invention for convenience of description and simplified characterization, instead of indicate or imply that the device of indication or element must have specific orientation, with specific azimuth configuration and operation, therefore limitation of the present invention can not be interpreted as.
In addition, term " first ", " second " only for describing object, and can not be interpreted as instruction or hint relative importance or imply the quantity indicating indicated technical characteristic.Thus, be limited with " first ", the feature of " second " can express or impliedly comprise at least one this feature.In describing the invention, the implication of " multiple " is at least two, such as two, three etc., unless otherwise expressly limited specifically.
In the present invention, unless otherwise clearly defined and limited, the term such as term " installation ", " being connected ", " connection ", " fixing " should be interpreted broadly, and such as, can be fixedly connected with, also can be removably connect, or integral; Can be mechanical connection, also can be electrical connection; Can be directly be connected, also indirectly can be connected by intermediary, can be the connection of two element internals or the interaction relationship of two elements, unless otherwise clear and definite restriction.For the ordinary skill in the art, above-mentioned term concrete meaning in the present invention can be understood as the case may be.
In the present invention, unless otherwise clearly defined and limited, fisrt feature second feature " on " or D score can be that the first and second features directly contact, or the first and second features are by intermediary indirect contact.And, fisrt feature second feature " on ", " top " and " above " but fisrt feature directly over second feature or oblique upper, or only represent that fisrt feature level height is higher than second feature.Fisrt feature second feature " under ", " below " and " below " can be fisrt feature immediately below second feature or tiltedly below, or only represent that fisrt feature level height is less than second feature.
In the description of this specification, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means to describe in conjunction with this embodiment or example are contained at least one embodiment of the present invention or example.In this manual, to the schematic representation of above-mentioned term not must for be identical embodiment or example.And the specific features of description, structure, material or feature can combine in one or more embodiment in office or example in an appropriate manner.In addition, when not conflicting, the feature of the different embodiment described in this specification or example and different embodiment or example can carry out combining and combining by those skilled in the art.
Although illustrate and describe embodiments of the invention above, be understandable that, above-described embodiment is exemplary, can not be interpreted as limitation of the present invention, and those of ordinary skill in the art can change above-described embodiment within the scope of the invention, revises, replace and modification.
Claims (10)
1. a data processing control method of universal asynchronous receiving-transmitting transmitter UART, is characterized in that, comprises the following steps:
Obtain Frame to be sent, and described Frame to be sent is stored to circular buffer;
Read the packet header of the i-th frame data to be sent in described circular buffer, and obtain the data length information in described packet header, wherein, i is positive integer;
According to described data length information, described i-th frame data to be sent are transferred to transmitting-receiving buffer memory from described circular buffer; And
The address of described transmitting-receiving buffer memory and described data length information are sent to logic controller by transmit queue, obtain described i-th frame Data Concurrent to be sent send to make described logic controller according to the address of described transmitting-receiving buffer memory and described data length information.
2. the data processing control method of UART as claimed in claim 1, is characterized in that, described circular buffer and described transmitting-receiving buffer setting are at the global area of internal memory.
3. the data processing control method of UART as claimed in claim 1, it is characterized in that, described circular buffer and described transmitting-receiving buffer memory exist with static overall variable form.
4. the data processing control method of UART as claimed in claim 1, is characterized in that, according to described data length information, described i-th frame data to be sent is transferred to transmitting-receiving buffer memory from described circular buffer and specifically comprises:
From described circular buffer, read described i-th frame data to be sent according to described data length information, and empty described transmitting-receiving buffer memory;
Described i-th frame data to be sent are stored to described transmitting-receiving buffer memory.
5. the data processing control method of UART as claimed in claim 1, it is characterized in that, when circular buffer is filled with, described circular buffer discharges the buffer memory taken the earliest automatically.
6. a data processing control device of UART, is characterized in that, comprising:
Acquisition module, for obtaining Frame to be sent, and is stored to circular buffer by described Frame to be sent;
Read module, for reading the packet header of the i-th frame data to be sent in described circular buffer, and obtain the data length information in described packet header, wherein, i is positive integer;
Shift module, for being transferred to transmitting-receiving buffer memory by described i-th frame data to be sent according to described data length information from described circular buffer; And
Sending module, for transmit queue, the address of described transmitting-receiving buffer memory and described data length information are sent to logic controller, obtain described i-th frame Data Concurrent to be sent to make described logic controller according to the address of described transmitting-receiving buffer memory and described data length information and send.
7. the data processing control device of universal asynchronous receiving-transmitting transmitter UART as claimed in claim 6, is characterized in that, described circular buffer and described transmitting-receiving buffer setting are at the global area of internal memory.
8. the data processing control device of universal asynchronous receiving-transmitting transmitter UART as claimed in claim 6, it is characterized in that, described circular buffer and described transmitting-receiving buffer memory exist with static overall variable form.
9. the data processing control device of universal asynchronous receiving-transmitting transmitter UART as claimed in claim 6, it is characterized in that, described sending module also comprises:
Emptying unit, for reading described i-th frame data to be sent according to described data length information from described circular buffer, and emptying described transmitting-receiving buffer memory;
Memory cell, for being stored to described transmitting-receiving buffer memory by described i-th frame data to be sent.
10. the data processing control device of universal asynchronous receiving-transmitting transmitter UART as claimed in claim 6, it is characterized in that, when circular buffer is filled with, described circular buffer discharges the buffer memory taken the earliest automatically.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510906589.6A CN105577568A (en) | 2015-12-09 | 2015-12-09 | UART data processing control method and control device |
| PCT/CN2015/097488 WO2017096633A1 (en) | 2015-12-09 | 2015-12-15 | Uart data processing control method and control device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510906589.6A CN105577568A (en) | 2015-12-09 | 2015-12-09 | UART data processing control method and control device |
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| CN105577568A true CN105577568A (en) | 2016-05-11 |
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| CN201510906589.6A Pending CN105577568A (en) | 2015-12-09 | 2015-12-09 | UART data processing control method and control device |
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| CN (1) | CN105577568A (en) |
| WO (1) | WO2017096633A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110555890A (en) * | 2018-05-30 | 2019-12-10 | 珠海全志科技股份有限公司 | Memory management method and system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112506676B (en) * | 2020-12-02 | 2024-04-05 | 深圳市广和通无线股份有限公司 | Inter-process data transmission method, computer device and storage medium |
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| US7242736B2 (en) * | 2003-05-15 | 2007-07-10 | Sun Microsystems, Inc. | Data transfer |
| KR20050069694A (en) * | 2003-12-31 | 2005-07-05 | 엘지전자 주식회사 | Method for reducing receive interrupt interconnecting data of uart |
| CN100574400C (en) * | 2006-12-30 | 2009-12-23 | 技嘉科技股份有限公司 | A kind of time-shifted video recording method |
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- 2015-12-09 CN CN201510906589.6A patent/CN105577568A/en active Pending
- 2015-12-15 WO PCT/CN2015/097488 patent/WO2017096633A1/en active Application Filing
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| US20070028015A1 (en) * | 2005-07-28 | 2007-02-01 | Wickham Mark H | System and method for processing data streams |
| CN101169759A (en) * | 2007-11-08 | 2008-04-30 | Ut斯达康通讯有限公司 | Memory management method for application program |
| CN101986613A (en) * | 2010-08-26 | 2011-03-16 | 中国航天科技集团公司第九研究院第七七一研究所 | All-purpose asynchronous serial communication controller |
| CN102567260A (en) * | 2010-12-27 | 2012-07-11 | 北京国睿中数科技股份有限公司 | Device with multiple UART (universal asynchronous receiver/transmitter) interfaces and method using same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110555890A (en) * | 2018-05-30 | 2019-12-10 | 珠海全志科技股份有限公司 | Memory management method and system |
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| WO2017096633A1 (en) | 2017-06-15 |
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