WO2017092705A1 - 多模功率放大器模组、芯片及通信终端 - Google Patents
多模功率放大器模组、芯片及通信终端 Download PDFInfo
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- WO2017092705A1 WO2017092705A1 PCT/CN2016/108305 CN2016108305W WO2017092705A1 WO 2017092705 A1 WO2017092705 A1 WO 2017092705A1 CN 2016108305 W CN2016108305 W CN 2016108305W WO 2017092705 A1 WO2017092705 A1 WO 2017092705A1
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- H—ELECTRICITY
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- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
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- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
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- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
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- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
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- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0261—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A
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- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0277—Selecting one or more amplifiers from a plurality of amplifiers
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- H04B2001/0408—Circuits with power amplifiers
Definitions
- the invention relates to a multi-mode power amplifier module, and also relates to a control method of the multi-mode power amplifier module, and to a chip and a communication terminal including the multi-mode power amplifier module, and belongs to the technical field of wireless communication.
- VoLTE IP Multimedia Subsystem
- the three-mode mainly refers to three modes of GSM/TD_SCDMA/TDD_LTE.
- the five-mode mainly refers to five modes of GSM/TD_SCDMA/TDD_LTE/WCDMA/FDD_LTE. It is not difficult to see that Both the three-mode and the five-mode are inseparable from the GSM/EDGE/TD_SCDMA/TDD_LTE modes.
- the two time division multiplexing modes of TD-SCDMA and TDD-LTE are mainly used for data transmission, so the power consumption problem will be more serious.
- the power consumption of the multimode power amplifier module is mainly concentrated on the power amplifier. If the performance and power optimization of the power amplifier chip can be optimized in both time division multiplexing modes, the performance and power consumption of the multimode power amplifier module can be optimized.
- the primary technical problem to be solved by the present invention is to provide a multimode power amplifier module.
- Another technical problem to be solved by the present invention is to provide a control method for a multimode power amplifier module.
- Another technical problem to be solved by the present invention is to provide a chip and a communication terminal including the multimode power amplifier module.
- a multimode power amplifier module includes a low frequency power amplifier path, a high frequency power amplifier path, a control circuit, and a transceiver switch;
- the low frequency power amplifier path includes a low frequency input matching network, a low frequency power amplifier and a low frequency output matching network, which are sequentially connected in series; the low frequency input matching network is used to access a low frequency RF signal to achieve impedance matching; and the low frequency power amplifier is used Amplifying the low frequency radio frequency signal; the low frequency output matching network is configured to implement low frequency impedance conversion to output low frequency output power according to the amplified low frequency radio frequency signal;
- the high frequency power amplifier path includes a high frequency input matching network, a high frequency power amplifier and a high frequency output matching network, which are sequentially connected in series; the high frequency input matching network is used to access a high frequency radio frequency signal to achieve impedance matching; a high frequency power amplifier for realizing amplification of the high frequency radio frequency signal; the high frequency output matching network for realizing high frequency impedance conversion to output high frequency output power according to the amplified high frequency radio frequency signal ;
- the control circuit is configured to access a control power source Vbat, a baseband signal Vramp, and an operation mode selection signal; the control circuit sends an amplifier to the low frequency power amplifier or the high frequency power amplifier according to the baseband signal Vramp and the operation mode selection signal Controlling a signal to control the low frequency power amplifier or the high frequency power amplifier to amplify the accessed low frequency radio frequency signal or high frequency radio frequency signal;
- the transceiver switch is respectively connected to the control circuit, the low frequency output matching network and the high frequency output matching network; the transceiver switch is configured to select a corresponding working mode for transmitting or receiving according to the working mode selection signal.
- the multi-mode power amplifier module supports GSM, EDGE, TD_SCDMA, and/or TDD_LTE working modes;
- the low frequency input matching network is configured to access a low frequency GSM signal or a low frequency EDGE signal;
- the high frequency input matching network is configured to access a high frequency GSM signal, a high frequency EDGE signal, a TD_SCDMA signal, or a TDD_LTE signal.
- the amplifier control signal sent by the control circuit to the low frequency power amplifier or the high frequency power amplifier comprises: a logic signal Vmode, a bias signal Reg and/or a collector voltage Vcc.
- the low frequency power amplifier or the high frequency power amplifier is provided with a feedback circuit;
- the logic signal Vmode is used to control the feedback switch on the feedback circuit to open or close;
- the logic signal Vmode controls the feedback switch to be turned on, the low frequency power amplifier or the high frequency power amplifier operates in a high gain mode;
- the low frequency power amplifier or high frequency power amplifier operates in a low gain mode when the logic signal Vmode controls the feedback switch to close.
- the collector voltage Vcc is used to supply power to the low frequency power amplifier or the high frequency power amplifier to control the low frequency radio frequency signal or the high frequency radio frequency signal amplified by the low frequency power amplifier or the high frequency power amplifier.
- Output power is used to supply power to the low frequency power amplifier or the high frequency power amplifier to control the low frequency radio frequency signal or the high frequency radio frequency signal amplified by the low frequency power amplifier or the high frequency power amplifier.
- the control circuit selects a corresponding reference voltage according to the operation mode selection signal, and generates the collector voltage Vcc according to the reference voltage.
- the control circuit selects the baseband signal Vramp as the reference voltage to generate the collector voltage Vcc;
- the control circuit selects a reference voltage Vref as the reference voltage to generate the collector voltage Vcc; wherein the reference voltage Vref and the control The power supply Vbat changes linearly.
- the bias signal Reg is used to adjust the current of the low frequency power amplifier or the high frequency power amplifier
- the control circuit closes a corresponding switch in the bias signal switch group according to the operating mode selection signal to generate a bias signal Reg corresponding to the working mode; the bias signal switch group is provided with a corresponding operation mode switch.
- control circuit includes a bias signal generating circuit;
- the bias signal generating circuit includes: an operational amplifier, a P-channel metal oxide semiconductor field effect transistor (PMOS), and the bias signal Switch group
- a positive input terminal of the operational amplifier is coupled to a reference voltage Vref; an output of the operational amplifier is coupled to a gate of a P-channel metal oxide semiconductor field effect transistor (PMOS); a source of the PMOS is coupled to the Control the power supply Vbat; the drain of the PMOS is the output of the bias signal generating circuit, for outputting the bias signal Reg;
- PMOS metal oxide semiconductor field effect transistor
- the bias signal switch is coupled between the negative input terminal of the operational amplifier and the resistor; A resistor is connected in series between the switches in the set of bias signal switches.
- the bias signals Reg corresponding to the GSM, EDGE, TDD_LTE, and TD_SCDMA working modes are sequentially reduced.
- the bias signal Reg is connected to a bias circuit of the power amplifier; the bias circuit comprises a collector of R71, D71, D72 and Q71 bipolar transistors; and the diodes D71, D72 and R71 are used.
- the voltage V71 is generated by dividing the voltage; the voltage V71 generates a voltage V72 after the voltage drop; the current control of the bipolar transistor Q72 is implemented according to V72 and V73; the bipolar transistor Q72 is a power amplifier tube of the power amplifier.
- a multi-mode power amplifier module for time division multiplexing including a low frequency power amplifier path, a high frequency power amplifier path, a control circuit, and a transceiver switch;
- the low frequency power amplifier path includes a low frequency input matching network, a low frequency power amplifier and a low frequency output matching network, which are sequentially connected in series; the low frequency input matching network is used to access a low frequency RF signal to achieve impedance matching; and the low frequency power amplifier is used to implement the pair Amplifying the low frequency radio frequency signal; the low frequency output matching network is configured to implement low frequency impedance conversion to output low frequency output power according to the amplified low frequency radio frequency signal;
- the high frequency power amplifier path includes a high frequency input matching network, a high frequency power amplifier and a high frequency output matching network, which are sequentially connected in series; the high frequency input matching network is used to access a high frequency radio frequency signal to achieve impedance matching;
- the frequency power amplifier is configured to implement amplification of the high frequency radio frequency signal;
- the high frequency output matching network is configured to implement high frequency impedance conversion to output high frequency output power according to the amplified high frequency radio frequency signal;
- the control circuit generates different bias signals according to the size of the baseband signal in a time division multiplexing mode to bias the low frequency RF signal or the high frequency power amplifier to which the low frequency power amplifier or the high frequency power amplifier is connected.
- the frequency RF signal is amplified; the transceiver switch selects a signal according to an operation mode, and selects a corresponding working mode to transmit or receive.
- the working mode of the time division multiplexing is a TD_SCDMA and/or a TDD_LTE working mode.
- the baseband signal is input to a negative input terminal of the operational amplifier, and an output end of the operational amplifier is connected to a gate of the transistor;
- the source of the transistor is connected to a control power supply, and the drain outputs the bias signal.
- the baseband signal and the reference voltage are respectively connected to a positive input terminal and a negative input terminal of the multi-channel analog switch, and the multi-channel analog switch is input.
- the output is connected to the negative input of the operational amplifier.
- the multi-channel analog switch has at least two paths, and the opening or closing of the path is determined by the baseband signal and the operation mode.
- the drain of the transistor is connected in series through the first resistor and the second resistor, and the connection point of the first resistor and the second resistor is connected to the positive of the operational amplifier. Input.
- a gate switch is disposed between a connection point of the adjacent resistor and a positive input end of the operational amplifier, and the gate switch is changed according to the baseband signal or the operation mode. On and off status.
- the drain of the transistor is grounded through a plurality of resistors connected in series; the connection point of the adjacent resistor is connected to the positive input terminal of the operational amplifier.
- the low frequency power amplifier path has at least one level of amplifying circuit
- the high frequency power channel has at least one level of amplifying circuit
- a method for controlling a multimode power amplifier module includes the following steps:
- a bias signal is provided for the high frequency power amplifier path, the size of which is determined by the size and mode of operation of the baseband signal.
- the bias signal is controlled by the baseband signal and the operating mode, and varies linearly or nearly linearly with the baseband signal.
- the bias signal is controlled by the baseband signal and the operational mode and varies stepwise with the baseband signal.
- the bias signal is controlled by the baseband signal and the operational mode, and varies linearly with the baseband signal in a stepped manner.
- a chip having a multimode power amplifier module including any of the foregoing multimode power amplifier modules is provided.
- a communication terminal having a multimode power amplifier module including any one of the foregoing multimode power amplifier modules is provided.
- the multi-mode power amplifier module, the chip and the communication terminal charge the power amplifier channel according to the frequency band characteristics of different modes in the communication protocol.
- the multiplexing of the sub-bands enables the different operating modes of the high and low frequency bands to share the power amplifier path under the adjustment of the control circuit, and realizes multiple values of the bias voltage or the bias current with the change of the baseband signal in the time division multiplexing mode. This simplifies the design complexity of the power amplifier module and reduces the cost of the associated design implementation.
- FIG. 1 is a block diagram showing the structure of a multimode power amplifier module shown in an embodiment
- FIG. 2 is a circuit diagram of a multimode power amplifier module shown in an embodiment
- FIG. 3 is a schematic diagram showing a circuit diagram of controlling a power amplifier gain according to a logic signal according to an embodiment
- FIG. 4 is a schematic diagram of a collector voltage generating circuit shown in an embodiment
- FIG. 5 is a schematic diagram of a reference voltage generating circuit shown in an embodiment
- FIG. 6 is a schematic diagram of a bias signal generating circuit shown in an embodiment
- FIG. 7 is a schematic diagram showing a current adjustment circuit of a bias signal to a stage in a power amplifier according to an embodiment
- FIG. 8 is a schematic diagram of a first embodiment of controlling a power amplifier bias signal according to a baseband signal
- Figure 9 is a diagram showing the relationship between the bias signal Reg and the baseband signal Vramp shown in the first embodiment
- FIG. 10 is a schematic diagram of a second embodiment of controlling a power amplifier bias signal based on a baseband signal
- Figure 11 is a diagram showing the relationship between the bias signal Reg and the baseband signal Vramp shown in the second embodiment
- FIG. 12 is a schematic diagram of a third embodiment of controlling a power amplifier bias signal according to a baseband signal
- Figure 13 is a diagram showing the relationship between the bias signal Reg and the baseband signal Vramp shown in the third embodiment.
- the communication terminal involved can be used in a mobile environment and supports GSM, EDGE, TD_SCDMA, TDD_LTE, FDD_LTE.
- Computer equipment such as a variety of communication systems, including but not limited to mobile phones, notebook computers, tablet computers, car computers, and the like.
- the multimode power amplifier module is also suitable for other multi-mode technology applications, such as communication base stations compatible with a variety of communication systems.
- both the three-mode and five-mode schemes include three modes of GSM/TD_SCDMA/TDD_LTE, and due to the limited coverage of the LTE network, compatibility is still required in the current three-mode/five-mode scheme.
- EDGE mode in which the frequency of the PCS segment in the high frequency GSM is 1850 MHz to 1910 MHz, the frequency band of the TD_SCDMA is 1880 MHz to 1920 MHz, 2010 MHz to 2025 MHz, and the B39 frequency band of the TDD_LTE is 1880 MHz to 1920 MHz.
- the frequency in the three modes is the frequency. Relatively close, the bands of GSM and EDGE are completely coincident, which provides the possibility of circuit multiplexing.
- the power amplifier module operates in different modes and requires different output power, gain, linearity and operating current.
- the above indicators of the power amplifier module are determined by the power amplifier in the module, so the output power can be realized by optimizing the gain network, collector voltage and bias voltage (current) of the power amplifier in different modes. Optimization of gain, current and linearity.
- the multi-mode power amplifier module includes: a low-frequency power amplifier path, a high-frequency power amplifier path, a control circuit, and a transceiver switch.
- the low frequency power amplifier path has at least one level of amplifying circuit
- the high frequency power channel has at least one level of amplifying circuit.
- the low frequency power amplifier path includes a low frequency input matching network, a low frequency power amplifier and a low frequency output matching network in series.
- the low frequency input matching network has a low frequency input terminal for accessing low frequency RF signals for impedance matching.
- the low-frequency power amplifier is connected to a low-frequency input signal of a low-frequency input matching network output for amplifying the low-frequency RF signal.
- the low frequency output matching network is used to implement low frequency impedance conversion to output low frequency output power according to the amplified low frequency RF signal.
- the high frequency power amplifier path includes a high frequency input matching network, a high frequency power amplifier, and a high frequency output matching network in series.
- the high-frequency input matching network has a high-frequency input terminal for accessing high-frequency RF signals for impedance matching.
- the high-frequency power amplifier is connected to a high-frequency input signal of a high-frequency input matching network for amplifying the high-frequency RF signal.
- the high frequency output matching network is used to implement high frequency impedance conversion to output high frequency output power according to the amplified high frequency radio frequency signal.
- the control circuit is the core control component of the multimode power amplifier module.
- the control circuit is provided with at least three inputs for respectively accessing the control power source Vbat, the baseband signal Vramp and the operating mode selection signal.
- the control circuit is respectively connected to the low frequency power amplifier and the high frequency power amplifier, and transmits an amplifier control signal to the low frequency power amplifier or the high frequency power amplifier according to the baseband signal Vramp and the operation mode selection signal. Through the control signal, the low frequency power amplifier or the high frequency power amplifier is controlled to amplify and optimize the accessed low frequency radio frequency signal or high frequency radio frequency signal.
- the transceiver switch is respectively connected to the above control circuit, the low frequency output matching network and the high frequency output matching network.
- the transceiver switch is configured to select a signal according to an operation mode and select a corresponding working mode for transmitting or receiving.
- the multi-mode power amplifier module fully multiplexes the power amplifier path according to the frequency band characteristics of different modes in the communication protocol, so that different working modes of the high and low frequency bands can share the power amplifier path under the adjustment of the control circuit, thereby simplifying the power.
- the design complexity of the amplifier module reduces the cost of the relevant design implementation, and is simple, flexible, and easy to implement.
- the multi-mode power amplifier module shown in this embodiment is designed to operate in GSM (Global System for Mobile communication), EDGE (Enhanced Data Rate for GSM Evolution), enhanced data rate. GSM evolution technology), TD_SCDMA (Time Division-Synchronous Code Division Multiple Access), TDD_LTE (Time Division Long Term Evolution) mode.
- GSM Global System for Mobile communication
- EDGE Enhanced Data Rate for GSM Evolution
- TD_SCDMA Time Division-Synchronous Code Division Multiple Access
- TDD_LTE Time Division Long Term Evolution
- the external pin of the multimode power amplifier module includes: 109 is a low frequency input end of the low frequency power amplifier path for accessing the low frequency GSM/EDGE radio frequency signal.
- 110 is a control power supply access terminal of the control circuit 104 for accessing the control power source Vbat.
- 111 is a TX_enble interface for enabling the control circuit to access the TX enable signal.
- 113/114/115 is the logic signal B0/B1/B2 interface, used to connect the B0/B1/B2 logic signals to the control circuit.
- the three logic signals of B0/B1/B2 and the enable signals of TX together constitute an operation mode selection signal of the control circuit, and together control the selection of the working mode of the multi-mode power amplifier module.
- the 112 is a baseband signal interface of the control circuit for accessing the baseband signal Vramp.
- the baseband signal Vramp can be any value from 0 to 1.8V.
- the output power of the multimode power amplifier module can be adjusted by setting different baseband signals Vramp.
- 116 is a high frequency input terminal of the low frequency power amplifier path for accessing GSM/EDGE/TD_SCDMA/TDD_LTE radio frequency signals.
- 117 is a transceiver switch located at the antenna end.
- 118/119/120/121/122/123, corresponding to TRX1, TRX2, TRX3, TRX4, TRX5, and TRX6, respectively, are six transceiver ports that can be used as either a transmit port or an output port.
- the multi-mode power amplifier module includes: a low-frequency input matching network 101 for accessing low-frequency GSM/EDGE radio frequency signals to achieve matching to 50 Ohm impedance.
- the low frequency power amplifier 102 is configured to achieve amplification of the connected low frequency GSM/EDGE radio frequency signals (824 MHz to 849 MHz; 880 MHz to 915 MHz).
- the low frequency output matching network 103 is used to implement low frequency impedance conversion to output the desired output power.
- the control circuit 104 can be implemented in CMOS, which is mainly considered in terms of design flexibility and cost.
- the control circuit 104 mainly provides an amplifier control signal for the low frequency power amplifier 103 and the high frequency power amplifier 106 based on the baseband signal Vramp and the operating mode selection signal.
- the amplifier control signal includes a logic signal Vmode, a bias signal Reg, and/or a collector voltage Vcc.
- the control circuit 104 also supplies a power supply voltage and a logic voltage to the transceiver switch 108.
- the high frequency input matching network 105 is used to access the high frequency GSM/EDGE signal, the TD_SCDMA signal and the TDD_LTE signal to achieve a matching of 50 Ohm.
- the high frequency power amplifier 106 realizes amplification of the connected high frequency GSM/EDGE radio frequency signal, TD_SCDMA signal and TDD_LTE signal (1710 MHz to 2025 MHz).
- the high frequency output network 107 is used to implement high frequency impedance conversion to output a desired output power.
- the transceiver switch 108 is located at the antenna end and is respectively connected to the output of the transmission and the input of the reception.
- the transceiver switch 108 in the embodiment shown in FIG. 2 is SP8T.
- the transceiver switch can also be extended to any SPXT as needed, generally applied at the antenna end of the mobile phone, and X is not less than 4. For example, SP8T required for 3 mode 5 frequency, SP16T is required for 5 mode 12 frequency, and some applications are SP10T, SP12T or SP14T.
- the control circuit in the multi-mode power amplifying module provides an amplifier control signal for the power amplifier according to the baseband signal Vramp and the operation mode selection signal to control the power amplifier for amplification adjustment.
- the multi-mode power amplifier module is based on this method, and the power amplifier path is fully multiplexed, so that different working modes of the high and low frequency bands can share the power amplifier path under the adjustment of the control circuit.
- the amplifier control signal herein includes a logic signal Vmode, a bias signal Reg, and/or a collector voltage Vcc.
- control circuit amplifies and adjusts the power amplifier through the amplifier control signal through several embodiments.
- FIG. 3 is a schematic diagram of controlling a power amplifier gain circuit based on a logic signal.
- the power amplifier shown in FIG. 3 may be a low frequency power amplifier or a high frequency power amplifier.
- the collector of the power amplifier is powered by the collector voltage Vcc output from the control circuit.
- a feedback circuit is provided in the power amplifier.
- the feedback circuit of the power amplifier is composed of capacitors C30, C31, and R30 connected in series.
- the logic signal Vmode (eg, 0 or Vbat) output by the control circuit is used to control the feedback switch on the feedback circuit to open or close.
- the logic signal Vmode controls the feedback switch to be turned on
- the feedback circuit is in an off-state.
- the power amplifier is in a high gain mode because it has no feedback circuit.
- the system requires the power amplifier module to have the highest output power, so when the control circuit is in the operating mode, the logic signal Vmode can be output to control the power amplifier to operate in the high gain mode.
- the logic signal Vmode controls the feedback switch to be closed
- the feedback circuit is in an on-state.
- the power amplifier is in a low gain mode due to the feedback circuit.
- the logic signal Vmode can be output to control the power amplifier to operate in the low gain mode.
- control circuit can determine the current operating mode according to the operating mode selection signal, and further determine whether the power amplifier should be in the high gain mode or the low gain mode, thereby outputting the corresponding logic signal Vmode to the power amplifier.
- the collector voltage Vcc output from the control circuit is used to supply power to the corresponding power amplifier as the collector voltage, thereby adjusting the output power of the power amplifier. Therefore, the control circuit outputs different collector voltages Vcc to the power amplifier according to different current operating modes, and can function to adjust the output of the power amplifier.
- the collector voltage generating circuit is located in the control circuit.
- the control circuit determines the current operating mode based on the operating mode selection signal.
- a corresponding reference voltage is selected according to the current operating mode to generate a collector voltage Vcc based on the reference voltage.
- an operational amplifier is provided in the collector voltage generating circuit.
- the output of the operational amplifier is connected to the gate of an insulated gate bipolar transistor. Insulated gate bipolar crystal
- the emitter of the tube is connected to the control power supply Vbat.
- the collector of the insulated gate bipolar transistor is the output of the collector voltage Vcc for outputting the collector voltage Vcc.
- a voltage R41 is provided between the negative input terminal of the operational amplifier and the output terminal of the collector voltage Vcc.
- a voltage R42 is provided between the negative input terminal of the operational amplifier and ground.
- the positive input of the operational amplifier is the reference input for inputting the reference voltage selected by the control circuit. As shown in FIG. 4, the reference voltage input terminal selects and accesses different reference voltages through different switches.
- the GSM_enble switch When the operation mode selection signal is in the GSM mode, the GSM_enble switch is closed in FIG. 4, and the control circuit selects the baseband signal Vramp as the reference voltage to generate the collector voltage Vcc. among them, Different Vcc values are obtained by different Vramp values of the baseband. Since Vcc is the supply voltage of the collector of the power amplifier, the output powers P and Vcc have the following correspondences: Where RL is the load of the power amplifier and is determined by the output matching network. Therefore, the control circuit can adjust the output power of the power amplifier through different baseband signals Vramp.
- the operation mode selection signal is EDGE, TD_SCDMA or TDD_LTE mode
- the EDGE/TD_SCDMA/TDD_LTE_enble switch in FIG. 4 is closed, and the control circuit selects the reference voltage Vref as a reference voltage to generate the collector voltage Vcc.
- the power amplifier module is in a linear operation mode, and the change in output power is achieved by changing the change of the input signal. among them
- the collector voltage Vcc Vbat - V DS , where V DS is the saturation voltage difference of the source and drain levels of M41, typically 0.15V to 0.2V.
- Vref4 is generated by the circuit schematic of FIG.
- V BE53 is the base-to-emitter voltage difference of the bipolar transistor Q53. It is generally 0.7V in the silicon process.
- n is the ratio of the Q52 to the Q51 emitter area, and V T is the thermal voltage, which is 0.026V.
- the bias signal Reg is used to adjust the current of the power amplifier.
- Control circuit according to work
- the mode selection signal controls the corresponding switch in the closed bias signal switch group to generate a bias signal Reg corresponding to the operating mode.
- a switch corresponding to each operation mode is provided in the bias signal switch group.
- the bias signal can be a voltage signal or a current signal.
- Fig. 6 is a schematic diagram of a bias signal generating circuit.
- the bias signal generating circuit is located in the control circuit.
- the control circuit determines the current operating mode based on the operating mode selection signal.
- the corresponding switch in the closed bias signal switch group is selected according to the current working mode to generate a bias signal Reg corresponding to the working mode.
- the bias signal generating circuit includes an operational amplifier, a PMOS transistor, and a bias signal switch group.
- the positive input of the operational amplifier is connected to the reference voltage Vref; the reference voltage Vref is determined according to the bias signal Reg. Different bias signals Reg are required in different modes, and Reg and Vref are in accordance with a certain formula; the output of the operational amplifier is connected to the gate of the PMOS transistor.
- the source of the PMOS is connected to the control power supply Vbat.
- the drain of the PMOS is the output of the bias signal generating circuit for outputting the bias signal Reg.
- the reference voltage Vref is generated based on the circuit shown in FIG. 5, and details are not described herein again.
- the bias signal switch group is connected between the negative input terminal of the operational amplifier and the collector of the PMOS transistor.
- a resistor is connected in series between the switches in the bias signal switch group.
- the bias signal switch group is provided with a TDD_SCDMA_enble switch, a TDD_LTE_enble switch, an EDGE_enble switch, and a GSM_enble switch.
- resistors R61, R62, R63, R64, and R65 are connected in series between the switches.
- the control circuit determines a current operating mode based on the operating mode selection signal.
- the corresponding switch in the closed bias signal switch group is controlled according to the current working mode. For example, when currently in the TDD_LTE mode, the TDD_LTE_enble switch is selected to be closed, and the other switches remain off. Based on this, the bias signal Reg is generated.
- the bias signal Reg is higher, EDGE/TD_SCDMA is sequentially decreased, and the bias voltage in the TDD_LTE mode is in between, mainly balancing power consumption and linearity.
- the bias signal generation circuit given in Figure 6, in GSM mode In EDGE mode TDD_SCDMA mode TD_LTE mode It can be seen that the bias signals Reg corresponding to the above GSM, EDGE, TD_SCDMA, and TDD_LTE working modes are sequentially reduced.
- the general design described herein also includes that TD_SDMA and TDD_LTE share one Reg, or TDD_LTE.
- the bias signal is greater than TD_SCDMA.
- the setting of the specific switch in the bias signal switch group can be adjusted according to the specific working mode type supported by the multi-mode power amplifier module.
- the basic design principles are the same. Those skilled in the art, based on the technical suggestion given in this embodiment, that any adjustments made to the set of bias signal switches are considered to be within the scope of the present invention.
- the bias signal is used to adjust the power amplifier current through the circuit shown in FIG.
- Figure 7 is a circuit schematic diagram of a stage in the bias signal control power amplifier.
- the power amplifier can be two or three stages, and each stage can be controlled by the bias circuit part of FIG.
- R D2 is the on-resistance of diodes D1 and D2. After diodes D1 and D2 are selected, R D1 and R D2 are constant values.
- V 72 V 71 -V BEQ71
- V 73 V BEQ72
- V BEQ71 and V BEQ72 are the voltage difference between the base and emitter of heterojunction bipolar transistor (HBT) Q71 and Q72.
- HBT heterojunction bipolar transistor
- V BE 1.3V
- I BQ72 is the base current of Q72 heterojunction bipolar transistor
- ⁇ is the amplification factor, generally from 60 to 160, mainly depending on the process of heterojunction bipolar transistor.
- the bias signal Reg is connected to the bias circuit of the power amplifier, and the bias circuit includes the collectors of the R71, D71, D72, and Q71 bipolar transistors, wherein the diodes D71, D72, and R71 are divided to generate V71, and the V71 passes through a V BE voltage drop, the voltage difference between V72, V72 and V73 determines the current through R72, that is, the base current of Q72 bipolar transistor, thus realizing the current control of Q72, where Q72 is the power amplifier power amplifier tube.
- the collector of Q71 can also be directly connected to Vbat.
- the power amplifier should always be in a linear power amplification state.
- the bias current required by the power amplifier is relatively large in order to ensure a certain degree of linearity.
- the bias signal Reg provided by the control circuit is also relatively large, thus optimizing the performance of the multi-mode power amplifier module.
- the power amplifier only needs a relatively low bias current to achieve sufficient linearity. In this case, if the bias signal Reg provided by the control circuit is relatively small, the bias current required by the power amplifier can be lowered, thereby achieving the purpose of reducing power consumption of the multimode power amplifier module.
- the control circuit in the multimode power amplifier module provides an amplifier control signal for the power amplifier to control the power amplifier for amplification adjustment based on the baseband signal and the operating mode selection signal.
- the amplifier control signals herein include, but are not limited to, a logic signal Vmode, a bias signal Reg, and/or a collector voltage Vcc.
- the baseband signal Vramp participates in the selection of the two time division multiplexing modes as a logic level, either high level or low level. Therefore, the bias voltage or bias current in the two time division multiplexing modes has only one value, which cannot be adjusted according to the output power of the multimode power amplifier module.
- bias signal Reg the bias voltage or bias current
- the bias signal Reg when a voltage signal is required as the bias signal, the bias signal Reg is a bias voltage;
- the bias signal Reg is a bias current.
- the above variation of the bias voltage or bias current causes the output current of the power amplifier to change, thereby optimizing the performance and power consumption of the entire multimode power amplifier module.
- control circuit adjusts the bias signal Reg of the power amplifier through the baseband signal Vramp is specifically described.
- Figure 8 is a schematic diagram of a first embodiment of controlling a power amplifier bias signal based on a baseband signal.
- the baseband signal Vramp is input to the negative input terminal (also referred to as the inverting input terminal) of the operational amplifier, and the output terminal of the operational amplifier is connected to the gate of an insulated gate bipolar transistor.
- the source of the insulated gate bipolar transistor is connected to the control power supply Vbat.
- the drain of the insulated gate bipolar transistor is the output of the bias signal Reg for outputting the bias signal.
- the drain of the insulated gate bipolar transistor is grounded via resistors R21 and R22.
- the junction of resistors R21 and R22 is directly connected to the positive input of the op amp (also known as the non-inverting input).
- the bias signal Reg can be either a voltage signal or a current signal.
- the corresponding parameter G can be obtained according to the value of the baseband signal Vramp and the bias voltage or bias current value required for design optimization.
- the following formula can be derived: In other words, by selecting the appropriate resistance of the resistors R21 and R22, the parameter G required by the user can be obtained.
- Figure 10 is a schematic diagram of a second embodiment of controlling a power amplifier bias signal based on a baseband signal.
- the second embodiment most of the circuits are connected in substantially the same manner as the first embodiment, except for the drain output portion of the insulated gate bipolar transistor.
- the collector of the insulated gate bipolar transistor is grounded via resistors R31, R32, R33 and R34.
- a gate switch is arranged between the connection point of the resistors R31 and R32 and the positive input terminal of the operational amplifier, the gate switch is turned on when Vramp ⁇ A, and is turned off during the rest of the time; the connection point and operation of the resistor R32 and R33
- a strobe switch is provided between the positive input terminals of the amplifier, and the strobe switch is turned on when A ⁇ Vramp ⁇ B, and is turned off for the rest of the time; a connection between the connection point of the resistors R33 and R34 and the positive input terminal of the operational amplifier is set.
- the strobe switch is turned on when Vramp>B and turned off during the rest of the time.
- a and B are a certain threshold voltage.
- the stepped linear relationship shown in FIG. 11 can be presented between the bias signal Reg and the baseband signal Vramp.
- the value of the relationship between V1, V2, and V3 is determined by the performance requirements of the design, and the value can be zero.
- Figure 12 is a schematic diagram of a third embodiment of controlling a power amplifier bias signal based on a baseband signal.
- the third embodiment most of the circuits are connected in substantially the same manner as the second embodiment, except that the baseband signal Vramp and the reference voltage Vref41 are respectively connected to the positive input and the negative input of the multi-channel analog switch (MUX).
- the output signal Vref42 of the multi-channel analog switch replaces the original baseband signal Vramp to the negative input terminal of the operational amplifier.
- the above multi-channel analog switch has at least two paths, and the opening or closing of the path is determined by the baseband signal and the operation mode.
- the collector of the insulated gate bipolar transistor is grounded via resistors R41, R42, R43 and R44.
- a gate switch is arranged between the connection point of the resistors R41 and R42 and the positive input terminal of the operational amplifier, the gate switch is turned on when Vramp ⁇ A, and is turned off during the rest of the time; the connection point and operation of the resistor R42 and R43
- a strobe switch is provided between the positive input terminals of the amplifier.
- the strobe switch is turned on when A ⁇ Vramp ⁇ B, and is turned off during the rest of the time; a connection between the connection point of the resistors R43 and R44 and the positive input terminal of the operational amplifier is set.
- the strobe switch is turned on when Vramp>B and turned off during the rest of the time.
- a and B are a certain threshold voltage.
- the stepped linear relationship shown in FIG. 13 can be presented between the bias signal Reg and the baseband signal Vramp.
- Transistors herein include, but are not limited to, insulated gate bipolar transistors, field effect transistors, or triodes. Corresponding circuit adjustments are conventional technical means that can be grasped by those skilled in the art, and do not go beyond the technical revelation provided by the present invention, and will not be described herein.
- TD_SCDMA and TDD_LTE are also part of the time division multiplexing operation mode, they still have different requirements for the bias signal Reg. Therefore, in the TD_SCDMA and TDD_LTE modes, the work can be realized by setting different baseband signals Vramp. Further optimization of performance.
- the output control method of the multimode power amplifier module provided by the present invention comprises the steps of: providing a bias signal to the low frequency power amplifier path, the size of which is determined by the size and operation mode of the baseband signal; and providing a bias signal to the high frequency power amplifier path, the size of which is determined by the size and operation mode of the baseband signal.
- the bias signal is controlled by the baseband signal and the operating mode, and the linear or very linear change with the baseband signal.
- the bias signal is controlled by the baseband signal and the operational mode and varies stepwise with the baseband signal.
- the bias signal is controlled by the baseband signal and the operational mode, and varies linearly with the baseband signal in a stepped manner.
- the multimode power amplifier module shown in the above embodiment can be used in a chip.
- the structure of the multimode power amplifier module in the chip will not be detailed here.
- the above multimode power amplifier module can also be used in a communication terminal as An important part of the RF circuit.
- the term "communication terminal” as used herein refers to a computer device that can be used in a mobile environment and supports multiple communication modes such as GSM, EDGE, TD_SCDMA, TDD_LTE, FDD_LTE, etc., including but not limited to mobile phones, notebook computers, tablet computers, car computers, and the like.
- the multi-mode power amplifier module is also suitable for other multi-mode technology applications, such as communication base stations compatible with multiple communication modes, etc., which will not be detailed here.
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Abstract
一种多模功率放大器模组、芯片及通信终端。该多模功率放大器模组中，控制电路（104）根据基带信号向低频功率放大器（102）或高频功率放大器（106）发送偏置信号，以控制低频功率放大器（102）或高频功率放大器（106）对所接入的低频射频信号或高频射频信号进行放大；收发开关（108）根据工作模式选择信号，选择对应的工作模式进行发射或接收。根据不同模式对功放通路进行复用，使得高低频段的不同工作模式可以在控制电路（104）的调整下共用功放通路，从而简化了功率放大器模组的设计复杂度，降低了相关设计实现的成本。
Description
本发明涉及一种多模功率放大器模组，同时也涉及该多模功率放大器模组的控制方法，还涉及包括该多模功率放大器模组的芯片及通信终端，属于无线通信技术领域。
当前，4G LTE已经进入大规模推广阶段。但实现VoLTE的全覆盖即移动宽带语音应用，而让传统的电路交换退出历史舞台，却是个相当长的过程。这是因为一方面，VoLTE涉及较多新技术，需要必要的测试和试验；另一方面，IMS(IP多媒体子系统)的部署和集成需要一定的时间，现有网络的设备也需要逐步升级和改造。
在相当长的一段时间段里，LTE网络本身仍不能提供语音业务，语音部分需要利用3G/2G网络，又因为3G WCDMA/CDMA涉及到高通的专利费用问题，所以平台厂商例如联发科、展讯、联芯科技都推出的是语音部分应用2G的方案。所以2G GSM在4G通信中，在相当长的一段时间内是必不可少的。为此，移动运营商正在大力推广三模和五模的方案，三模主要指GSM/TD_SCDMA/TDD_LTE三种模式，五模主要指GSM/TD_SCDMA/TDD_LTE/WCDMA/FDD_LTE五种模式，不难看出无论是三模还是五模都离不开GSM/EDGE/TD_SCDMA/TDD_LTE几种模式。
在上述几种模式中，TD-SCDMA和TDD-LTE这两种时分复用模式主要用于数据传输，所以耗电问题会比较严重。多模功率放大器模组的功耗又主要集中在功率放大器上。如果能够在这两种时分复用模式下进行功率放大芯片的性能和功耗优化，就可以实现对多模功率放大器模组的性能和功耗的优化。
发明内容
本发明所要解决的首要技术问题在于提供一种多模功率放大器模组。
本发明所要解决的另一技术问题在于提供一种多模功率放大器模组的控制方法。
本发明所要解决的又一技术问题在于提供一种包括该多模功率放大器模组的芯片及通信终端。
为实现上述发明目的，本发明采用下述的技术方案：
根据本发明实施例的第一方面，提供一种多模功率放大器模组，包括低频功放通路、高频功放通路、控制电路和收发开关；
所述低频功放通路，包括顺序串联的低频输入匹配网络、低频功率放大器和低频输出匹配网络；所述低频输入匹配网络，用于接入低频射频信号，实现阻抗匹配；所述低频功率放大器，用于实现对所述低频射频信号的放大；所述低频输出匹配网络，用于实现低频的阻抗转换，以根据放大后的低频射频信号输出低频输出功率；
所述高频功放通路，包括顺序串联的高频输入匹配网络、高频功率放大器和高频输出匹配网络；所述高频输入匹配网络，用于接入高频射频信号，实现阻抗匹配；所述高频功率放大器，用于实现对所述高频射频信号的放大；所述高频输出匹配网络，用于实现高频的阻抗转换，以根据放大后的高频射频信号输出高频输出功率；
所述控制电路，接入控制电源Vbat、基带信号Vramp和工作模式选择信号；所述控制电路，根据所述基带信号Vramp和工作模式选择信号，向所述低频功率放大器或高频功率放大器发送放大器控制信号，以控制所述低频功率放大器或高频功率放大器对所接入的低频射频信号或高频射频信号进行放大；
所述收发开关，与所述控制电路、低频输出匹配网络和高频输出匹配网络分别连接；所述收发开关，用于根据所述工作模式选择信号，选择对应的工作模式进行发射或接收。
其中较优地，所述多模功率放大器模组支持GSM、EDGE、TD_SCDMA和/或TDD_LTE工作模式；
所述低频输入匹配网络，用于接入低频GSM信号或低频EDGE信号；
所述高频输入匹配网络，用于接入高频GSM信号、高频EDGE信号、TD_SCDMA信号或TDD_LTE信号。
其中较优地，所述控制电路向所述低频功率放大器或高频功率放大器发送的放大器控制信号包括：逻辑信号Vmode、偏置信号Reg和/或集电极电压Vcc。
其中较优地，所述低频功率放大器或高频功率放大器中设有反馈电路；所述逻辑信号Vmode，用于控制所述反馈电路上的反馈开关打开或闭合；
当所述逻辑信号Vmode控制所述反馈开关打开时，所述低频功率放大器或高频功率放大器工作在高增益模式下；
当所述逻辑信号Vmode控制所述反馈开关闭合时，所述低频功率放大器或高频功率放大器工作在低增益模式下。
其中较优地，所述集电极电压Vcc用于对所述低频功率放大器或高频功率放大器进行供电，以控制所述低频功率放大器或高频功率放大器放大后的低频射频信号或高频射频信号的输出功率；
所述控制电路，根据所述工作模式选择信号选择对应的基准电压，并根据所述基准电压生成所述集电极电压Vcc。
其中较优地，当所述工作模式选择信号为GSM模式时，所述控制电路选择所述基带信号Vramp作为所述基准电压，以生成所述集电极电压Vcc；
当所述工作模式选择信号为EDGE、TD_SCDMA或TDD_LTE模式时，所述控制电路选择参考电压Vref作为所述基准电压，以生成所述集电极电压Vcc；其中，所述参考电压Vref与所述控制电源Vbat呈线性变化。
其中较优地，所述偏置信号Reg，用于对所述低频功率放大器或高频功率放大器电流进行调整；
所述控制电路，根据所述工作模式选择信号闭合偏置信号开关组中对应的开关，以生成对应工作模式的偏置信号Reg；所述偏置信号开关组中设置有对应于各个工作模式的开关。
其中较优地，所述控制电路中包括有偏置信号生成电路；所述偏置信号生成电路，包括：运算放大器、P沟道金属氧化物半导体场效应晶体管(PMOS)以及所述偏置信号开关组；
所述运算放大器的正输入端接入参考电压Vref；所述运算放大器的输出端与P沟道金属氧化物半导体场效应晶体管(PMOS)的栅极相连；所述PMOS的源极接入所述控制电源Vbat；所述PMOS的漏极为偏置信号生成电路的输出端，用于输出所述偏置信号Reg；
所述偏置信号开关组接于所述运算放大器的负输入端与电阻之间；
在所述偏置信号开关组中的各个开关之间串接有电阻。
其中较优地，所述GSM、EDGE、TDD_LTE、TD_SCDMA工作模式下所对应的偏置信号Reg依序减小。
其中较优地，所述偏置信号Reg接入功率放大器的偏置电路；所述偏置电路包括R71、D71、D72和Q71双极晶体管的集电极；所述二极管D71、D72和电阻R71用于分压产生电压V71；所述电压V71经过压降产生电压V72；根据V72与V73实现对双极性晶体管Q72的电流控制；所述双极性晶体管Q72为功率放大器的功率放大管。
根据本发明实施例的第二方面，提供一种面向时分复用的多模功率放大器模组，包括低频功放通路、高频功放通路、控制电路和收发开关；
所述低频功放通路包括顺序串联的低频输入匹配网络、低频功率放大器和低频输出匹配网络；所述低频输入匹配网络用于接入低频射频信号，实现阻抗匹配；所述低频功率放大器用于实现对所述低频射频信号的放大；所述低频输出匹配网络用于实现低频的阻抗转换，以根据放大后的低频射频信号输出低频输出功率；
所述高频功放通路包括顺序串联的高频输入匹配网络、高频功率放大器和高频输出匹配网络；所述高频输入匹配网络用于接入高频射频信号，实现阻抗匹配；所述高频功率放大器用于实现对所述高频射频信号的放大；所述高频输出匹配网络用于实现高频的阻抗转换，以根据放大后的高频射频信号输出高频输出功率；
所述控制电路在时分复用的工作模式下，根据基带信号的大小，产生不同的偏置信号，用以偏置所述低频功率放大器或高频功率放大器对所接入的低频射频信号或高频射频信号进行放大；所述收发开关根据工作模式选择信号，选择对应的工作模式进行发射或接收。
其中较优地，所述时分复用的工作模式为TD_SCDMA和/或TDD_LTE工作模式。
其中较优地，在所述控制电路中，所述基带信号输入运算放大器的负输入端，所述运算放大器的输出端连接所述晶体管的栅极；
所述晶体管的源极接入控制电源，漏极输出所述偏置信号。
其中较优地，在所述控制电路中，所述基带信号和所述参考电压分别接入多路模拟开关的正输入端和负输入端，所述多路模拟开关的输
出端接入运算放大器的负输入端。
其中较优地，所述多路模拟开关至少有两个通路，通路的打开或关断由基带信号和工作模式决定。
其中较优地，在所述控制电路中，所述晶体管的漏极经过第一电阻和第二电阻串联接地，所述第一电阻和所述第二电阻的连接点连接所述运算放大器的正输入端。
其中较优地，在所述控制电路中，在相邻电阻的连接点与所述运算放大器的正输入端之间设置有选通开关，所述选通开关根据所述基带信号或工作模式改变通断状态。
其中较优地，在所述控制电路中，所述晶体管的漏极经过相互串联的多个电阻接地；相邻电阻的连接点连接所述运算放大器的正输入端。
其中较优地，所述低频功放通路至少有一级放大电路，所述高频功放通路至少有一级放大电路。
根据本发明实施例的第三方面，提供一种多模功率放大器模组的控制方法，包括如下步骤：
对低频功放通路提供偏置信号，其大小由基带信号的大小和工作模式决定；
对高频功放通路提供偏置信号，其大小由基带信号的大小和工作模式决定。
其中较优地，所述偏置信号由基带信号和工作模式控制，随基带信号呈线性或接近线性变化。
或者，所述偏置信号由基带信号和工作模式控制，随基带信号呈阶梯状变化。
或者，所述偏置信号由基带信号和工作模式控制，随基带信号呈台阶状线性变化。
根据本发明实施例的第四方面，提供一种具有多模功率放大器模组的芯片，所述芯片中包括有前述任意一种多模功率放大器模组。
根据本发明实施例的第五方面，提供一种具有多模功率放大器模组的通信终端，所述芯片中包括有前述任意一种多模功率放大器模组。
与现有技术相比较，本发明所提供的多模功率放大器模组、芯片及通信终端，根据通信协议中不同模式下的频段特点，对功放通路进行充
分的复用，使得高低频段的不同工作模式可以在控制电路的调整下共用功放通路，并在时分复用模式下让偏置电压或偏置电流随基带信号的变化而实现多个取值，从而简化了功率放大器模组的设计复杂度，降低了相关设计实现的成本。
图1是实施例示出的多模功率放大器模组的结构框图；
图2是实施例示出的多模功率放大器模组的电路图；
图3是实施例示出的根据逻辑信号控制功率放大器增益电路图示意图；
图4是实施例示出的集电极电压生成电路示意图；
图5是实施例示出的参考电压生成电路示意图；
图6是实施例示出的偏置信号生成电路示意图；
图7是实施例示出的偏置信号对功率放大器中的一级的电流调整电路示意图；
图8是根据基带信号控制功率放大器偏置信号的第一实施例示意图；
图9是第一实施例示出的偏置信号Reg和基带信号Vramp之间关系的示意图；
图10是根据基带信号控制功率放大器偏置信号的第二实施例示意图；
图11是第二实施例示出的偏置信号Reg和基带信号Vramp之间关系的示意图；
图12是根据基带信号控制功率放大器偏置信号的第三实施例示意图；
图13为第三实施例示出的偏置信号Reg和基带信号Vramp之间关系的示意图。
下面结合附图和具体实施例对本发明的技术内容做进一步的详细说明。
首先需要说明的是，在本发明的各个实施例中，所涉及的通信终端指可以在移动环境中使用，支持GSM、EDGE、TD_SCDMA、TDD_LTE、FDD_LTE
等多种通信制式的计算机设备，包括但不限于移动电话、笔记本电脑、平板电脑、车载电脑等。此外，该多模功率放大器模组也适用于其他多模技术应用的场合，例如兼容多种通信制式的通信基站等。
如本发明的背景技术所述，无论是三模还是五模方案都包括GSM/TD_SCDMA/TDD_LTE三种模式，又由于LTE网络覆盖的有限性，目前的三模/五模方案中，仍然要求兼容EDGE模式，其中高频GSM中PCS段的频率是1850MHz～1910MHz，TD_SCDMA的频段是1880MHz～1920MHz，2010MHz～2025MHz，TDD_LTE的B39频段是1880MHz～1920MHz，从频率上看这三个模式下的频率是比较接近的，另外GSM和EDGE的频段是完全重合的，这些为电路复用提供了可能性。功率放大器模组在不同模式下工作，对输出功率，增益，线性度和工作电流的要求是不一样的。而功率放大器模组的如上指标是由模组中的功率放大器决定，所以通过对功率放大器的增益网络、集电极电压和偏置电压(电流)在不同模式下的进行优化，可以实现输出功率、增益、电流和线性方面的优化。
图1是实施例示出的多模功率放大器模组的结构框图。如图1所示，该多模功率放大器模组，包括：低频功放通路、高频功放通路、控制电路和收发开关。这里的低频功放通路至少有一级放大电路，高频功放通路也至少有一级放大电路。
其中，该低频功放通路包括顺序串联的低频输入匹配网络、低频功率放大器和低频输出匹配网络。该低频输入匹配网络，设有低频输入端，用于接入低频射频信号，实现阻抗匹配。该低频功率放大器，接入低频输入匹配网络输出的低频射频信号，用于实现对低频射频信号的放大。该低频输出匹配网络，用于实现低频的阻抗转换，以根据放大后的低频射频信号输出低频输出功率。
该高频功放通路包括顺序串联的高频输入匹配网络、高频功率放大器和高频输出匹配网络。该高频输入匹配网络，设有高频输入端，用于接入高频射频信号，实现阻抗匹配。该高频功率放大器，接入高频输入匹配网络输出的高频射频信号，用于实现对高频射频信号的放大。该高频输出匹配网络，用于实现高频的阻抗转换，以根据放大后的高频射频信号输出高频输出功率。
该控制电路为该多模功率放大器模组的核心控制部件。该控制电路设有至少三个输入端，分别用于接入控制电源Vbat、基带信号Vramp和工作模式选择信号。控制电路分别与上述低频功率放大器和高频功率放大器相连，根据该基带信号Vramp和工作模式选择信号，向低频功率放大器或高频功率放大器发送放大器控制信号。通过该控制信号，以控制该低频功率放大器或高频功率放大器对所接入的低频射频信号或高频射频信号进行放大和优化。
收发开关与上述控制电路、低频输出匹配网络和高频输出匹配网络分别连接。该收发开关，用于根据工作模式选择信号，选择对应的工作模式进行发射或接收。
上述多模功率放大器模组，根据通信协议中不同模式下的频段特点，对功放通路进行充分的复用，使得高低频段的不同工作模式可以在控制电路的调整下共用功放通路，从而简化了功率放大器模组的设计复杂度，降低了相关设计实现的成本，并且具有简单灵活，易于实现等优点。
图2是实施例示出的多模功率放大器模组的电路图。如图2所示，本实施例所示出的多模功率放大器模组，设计工作在GSM(Global System for Mobile communication，全球移动通信系统)、EDGE(Enhanced Data Rate for GSM Evolution，增强型数据速率GSM演进技术)、TD_SCDMA(Time Division-Synchronous Code Division Multiple Access，时分同步码分多址)、TDD_LTE(Time Division Long Term Evolution，分时长期演进)模式下。基于前面的分析，GSM模式和EDGE模式中又分别包括高频模式和低频模式。因此，将该两种模式划分为低频GSM模式、高频GSM模式和低频EDGE模式和高频EDGE模式。
如图2所示，在本实施例中，该多模功率放大器模组的对外引脚包括：109为低频功放通路的低频输入端，用于接入低频GSM/EDGE射频信号。110为控制电路104的控制电源电源接入端，用于接入控制电源Vbat。111为TX_enble接口，用于为控制电路接入TX的使能信号。113/114/115为逻辑信号B0/B1/B2接口，用于为控制电路接入B0/B1/B2逻辑信号。该B0/B1/B2三个逻辑信号和TX的使能信号共同构成了该控制电路的工作模式选择信号，一起控制多模功率放大器模组进行工作模式的选择。112为控制电路的基带信号接口，用于接入基带信号Vramp。该基带信号
Vramp可以是0～1.8V的任意值。GSM模式开始工作时，通过设置不同的基带信号Vramp，可以调整多模功率放大器模组的输出功率。116为低频功放通路的高频输入端，用于接入GSM/EDGE/TD_SCDMA/TDD_LTE射频信号。117为收发开关，位于天线端。118/119/120/121/122/123，分别对应于TRX1、TRX2、TRX3、TRX4、TRX5和TRX6，它们是六个收发端口，可以用作发射端口也可以用作输出端口。
如图2所示，在本实施例中，该多模功率放大器模组包括：低频输入匹配网络101，用于接入低频GSM/EDGE射频信号，实现到50Ohm阻抗的匹配。低频功率放大器102，用于实现对所接入低频GSM/EDGE射频信号(824MHz～849MHz；880MHz～915MHz)的放大。低频输出匹配网络103，用于实现低频的阻抗转换，以输出所希望的输出功率。控制电路104，可以采用CMOS实现，这主要是从设计的灵活度和成本上考虑的。该控制电路104主要是根据基带信号Vramp和工作模式选择信号，为低频功率放大器103和高频功率放大器106提供放大器控制信号。该放大器控制信号包括：逻辑信号Vmode、偏置信号Reg和/或集电极电压Vcc。同时，该控制电路104也为收发开关108提供电源电压和逻辑电压。高频输入匹配网络105，用于接入高频GSM/EDGE信号、TD_SCDMA信号和TDD_LTE信号，以实现到50Ohm的匹配。高频功率放大器106，实现对所接入高频GSM/EDGE射频信号、TD_SCDMA信号和TDD_LTE信号(1710MHz～2025MHz)的放大。高频输出网络107，用于实现高频的阻抗转换，以输出所希望的输出功率。收发开关108，位于天线端，分别连接发射的输出和接收的输入。其中，图2所示实施例中收发开关108为SP8T。该收发开关也可以根据需要扩展为任意SPXT，一般在手机天线端应用，X不小于4。例如3模5频需要的SP8T，5模12频需要的是SP16T，也有些应用是SP10T，SP12T或SP14T的。
上述多模功率放大模组中的控制电路，根据基带信号Vramp和工作模式选择信号，为功率放大器提供放大器控制信号，以控制功率放大器进行放大调整。该多模功率放大器模组，正是根据通过这一方式，对功放通路进行充分的复用，使得高低频段的不同工作模式可以在控制电路的调整下共用功放通路的。这里的放大器控制信号包括：逻辑信号Vmode、偏置信号Reg和/或集电极电压Vcc。
下面通过几个实施例，具体说明控制电路是如何通过放大器控制信号对功率放大器进行放大调整的。
图3为根据逻辑信号控制功率放大器增益电路的示意图。图3中所示的功率放大器可以是低频功率放大器，也可以是高频功率放大器。如图3所示，该功率放大器的集电极由控制电路输出的集电极电压Vcc供电。功率放大器中设有反馈电路。在图3中，该功率放大器的反馈电路由相互串联的电容C30、C31和R30构成。控制电路输出的逻辑信号Vmode(例如，0或者Vbat)，用于控制反馈电路上的反馈开关打开或闭合。
当逻辑信号Vmode控制反馈开关打开时，该反馈电路处于断开工作状态，此时功率放大器由于没有反馈电路起作用，因此处于高增益模式下。一般在GSM工作模式下，系统要求功率放大器模组的输出功率最高，所以当控制电路处于该工作模式下时，即可输出逻辑信号Vmode以控制功率放大器工作在高增益模式下。
当逻辑信号Vmode控制所述反馈开关闭合时，该反馈电路处于导通工作状态，此时功率放大器由于有反馈电路起作用，因此处于低增益模式下。一般当EDGE/TD_SCDMA/TDD_LTE模式下，由于系统要求功率放大器模组的输出功率相对低，当控制电路处于该工作模式下时，即可输出逻辑信号Vmode以控制功率放大器工作在低增益模式下。
可见，在本实施例中，控制电路可以根据工作模式选择信号确定当前所处于的工作模式，进而确定功率放大器应该处于高增益模式或是低增益模式，从而向功率放大器输出对应的逻辑信号Vmode。
如前所述，控制电路输出的集电极电压Vcc用于作为集电极电压为对应的功率放大器供电，从而对功率放大器的输出功率进行调整。因此，控制电路根据当前工作模式的不同，对功率放大器输出不同的集电极电压Vcc，可以起到对功率放大器输出进行调整的作用。
图4是集电极电压生成电路示意图。该集电极电压生成电路位于控制电路中。控制电路根据所述工作模式选择信号确定当前处于的工作模式。根据当前所处于的工作模式选择对应的基准电压，以基于该基准电压生成集电极电压Vcc。
如图4所示，该集电极电压生成电路中设有运算放大器。该运算放大器的输出端与一个绝缘栅双极晶体管的栅极相连。该绝缘栅双极晶体
管的发射极接入控制电源Vbat。绝缘栅双极晶体管的集电极为集电极电压Vcc的输出端，用于输出集电极电压Vcc。在该运算放大器的负输入端与集电极电压Vcc的输出端之间设有电压R41。在该运算放大器的负输入端与接地之间设有电压R42。运算放大器的正输入端为基准电压输入端，用于输入控制电路所选择的基准电压。如图4所示，该基准电压输入端，通过不同的开关选择接入不同的基准电压。
当工作模式选择信号为GSM模式时，图4中GSM_enble开关闭合，控制电路选择基带信号Vramp作为基准电压，以生成集电极电压Vcc。其中，
通过基带不同的Vramp值得到不同的Vcc值，由于Vcc是功率放大器集电极的供电电压，输出功率P和Vcc存在如下的对应关系：
其中RL为功率放大器的负载，由输出匹配网络决定。因此，控制电路可以通过不同的基带信号Vramp来调整功率放大器的输出功率。
当工作模式选择信号为EDGE、TD_SCDMA或TDD_LTE模式时，图4中EDGE/TD_SCDMA/TDD_LTE_enble开关闭合，控制电路选择参考电压Vref作为基准电压，以生成集电极电压Vcc。此时，功率放大器模组处于线性工作模式，输出功率的改变是通过改变输入信号的变化来实现的。其中
通过选择合适的参考电压Vref，使得集电极电压Vcc＝Vbat-VDS，其中VDS为M41源漏级的饱和电压差，一般为0.15V～0.2V。
其中，Vref4由图5的电路原理图产生。在图5中，
VBE53为双极晶体管Q53基极到发射极的电压差，在硅工艺中一般为0.7V，n为Q52与Q51发射极面积之比，VT为热电压，为0.026V。
偏置信号Reg用于对功率放大器的电流进行调整。控制电路根据工
作模式选择信号控制闭合偏置信号开关组中对应的开关，以生成对应工作模式的偏置信号Reg。偏置信号开关组中设置有对应于各个工作模式的开关。该偏置信号可以是电压信号，也可以电流信号。
图6是偏置信号生成电路的示意图。该偏置信号生成电路位于控制电路中。控制电路根据工作模式选择信号确定当前所处的工作模式。根据当前所处的工作模式选择控制闭合偏置信号开关组中对应的开关，以生成对应工作模式的偏置信号Reg。
如图6所示，该偏置信号生成电路包括：运算放大器、PMOS管以及偏置信号开关组。
该运算放大器的正输入端接入参考电压Vref；参考电压Vref根据偏置信号Reg确定。在不同模式中需要不同的偏置信号Reg，所述Reg和Vref符合一定的公式；运算放大器的输出端与PMOS管的栅极相连。PMOS的源极接入控制电源Vbat。PMOS的漏极为偏置信号生成电路的输出端，用于输出偏置信号Reg。其中，参考电压Vref基于前述图5所示电路生成，在此不再赘述。
偏置信号开关组连接在运算放大器的负输入端与PMOS管的集电极之间。在偏置信号开关组中的各个开关之间串接有电阻。
如图6所示，该偏置信号开关组中设有：TDD_SCDMA_enble开关、TDD_LTE_enble开关、EDGE_enble开关、GSM_enble开关。依据图6所示，在各个开关之间分别串接有电阻R61、R62、R63、R64、R65。所述控制电路根据所述工作模式选择信号确定当前处于的工作模式。根据当前所处于的工作模式选择控制闭合偏置信号开关组中对应的开关。例如，当前处于TDD_LTE模式下时，则选择闭合TDD_LTE_enble开关，其他开关保持断开状态。基于此生成偏置信号Reg。
一般在GSM模式下，偏置信号Reg高些，EDGE/TD_SCDMA依次减小，而TDD_LTE模式下的偏置电压处于两者之间，主要是平衡功耗和线性。基于图6所给出的偏置信号生成电路，在GSM模式下
EDGE模式下
TDD_SCDMA模式下
TD_LTE模式下
可以看出，上述GSM、EDGE、TD_SCDMA、TDD_LTE工作模式下所对应的偏置信号Reg是依序减小的，这里所述的一般的设计，也包括TD_SDMA和TDD_LTE共用一个Reg，或是TDD_LTE的偏置信号大于TD_SCDMA的。
当然，偏置信号开关组中具体开关的设置，可以根据多模功率放大器模组所支持的具体工作模式类型而对应调整。但是，其基本的设计原理是一样的。本领域一般技术人员，基于本实施例所给出的技术启示，对该偏置信号开关组所做任何调整，均应视为在本发明的保护范围之内。
该偏置信号通过图7所示电路实现对功率放大器电流的调整。图7为偏置信号控制功率放大器中的一级的电路原理图。实际设计中，功率放大器可以是两级或三级，每一级都可以用图7中偏置电路部分进行控制。图7中，
RD2为二极管D1和D2的导通电阻，选定二极管D1和D2后，该RD1，RD2为定值。
V72＝V71-VBEQ71，V73＝VBEQ72，
其中VBEQ71，VBEQ72为异质结双极晶体管(HBT)Q71、Q72基极与发射极的电压差，以砷化镓HBT为例，VBE＝1.3V。IBQ72为Q72异质结双极晶体管的基极电流，β为放大倍数，一般从60～160不等主要取决于异质结双极晶体管的工艺制成。
如上所述，偏置信号Reg接入功率放大器的偏置电路，偏置电路包括R71、D71、D72和Q71双极晶体管的集电极，其中二极管D71、D72和
R71分压产生V71，V71经过一个VBE压降，产生了V72、V72与V73的压差决定了通过R72的电流即Q72双极性晶体管的基极电流，从而实现了对Q72的电流控制，这里的Q72为功率放大器的功率放大管。其中Q71的集电极也可以直接连接Vbat。
另一方面，在TD_SCDMA和TDD_LTE这两种时分复用模式下，功率放大器应该始终处于线性功率放大状态。当多模功率放大器模组输出功率比较高的情况下，为了保证一定的线性度，功率放大器所需要的偏置电流相对大一些。在这种情况下，需要控制电路提供的偏置信号Reg也相对大一些，这样就实现了多模功率放大器模组性能的优化。而当多模功率放大器模组输出功率比较低时，这时功率放大器只需要相对低的偏置电流即可以实现足够的线性度。在这种情况下，如果控制电路提供的偏置信号Reg相对小一些，功率放大器所需要的偏置电流就可以降下来，从而实现多模功率放大器模组降低功耗的目的。
如前文所述，多模功率放大模组中的控制电路根据基带信号和工作模式选择信号，为功率放大器提供放大器控制信号，以控制功率放大器进行放大调整。这里的放大器控制信号包括但不限于：逻辑信号Vmode、偏置信号Reg和/或集电极电压Vcc。在现有的TD_SCDMA和TDD_LTE这两种时分复用模式下，基带信号Vramp作为一个逻辑电平参与这两种时分复用模式的选择，要么是高电平，要么是低电平。所以，这两种时分复用模式下的偏置电压或偏置电流也只有一种取值，不能根据多模功率放大器模组的输出功率进行调节。
本发明所提供的其它实施例突破了上述技术的局限性，创造性地提出在时分复用模式下让偏置电压或偏置电流随基带信号Vramp的变化而实现多个取值。为描述统一起见，上述的偏置电压或偏置电流统称为偏置信号Reg，即在需要采用电压信号作为偏置信号的场合，偏置信号Reg为偏置电压；在需要采用电流信号作为偏置信号的场合，偏置信号Reg为偏置电流。上述偏置电压或偏置电流的变化，会引起功率放大器的输出电流发生变化，从而实现整个多模功率放大器模组性能和功耗的优化。
下面通过另外几个实施例，具体说明控制电路怎样通过基带信号Vramp实现对功率放大器的偏置信号Reg的调整。
图8为根据基带信号控制功率放大器偏置信号的第一实施例示意图。在第一实施例中，基带信号Vramp输入运算放大器的负输入端(也称反相输入端)，该运算放大器的输出端与一个绝缘栅双极晶体管的栅极相连。绝缘栅双极晶体管的源极接入控制电源Vbat。绝缘栅双极晶体管的漏极为偏置信号Reg的输出端，用于输出偏置信号。绝缘栅双极晶体管的漏极经过电阻R21和R22接地。电阻R21和R22的连接点直接连接运算放大器的正输入端(也称同相输入端)。
如图9所示，在TD_SCDMA和TDD_LTE这两种时分复用模式下，利用基带信号Vramp，使偏置信号Reg和基带信号Vramp满足一定的线性函数关系，例如Reg＝G*Vramp或者Reg＝G*(Vramp+Voffset)，其中参数G是固定值。这里的偏置信号Reg既可以是个电压信号，也可以是个电流信号。根据基带信号Vramp的值，以及设计优化所需要的偏置电压或偏置电流值，可以得到相应的参数G。在图8所示的第一实施例中，可以得出如下公式：
换句话说，通过选择电阻R21和R22的合适阻值，可以得到用户所需要的参数G。
图10为根据基带信号控制功率放大器偏置信号的第二实施例示意图。在第二实施例中，大部分电路的连接方式与第一实施例基本相同，不同之处主要在于绝缘栅双极晶体管的漏极输出部分。在第二实施例中，绝缘栅双极晶体管的集电极经过电阻R31、R32、R33和R34接地。其中，电阻R31与R32的连接点与运算放大器的正输入端之间设置一个选通开关，该选通开关在Vramp<A时导通，其余时间关断；电阻R32与R33的连接点与运算放大器的正输入端之间设置一个选通开关，该选通开关在A<Vramp<B时导通，其余时间关断；电阻R33与R34的连接点与运算放大器的正输入端之间设置一个选通开关，该选通开关在Vramp>B时导通，其余时间关断。这里，A和B为某个特定阈值电压。
基于图10所示的第二实施例电路图，可以使偏置信号Reg和基带信号Vramp之间呈现图11所示的阶梯状线性关系。在图11所示的实施例中，以阶梯状分为三段为例，偏置信号Reg可以随基带信号Vramp
的不同值，设定为几个固定的值。即，当Vramp<A时，Reg＝V1；当A<Vramp<B时，Reg＝V2；当Vramp>B时，Reg＝V3。进一步地，当Vramp<A时，
当A<Vramp<B，
当Vramp>B，
这里的V1<V2<V3。在实际的实施过程中，V1、V2、V3之间的大小关系的取值由该设计的性能要求决定，取值可以为零。
图12为根据基带信号控制功率放大器偏置信号的第三实施例示意图。在第三实施例中，大部分电路的连接方式与第二实施例基本相同，不同之处主要在于基带信号Vramp和参考电压Vref41分别接入多路模拟开关(MUX)的正输入端和负输入端，多路模拟开关的输出端信号Vref42取代原有的基带信号Vramp接入运算放大器的负输入端。上述多路模拟开关至少有两个通路，通路的打开或关断由基带信号和工作模式决定。在第三实施例中，绝缘栅双极晶体管的集电极经过电阻R41、R42、R43和R44接地。其中，电阻R41与R42的连接点与运算放大器的正输入端之间设置一个选通开关，该选通开关在Vramp<A时导通，其余时间关断；电阻R42与R43的连接点与运算放大器的正输入端之间设置一个选通开关，该选通开关在A<Vramp<B时导通，其余时间关断；电阻R43与R44的连接点与运算放大器的正输入端之间设置一个选通开关，该选通开关在Vramp>B时导通，其余时间关断。这里，A和B为某个特定阈值电压。
基于图12所示的第三实施例电路图，可以使偏置信号Reg和基带信号Vramp之间呈现图13所示的台阶状线性关系。在图13所示的实施例中，以台阶状分为三段为例，偏置信号Reg可以随基带信号Vramp的不同值，设定为几个固定的值。即，当基带信号Vramp<A时，偏置信号Reg为一个固定电压值V4；当A<Vramp<B，偏置信号Reg＝V5＝G*Vramp；当基带信号Vramp>B，偏置信号Reg也为一个固定电压值，
Reg＝V6。进一步地，当基带信号Vramp<A时，多路模拟开关改变其输出为Vref4＝Vref，
A<Vramp<B，多路模拟开关改变其输出为Vref4＝Vramp，
当基带信号Vramp>B时，多路模拟开关改变其输出为Vref42＝Vref41， 
需要说明的是，如果在晶体管的漏极与地之间设置更多的电阻，同时设置更多的选通开关，可以使基带信号Vramp和偏置信号Reg之间的阶梯状线性关系变得更加复杂多样，从而满足各种不同应用场景的实际需求。这里的晶体管包括但不限于绝缘栅双极晶体管、场效应晶体管或三极管。相应的电路调整是本领域普通技术人员都能掌握的常规技术手段，并不超出本发明所提供的技术启示，在此就不赘述了。
另一方面，TD_SCDMA和TDD_LTE虽然同样属于时分复用的工作模式，但它们对偏置信号Reg的要求还是有所区别的，因此在TD_SCDMA和TDD_LTE模式下，可以通过设置不同的基带信号Vramp实现工作性能的进一步优化。
在上述多模功率放大器模组的不同实施例基础上，可以进一步总结出本发明提供的多模功率放大器模组输出控制方法。它包括如下步骤：对低频功放通路提供偏置信号，其大小由基带信号的大小和工作模式决定；对高频功放通路提供偏置信号，其大小由基带信号的大小和工作模式决定。其中，偏置信号由基带信号和工作模式控制，随基带信号呈线性或非常接近线性的变化。或者，偏置信号由基带信号和工作模式控制，随基带信号呈阶梯状变化。或者，偏置信号由基带信号和工作模式控制，随基带信号呈台阶状线性变化。
上述实施例中所示出的多模功率放大器模组可以被用在芯片中。对该芯片中的多模功率放大器模组结构，在此就不再一一详述了。
另外，上述多模功率放大器模组还可以被用在通信终端中，作为
射频电路的重要组成部分。这里所说的通信终端指可以在移动环境中使用、支持GSM、EDGE、TD_SCDMA、TDD_LTE、FDD_LTE等多种通信模式的计算机设备，包括但不限于移动电话、笔记本电脑、平板电脑、车载电脑等。此外，该多模功率放大器模组也适用于其他多模技术应用的场合，例如兼容多种通信模式的通信基站等，在此就不一一详述了。
上面对本发明所提供的多模功率放大器模组、芯片及通信终端进行了详细的说明。对本领域的一般技术人员而言，在不背离本发明实质精神的前提下对它所做的任何显而易见的改动，都将构成对本发明专利权的侵犯，将承担相应的法律责任。
Claims (26)
- 一种多模功率放大器模组，其特征在于包括低频功放通路、高频功放通路、控制电路和收发开关；所述低频功放通路，包括顺序串联的低频输入匹配网络、低频功率放大器和低频输出匹配网络；所述低频输入匹配网络，用于接入低频射频信号，实现阻抗匹配；所述低频功率放大器，用于实现对所述低频射频信号的放大；所述低频输出匹配网络，用于实现低频的阻抗转换，以根据放大后的低频射频信号输出低频输出功率；所述高频功放通路，包括顺序串联的高频输入匹配网络、高频功率放大器和高频输出匹配网络；所述高频输入匹配网络，用于接入高频射频信号，实现阻抗匹配；所述高频功率放大器，用于实现对所述高频射频信号的放大；所述高频输出匹配网络，用于实现高频的阻抗转换，以根据放大后的高频射频信号输出高频输出功率；所述控制电路，接入供电电源Vbat、基带信号Vramp和工作模式选择信号；所述控制电路，根据所述基带信号Vramp和工作模式选择信号，向所述低频功率放大器或高频功率放大器发送放大器控制信号，以控制所述低频功率放大器或高频功率放大器对所接入的低频射频信号或高频射频信号进行放大；所述收发开关，与所述控制电路、低频输出匹配网络和高频输出匹配网络分别连接；所述收发开关，用于根据所述工作模式选择信号，选择对应的工作模式进行发射或接收。
- 如权利要求1所述的多模功率放大器模组，其特征在于：所述多模功率放大器模组支持GSM、EDGE、TD_SCDMA和/或TDD_LTE工作模式；所述低频输入匹配网络，用于接入低频GSM信号或低频EDGE信号；所述高频输入匹配网络，用于接入高频GSM信号、高频EDGE信号、TD_SCDMA信号或TDD_LTE信号。
- 如权利要求1所述的多模功率放大器模组，其特征在于：所述控制电路向所述低频功率放大器或高频功率放大器发送的放大器控制信号包括：逻辑信号Vmode、偏置信号Reg和/或集电极电压Vcc。
- 如权利要求3所述的多模功率放大器模组，其特征在于：所述低频功率放大器或高频功率放大器中设有反馈电路；所述逻辑信号Vmode，用于控制所述反馈电路上的反馈开关打开或闭合；当所述逻辑信号Vmode控制所述反馈开关打开时，所述低频功率放大器或高频功率放大器工作在高增益模式下；当所述逻辑信号Vmode控制所述反馈开关闭合时，所述低频功率放大器或高频功率放大器工作在低增益模式下。
- 如权利要求3所述的多模功率放大器模组，其特征在于：所述集电极电压Vcc用于对所述低频功率放大器或高频功率放大器进行供电，以控制所述低频功率放大器或高频功率放大器放大后的低频射频信号或高频射频信号的输出功率；所述控制电路，根据所述工作模式选择信号选择对应的基准电压，并根据所述基准电压生成所述集电极电压Vcc。
- 如权利要求5所述的多模功率放大器模组，其特征在于：当所述工作模式选择信号为GSM模式时，所述控制电路选择所述基带信号Vramp作为所述基准电压，以生成所述集电极电压Vcc；当所述工作模式选择信号为EDGE、TD_SCDMA或TDD_LTE模式时，所述控制电路选择参考电压Vref作为所述基准电压，以生成所述集电极电压Vcc；其中，所述参考电压Vref根据所述偏置信号Reg确定。
- 如权利要求3所述的多模功率放大器模组，其特征在于：所述偏置信号LB_Reg、HB_Reg，用于对所述低频功率放大器或高频功率放大器电流进行调整；所述控制电路，根据所述工作模式选择信号闭合偏置信号开关组中对应的开关，以生成对应工作模式的偏置信号Reg；所述偏置信号开关组中设置有对应于各个工作模式的开关。
- 如权利要求7所述的多模功率放大器模组，其特征在于：所述控制电路中包括有偏置信号生成电路；所述偏置信号生成电路，包括：运算放大器、P沟道金属半导体绝缘场效应晶体管(PMOS)以及所述偏置信号开关组；所述运算放大器的正输入端接入参考电压Vref；所述参考电压Vref根据所述偏置信号Reg确定；所述运算放大器的输出端与所述PMOS场效 应晶体管的栅极相连；所述PMOS场效应晶体管的源极接入所述控制电源Vbat；所述PMOS场效应晶体管的漏极为偏置信号生成电路的输出端，用于输出所述偏置信号Reg；所述偏置信号开关组接于所述运算放大器的负输入端与所述绝缘栅双极晶体管的集电极之间；在所述偏置信号开关组中的各个开关之间串接有电阻。
- 如权利要求2或7所述的多模功率放大器模组，其特征在于：所述GSM、EDGE、TDD_LTE、TD_SCDMA工作模式下所对应的偏置信号Reg依序减小。
- 如权利要求7所述的多模功率放大器模组，其特征在于：所述偏置信号Reg接入功率放大器的偏置电路；所述偏置电路包括R71、D71、D72和Q71双极晶体管的集电极；所述二极管D71、D72和电阻R71用于分压产生电压V71；所述电压V71经过压降产生电压V72；根据V72与V73实现对双极性晶体管Q72的电流控制；所述双极性晶体管Q72为功率放大器的功率放大管。
- 一种面向时分复用的多模功率放大器模组，其特征在于包括低频功放通路、高频功放通路、控制电路和收发开关；所述低频功放通路包括顺序串联的低频输入匹配网络、低频功率放大器和低频输出匹配网络；所述低频输入匹配网络用于接入低频射频信号，实现阻抗匹配；所述低频功率放大器用于实现对所述低频射频信号的放大；所述低频输出匹配网络用于实现低频的阻抗转换，以根据放大后的低频射频信号输出低频输出功率；所述高频功放通路包括顺序串联的高频输入匹配网络、高频功率放大器和高频输出匹配网络；所述高频输入匹配网络用于接入高频射频信号，实现阻抗匹配；所述高频功率放大器用于实现对所述高频射频信号的放大；所述高频输出匹配网络用于实现高频的阻抗转换，以根据放大后的高频射频信号输出高频输出功率；所述控制电路在时分复用的工作模式下，根据基带信号的大小，产生不同的偏置信号，用以偏置所述低频功率放大器或高频功率放大器对所接入的低频射频信号或高频射频信号进行放大；所述收发开关根据工作模式选择信号，选择对应的工作模式进行发射或接收。
- 如权利要求11所述的多模功率放大器模组，其特征在于：所述时分复用的工作模式为TD_SCDMA和/或TDD_LTE工作模式。
- 如权利要求11或12所述的多模功率放大器模组，其特征在于：在所述控制电路中，所述基带信号输入运算放大器的负输入端，所述运算放大器的输出端连接所述晶体管的栅极；所述晶体管的源极接入控制电源，漏极输出所述偏置信号。
- 如权利要求11或12所述的多模功率放大器模组，其特征在于：在所述控制电路中，所述基带信号和所述参考电压分别接入多路模拟开关的正输入端和负输入端，所述多路模拟开关的输出端接入运算放大器的负输入端。
- 如权利要求14所述的所述的多模功率放大器模组，其特征在于：所述多路模拟开关至少有两个通路，通路的打开或关断由基带信号和工作模式决定。
- 如权利要求13或14所述的多模功率放大器模组，其特征在于：在所述控制电路中，所述晶体管的漏极经过第一电阻和第二电阻串联接地，所述第一电阻和所述第二电阻的连接点连接所述运算放大器的正输入端。
- 如权利要求16所述的多模功率放大器模组，其特征在于：在所述控制电路中，在相邻电阻的连接点与所述运算放大器的正输入端之间设置有选通开关，所述选通开关根据所述基带信号或工作模式改变通断状态。
- 如权利要求13所述的多模功率放大器模组，其特征在于：在所述控制电路中，所述晶体管的漏极经过相互串联的多个电阻接地；相邻电阻的连接点连接所述运算放大器的正输入端。
- 如权利要求11所述的多模功率放大器模组，其特征在于：所述低频功放通路至少有一级放大电路，所述高频功放通路至少有一级放大电路。
- 如权利要求1～19中任意一项所述的多模功率放大器模组，其特征在于：所述收发开关位于天线端；所述收发开关为SPXT，其中X不小于4。
- 一种权利要求1～20中任意一项所述的多模功率放大器模组的 控制方法，其特征在于包括如下步骤：对低频功放通路提供偏置信号，其大小由基带信号的大小和工作模式决定；对高频功放通路提供偏置信号，其大小由基带信号的大小和工作模式决定。
- 如权利要求21所述的控制方法，其特征在于：所述偏置信号由基带信号和工作模式控制，随基带信号呈线性或接近线性变化。
- 如权利要求21所述的控制方法，其特征在于：所述偏置信号由基带信号和工作模式控制，随基带信号呈阶梯状变化。
- 如权利要求21所述的控制方法，其特征在于：所述偏置信号由基带信号和工作模式控制，随基带信号呈台阶状线性变化。
- 一种具有多模功率放大器模组的芯片，其特征在于：所述芯片中包括有权利要求1～20中任意一种多模功率放大器模组。
- 一种具有多模功率放大器模组的通信终端，其特征在于：所述通信终端中包括有权利要求1～20中任意一种多模功率放大器模组。
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| EP16870015.1A EP3386101A4 (en) | 2015-12-01 | 2016-12-01 | MULTIMODAL POWER AMPLIFIER MODULE, CHIP AND COMMUNICATION TERMINAL |
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| CN110311693A (zh) * | 2019-08-01 | 2019-10-08 | 江西联智集成电路有限公司 | 一种功率放大器芯片及无线电发射器 |
| CN111294214B (zh) * | 2020-01-21 | 2021-09-14 | Oppo广东移动通信有限公司 | 供电方法及相关产品 |
| CN111313853B (zh) * | 2020-04-09 | 2023-07-21 | 西安芯辉光电科技有限公司 | 一种双模式多通道跨阻放大器 |
| CN113676193B (zh) * | 2021-08-12 | 2022-11-11 | Oppo广东移动通信有限公司 | 发射模组、射频系统及通信设备 |
| CN114978074B (zh) * | 2022-07-25 | 2022-11-11 | 成都嘉纳海威科技有限责任公司 | 一种三通道收发放大芯片 |
| CN115425993B (zh) * | 2022-09-01 | 2024-08-02 | Oppo广东移动通信有限公司 | 多模多频功率放大器件、切换方法、射频前端装置和设备 |
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Also Published As
| Publication number | Publication date |
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| EP4293900A2 (en) | 2023-12-20 |
| US10637407B2 (en) | 2020-04-28 |
| EP4293900A3 (en) | 2024-03-27 |
| EP3386101A4 (en) | 2019-07-03 |
| US20180375479A1 (en) | 2018-12-27 |
| EP3386101A1 (en) | 2018-10-10 |
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