WO2017092459A1 - 片上系统soc的监控方法、装置和计算机存储介质 - Google Patents

片上系统soc的监控方法、装置和计算机存储介质 Download PDF

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Publication number
WO2017092459A1
WO2017092459A1 PCT/CN2016/098040 CN2016098040W WO2017092459A1 WO 2017092459 A1 WO2017092459 A1 WO 2017092459A1 CN 2016098040 W CN2016098040 W CN 2016098040W WO 2017092459 A1 WO2017092459 A1 WO 2017092459A1
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Prior art keywords
monitoring
node
bus
module
soc
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PCT/CN2016/098040
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English (en)
French (fr)
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邹飞
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深圳市中兴微电子技术有限公司
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Publication of WO2017092459A1 publication Critical patent/WO2017092459A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3027—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038—System on Chip

Definitions

  • the present invention relates to the field of electronic technologies, and in particular, to a system, a system, and a computer storage medium for monitoring a system on chip (SOC).
  • SOC system on chip
  • bus (Bus) in the SOC is the transmission hub of all interconnected structures in the SOC, which is connected to the central processing unit (CPU), digital signal processor (DSP), direct memory in the SOC. Direct Memory Access (DMA), various hardware accelerators, various memories, and various peripheral interfaces, so the correct bus status directly affects the stability of the SOC.
  • CPU central processing unit
  • DSP digital signal processor
  • DMA Direct Memory Access
  • various hardware accelerators various memories
  • peripheral interfaces so the correct bus status directly affects the stability of the SOC.
  • embodiments of the present invention are directed to a method, apparatus, and computer storage medium for monitoring a system-on-chip SOC to simply and efficiently locate a device having a bus access abnormality within the SOC.
  • the embodiment of the invention discloses a method for monitoring the SOC of a system on a chip, the method comprising:
  • the node monitoring module monitors bus access behavior of the monitored node in the SOC, and obtains bus monitoring information of the monitored node;
  • the embodiment of the invention further discloses a monitoring device for a system-on-chip SOC, the device comprising:
  • At least one node monitoring module configured to monitor bus access behavior of the monitored node in the SOC, obtain bus monitoring information of the monitored node, and send the bus monitoring information to a monitoring main control module connected to the node monitoring module .
  • the embodiment of the invention further discloses a monitoring device for a system-on-chip SOC, the device comprising: a monitoring main control module and at least one node monitoring module;
  • the monitoring main control module is connected in series with the node monitoring module, and the first bus interface of the node monitoring module is connected with a bus interface of the monitored node in the SOC, and the second bus interface of the node monitoring module and the SOC a bus connection; when a plurality of the node monitoring modules are included, the node monitoring module and the monitoring main control module are connected in series: a plurality of the node monitoring modules are connected in series to each other to form a node monitoring module serial circuit.
  • the node monitoring module serial circuit is connected in series with the monitoring main control module.
  • the embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the foregoing method for monitoring the system SOC of the system.
  • the node monitoring module monitors the bus access behavior of the monitored node in the SOC, and obtains the bus monitoring information of the monitored node; the node monitoring module monitors the bus The information is sent to the monitoring main control module. In this way, the bus monitoring information can be obtained. If a bus access abnormality occurs, the information can be monitored through the bus, so that the location of the abnormal point that causes the bus access abnormality can be located. In this way, the device with the bus access abnormality in the SOC can be located simply and effectively, which helps to fundamentally solve the bus access abnormality of the SOC.
  • FIG. 1 is a schematic flowchart of a method for monitoring an SOC of a system on a chip according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a device for monitoring an SOC of a system on a chip according to an embodiment of the present invention
  • 3A is a schematic structural diagram of another apparatus for monitoring a SOC of a system on a chip according to an embodiment of the present invention
  • FIG. 3B is a schematic structural diagram of another embodiment of a monitoring device for a system-on-chip SOC according to the present invention.
  • FIG. 4 is a schematic structural diagram of a node monitoring module 201 in another embodiment of a device for monitoring a SOC of a system on chip provided by the present invention
  • FIG. 5 is a schematic structural diagram of a monitoring main control module 202 in another embodiment of a device for monitoring a SOC of a system on chip provided by the present invention
  • FIG. 6 is a schematic flowchart diagram of a first embodiment of a method for monitoring a SOC of a system on a chip according to the present invention
  • FIG. 7 is a schematic flowchart diagram of a second embodiment of a method for monitoring an SOC of a system on a chip according to the present invention.
  • FIG. 8 is a flow chart of a method for monitoring SOC of a system on chip according to a third embodiment of the present invention Schematic diagram.
  • the node monitoring module monitors the bus access behavior of the monitored node in the SOC, and obtains the bus monitoring information of the monitored node; the node monitoring module sends the bus monitoring information to the monitoring main control module connected to the node monitoring module.
  • the monitoring main control module or the device connected to the monitoring main control module can locate the abnormally monitored node by analyzing the bus monitoring information when the bus abnormality is found, thereby completing the abnormality of the bus abnormality. Positioning is convenient for subsequent troubleshooting based on abnormal positioning.
  • the bus monitoring information may include identification information of the monitored node. Convenient for subsequent abnormal positioning.
  • the bus monitoring information may not include the identification information of the monitored node, and may be other information that can uniquely identify the monitored node.
  • the node monitoring module may The bus monitoring information and the identification information of the node monitoring module are used as the bus monitoring result of the monitored node, and are sent to the monitoring main control module through the serial communication link established by the node monitoring module and the monitoring main control module.
  • the bus monitoring information may be data indicating that the access behavior of the monitored node is normal, such as behavior parameters and/or state parameters that indicate the access behavior of the monitored node.
  • the behavior parameters may include behavior types, behavior parameters carried by each behavior type.
  • the status parameter may be a parameter such as whether the access is successful.
  • FIG. 1 is a schematic flowchart of a method for monitoring an SOC of a system on a chip according to an embodiment of the present invention. As shown in FIG. 1 , the method includes:
  • Step 101 The node monitoring module monitors the bus access behavior of the monitored node in the SOC, and obtains The bus monitoring information of the monitored node.
  • the step may include: each node monitoring module receives bus access related information of the monitored node corresponding to the SOC; and each node monitoring module determines, according to the received bus access related information, the monitored node corresponding thereto Whether the bus access behavior is abnormal; each node monitoring module uses the bus access related information and the bus access behavior as the abnormal judgment result as the bus monitoring information of the corresponding monitored node.
  • the monitored node in the SOC may include a CPU, a DSP, a DMA, various hardware accelerators, various memories, and various peripheral interfaces in the SOC.
  • the node monitoring module receives the bus access related information of the monitored node in the SOC, and may include: each node monitoring module receives, the monitored node in the SOC monitored by itself passes the bus to the SOC. Relevant information sent by other nodes; or, each node monitoring module receives relevant information sent by other nodes in the SOC to the monitored node in the SOC monitored by itself through the bus.
  • the related information may include read/write commands and address information or corresponding data packets.
  • the implementation manner of the node monitoring module receiving the bus access related information of the monitored node in the SOC may be: one end of the node monitoring module is connected to the bus interface of the monitored node, and the node monitoring module is another One end is connected to the bus in the SOC.
  • the each node monitoring module determines, according to the received bus access related information, whether the bus access behavior of the monitored node corresponding thereto is abnormal, and may include: receiving, by the node monitoring module, the monitored node of the monitored node that is monitored by itself / When writing the command and address information or the corresponding data packet, the node monitoring module starts its internal timer to start timing, and sets the handshake signal information to be empty; when the timer counts up to the predetermined time and stops timing, the node monitoring module judges Whether there is a handshake signal of the monitored node that has received its own monitoring; when receiving the handshake signal, the node monitoring module determines that the current bus access behavior of the monitored node monitored by itself is normal, and sets the handshake signal information of the monitored node.
  • the node monitoring mode determines that the current bus access behavior of the monitored node monitored by itself is abnormal, and the handshake signal information of the monitored node is set to be abnormal; the node monitoring module uses the handshake signal information as whether the current bus access behavior of the monitored node is abnormal. critical result. It should be noted that the predetermined time may be set according to the time interval of issuance of the handshake signal specified in the bus protocol.
  • each node monitoring module uses the bus access related information, and the bus access behavior is an abnormal judgment result as the bus monitoring information of the corresponding monitored node, and may be received by each node monitoring module.
  • the bus access related information of the monitored node monitored by itself and the current bus access behavior of the monitored node monitored by itself are abnormal judgment results, and the current bus monitoring information of the monitored node as its own monitoring is stored in the node monitoring module. Inside the register.
  • Step 102 The node monitoring module uses the bus monitoring information and its own identification information as the bus monitoring result of the monitored node, and sends the serial communication link established by the node monitoring module and the monitoring main control module to the monitoring main control module.
  • the step may include: each node monitoring module uses the bus monitoring information obtained by the self monitoring and the own identification information as a bus monitoring result of the monitored node that is monitored by itself; each first node monitoring module obtains its own monitoring. Bus monitoring result, and the bus monitoring result received from the first node monitoring module of the first level, is sent to the next node first node monitoring module; the second node monitoring module monitors the obtained bus monitoring result, and The bus monitoring result received from the first node monitoring module of the upper level is sent to the monitoring main control module; wherein the first node monitoring module refers to a node monitoring module in which the next level node connected in series is a node monitoring module; The second node monitoring module refers to a node monitoring module in which the next-level node connected in series is a monitoring main control module.
  • the monitoring main control module can know which monitored node in the SOC is the monitored device according to the bus monitoring result of each monitored node in the received SOC, and the bus access abnormality problem occurs, so that the simple and effective positioning can be realized.
  • a device with a bus access exception in the SOC is helpful to fundamentally solve the problem of bus access abnormality of the SOC.
  • the identifier information of the node monitoring module itself may uniquely identify each node monitoring module, that is, an identity identification (ID) is set for each node monitoring module, and the ID of each node monitoring module is not the same.
  • ID identity identification
  • each of the first node monitoring modules sends the bus monitoring result obtained by the self monitoring and the bus monitoring result received by the first node monitoring module of the previous level to the next node for monitoring.
  • the module may include: each first node monitoring module sends a bus monitoring result of the monitored node monitored by itself to a next-level first node monitoring module connected in series; each first node monitoring module receives the previous one connected in series The first node monitoring module sends the bus monitoring result; the first node monitoring module parses the received bus monitoring result; the first node monitoring module determines whether the parsed bus monitoring result includes its own identification information; When the identification information of the first node is sent, the first node monitoring module sends the received bus monitoring result to the next-level first node monitoring module connected in series, otherwise the bus monitoring result is not sent.
  • the second node monitoring module sends the bus monitoring result obtained by the self monitoring and the bus monitoring result received from the first node monitoring module of the upper level to the monitoring main control module, which may include, The two-node monitoring module sends the bus monitoring result of the monitored node monitored by itself to the monitoring main control module connected in series; the second node monitoring module receives the bus monitoring result sent by the first-level first node monitoring module connected in series with the second node; The node monitoring module parses the received bus monitoring result; the second node monitoring module determines whether the parsed bus monitoring result includes its own identification information; when the identity information is not included, the second node monitoring module receives the The bus monitoring result is sent to the monitoring main control module connected in series, otherwise the bus monitoring result is not sent.
  • the implementation manner of the serial communication link may be that the monitoring main control module, each of the first node monitoring module, and the second node monitoring module have a sending (Tx) interface and a receiving (Rx) interface. Each Rx interface is connected in series with the Tx interface of the upper level, thereby establishing a ring serial communication by monitoring the main control module, each first node monitoring module and the second node monitoring module. link.
  • the node monitoring module sends the bus monitoring result to the monitoring main control module through the serial communication link established by the node monitoring module and the monitoring main control module, and may be implemented in mode one or mode two.
  • the node monitoring module sends the bus monitoring result to the monitoring main control module through the serial communication link established by the node monitoring module and the monitoring main control module, and the monitoring module of each node is based on the monitoring main control module.
  • the obtaining instruction determines whether the bus monitoring result of the monitored node that is monitored by itself is sent to the monitoring main control module through the serial communication link established by each node monitoring module and the monitoring main control module.
  • each node monitoring module determines, according to the acquisition instruction of the monitoring main control module, whether to pass the serial communication link established by each node monitoring module and the monitoring main control module, and the monitored node of the monitoring node that is monitored by itself
  • the bus monitoring result is sent to the monitoring main control module, and the node monitoring module receives the acquiring instruction of the monitoring main control module; when receiving the obtaining instruction, the node monitoring module parses the obtaining instruction; and the node monitoring module determines whether the parsed obtaining instruction is Including the identification information of the self; the node monitoring module sends the acquisition instruction to the next-level node monitoring module connected in series with the identification information; when the self-identification information is included, the node monitoring module passes the monitoring module of each node.
  • the serial communication link established with the monitoring main control module transmits the bus monitoring result of the monitored node that is monitored by itself to the monitoring main control module.
  • the node monitoring module sends the bus monitoring result to the monitoring main control module through the serial communication link established by the node monitoring module and the monitoring main control module, and each node monitoring module passes each node monitoring module.
  • the serial communication link established with the monitoring main control module automatically sends the bus monitoring result of the monitored node monitored by itself to the monitoring main control module.
  • each of the node monitoring modules automatically sends the monitored bus monitoring result of the monitored node to the monitoring main control module through a serial communication link established by each node monitoring module and the monitoring main control module, which may include , the node monitoring module detects whether it is receiving the previous one
  • the node monitoring module detects whether it is sending information to the monitoring module of the next level node; when the information sent by the monitoring module of the upper level node is not received, and the information is not sent to the monitoring module of the next level node
  • the node monitoring module sends the bus monitoring result to the monitoring main control module through the serial communication link established by each node monitoring module and the monitoring main control module.
  • the node monitoring module When the information sent by the upper-level node monitoring module is being received, and the information is not sent to the next-level node monitoring module, the node monitoring module continues to receive the information sent by the upper-level node monitoring module, and caches the information; Upon completion, the node monitoring module sends the bus monitoring result to the monitoring main control module through the serial communication link established by each node monitoring module and the monitoring main control module; when the bus monitoring result is sent, the node monitoring module sends the cached The information sent by the upper-level node monitoring module.
  • the node monitoring module When the information sent by the upper-level node monitoring module is not received, and the information is being sent to the next-level node monitoring module, the node monitoring module continues to send the information; when the information is sent, the node monitoring module passes each node monitoring module and Monitor the serial communication link established by the main control module and send the bus monitoring result to the monitoring main control module.
  • the monitoring method of the SOC of the embodiment of the present invention may further include: after the bus monitoring result is sent to the monitoring main control module, the monitoring main control module sends the bus monitoring result. Give the SOC an external device. Therefore, the monitoring main control module can provide the SOC bus monitoring result to the SOC external device, so that the SOC externally can know that the bus access abnormality occurs in the SOC, and the external SOC bus monitoring result is diagnosed and the SOC bus access abnormality is diagnosed. The reason is to fundamentally solve the SOC bus access anomaly problem.
  • the implementation manner that the monitoring main control module sends the bus monitoring result to the SOC external device may be the mode one or the second mode.
  • the monitoring main control module sends the bus monitoring result to the SOC external device, and the SOC external device sends the user input instruction to the monitoring main control.
  • the monitoring main control module receives the acquisition instruction sent by the SOC external device; the monitoring main control module sends the acquisition instruction to the node monitoring module; each node monitoring module determines whether to pass the monitoring module of each node according to the acquisition instruction of the monitoring main control module.
  • the serial communication link established with the monitoring main control module transmits the bus monitoring result of the monitored node monitored by itself to the monitoring main control module; the monitoring main control module receives the bus monitoring result; and the monitoring main control module receives the received The bus monitoring result is sent to the SOC external device.
  • the monitoring module of each node determines whether to monitor the bus of the monitored node that is monitored by itself through the serial communication link established by each node monitoring module and the monitoring main control module according to the acquisition instruction of the monitoring main control module.
  • the specific implementation process of the result sent to the monitoring main control module may be the same as described above for the step.
  • the monitoring main control module sends the obtaining instruction to the node monitoring module, where the monitoring main control module parses the obtaining instruction, and converts the data format of the parsed obtaining instruction into the first predetermined data. Format; the monitoring main control module sends an acquisition instruction of the first predetermined data format to the node monitoring module.
  • the first predetermined data format is a data format that the node monitoring module can recognize.
  • the monitoring main control module sends the received bus monitoring result to the SOC external device, and may include: the monitoring main control module parses the received bus monitoring result, and parses the parsed bus monitoring result data.
  • the format is converted into a second predetermined data format; the monitoring main control module transmits the bus monitoring result of the second predetermined data format to the SOC external device.
  • the second predetermined data format is a data format that the SOC external device can recognize.
  • the second mode the monitoring main control module sends the bus monitoring result to the SOC external device, and the SOC external device sends the user input acquisition command to the monitoring main control module; the monitoring main control module receives the SOC external device to send The acquisition main control module sends the stored bus monitoring result to the SOC external device; wherein the process of obtaining the bus monitoring result may be, each node monitoring module passes each node monitoring module and the monitoring main The serial communication link established by the control module automatically sends the bus monitoring result of the monitored node monitored by itself to the monitoring main control module.
  • the monitoring module of each node automatically transmits the bus monitoring result of the monitored node to the monitoring main control module through the serial communication link established by each node monitoring module and the monitoring main control module. It can be the same as described above for this step.
  • the monitoring main control module sends the stored bus monitoring result to the SOC external device, which may include: the monitoring main control module parses the stored bus monitoring result, and parses the analyzed bus.
  • the resulting data format is converted to a second predetermined data format; the monitoring master module transmits the bus monitoring result of the second predetermined data format to the SOC external device.
  • the second predetermined data format is a data format that the SOC external device can recognize.
  • the monitoring main control module sends the bus monitoring result to the SOC external device, and the monitoring main control module is configured to set a low-speed interface, and the monitoring main control module and the SOC external device are connected through the low-speed interface, thereby The monitoring master module can send the bus monitoring result to the SOC external device.
  • the monitoring main control module receives the implementation manner of the acquisition instruction process sent by the SOC external device, and may: the monitoring main control module queries the low-speed interface to receive the acquisition instruction in real time; when the low-speed interface receives the acquisition instruction The monitoring main control module receives the acquisition instruction.
  • the foregoing process of receiving the SOC external device acquiring instruction may also be implemented by other methods.
  • the monitoring main control module periodically queries whether the low-speed interface receives the acquisition instruction by setting a timer, and monitors the main control when the low-speed interface receives the acquisition instruction.
  • the module receives the acquisition instruction, or sends an interrupt signal to the monitoring main control module when the low-speed interface receives the acquisition instruction, and triggers the monitoring main control module to receive the acquisition instruction.
  • the implementation manner of the process is not specifically limited in the embodiment of the present invention.
  • the SOC external device may be a terminal such as a personal computer (PC) or a mobile terminal.
  • PC personal computer
  • the monitoring method of the SOC in the embodiment of the present invention may further include: monitoring the main control module to monitor the status of each monitored node by using a communication link established with a bus in the SOC. Therefore, the monitoring main control module can monitor the state of each device in the SOC on the basis of locating the device with abnormal bus access in the SOC.
  • the monitoring main control module monitors the status of each monitored node by using a communication link established with the bus in the SOC, and may include: the monitoring main control module sends a query instruction to the bus in the SOC, the query instruction Carrying the original address information, that is, monitoring the address information of the main control module, the target address information, that is, the address information of the monitored node, and the query command; the bus router receives the query instruction; the bus router queries the query according to the target address information in the query instruction.
  • the instruction is sent to the corresponding monitored node; the monitored node receives the query instruction, and reads the corresponding information according to the query command in the query instruction; the information that the monitored node reads, the original address information is its own
  • the address information and the target address information are the address information of the monitoring main control module obtained from the query instruction, and are sent as a query result to the bus in the SOC; the bus router receives the query result; the bus router according to the target in the query result
  • the address information is sent to the monitoring main control module.
  • the reading the corresponding information according to the query command may be: the monitored node reads the corresponding information from its internal register according to the query command, for example, the DMA queries the command from its internal DMA_SxCR (DMA) according to the working mode. The name of a register) in the register, query the current working mode of the DMA.
  • the monitoring main control module sends the query instruction to the bus in the SOC, and the SOC external device sends the query instruction input by the user to the monitoring main control module; the monitoring main control module receives the query instruction sent by the SOC external device;
  • the monitoring master module sends the received query command to the bus within the SOC. Therefore, the monitoring main control module can also provide the state information of each device in the SOC to the SOC external device on the basis of the bus monitoring information that can provide the SOC to the SOC external device.
  • the monitoring main control module establishes a communication link with the bus in the SOC. It can be that the monitoring main control module is also provided with a bus, and the bus interface of the monitoring main control module is connected with the bus in the SOC. It should be noted that, in order to prevent the abnormal access problem of the bus in the SOC from being introduced into the bus of the monitoring main control module, a bus isolation module may be disposed in the monitoring main control module, one end of the bus isolation module is connected with the bus in the SOC, and the other end is connected with Monitor the bus connection of the main control module; the bus isolation module can prevent the abnormal access problem of the bus in the SOC from being introduced into the bus of the monitoring main control module.
  • the bus isolation module prevents an abnormal access problem of the bus in the SOC
  • the implementation of the bus process introduced into the monitoring main control module may be: the monitoring main control module communicates with the monitored node in the SOC through the bus, and the bus is isolated.
  • the bus isolation module detects that the handshake signal sent by the monitored node to the monitoring main control module is not received, the bus isolation module generates a handshake signal and sends it to the bus of the monitoring main control module.
  • the SOC monitoring method in the embodiment of the present invention may further include: each node monitoring module according to the monitoring main control module The control command controls the monitored node corresponding thereto. Therefore, the monitoring main control module can also control the devices in the SOC on the basis of locating the device with abnormal bus access in the SOC.
  • each node monitoring module controls the monitored node corresponding thereto according to the control instruction of the monitoring main control module, and may include: the node monitoring module receives the control instruction sent by the monitoring main control module; when receiving the control instruction, The node monitoring module parses the control instruction; the node monitoring module determines whether the parsed control instruction includes its own identification information; when not including its own identification information, the node monitoring module sends the control instruction to the next-level node monitored in series with it The module; when including its own identification information, the node monitoring module performs a corresponding operation on the monitored node that is monitored by itself according to the control command in the control instruction.
  • the control command may reset, turn on or off the command; the corresponding operation may be a reset, an on or off operation.
  • the control command sent by the monitoring main control module may be: the monitoring main control mode is sent according to an indication of an SOC external device connected thereto, and may also be a monitoring main The control module sends it actively.
  • the bus in the SOC may be a bus commonly used in the prior art, such as an AMBA (Advanced Microcontroller Bus Architecture) series bus, or may be an AXI (Advanced eXtensible Interface, Advanced Scalable Interfaces)
  • AMBA Advanced Microcontroller Bus Architecture
  • AXI Advanced eXtensible Interface, Advanced Scalable Interfaces
  • the transmission protocols of these buses typically specify that a master device (Slave) and a slave device (Slave) use a handshake signal for data transmission.
  • the present invention discloses a monitoring device for a system-on-chip SOC.
  • the apparatus provided in this embodiment may include at least one node monitoring module configured to monitor bus access behavior of the monitored node in the SOC, obtain bus monitoring information of the monitored node, and send the bus monitoring information to The monitoring main control module connected to the node monitoring module.
  • the bus monitoring information herein can be used by the monitoring main control module or the device connected to the monitoring main control module to access data for abnormal analysis, thereby locating an abnormal point that causes the bus access to be abnormal.
  • the anomaly can occur in the monitored node as well as the bus itself.
  • FIG. 2 is a schematic structural diagram of a device for monitoring a SOC of a system on a chip according to an embodiment of the present invention.
  • the monitoring device of the SOC includes:
  • the at least one node monitoring module 201 is configured to monitor bus access behavior of the monitored node in the SOC, obtain bus monitoring information of the monitored node, and use the bus monitoring information and its own identification information as the monitored node. Bus monitoring result, the serial communication link established by the node monitoring module and the monitoring main control module is sent to the monitoring main control module;
  • the monitoring main control module 202 is configured to receive the bus monitoring result.
  • the identification information of the foregoing may be the identification information of the node monitoring module 201, and the monitored node may identify the monitored node.
  • the monitoring main control module 202 is further configured to send the bus monitoring result to the SOC external device.
  • the at least one node monitoring module 201 is configured to receive the SOC and its pair The bus access information of the monitored node is determined; determining, according to the received bus access related information, whether the bus access behavior of the monitored node corresponding thereto is abnormal; accessing the bus to the related information, and the bus access The behavior is an abnormal judgment result as bus monitoring information of the monitored node corresponding thereto.
  • the at least one node monitoring module 201 is configured to use the bus monitoring information obtained by the self monitoring and the own identification information as a bus monitoring result of the monitored node that is monitored by itself;
  • the module is divided into a first node monitoring module and a second node monitoring module;
  • the first node monitoring module is specifically configured to monitor the bus monitoring result obtained by the self monitoring and the first node monitoring from the upper level
  • the bus monitoring result received by the module is sent to the first node monitoring module of the next level;
  • the second node monitoring module is specifically configured to monitor the bus monitoring result obtained by the self monitoring and
  • the bus monitoring result received by the first node monitoring module of the first level is sent to the monitoring main control module;
  • the first node monitoring module refers to a node monitoring module in which the next-level node connected in series is a node monitoring module; and the second node monitoring module refers to a node in which the next-level node in series is a monitoring main control module. Monitoring module.
  • the monitoring main control module 202 is further configured to monitor a status of each of the monitored nodes by a communication link established with a bus in the SOC.
  • the node monitoring module 201 and the monitoring main control module 202 can be configured by a central processing unit, a microprocessor (MPU), a digital signal processor, or a field programmable gate array (Field Programmable Gate Array). , FPGA) and other implementations.
  • MPU microprocessor
  • DSP digital signal processor
  • FPGA field programmable gate array
  • the present invention also discloses another monitoring device for the system-on-chip SOC.
  • FIG. 3A is a schematic structural diagram of another apparatus for monitoring a SOC of a system on a chip according to an embodiment of the present invention. As shown in FIG. 3A, the monitoring apparatus of the SOC includes:
  • the monitoring main control module 202 is connected in series with the node monitoring module 201, and the node
  • the first bus interface of the monitoring module 201 is connected to the bus interface of the monitored node 203 in the SOC, and the second bus interface of the node monitoring module 201 is connected to the bus 204 in the SOC; when a plurality of the node monitoring modules are included,
  • the node monitoring module 201 is connected in series with the monitoring main control module 202.
  • the plurality of node monitoring modules 201 are connected in series to form a node monitoring module serial circuit, and the node monitoring module serial circuit and the monitoring main The control modules 202 are connected in series.
  • the bus interface of the monitoring main control module 202 is connected to the bus 204 in the SOC.
  • the monitoring main control module 202 is connected to an SOC external device.
  • FIG. 3B is a schematic structural diagram of another embodiment of a monitoring device for a system-on-chip SOC according to the present invention. As shown in FIG. 3B, the SOC monitoring device monitors bus access behavior of each device in the SOC; each device in the SOC includes a high speed.
  • the interface 301, the low speed interface 302, the memory 303, the DMA 304, the accelerator N 305, the accelerator 306, the DSP 307 and the CPU 308, the high speed interface 301, and the dotted line at the low speed interface 302 indicate that the high speed interface 301 and the low speed interface one 302 are An interface for communicating with the SOC external device;
  • the bus in the SOC is an AMBA bus
  • the monitoring device of the SOC specifically includes: a monitoring main control module 202 and a plurality of node monitoring modules 201; as shown in FIG. 4, the node monitoring module 201 includes a bus monitoring module. 2011 and node monitoring transceiver module 2012.
  • the bus monitoring module 2011 is configured to monitor the bus access behavior of the device in the SOC connected thereto, obtain the bus monitoring information of the device in the SOC connected thereto, and send the bus monitoring information to the node monitoring transceiver module 2012.
  • the node monitoring transceiver module 2012 is configured to store the bus monitoring information sent by the bus monitoring module 2011 and the identification information of the node monitoring module 201 as a bus monitoring result stored in the SOC device connected to the bus monitoring module 2011.
  • the bus monitoring result is sent to the monitoring main control module through the serial communication link established by each node monitoring module and the monitoring main control module.
  • the monitoring main control module is configured to receive the bus monitoring result; send the bus monitoring result to the SOC external device connected thereto according to the obtaining instruction sent by the SOC external device connected thereto; and pass the bus in the SOC according to the query instruction of the SOC external device Established communication links to monitor the status of individual devices within the SOC.
  • the monitoring by the query command of the SOC external device, monitoring the state of each device in the SOC through a communication link established with the bus in the SOC, including sending the query instruction sent by the SOC external device to the SOC through the bus in the SOC
  • Each device in the SOC reads the corresponding information from its own register according to the query instruction, and sends the query information as a query result to the monitoring main control module 202 through the bus in the SOC; the monitoring main control module 202 will query The result is sent to the SOC external device.
  • the monitoring device of the SOC is connected to each device in the SOC and the bus in the SOC.
  • One end of each node monitoring module 201 is connected to each device in the SOC, and the other end of each node monitoring module 201 and the Crossbar of the AMBA bus (interconnecting matrix) ) 309 connection.
  • the monitoring main control module 202 is connected to the Crossbar 309 of the AMBA bus, so that the monitoring main control module can flexibly monitor the state of each device in the SOC; the dashed line at the monitoring main control module 202 represents the interface that monitors the main control module 202 to communicate with the SOC external device.
  • the monitoring main control module 202 of the SOC monitoring device and the node monitoring module 201 are connected.
  • the monitoring main control module 202 and each node monitoring module 201 have a transmitting Tx interface 310 and a receiving Rx interface 311, and each Rx interface 311 is It is connected in series with the Tx interface 310 of the upper stage, thereby establishing a ring serial communication link.
  • the monitoring device of the SOC can be unaffected by the number of node monitoring modules, that is, when the node monitoring module needs to be added, the node monitoring module can be directly connected to the ring serial communication link, and when the node monitoring module needs to be reduced, The node monitoring module is directly removed from the ring serial communication link; at the same time, when the circuit board of the SOC monitoring device is fabricated, the routing of the circuit board can be reduced, and the influence of the change of the number of node monitoring modules on the production is reduced.
  • the monitoring device of the SOC is connected to each device in the SOC and the bus in the SOC.
  • the first bus interface at one end of the bus monitoring module 2011 of the node monitoring module 201 is connected to the bus interface of the device in the SOC, and the second bus interface at the other end of the bus monitoring module 2011 is connected to the Crossbar 309 of the AMBA bus; optionally,
  • the M (Master) interface 312 of the second bus interface at the other end of the bus monitoring module 2011 is connected to the S (Slave) interface 313 of the Crossbar 309 of the AMBA bus, and the S interface 313 and the AMBA bus of the second bus interface at the other end of the bus monitoring module 2011
  • the Crossbar309's M interface 312 is connected.
  • the connection manner between the monitoring main control module 202 and each node monitoring module 201 in the monitoring device of the SOC is specifically that the Rx interface 311 of the node monitoring transceiver module 2012 of the node monitoring module 201 is connected in series with the Tx interface 310 of the upper level, and the node monitoring The Tx interface 310 of the transceiver module 2012 is connected in series with the Rx interface 311 of the next stage.
  • the monitoring main control module 202 includes a controller 2021, an on-chip memory 2022, a bus isolation module 2023, a total control transceiver module 2024, a low-speed interface 2205, and a total control Crossbar 2027.
  • the master control transceiver module 2024 is configured to receive the bus monitoring result; the bus monitoring result is sent to the on-chip memory 2022 through the master control Crossbar 2027.
  • the master control transceiver module 2024 can be a serial port controller in practical applications. When the master control transceiver module 2024 receives the information, the master control transceiver module 2024 can generate an interrupt signal to the controller 2021.
  • the on-chip memory 2022 is configured to store bus monitoring results.
  • the program of the controller 2021 is also stored in a practical application, which enables the controller 2021 to perform the operations required by the controller 2021; it can also be used to store other data; the memory size can be based on the amount of data of the controller 2021 program. And the number of node monitoring modules 201 is adjusted.
  • the program of the controller 2021 can be downloaded to the on-chip memory 2022 through the low-speed interface 2205, or downloaded to the on-chip memory 2022 through the high-speed interface 301 and the low-speed interface 302 of the SOC.
  • the low-speed interface two 2025 is configured to receive an acquisition instruction sent by the SOC external device, send the acquisition instruction to the controller 2021 through the master control Crossbar 2027, and send the received bus monitoring result to the SOC external device; and receive the SOC external device to send the Query instruction, through total
  • the control Crossbar 2027 is sent to the controller 2021, receives the query result, and sends the received query result to the SOC external device.
  • the low speed interface 2 2025 can generate an interrupt signal to the controller 2021.
  • the controller 2021 is configured to receive the acquisition instruction, read the bus monitoring result from the on-chip memory 2022, and send the bus monitoring result to the low-speed interface 2205 through the total control Crossbar 2027; receive the query instruction, and send it to the bus isolation through the total control Crossbar 2027.
  • the module 2023 receives the query result and sends the query result to the low speed interface 2 2025 through the master control Crossbar 2027.
  • the controller 2021 may be a controller such as a CPU or a DSP in an actual application. In a case where the performance of the controller 2021 is not high, the controller 2021 may use a low-power CPU or in order to save the area and cost of the SOC. Controllers such as DSP.
  • the bus isolation module 2023 is configured to receive the query instruction, send the query instruction to each device in the SOC through the Crossbar 309 of the AMBA bus, receive the query result of each device in the SOC, and send the query result to the controller through the total control Crossbar 2027. 2021.
  • the bus isolation module 2023 is configured to communicate with the device in the SOC through the bus in the monitoring main control module 202, and the bus isolation module monitors When the handshake signal sent by the device in the SOC to the monitoring main control module 202 is not received, the bus isolation module generates a handshake signal and sends it to the total control Crossbar 2027 of the monitoring main control module 202.
  • the monitoring main control module 202 may further include a timer 2026.
  • the controller 2021 may be configured to periodically query the low-speed interface 2205 by receiving a timer to receive an acquisition instruction, and receive the acquisition on the low-speed interface. When instructed, the controller 2021 receives the acquisition instruction. At the end of timer 2026 timing, timer 2026 can generate an interrupt signal to controller 2021.
  • the bus monitoring module 2011 is configured to receive bus access related information of the device in the SOC connected thereto; and determine the SOC connected thereto according to the received bus access related information. Whether the bus access behavior of the device is abnormal; the bus access related information, and the bus access behavior are abnormal judgment results as the bus monitoring information of the devices in the SOC connected thereto.
  • the controller 2021 is configured to send the received acquisition instruction to the master control transceiver module 2024 through the master control Crossbar 2027.
  • the master control transceiver module 2024 is further configured to send the received acquisition command to each node monitoring module 201 through a serial communication link.
  • the node monitoring transceiver module 2012 is specifically configured to receive the acquisition instruction sent by the monitoring main control module 202; when receiving the acquisition instruction, parse the acquisition instruction; and determine whether the parsed acquisition instruction includes its own identification information; When the identification information of the self is included, the acquisition instruction is sent to the next-level node monitoring module connected in series; when the identification information of the self is included, the serial communication link established by each node monitoring module 201 and the monitoring main control module 202 The bus monitoring result of the device in the SOC connected to the bus monitoring module 2011 is sent to the monitoring main control module.
  • the node monitors the transceiver module 2012, or is configured to automatically send the bus monitoring result of the device in the SOC connected to the bus monitoring module 2011 through the serial communication link established by each node monitoring module 201 and the monitoring main control module 202. Give the monitoring master module.
  • the node monitoring module 201 may further include a control module 2013 connected to the node monitoring transceiver module 2012.
  • the control module 2013 is also coupled to the SOC device monitored by the bus monitoring module 2021.
  • the control module 2013 is specifically configured to receive a control command, and perform a corresponding operation on the device in the SOC monitored by the bus monitoring module 2021.
  • the control command may reset, turn on or off the command; the corresponding operation may be a reset, an on or off operation.
  • a plurality of control modules 2013 may be included, with different control modules 2013 performing different operations on devices within the SOC.
  • the control module 2013 can be a CPU or a DSP or the like.
  • the node monitoring module can also communicate with other interfaces of the accelerator device, and other interfaces refer to An interface other than the line interface, as shown in FIG. 4, the node monitoring module 201 may further include an accelerator interface module 2014 connected to the node monitoring transceiver module 2012, and the accelerator interface module 2014 may be monitored by the bus monitoring module 2021 with an SOC internal accelerator device. Other interfaces are connected.
  • a plurality of accelerator interface modules 2014 may be included, with different accelerator interface modules 2014 being coupled to different interfaces of the accelerator devices within the SOC.
  • the accelerator interface module 2014 can be a CPU or a DSP or the like.
  • the node monitoring transceiver module 2012 is configured to receive an instruction sent by the monitoring main control module 202; parse the received instruction; and send the instruction to the control module 2013 when determining that the parsed instruction is a control instruction;
  • the subsequent instruction sends the instruction to the bus monitoring module 2011 when the instruction is fetched, and sends the instruction to the accelerator interface 2014 when it determines that the parsed instruction is an accelerator interface communication command.
  • the bus monitoring module 2011 is further configured to receive the acquisition instruction, and send the bus monitoring result of the device in the SOC connected thereto to the node monitoring transceiver module 2012.
  • the control command may be sent to the monitoring main control module 202 for the SOC external device.
  • the bus monitoring module 2011 may be a CPU or a DSP having a bus interface in the actual application, and the node monitoring transceiver module 2012 may be a CPU or a DSP having a Tx or Rx interface.
  • FIG. 6 is a schematic flowchart of a method for monitoring a SOC of a system on a chip according to a first embodiment of the present invention. As shown in FIG. 6, the specific steps include:
  • Step 601 Each node monitoring module monitors bus access behavior of each device in the SOC, obtains bus monitoring information of each device, and uses the bus monitoring information obtained by the self monitoring and its own ID as the bus monitoring result of the device in the SOC monitored by itself.
  • the node monitoring module may be implemented by a CPU or a DSP or the like.
  • the various devices within the SOC may include devices such as CPU, DSP, DMA, various hardware accelerators, various memories, and various peripheral interfaces within the SOC.
  • Step 602 The monitoring main control module determines whether it has received the SOC external device. instruction. When the instruction is received, step 603 is performed; otherwise, step 602 is performed.
  • the monitoring main control module may be implemented by a CPU or a DSP or the like.
  • the SOC external device may be a terminal set for a personal computer, a mobile terminal, or the like.
  • Step 603 The monitoring main control module parses the received instruction, and sends the parsed instruction to the node monitoring module through the serial communication link established by each node monitoring module and the monitoring main control module in the first predetermined data format.
  • the first predetermined data format is a data format that the node monitoring module can recognize.
  • Step 604 The node monitoring module parses the received instruction, and determines whether the parsed instruction includes its own ID. When the ID is not included, the instruction is sent to the next-level node monitoring module connected in series with the node.
  • Step 605 When including its own ID, the node monitoring module determines whether the received instruction is an acquisition instruction.
  • Step 606 When the instruction is acquired, the node monitoring module sends the bus monitoring result of the device in the SOC monitored by itself to the monitoring main control module through the serial communication link established by each node monitoring module and the monitoring main control module.
  • Step 607 The monitoring main control module receives the bus monitoring result, and sends the bus monitoring result to the SOC external device.
  • FIG. 7 is a schematic flowchart of a method for monitoring a SOC of a system on a chip according to a second embodiment of the present invention. As shown in FIG. 7, the specific steps include:
  • Step 701 Each node monitoring module monitors bus access behavior of each device in the SOC, obtains bus monitoring information of each device, and uses the bus monitoring information obtained by the self monitoring and its own ID as the bus monitoring result of the device in the SOC monitored by itself.
  • the each node monitoring module monitors bus access behavior of each device in the SOC, and obtains bus monitoring information of each device, and may include: each node monitoring module receives bus access related information of a device corresponding to the SOC; Node monitoring module based on the total received The line access related information determines whether the bus access behavior of the corresponding device is abnormal; each node monitoring module uses the bus access related information, and the bus access behavior is an abnormal judgment result as the bus monitoring information of the corresponding device.
  • the node monitoring module may be implemented by a CPU or a DSP or the like.
  • the various devices within the SOC may include devices such as CPU, DSP, DMA, various hardware accelerators, various memories, and various peripheral interfaces within the SOC.
  • Step 702 Each node monitoring module automatically sends a bus monitoring result to the monitoring main control module through a serial communication link established between each node monitoring module and the monitoring main control module.
  • the monitoring main control module may be implemented by a CPU or a DSP or the like.
  • Step 703 The monitoring main control module receives and stores the bus monitoring result.
  • Step 704 The monitoring main control module determines whether it has received an instruction sent by the SOC external device.
  • Step 705 When receiving the instruction, the monitoring main control module determines whether the received instruction is an acquisition instruction. When the instruction is acquired, the monitoring main control module sends the stored bus monitoring result to the SOC external device.
  • FIG. 8 is a schematic flowchart of a method for monitoring a SOC of a system on a chip according to a third embodiment of the present invention. As shown in FIG. 8, the specific steps include:
  • Step 801 The monitoring main control module determines whether it has received an instruction sent by the SOC external device.
  • the monitoring main control module may be implemented by a CPU or a DSP or the like.
  • the SOC external device may be a terminal set for a personal computer, a mobile terminal, or the like.
  • Step 802 When receiving the instruction, the monitoring main control module determines whether the received instruction is a query instruction.
  • Step 803 When the command is queried, the monitoring main control module sends the query instruction to the corresponding device in the SOC through a communication link established with the bus in the SOC.
  • Step 804 The corresponding device in the SOC reads the corresponding information from its register according to the query instruction, and sends the information as a query result to the monitoring main control module through the bus in the SOC.
  • Step 805 The monitoring main control module receives the query result, and sends the query result to the SOC external device.
  • the embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the monitoring method of any one of the foregoing system-on-system SOCs, for example, as shown in the figure. 1 and the method shown in one or more of Figures 6-8.
  • the computer storage medium may include various storage media such as an optical disk, a magnetic disk, a random storage medium RAM, a read-only storage medium ROM, or a flash memory, and is preferably a non-transitory storage medium.

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Abstract

一种片上系统SOC的监控方法，该方法包括：节点监控模块监测SOC内被监控节点的总线访问行为，获得被监控节点的总线监测信息（101）；节点监控模块将总线监测信息、及自身的标识信息作为被监控节点的总线监测结果，通过节点监控模块与监控主控模块建立的串行通信链路，发送给监控主控模块（102）。通过上述方法，可以简单定位出导致总线访问异常的异常点的位置。

Description

片上系统SOC的监控方法、装置和计算机存储介质 技术领域
本发明涉及电子技术领域，尤其涉及一种片上系统(System On Chip，SOC)的监控方法、装置和计算机存储介质。
背景技术
随着微电子技术的不断发展，芯片集成度越来越高，SOC规模也越来越大，SOC内的互联结构也越来越复杂。其中，SOC内的总线(Bus)是SOC内部所有互联结构的传输枢纽，它连接了SOC内的中央处理器(Central Processing Unit，CPU)、数字信号处理器(Digital Signal Processor，DSP)、直接内存访问(Direct Memory Access，DMA)、各种硬件加速器、各种存储器以及各种外设接口，因此总线状态的正确与否直接影响到SOC的稳定性。
但随着SOC规模的日益庞大，其内嵌的CPU、DSP及硬件加速器数目越来越多，SOC内部总线互联结构越来越复杂，SOC的软件系统也越来越复杂，且内嵌的硬件加速器、DMA可以独立于CPU，并与CPU并行工作，因此在软件系统或者软件系统产品开发初期，协调SOC内部各种器件正常工作变得越来越困难，从而导致SOC内的器件可能会出现总线访问异常。为了解决该问题，相关现有技术的处理方式通常是，在SOC出现总线访问异常时，对SOC的软件系统进行复位，使该软件系统重新启动，从而使得SOC恢复正常。但该种方式并不能定位出具体是SOC内哪个器件出现了总线访问异常，从而不能从根本上解决该问题。
发明内容
有鉴于此，本发明实施例期望提供一种片上系统SOC的监控方法、装置和计算机存储介质，以简单、有效地定位出SOC内出现了总线访问异常的器件。
本发明的技术方案是这样实现的：
本发明实施例公开了一种片上系统SOC的监控方法，所述方法包括：
节点监控模块监测SOC内被监控节点的总线访问行为，获得所述被监控节点的总线监测信息；
将所述总线监测信息发送给与所述节点监控模块连接的监控主控模块。
本发明实施例还公开了一种片上系统SOC的监控装置，所述装置包括：
至少一个节点监控模块，配置为监测SOC内被监控节点的总线访问行为，获得所述被监控节点的总线监测信息；将所述总线监测信息发送给与所述节点监控模块连接的监控主控模块。
本发明实施例还公开了一种片上系统SOC的监控装置，所述装置包括：监控主控模块和至少一个节点监控模块；
所述监控主控模块与所述节点监控模块串联连接，所述节点监控模块的第一总线接口与SOC内被监控节点的总线接口连接，所述节点监控模块的第二总线接口与SOC内的总线连接；在包括多个所述节点监控模块时，所述节点监控模块与所述监控主控模块串联连接具体为：多个所述节点监控模块相互串联连接，形成节点监控模块串联电路，所述节点监控模块串联电路与所述监控主控模块串联连接。
本发明实施例还提供一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行前述片上系统SOC的监控方法。
本发明实施例提供的一种片上系统SOC的监控方法、装置和计算机存储介质，节点监控模块监测SOC内被监控节点的总线访问行为，获得被监控节点的总线监测信息；节点监控模块将总线监测信息发送给监控主控模块。这样可以获取了所述总线监控信息，若出现总线访问异常时，可以通过所述总线监控信息，从而可以知道定位出导致总线访问异常的异常点的位置。如此，能简单、有效地定位出SOC内出现了总线访问异常的器件，有助于从根本上解决SOC的总线访问异常问题。
附图说明
图1为本发明实施例提供的一种片上系统SOC的监控方法的流程示意图；
图2为本发明实施例提供的一种片上系统SOC的监控装置的结构示意图；
图3A为本发明实施例提供的另一种片上系统SOC的监控装置的结构示意图；
图3B为本发明提供的另一种片上系统SOC的监控装置具体实施例的结构示意图；
图4为本发明提供的另一种片上系统SOC的监控装置具体实施例中节点监控模块201的结构示意图；
图5为本发明提供的另一种片上系统SOC的监控装置具体实施例中监控主控模块202的结构示意图；
图6为本发明提供的一种片上系统SOC的监控方法具体实施例一的流程示意图；
图7为本发明提供的一种片上系统SOC的监控方法具体实施例二的流程示意图；
图8为本发明提供的一种片上系统SOC的监控方法具体实施例三的流 程示意图。
具体实施方式
以下结合附图对本发明的优选实施例进行详细说明，应当理解，以下所说明的优选实施例仅用于说明和解释本发明，并不用于限定本发明。
在本发明实施例中，节点监控模块监测SOC内被监控节点的总线访问行为，获得被监控节点的总线监测信息；节点监控模块将总线监测信息发送给与节点监控模块连接的监控主控模块。这样所述监控主控模块或与所述监控主控模块连接的设备就可以在发现总线异常时，通过分析所述总线监测信息，从而定位出导致异常的被监控节点，从而完成总线异常的异常定位，方便后续进行根据异常定位进行异常排查。
在本发明实施例中所述总线监测信息可包括所述被监控节点的标识信息。方便后续异常的定位。当然在有些实施例中，所述总线监测信息也可以不包括所述被监控节点的标识信息，还可以是其他可唯一标识所述被监控节点的其他信息。例如，当一个所述节点监控模块监控一个被监控节点时，则所述节点监控模块监控的被监控节点，是可以由所述节点监控模块唯一确定时，则所述节点监控模块可是将所述总线监测信息及所述节点监控模块的标识信息作为被监控节点的总线监测结果，通过节点监控模块与监控主控模块建立的串行通信链路，发送给监控主控模块。在本发明实施例中所述总线监测信息可为表征所述被监控节点的访问行为的行为参数和/或状态参数等可以反映被监控节点的访问行为是否正常的数据。所述行为参数可包括行为类型，每一个行为类型携带的行为参数。所述状态参数可为访问是否成功等参数。
图1为本发明实施例提供的一种片上系统SOC的监控方法的流程示意图，如图1所示，该方法包括：
步骤101：节点监控模块监测SOC内被监控节点的总线访问行为，获 得被监控节点的总线监测信息。
可选地，本步骤可以包括，每个节点监控模块接收SOC内与其对应的被监控节点的总线访问相关信息；每个节点监控模块根据接收到的总线访问相关信息判断与其对应的被监控节点的总线访问行为是否异常；每个节点监控模块将总线访问相关信息、及总线访问行为是异常的判断结果作为与其对应的被监控节点的总线监测信息。
其中，所述SOC内的被监控节点可以包括，SOC内的CPU、DSP、DMA、各种硬件加速器、各种存储器以及各种外设接口等器件。
可选地，所述每个节点监控模块接收SOC内与其对应的被监控节点的总线访问相关信息，可以包括，每个节点监控模块接收，自身监测的SOC内的被监控节点通过总线向SOC内的其它节点发送的相关信息；或者，每个节点监控模块接收，SOC内的其它节点通过总线向自身监测的SOC内的被监控节点发送的相关信息。需说明的是，所述相关信息可以包括读/写命令及地址信息或相应的数据包。可选地，所述每个节点监控模块接收SOC内与其对应的被监控节点的总线访问相关信息的实现方式可以为，节点监控模块的一端与被监控节点的总线接口连接，节点监控模块的另一端与SOC内的总线连接。
可选地，所述每个节点监控模块根据接收到的总线访问相关信息判断与其对应的被监控节点的总线访问行为是否异常，可以包括，在节点监控模块接收到自身监测的被监控节点的读/写命令及地址信息或相应的数据包时，节点监控模块启动其内部的定时器开始计时，并将握手信号信息设置为空；在定时器计时到预定时间并停止计时时，节点监控模块判断是否有接收到自身监测的被监控节点的握手信号；在接收到该握手信号时，节点监控模块判定自身监测的被监控节点的本次总线访问行为正常，将该被监控节点的握手信号信息设置为正常；在未接收到握手信号时，节点监控模 块判定自身监测的被监控节点的本次总线访问行为异常，将该被监控节点的握手信号信息设置为异常；节点监控模块将握手信号信息作为该被监控节点的本次总线访问行为是否异常的判断结果。需说明的是，所述预定时间可以根据总线协议中规定的握手信号的发出时间间隔来设置。
可选地，所述每个节点监控模块将总线访问相关信息，及总线访问行为是异常的判断结果作为与其对应的被监控节点的总线监测信息，可以为，每个节点监控模块将接收到的自身监测的被监控节点的总线访问相关信息，及自身监测的被监控节点的本次总线访问行为是异常的判断结果，作为自身监测的被监控节点的本次总线监测信息，存放在节点监控模块内的寄存器中。
步骤102：节点监控模块将总线监测信息、及自身的标识信息作为被监控节点的总线监测结果，通过节点监控模块与监控主控模块建立的串行通信链路，发送给监控主控模块。
可选地，本步骤可以包括，各个节点监控模块将自身监测获得的总线监测信息，及自身的标识信息作为自身监测的被监控节点的总线监测结果；每个第一节点监控模块将自身监测获得的总线监测结果，及从上一级第一所述节点监控模块接收到的总线监测结果，发送给下一级第一节点监控模块；第二节点监控模块将自身监测获得的总线监测结果，及从上一级第一节点监控模块接收到的总线监测结果，发送给监控主控模块；其中，所述第一节点监控模块是指与其串联的下一级节点为节点监控模块的节点监控模块；所述第二节点监控模块是指与其串联的下一级节点为监控主控模块的节点监控模块。如此，监控主控模块根据接收到的SOC内各个被监测节点的总线监测结果，即可获知SOC内的哪个被监测节点即被监测器件，出现了总线访问异常问题，实现能简单、有效地定位出SOC内出现了总线访问异常的器件，有助于从根本上解决SOC的总线访问异常问题。
可选地，所述节点监控模块自身的标识信息可以唯一地标识每个节点监控模块，即为每个节点监控模块设置一个身份标识(Identity identification，ID)，每个节点监控模块的ID均不相同。
可选地，所述每个第一所述节点监控模块将自身监测获得的总线监测结果，及从上一级第一节点监控模块接收到的总线监测结果，发送给下一级第一节点监控模块，可以包括，每个第一节点监控模块将自身监测的被监控节点的总线监测结果发送给与其串联的下一级第一节点监控模块；每个第一节点监控模块接收与其串联的上一级第一节点监控模块发送的总线监测结果；第一节点监控模块解析接收到的该总线监测结果；第一节点监控模块判断解析后的该总线监测结果中是否包括自身的标识信息；在不包括自身的标识信息时，第一节点监控模块将接收到的该总线监测结果发送给与其串联的下一级第一节点监控模块，否则不发送该总线监测结果。
可选地，所述第二所述节点监控模块将自身监测获得的总线监测结果，及从上一级第一节点监控模块接收到的总线监测结果，发送给监控主控模块，可以包括，第二节点监控模块将自身监测的被监控节点的总线监测结果发送给与其串联的监控主控模块；第二节点监控模块接收与其串联的上一级第一节点监控模块发送的总线监测结果；第二节点监控模块解析接收到的该总线监测结果；第二节点监控模块判断解析后的该总线监测结果中是否包括自身的标识信息；在不包括自身的标识信息时，第二节点监控模块将接收到的该总线监测结果发送给与其串联的监控主控模块，否则不发送该总线监测结果。
需说明的是，所述串行通信链路的实现方式可以为，监控主控模块、每个第一节点监控模块及第二节点监控模块均具有发送(Tx)接口和接收(Rx)接口，每个Rx接口均与上一级的Tx接口串接，从而通过监控主控模块、每个第一节点监控模块及第二节点监控模块，建立了环形串行通信 链路。
可选地，所述节点监控模块将总线监测结果，通过节点监控模块与监控主控模块建立的串行通信链路，发送给监控主控模块的实现方式可以为方式一或方式二。
方式一，所述节点监控模块将总线监测结果，通过节点监控模块与监控主控模块建立的串行通信链路，发送给监控主控模块，可以为，每个节点监控模块根据监控主控模块的获取指令，决策是否通过各个节点监控模块与监控主控模块建立的串行通信链路，将自身监测的所述被监控节点的总线监测结果发送给监控主控模块。
可选地，所述每个节点监控模块根据监控主控模块的获取指令，决策是否通过各个节点监控模块与监控主控模块建立的串行通信链路，将自身监测的所述被监控节点的总线监测结果发送给监控主控模块，可以包括，节点监控模块接收监控主控模块的获取指令；在接收到获取指令时，节点监控模块解析获取指令；节点监控模块判断解析后的获取指令中是否包括自身的标识信息；在不包括自身的标识信息时，节点监控模块将该获取指令发送给与其串联的下一级节点监控模块；在包括自身的标识信息时，节点监控模块通过各个节点监控模块与监控主控模块建立的串行通信链路，将自身监测的所述被监控节点的总线监测结果发送给监控主控模块。
方式二，所述节点监控模块将总线监测结果，通过节点监控模块与监控主控模块建立的串行通信链路，发送给监控主控模块，可以为，每个节点监控模块通过各个节点监控模块与监控主控模块建立的串行通信链路，自动将自身监测的被监控节点的总线监测结果发送给监控主控模块。
可选地，所述每个节点监控模块通过各个节点监控模块与监控主控模块建立的串行通信链路，自动将自身监测的被监控节点的总线监测结果发送给监控主控模块，可以包括，节点监控模块检测自身是否正在接收上一 级节点监控模块发送的信息，节点监控模块检测自身是否正在向下一级节点监控模块发送信息；在未接收上一级节点监控模块发送的信息，且未向下一级节点监控模块发送信息时，节点监控模块通过各个节点监控模块与监控主控模块建立的串行通信链路，将总线监测结果发送给监控主控模块。
在正在接收上一级节点监控模块发送的信息，且未向下一级节点监控模块发送信息时，节点监控模块继续接收上一级节点监控模块发送的信息，并缓存该信息；在该信息缓存完成时，节点监控模块通过各个节点监控模块与监控主控模块建立的串行通信链路，将总线监测结果发送给监控主控模块；在总线监测结果发送完成时，节点监控模块发送已缓存的上一级节点监控模块发送的信息。
在未接收上一级节点监控模块发送的信息，且正在向下一级节点监控模块发送信息时，节点监控模块继续发送该信息；在该信息发送完成时，节点监控模块通过各个节点监控模块与监控主控模块建立的串行通信链路，将总线监测结果发送给监控主控模块。
需说明的是，为了向SOC外部提供SOC的总线监测结果，本发明实施例的SOC的监控方法还可以包括，将总线监测结果发送给监控主控模块之后，监控主控模块将总线监测结果发送给SOC外部设备。从而使得监控主控模块可以向SOC外部设备提供SOC的总线监测结果，使得SOC外部可以获知SOC内出现了总线访问异常的器件，有助于外部根据SOC的总线监测结果诊断出SOC出现总线访问异常的原因，从根本上解决SOC的总线访问异常问题。
可选地，所述监控主控模块将总线监测结果发送给SOC外部设备的实现方式可以为，方式一或方式二。
方式一，所述监控主控模块将总线监测结果发送给SOC外部设备的实现方式，可以包括，SOC外部设备将用户输入的获取指令发送给监控主控 模块；监控主控模块接收SOC外部设备发送的获取指令；监控主控模块将该获取指令发送给节点监控模块；每个节点监控模块根据监控主控模块的获取指令，决策是否通过各个节点监控模块与监控主控模块建立的串行通信链路，将自身监测的所述被监控节点的总线监测结果发送给监控主控模块；监控主控模块接收总线监测结果；监控主控模块将接收到的总线监测结果发送给SOC外部设备。
其中，所述每个节点监控模块根据监控主控模块的获取指令，决策是否通过各个节点监控模块与监控主控模块建立的串行通信链路，将自身监测的所述被监控节点的总线监测结果发送给监控主控模块步骤的具体实现过程，可以与上述对该步骤的描述相同。
可选地，所述监控主控模块将该获取指令发送给节点监控模块，可以包括，监控主控模块对该获取指令进行解析，并将解析后的获取指令的数据格式转换为第一预定数据格式；监控主控模块将第一预定数据格式的获取指令发送给节点监控模块。其中，所述第一预定数据格式为节点监控模块可以识别的数据格式。
可选地，所述监控主控模块将接收到的总线监测结果发送给SOC外部设备，可以包括，监控主控模块对接收到的总线监测结果进行解析，并将解析后的总线监测结果的数据格式转化为第二预定数据格式；监控主控模块将第二预定数据格式的总线监测结果发送给SOC外部设备。其中，所述第二预定数据格式为SOC外部设备可以识别的数据格式。
方式二，所述监控主控模块将总线监测结果发送给SOC外部设备的实现方式，可以包括，SOC外部设备将用户输入的获取指令发送给监控主控模块；监控主控模块接收SOC外部设备发送的获取指令；监控主控模块将自身已存储的总线监测结果发送给SOC外部设备；其中，所述总线监测结果获得的过程可以为，每个节点监控模块通过各个节点监控模块与监控主 控模块建立的串行通信链路，自动将自身监测的被监控节点的总线监测结果发送给监控主控模块。
其中，所述每个节点监控模块通过各个节点监控模块与监控主控模块建立的串行通信链路，自动将自身监测的被监控节点的总线监测结果发送给监控主控模块步骤的具体实现过程，可以与上述对该步骤的描述相同。
可选地，所述监控主控模块将自身已存储的总线监测结果发送给SOC外部设备，可以包括，监控主控模块对自身已存储的的总线监测结果进行解析，并将解析后的总线监测结果的数据格式转换为第二预定数据格式；监控主控模块将第二预定数据格式的总线监测结果发送给SOC外部设备。其中，所述第二预定数据格式为SOC外部设备可以识别的数据格式。
可选地，所述监控主控模块将总线监测结果发送给SOC外部设备的实现方式可以为，为监控主控模块设置低速接口，监控主控模块与SOC外部设备通过该低速接口连接，从而使得监控主控模块可以将总线监测结果发送给SOC外部设备。可选地，所述监控主控模块接收SOC外部设备发送的获取指令过程的实现方式，可以为，监控主控模块实时地查询低速接口是否有接收到获取指令；在低速接口接收到获取指令时，监控主控模块接收该获取指令。当然，还可以通过其它方式实现上述接收SOC外部设备获取指令过程，如监控主控模块通过设置定时器定时地查询低速接口是否有接收到获取指令，在低速接口接收到获取指令时，监控主控模块接收该获取指令，或低速接口接收到获取指令时向监控主控模块发送一个中断信号，触发监控主控模块接收该获取指令，本发明实施例不对该过程的实现方式进行具体限定。
其中，所述SOC外部设备可以为个人计算机(Personal Computer，PC)、移动终端等终端设。
需说明的是，为了在定位出SOC内出现总线访问异常的器件的基础上， 监控SOC内各个器件的状态，本发明实施例的SOC的监控方法还可以包括，监控主控模块通过与SOC内的总线建立的通信链路，监测各个被监控节点的状态。从而使得监控主控模块可以在定位出SOC内出现总线访问异常的器件的基础上，还可以监控SOC内各个器件的状态。
可选地，所述监控主控模块通过与SOC内的总线建立的通信链路，监测各个被监控节点的状态，可以包括，监控主控模块发送查询指令到SOC内的总线上，该查询指令携带有原地址信息即监控主控模块的地址信息、目标地址信息即被监控节点的地址信息、及查询命令；总线路由器接收查询指令；总线路由器根据该查询指令中的目标地址信息，将该查询指令发送给相应的被监控节点；该被监控节点接收查询指令，并根据该查询指令中的查询命令读取出相应的信息；该被监控节点将读取到的信息、原地址信息即自身的地址信息，及目标地址信息即从查询指令中获取到的监控主控模块的地址信息，作为查询结果发送到SOC内的总线上；总线路由器接收该查询结果；总线路由器根据该查询结果中的目标地址信息，将该查询结果发送给监控主控模块。
其中，所述根据查询命令读取出相应的信息，可以为，被监控节点根据查询命令从其内部的寄存器中读取出相应的信息，如DMA根据工作模式查询命令从其内部的DMA_SxCR(DMA的一个寄存器的名称)寄存器中，查询DMA当前的工作模式。其中，所述监控主控模块发送查询指令到SOC内的总线上，可以包括，SOC外部设备将用户输入的查询指令发送给监控主控模块；监控主控模块接收SOC外部设备发送的查询指令；监控主控模块将接收到的查询指令发送到SOC内的总线上。从而使得监控主控模块在可以向SOC外部设备提供SOC的总线监测信息的基础上，还可以向SOC外部设备提供SOC内各个器件的状态信息。
可选地，所述监控主控模块与SOC内的总线建立通信链路的实现方式 可以为，监控主控模块内也设置有总线，监控主控模块的总线接口与SOC内的总线连接。需说明的是，为了防止SOC内总线的访问异常问题被引入到监控主控模块的总线，可以为监控主控模块内设置总线隔离模块，总线隔离模块一端与SOC内的总线连接，另一端与监控主控模块的总线连接；总线隔离模块可以防止SOC内总线的访问异常问题被引入监控主控模块的总线。可选地，所述总线隔离模块防止SOC内总线的访问异常问题，被引入监控主控模块的总线过程的实现方式可以为，在监控主控模块与SOC内被监测节点通过总线通信，总线隔离模块监测到未接收到SOC内被监测节点向监控主控模块发送的握手信号时，总线隔离模块产生一个握手信号并发送到监控主控模块的总线上。
需说明的是，为了在定位出SOC内出现总线访问异常的器件的基础上，控制SOC内的器件，本发明实施例的SOC监控方法还可以包括，每个节点监控模块根据监控主控模块的控制指令控制与其对应的被监控节点。从而使得监控主控模块在定位出SOC内出现总线访问异常的器件的基础上，还可以控制SOC内的器件。
可选地，所述每个节点监控模块根据监控主控模块的控制指令控制与其对应的被监控节点，可以包括，节点监控模块接收监控主控模块发送的控制指令；在接收到控制指令时，节点监控模块解析控制指令；节点监控模块判断解析后的控制指令中是否包括自身的标识信息；在不包括自身的标识信息时，节点监控模块将该控制指令发送给与其串联的下一级节点监控模块；在包括自身的标识信息时，节点监控模块根据控制指令中的控制命令，对自身监测的被监控节点执行相应的操作。
其中，所述控制指令可以复位、开启或关闭等命令；相应的操作可以为复位、开启或关闭等操作。所述监控主控模块发送的控制指令可以为，监控主控模根据与其连接的SOC外部设备的指示发送的，还可以为监控主 控模块主动发送的。
需说明的是，所述SOC内的总线可以为现有技术中常用的总线，如可以为AMBA(Advanced Microcontroller Bus Architecture，高级微处理器总线结构)系列总线，或可以为AXI(Advanced eXtensible Interface，高级可扩展接口)总线，这些总线的传输协议通常规定主设备(Master)与从属设备(Slave)之间通过握手信号来进行数据传输。
为了实现上述方法，本发明公开了一种片上系统SOC的监控装置。本实施例提供的所述装置，可包括至少一个节点监控模块，配置为监测SOC内被监控节点的总线访问行为，获得所述被监控节点的总线监测信息；将所述总线监测信息发送给与所述节点监控模块连接的监控主控模块。这里的总线监测信息可供所述监控主控模块或与所述监控主控模块连接的设备进行访问异常分析的数据，从而定位导致总线访问异常的异常点。这里的异常点可发生在被监控节点以及总线自身等。
例如，图2为本发明实施例提供的一种片上系统SOC的监控装置的结构示意图，如图2所示，所述SOC的监控装置包括：
至少一个节点监控模块201，配置为监测SOC内被监控节点的总线访问行为，获得所述被监控节点的总线监测信息；将所述总线监测信息、及自身的标识信息作为所述被监控节点的总线监测结果，通过所述节点监控模块与监控主控模块建立的串行通信链路，发送给所述监控主控模块；
监控主控模块202，配置为接收所述总线监测结果。
上述自身的标识信息可为所述节点监控模块201的标识信息，通过该标识信息可以标识被监控节点。
可选地，所述监控主控模块202，还配置为将所述总线监测结果发送给SOC外部设备。
可选地，所述至少一个节点监控模块201，配置为接收SOC内与其对 应的被监控节点的总线访问相关信息；根据接收到的所述总线访问相关信息判断与其对应的所述被监控节点的总线访问行为是否异常；将所述总线访问相关信息，及所述总线访问行为是异常的判断结果作为与其对应的所述被监控节点的总线监测信息。
可选地，所述至少一个节点监控模块201，配置为将自身监测获得的所述总线监测信息，及自身的标识信息作为自身监测的所述被监控节点的总线监测结果；所述各个节点监控模块分为第一节点监控模块和第二节点监控模块；所述第一所述节点监控模块，具体用于将自身监测获得的所述总线监测结果，及从上一级第一所述节点监控模块接收到的所述总线监测结果，发送给下一级第一所述节点监控模块；所述第二所述节点监控模块，具体用于将自身监测获得的所述总线监测结果，及从上一级第一所述节点监控模块接收到的所述总线监测结果，发送给所述监控主控模块；
其中，所述第一节点监控模块是指与其串联的下一级节点为节点监控模块的节点监控模块；所述第二节点监控模块是指与其串联的下一级节点为监控主控模块的节点监控模块。
可选地，所述监控主控模块202，还配置为通过与SOC内的总线建立的通信链路，监测各个所述被监控节点的状态。
在实际应用中，所述节点监控模块201、监控主控模块202均可由中央处理器、微处理器(Micro Processor Unit，MPU)、数字信号处理器、或现场可编程门阵列(Field Programmable Gate Array，FPGA)等实现。
为了实现上述方法，本发明还公开了另一种片上系统SOC的监控装置。
图3A为本发明实施例提供的另一种片上系统SOC的监控装置的结构示意图，如图3A所示，所述SOC的监控装置包括：
监控主控模块202和至少一个节点监控模块201；
所述监控主控模块202与所述节点监控模块201串联连接，所述节点 监控模块201的第一总线接口与SOC内被监控节点203的总线接口连接，所述节点监控模块201的第二总线接口与SOC内的总线204连接；在包括多个所述节点监控模块时，所述节点监控模块201与所述监控主控模块202串联连接具体为：多个所述节点监控模块201相互串联连接，形成节点监控模块串联电路，所述节点监控模块串联电路与所述监控主控模块202串联连接。
可选地，所述监控主控模块202的总线接口与所述SOC内的总线204连接。
可选地，所述监控主控模块202与SOC外部设备连接。
图3B为本发明提供的另一种片上系统SOC的监控装置具体实施例的结构示意图，如图3B所示，SOC的监控装置监测SOC内的各个器件的总线访问行为；SOC内各个器件包括高速接口301、低速接口一302、存储器303、DMA 304、加速器N 305、加速器一306、DSP 307及CPU 308，高速接口301、低速接口一302处的虚线，表示高速接口301和低速接口一302为与SOC外部设备通信的接口；SOC内的总线为AMBA总线，SOC的监控装置具体包括：监控主控模块202和多个节点监控模块201；如图4所示，节点监控模块201包括总线监控模块2011和节点监控收发模块2012。
总线监控模块2011，配置为监测与其连接的SOC内器件的总线访问行为，获得与其连接的SOC内器件的总线监测信息；将该总线监测信息发送给节点监控收发模块2012。
节点监控收发模块2012，配置为将总线监控模块2011发送的总线监测信息，及节点监控模块201的标识信息，作为与总线监控模块2011连接的SOC内器件的总线监测结果存放在其内的寄存器中；通过各个节点监控模块与监控主控模块建立的串行通信链路，将总线监测结果发送给监控主控模块。
监控主控模块，配置为接收总线监测结果；根据与其连接的SOC外部设备发送的获取指令，将总线监测结果发送至与其连接的SOC外部设备；根据SOC外部设备的查询指令通过与SOC内的总线建立的通信链路，监测SOC内的各个器件的状态。
其中，所述根据SOC外部设备的查询指令通过与SOC内的总线建立的通信链路，监测SOC内的各个器件的状态包括，将SOC外部设备发送的查询指令通过SOC内的总线发送至SOC内的各个器件；SOC内的各个器件根据查询指令从自身的寄存器中读取相应信息，并将该查询信息作为查询结果通过SOC内的总线发送给监控主控模块202；监控主控模块202将查询结果发送至SOC外部设备。
SOC的监控装置与SOC内的各个器件及SOC内的总线的连接方式为，各个节点监控模块201一端与SOC内的各个器件连接，各个节点监控模块201另一端与AMBA总线的Crossbar(互联交换矩阵)309连接。监控主控模块202与AMBA总线的Crossbar309连接，使得监控主控模块可以灵活地监控SOC内各个器件的状态；监控主控模块202处的虚线表示监控主控模块202与SOC外部设备通信的接口。SOC的监控装置的监控主控模块202和各个节点监控模块201的连接方式为，监控主控模块202和各个节点监控模块201均具有发送Tx接口310和接收Rx接口311，每个Rx接口311均与上一级的Tx接口310串接，从而建立了环形串行通信链路。从而使得SOC的监控装置可以不受节点监控模块数目的影响，即在需增加节点监控模块时，可直接向环形串行通信链路中串接节点监控模块，在需减少节点监控模块时，可直接从环形串行通信链路中移除节点监控模块；同时，在制作SOC的监控装置的电路板时，可以减少该电路板的走线，减少节点监控模块数目的变化对制作的影响。
SOC的监控装置与SOC内的各个器件及SOC内的总线的连接方式具 体为，节点监控模块201的总线监控模块2011一端的第一总线接口与SOC内的器件的总线接口连接，总线监控模块2011另一端的第二总线接口与AMBA总线的Crossbar309连接；可选地，总线监控模块2011另一端的第二总线接口的M(Master)接口312与AMBA总线的Crossbar309的S(Slave)接口313连接，总线监控模块2011另一端的第二总线接口的S接口313与AMBA总线的Crossbar309的M接口312连接。SOC的监控装置内的监控主控模块202和各个节点监控模块201的连接方式具体为，节点监控模块201的节点监控收发模块2012的Rx接口311与上一级的Tx接口310串接，节点监控收发模块2012的Tx接口310与下一级的Rx接口311串接。
可选地，如图5所示，监控主控模块202包括控制器2021、片内存储器2022、总线隔离模块2023、总控收发模块2024、低速接口二2025及总控Crossbar2027。
其中，总控收发模块2024，配置为接收总线监测结果；将总线监测结果通过总控Crossbar2027发送至片内存储器2022。总控收发模块2024在实际应用中可以为串口控制器。在总控收发模块2024接收到信息时，总控收发模块2024可以产生中断信号发送至控制器2021。
其中，片内存储器2022，配置为存储总线监测结果。在实际应用中还存储控制器2021的程序，该程序使得控制器2021可以执行控制器2021所需执行的操作；也可以用于存储其它数据；其内存大小可以根据控制器2021程序的数据量大小及节点监控模块201的数目进行调整。其中，控制器2021的程序可以通过低速接口二2025下载至片内存储器2022，或者通过SOC的高速接口301、低速接口一302下载至片内存储器2022。
其中，低速接口二2025，配置为接收SOC外部设备发送的获取指令，将获取指令通过总控Crossbar2027发送至控制器2021，将接收到的总线监测结果发送至SOC外部设备；接收SOC外部设备发送的查询指令，通过总 控Crossbar2027发送至控制器2021，接收查询结果，将接收到的查询结果发送至SOC外部设备。在低速接口二2025接收到信息时，低速接口二2025可以产生中断信号发送至控制器2021。
其中，控制器2021，配置为接收获取指令；从片内存储器2022读取总线监测结果，将总线监测结果通过总控Crossbar2027发送至低速接口二2025；接收查询指令，通过总控Crossbar2027发送至总线隔离模块2023，接收查询结果，并将查询结果通过总控Crossbar2027发送至低速接口二2025。控制器2021在实际应用中控制器2021可以为CPU或DSP等控制器，在对控制器2021性能要求不高的情况下，为了节省SOC的面积及成本，控制器2021可以采用低能耗的CPU或DSP等控制器。
其中，总线隔离模块2023，配置为接收查询指令，将查询指令通过AMBA总线的Crossbar309发送至SOC内的各个器件，接收SOC内的各个器件的查询结果，将查询结果通过总控Crossbar2027发送至控制器2021。
可选地，为了防止SOC的总线的访问异常问题被引入到监控主控模块202的总线，总线隔离模块2023，配置为在监控主控模块202与SOC内器件通过总线通信，总线隔离模块监测到未接收到SOC内器件向监控主控模块202发送的握手信号时，总线隔离模块产生一个握手信号并发送到监控主控模块202的总控Crossbar2027上。
可选地，监控主控模块202还可以包括定时器2026；相应的，控制器2021，可配置为通过设置定时器定时地查询低速接口二2052是否有接收到获取指令，在低速接口接收到获取指令时，控制器2021接收该获取指令。在定时器2026计时结束时，定时器2026可以产生中断信号发送至控制器2021。
可选地，总线监控模块2011，配置为接收与其连接的SOC内器件的总线访问相关信息；根据接收到的总线访问相关信息判断与其连接的SOC内 器件的总线访问行为是否异常；将总线访问相关信息，及总线访问行为是异常的判断结果作为与其连接的SOC内器件的总线监测信息。
可选地，控制器2021，可配置为将接收到的获取指令通过总控Crossbar2027发送至总控收发模块2024。总控收发模块2024，具体还用于将接收到的获取指令通过串行通信链路发送至各个节点监控模块201。相应的，节点监控收发模块2012，具体用于接收监控主控模块202发送的获取指令；在接收到获取指令时，解析获取指令；判断解析后的获取指令中是否包括自身的标识信息；在不包括自身的标识信息时，将该获取指令发送给与其串联的下一级节点监控模块；在包括自身的标识信息时，通过各个节点监控模块201与监控主控模块202建立的串行通信链路，将与总线监控模块2011连接的SOC内器件的总线监测结果发送给监控主控模块。
可选地，节点监控收发模块2012，或者配置为通过各个节点监控模块201与监控主控模块202建立的串行通信链路，自动将与总线监控模块2011连接的SOC内器件的总线监测结果发送给监控主控模块。
可选地，为了在定位出SOC内出现总线访问异常的器件的基础上，控制SOC内的器件，如图4所示，节点监控模块201还可以包括与节点监控收发模块2012连接的控制模块2013，控制模块2013还与总线监控模块2021监测的SOC内器件相连接。控制模块2013，具体用于接收控制指令；对与总线监控模块2021监测的SOC内器件执行相应的操作。其中，所述控制指令可以复位、开启或关闭等命令；相应的操作可以为复位、开启或关闭等操作。可选地，可以包括多个控制模块2013，不同的控制模块2013对SOC内器件执行不同的操作。在实际应用中，控制模块2013可以为CPU或DSP等。
可选地，为了在定位出SOC内出现总线访问异常的器件的基础上，使得节点监控模块还可以与加速器器件的其它接口通信，其它接口是指除总 线接口以外的接口，如图4所示，节点监控模块201还可以包括与节点监控收发模块2012连接的加速器接口模块2014，该加速器接口模块2014可以与总线监控模块2021监测的SOC内加速器器件的其它接口相连接。可选地，可以包括多个加速器接口模块2014，不同的加速器接口模块2014与SOC内加速器器件的不同接口连接。在实际应用中，加速器接口模块2014可以为CPU或DSP等。
可选地，节点监控收发模块2012，配置为接收监控主控模块202发送的指令；解析接收到的指令；在判定解析后的指令为控制指令时将该指令发送给控制模块2013；在判定解析后的指令为获取指令时将该指令发送给总线监控模块2011；在判定解析后的指令为加速器接口通信指令时将该指令发送给加速器接口2014。其中，总线监控模块2011还用于接收获取指令，将与其连接的SOC内器件的总线监测结果发送给节点监控收发模块2012。其中，控制指令可以为SOC外部设备发送给监控主控模块202的。
其中，总线监控模块2011在实际应用中可以为具有总线接口的CPU或DSP等，节点监控收发模块2012可以为具有Tx、Rx接口的CPU或DSP等。
图6为本发明提供的一种片上系统SOC的监控方法具体实施例一的流程示意图，如图6所示，具体步骤包括：
步骤601：各个节点监控模块监测SOC内各个器件的总线访问行为，获得各个器件的总线监测信息，将自身监测获得的总线监测信息及自身的ID作为自身监测的SOC内器件的总线监测结果。
可选地，在实际应用中，节点监控模块可以由CPU或DSP等实现。所述SOC内各个器件可以包括，SOC内的CPU、DSP、DMA、各种硬件加速器、各种存储器以及各种外设接口等器件。
步骤602：监控主控模块判断自身是否有接收到SOC外部设备发送的 指令。在接收到指令时，执行步骤603，否则，执行步骤602。
可选地，在实际应用中，监控主控模块可以由CPU或DSP等实现。所述SOC外部设备可以为个人计算机、移动终端等终端设。
步骤603：监控主控模块解析接收到的指令，并将解析后的指令以第一预定数据格式，通过各个节点监控模块与监控主控模块建立的串行通信链路，发送给节点监控模块。
其中，所述第一预定数据格式为节点监控模块可以识别的数据格式。
步骤604：节点监控模块解析接收到的指令，并判断解析后的指令中是否包括自身的ID，在不包括自身的ID时，将该指令发送给与其串联的下一级节点监控模块。
步骤605：在包括自身的ID时，节点监控模块判断接收到的指令是否为获取指令。
步骤606：在是获取指令时，节点监控模块将自身监测的SOC内器件的总线监测结果，通过各个节点监控模块与监控主控模块建立的串行通信链路，发送给监控主控模块。
步骤607：监控主控模块接收总线监测结果，并将该总线监测结果发送给SOC外部设备。
图7为本发明提供的一种片上系统SOC的监控方法具体实施例二的流程示意图，如图7所示，具体步骤包括：
步骤701：各个节点监控模块监测SOC内各个器件的总线访问行为，获得各个器件的总线监测信息，将自身监测获得的总线监测信息及自身的ID作为自身监测的SOC内器件的总线监测结果。
可选地，所述各个节点监控模块监测SOC内各个器件的总线访问行为，获得各个器件的总线监测信息，可以包括，每个节点监控模块接收SOC内与其对应的器件的总线访问相关信息；每个节点监控模块根据接收到的总 线访问相关信息判断与其对应的器件的总线访问行为是否异常；每个节点监控模块将总线访问相关信息，及总线访问行为是异常的判断结果作为与其对应的器件的总线监测信息。
可选地，在实际应用中，节点监控模块可以由CPU或DSP等实现。所述SOC内各个器件可以包括，SOC内的CPU、DSP、DMA、各种硬件加速器、各种存储器以及各种外设接口等器件。
步骤702：每个节点监控模块自动通过各个节点监控模块与监控主控模块建立的串行通信链路，将总线监测结果发送给监控主控模块。
可选地，在实际应用中，监控主控模块可以由CPU或DSP等实现。
步骤703：监控主控模块接收并存储总线监测结果。
步骤704：监控主控模块判断其是否有接收到SOC外部设备发送的指令。
步骤705：在接收到指令时，监控主控模块判断接收到的指令是否为获取指令，在是获取指令时，监控主控模块将其已存储的总线监测结果发送给SOC外部设备。
图8为本发明提供的一种片上系统SOC的监控方法具体实施例三的流程示意图，如图8所示，具体步骤包括：
步骤801：监控主控模块判断其是否有接收到SOC外部设备发送的指令。
可选地，在实际应用中，监控主控模块可以由CPU或DSP等实现。所述SOC外部设备可以为个人计算机、移动终端等终端设。
步骤802：在接收到指令时，监控主控模块判断接收到的指令是否为查询指令。
步骤803：在是查询指令时，监控主控模块通过与SOC内的总线建立的通信链路，将查询指令发送给SOC内相应的器件。
步骤804：SOC内相应的器件根据查询指令从其寄存器中读取相应的信息，并将该信息作为查询结果通过SOC内的总线发送给监控主控模块。
步骤805：监控主控模块接收查询结果，并将该查询结果发送给SOC外部设备。
本发明实施例还提供一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行前述任意一个所述片上系统SOC的监控方法，例如，如图1及图6至图8中的一个或多个所示的方法。所述计算机存储介质可包括光盘、磁盘、随机存储介质RAM、只读存储介质ROM或闪存Flash等各种存储介质，优选的为非瞬间存储介质。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，凡按照本发明原理所作的修改，都应当理解为落入本发明的保护范围。

Claims (16)

  1. 一种片上系统SOC的监控方法，所述方法包括：
    节点监控模块监测SOC内被监控节点的总线访问行为，获得所述被监控节点的总线监测信息；
    将所述总线监测信息发送给与所述节点监控模块连接的监控主控模块。
  2. 根据权利要求1所述的方法，其中，
    所述将所述总线监测信息发送给与所述节点监控模块连接的监控主控模块，包括：
    所述节点监控模块将所述总线监测信息、及所述节点监控模块的标识信息作为所述被监控节点的总线监测结果，通过所述节点监控模块与监控主控模块建立的串行通信链路，发送给所述监控主控模块。
  3. 根据权利要求2所述的方法，其中，所述发送给所述监控主控模块之后，还包括：
    所述监控主控模块将所述总线监测结果发送给SOC外部设备。
  4. 根据权利要求2所述的方法，其中，所述节点监控模块监测SOC内被监控节点的总线访问行为，获得所述被监控节点的总线监测信息，包括：
    每个节点监控模块接收SOC内与其对应的被监控节点的总线访问相关信息；
    每个所述节点监控模块根据接收到的所述总线访问相关信息判断与其对应的所述被监控节点的总线访问行为是否异常；
    每个所述节点监控模块将所述总线访问相关信息，及所述总线访问行为是异常的判断结果作为与其对应的所述被监控节点的总线监测信息。
  5. 根据权利要求2所述的方法，其中，所述节点监控模块将所述总线监测信息、及自身的标识信息作为所述被监控节点的总线监测结果，通过所述节点监控模块与监控主控模块建立的串行通信链路，发送给所述监控主控模块，包括：
    各个所述节点监控模块将自身监测获得的所述总线监测信息，及自身的标识信息作为自身监测的所述被监控节点的总线监测结果；
    每个第一所述节点监控模块将自身监测获得的所述总线监测结果，及从上一级第一所述节点监控模块接收到的所述总线监测结果，发送给下一级第一所述节点监控模块；
    第二所述节点监控模块将自身监测获得的所述总线监测结果，及从上一级第一所述节点监控模块接收到的所述总线监测结果，发送给所述监控主控模块；
    其中，所述第一节点监控模块是指与其串联的下一级节点为节点监控模块的节点监控模块；所述第二节点监控模块是指与其串联的下一级节点为监控主控模块的节点监控模块。
  6. 根据权利要求2所述的方法，其中，所述方法还包括：
    所述监控主控模块通过与SOC内的总线建立的通信链路，监测各个所述被监控节点的状态。
  7. 一种片上系统SOC的监控装置，所述装置包括：
    至少一个节点监控模块，配置为监测SOC内被监控节点的总线访问行为，获得所述被监控节点的总线监测信息；将所述总线监测信息发送给与所述节点监控模块连接的监控主控模块。
  8. 根据权利要求7所述的装置，其中，
    所述节点监控模块，配置为将所述总线监测信息、及自身的标识信息作为所述被监控节点的总线监测结果，通过所述节点监控模块与监控主控 模块建立的串行通信链路，发送给所述监控主控模块；
    监控主控模块，配置为接收所述总线监测结果。
  9. 根据权利要求8所述的装置，其中，所述监控主控模块，还配置为将所述总线监测结果发送给SOC外部设备。
  10. 根据权利要求8所述的装置，其中，所述至少一个节点监控模块，配置为接收SOC内与其对应的被监控节点的总线访问相关信息；根据接收到的所述总线访问相关信息判断与其对应的所述被监控节点的总线访问行为是否异常；将所述总线访问相关信息，及所述总线访问行为是异常的判断结果作为与其对应的所述被监控节点的总线监测信息。
  11. 根据权利要求8所述的装置，其中，所述至少一个节点监控模块，配置为将自身监测获得的所述总线监测信息，及自身的标识信息作为自身监测的所述被监控节点的总线监测结果；所述各个节点监控模块分为第一节点监控模块和第二节点监控模块；所述第一所述节点监控模块，陪孩子为将自身监测获得的所述总线监测结果，及从上一级第一所述节点监控模块接收到的所述总线监测结果，发送给下一级第一所述节点监控模块；所述第二所述节点监控模块，配置为将自身监测获得的所述总线监测结果，及从上一级第一所述节点监控模块接收到的所述总线监测结果，发送给所述监控主控模块；
    其中，所述第一节点监控模块是指与其串联的下一级节点为节点监控模块的节点监控模块；所述第二节点监控模块是指与其串联的下一级节点为监控主控模块的节点监控模块。
  12. 根据权利要求8所述的装置，其中，所述监控主控模块，还配置为通过与SOC内的总线建立的通信链路，监测各个所述被监控节点的状态。
  13. 一种片上系统SOC的监控装置，所述装置包括：监控主控模块和至少一个节点监控模块；
    所述监控主控模块与所述节点监控模块串联连接，所述节点监控模块的第一总线接口与SOC内被监控节点的总线接口连接，所述节点监控模块的第二总线接口与SOC内的总线连接；在包括多个所述节点监控模块时，所述节点监控模块与所述监控主控模块串联连接为：多个所述节点监控模块相互串联连接，形成节点监控模块串联电路，所述节点监控模块串联电路与所述监控主控模块串联连接。
  14. 根据权利要求13所述的装置，其中，所述监控主控模块的总线接口与所述SOC内的总线连接。
  15. [根据细则26改正25.10.2016]　
    根据权利要求13所述的装置，其中，所述监控主控模块与SOC外部设备连接。
  16. [根据细则26改正25.10.2016]　
    一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行权利要求1至7任一项所述片上系统SOC的监控方法。
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