WO2017092279A1 - Igbt rear surface manufacturing method and igbt structure - Google Patents

Igbt rear surface manufacturing method and igbt structure Download PDF

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WO2017092279A1
WO2017092279A1 PCT/CN2016/085835 CN2016085835W WO2017092279A1 WO 2017092279 A1 WO2017092279 A1 WO 2017092279A1 CN 2016085835 W CN2016085835 W CN 2016085835W WO 2017092279 A1 WO2017092279 A1 WO 2017092279A1
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film layer
semiconductor thin
thin film
back surface
silicon
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PCT/CN2016/085835
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French (fr)
Chinese (zh)
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肖海波
罗海辉
刘国友
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株洲中车时代电气股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET

Definitions

  • the present invention relates to the field of semiconductor device technologies, and in particular, to a method for fabricating an IGBT back surface and an IGBT structure.
  • the carrier injection efficiency of the collector of an insulated gate bipolar transistor largely determines the switching characteristics and conduction voltage drop of the device.
  • the injection ratio in the homojunction mainly depends on the doping concentration ratio of the N region and the P region, and therefore the carrier injection efficiency is generally adjusted by adjusting the doping concentration of the P-type collector.
  • the doping concentration of the high P-type collector region can improve the implantation efficiency and reduce the on-state voltage drop of the device.
  • the carrier in the base region is too high when turned on, the carrier extraction rate is slow at the turn-off, resulting in a long turn-off time. Therefore, the method of adjusting the carrier injection efficiency by adjusting the doping concentration of the P-type collector has a contradiction between lowering the conduction voltage drop and increasing the switching speed.
  • the invention provides an IGBT back surface fabrication method and an IGBT structure, which are used to solve the technical problem that the IGBT in the prior art cannot simultaneously reduce the conduction voltage drop and increase the switching speed.
  • An aspect of the present invention provides a method for fabricating an IGBT back surface, including:
  • a back metal electrode is deposited on the third back side.
  • the first semiconductor thin film layer is amorphous silicon, microcrystalline silicon, carbon doped amorphous silicon or carbon doped microcrystalline silicon
  • the second semiconductor thin film layer is silicon germanium, germanium or germanium doped microcrystalline silicon.
  • the first semiconductor thin film layer is silicon germanium, germanium or germanium doped microcrystalline silicon
  • the second semiconductor thin film layer is amorphous silicon, microcrystalline silicon, carbon doped amorphous silicon or carbon doped microcrystalline silicon.
  • the first semiconductor thin film layer and the dielectric layer are sequentially deposited on the first back surface, and specifically include:
  • a buffer layer is formed on the first back surface, and a first semiconductor thin film layer and a dielectric layer are sequentially deposited on the buffer layer.
  • the dielectric layer is silicon oxide, silicon nitride or silicon oxynitride.
  • Another aspect of the present invention provides an IGBT structure including a first semiconductor thin film layer and a second semiconductor thin film layer overlying a back surface substrate of an IGBT, and a back metal covering the first semiconductor thin film layer and the second semiconductor thin film layer And an electrode, wherein a band gap of the substrate is between a band gap of the first semiconductor film layer and a band gap of the second semiconductor film layer.
  • the first semiconductor thin film layer is amorphous silicon, microcrystalline silicon, carbon doped amorphous silicon or carbon doped microcrystalline silicon
  • the second semiconductor thin film layer is silicon germanium, germanium or germanium doped microcrystalline silicon.
  • the first semiconductor thin film layer is silicon germanium, germanium or germanium doped microcrystalline silicon
  • the second semiconductor thin film layer is amorphous silicon, microcrystalline silicon, carbon doped amorphous silicon or carbon doped microcrystalline silicon.
  • the substrate includes a buffer layer, and the first semiconductor thin film layer and the second semiconductor thin film layer are overlaid on the buffer layer.
  • the IGBT back surface fabrication method and the IGBT structure proposed by the present invention after the silicon wafer is subjected to the front side process, the back surface is thinned to a desired thickness, and the first semiconductor film layer is sequentially deposited on the first back surface or the substrate.
  • a dielectric layer then photolithography and etching the first semiconductor thin film layer and the dielectric layer, and retaining the first semiconductor thin film layer and the dielectric layer of the first region to obtain a second back surface, and depositing a second semiconductor thin film layer on the second back surface, the light
  • the second semiconductor film layer and the dielectric layer are etched and etched, and the second semiconductor film layer of the second region is left to obtain a third back surface, and finally the back metal electrode is deposited on the third back surface, and the IGBT back surface is completed.
  • the band gap of the first semiconductor film layer is higher than the band gap of the first back surface and the band gap of the second semiconductor film layer is lower than that of the first back surface, or the band gap of the first semiconductor film layer is smaller than that of the first back surface layer
  • the gap is low and the band gap of the second semiconductor film layer is higher than the band gap of the first back surface, that is, by selecting materials of different band gaps for the first semiconductor film layer and the second semiconductor film layer, using the first semiconductor film layer and the second
  • the difference between the semiconductor film layer and the first back surface is to adjust the carrier injection efficiency and the conduction voltage drop.
  • the band gap of the first semiconductor film layer is higher than the band gap of the first back surface, the current carrying current The sub-injection efficiency is high, and the on-voltage of the device is lowered.
  • the turn-off since the band gap of the second semiconductor thin film layer is lower than the band gap of the first back surface, the carrier extraction rate is fast, and the device can be quickly turned off and lowered. Turn off the loss and increase the operating frequency of the device.
  • FIG. 1 is a schematic flow chart of a method for fabricating a back surface of an IGBT according to Embodiment 1 of the present invention
  • FIG. 2 is a schematic structural diagram of an IGBT structure according to Embodiment 2 of the present invention.
  • FIG. 3 is a schematic structural diagram of an IGBT structure according to Embodiment 3 of the present invention.
  • FIG. 1 is a schematic flow chart of a method for fabricating a back surface of an IGBT according to a first embodiment of the present invention. As shown in FIG. 1 , the present invention provides a method for fabricating a back surface of an IGBT, including:
  • step 101 a first semiconductor thin film layer and a dielectric layer are sequentially deposited on the first back surface, and the first back surface is divided into a first region and a second region.
  • the first back surface here is a silicon substrate of an IGBT, and the silicon substrate may be N-type doped or P-type doped.
  • Depositing a first semiconductor thin film layer and a dielectric layer on the first back surface that is, depositing a first semiconductor thin film layer on the first back surface, then depositing a dielectric layer on the first semiconductor thin film layer, and dividing the first back surface into One area and two areas.
  • first semiconductor thin film layer and the dielectric layer are sequentially deposited on the first back surface, and specifically include:
  • a buffer layer is formed on the first back surface, and a first semiconductor thin film layer and a dielectric layer are sequentially deposited on the buffer layer.
  • a buffer layer is first formed on the first back surface, and the buffer layer may be N-type doped or P-type doped. If the first back surface is N-type doped, the buffer layer here is N-type doped. Buffer layer, if the first back surface is P-type doped, the buffer layer here should be a P-type doping buffer layer, and the doping concentration of the buffer layer should be higher than the doping concentration of the first back surface, the buffer layer can be Improve the withstand voltage performance of IGBTs.
  • the dielectric layer is silicon oxide, silicon nitride or silicon oxynitride.
  • the dielectric layer herein can effectively protect the first semiconductor film layer from being etched away when a portion of the second semiconductor film layer is removed in a subsequent step.
  • Step 102 Photolithography and etching the first semiconductor thin film layer and the dielectric layer of the second region, and retaining the first semiconductor thin film layer and the dielectric layer of the first region to obtain a second back surface.
  • photolithography means that a photoresist plate is coated on a photoresist-coated silicon wafer, and then the silicon wafer is irradiated with ultraviolet rays for a certain period of time.
  • the principle is to use ultraviolet rays to deteriorate part of the photoresist. , easy to corrode. After the etching is photolithography, the deteriorated portion of the photoresist is etched away with an etching solution.
  • the first semiconductor thin film layer may be P-type doped or N-type doped as needed, and the specific doping type needs to be opposite to the doping type of the first back surface. If the first back surface is N-type doped, the first semiconductor thin film layer Then it is P-type doping.
  • Step 103 depositing a second semiconductor thin film layer on the second back surface; wherein a band gap of the first back surface is between a band gap of the first semiconductor thin film layer and a band gap of the second semiconductor thin film layer.
  • the band gap of the first semiconductor film layer may be higher than the band gap of the first back surface and the band gap of the second semiconductor film layer is lower than the band gap of the first back surface, and the band gap of the first semiconductor film layer may also be set.
  • the band gap is lower than the first back surface and the band gap of the second semiconductor film layer is higher than the band gap of the first back surface.
  • the band gap of the first semiconductor thin film layer and the second semiconductor thin film layer itself can be adjusted by the content of the gas and the enthalpy, and the gas is a carbon-containing gas such as methane.
  • the second semiconductor thin film layer may be P-doped or N-doped as needed, and the specific doping type needs to be opposite to the doping type of the first back surface. If the first back surface is N-type doped, then the second semiconductor thin film layer Then it is P-type doping.
  • the first semiconductor thin film layer is amorphous silicon, microcrystalline silicon, carbon doped amorphous silicon or carbon doped microcrystalline silicon
  • the second semiconductor thin film layer is silicon germanium, germanium or germanium doped microcrystalline silicon.
  • the first semiconductor thin film layer is deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD), and the first semiconductor thin film layer is amorphous silicon, microcrystalline silicon, carbon doped amorphous silicon or carbon doped Microcrystalline silicon, specifically on the first back surface, decomposes silane (SiH4) by PECVD, using a power generator of a frequency such as radio frequency or microwave, and then adds borane (B2H6) according to the P-type doping concentration requirement.
  • the doping concentration can be adjusted according to the needs of the P-type collector, and the process parameters such as deposition pressure, temperature and power, etc., can be controlled by adjusting the time and power to control the thickness of the first semiconductor film layer.
  • the second semiconductor film layer is silicon germanium, germanium or germanium doped microcrystalline silicon, specifically on the second back surface, by PECVD, using a power generator of radio frequency or microwave frequency to decompose the germanium fluoride (GeF4), and then according to P-type doping concentration requirement, adding borane (B2H6), the doping concentration can be adjusted according to the needs of the P-type collection area, and the process parameters such as deposition pressure, temperature and power are adjusted. Time and power to control the thickness of the first semiconductor film layer.
  • the band gap of the amorphous silicon is higher than the band gap of the silicon substrate, the carrier injection efficiency is high, the on-voltage of the device is lowered, and the band gap of the silicon germanium (SiGe) is lower than that of the silicon substrate.
  • the gap is lower and the carrier extraction rate is fast, which can quickly turn off the device, reduce the turn-off loss, and increase the operating frequency of the device.
  • the fabrication temperature of the first semiconductor thin film layer and the second semiconductor thin film layer on the back surface is not higher than the melting temperature of the front metal, the high temperature annealing process is not required to activate the impurity, thereby reducing the thermal budget of the silicon wafer.
  • the first semiconductor thin film layer is silicon germanium, germanium or germanium doped microcrystalline silicon
  • the second semiconductor thin film layer is amorphous silicon, microcrystalline silicon, carbon doped amorphous silicon or carbon doped microcrystalline silicon.
  • Step 104 photolithography and etching a second semiconductor thin film layer and a dielectric layer overlying the first semiconductor thin film layer, and retaining the second semiconductor thin film layer of the second region to obtain a third back surface.
  • photolithography and etching cover the second semiconductor thin film layer on the first semiconductor thin film layer and the dielectric layer remaining in step 102, and retain the second semiconductor thin film layer in the second region, where the second region is the first A portion of the back surface on which the first region is removed, that is, the remaining first semiconductor film layer and the second semiconductor film layer are overlaid on the first back surface.
  • Step 105 depositing a back metal electrode on the third back side.
  • a back metal electrode is deposited on the third back surface to complete the fabrication of the back surface of the IGBT.
  • the IGBT back surface fabrication method provided by the present invention has a band gap of the first semiconductor film layer being higher than a band gap of the first back surface and a band gap of the second semiconductor film layer being lower than a band gap of the first back surface, or a first semiconductor film layer
  • the band gap is lower than the band gap of the first back surface and the band gap of the second semiconductor film layer is higher than the band gap of the first back surface, and the band gap between the first semiconductor film layer and the second semiconductor film layer and the first back surface, respectively
  • the difference is to adjust the carrier injection efficiency and the conduction voltage drop.
  • the carrier injection efficiency is high, and the device conduction voltage is lowered.
  • the carrier extraction rate is fast, the device can be quickly turned off, the turn-off loss is reduced, and the operating frequency of the device is improved.
  • the IGBT in this embodiment is obtained by the IGBT back surface fabrication method in the first embodiment.
  • the present invention provides an IGBT including a first semiconductor thin film layer 2 and a second semiconductor thin film overlying the IGBT back substrate 1. a layer 3, and a back metal electrode 4 covering the first semiconductor film layer 2 and the second semiconductor film layer 3, wherein the band gap of the substrate 1 is between the band gap of the first semiconductor film layer 2 and the second semiconductor film Between the band gaps of layer 3.
  • the IGBT provided by the present invention has a band gap of the first semiconductor thin film layer 2 higher than that of the substrate 1 and a band gap of the second semiconductor thin film layer 3 is lower than that of the substrate 1, or the first semiconductor thin film layer 2 Band gap
  • the band gap between the first semiconductor thin film layer 2 and the second semiconductor thin film layer 3 and the substrate 1 is different from that of the substrate 1 by the band gap of the second semiconductor thin film layer 3 being higher than that of the substrate 1.
  • the difference is used to adjust the carrier injection efficiency and the on-state voltage drop.
  • the band gap of the first semiconductor thin film layer 2 is higher than the band gap of the substrate 1, the efficiency of injecting carriers into the P-type collector to the collector region High, the device's on-voltage is reduced.
  • the carrier extraction rate is fast, the device can be quickly turned off, and the turn-off is reduced. Loss, increase the operating frequency of the device.
  • the first semiconductor thin film layer 2 is amorphous silicon, microcrystalline silicon, carbon doped amorphous silicon or carbon doped microcrystalline silicon
  • the second semiconductor thin film layer 3 is silicon germanium, germanium or germanium doped microcrystalline silicon.
  • the first semiconductor thin film layer 2 is silicon germanium, germanium or germanium doped microcrystalline silicon
  • the second semiconductor thin film layer 3 is amorphous silicon, microcrystalline silicon, carbon doped amorphous silicon or carbon doped microcrystalline silicon.
  • the carrier injection efficiency is high, the device conduction voltage is lowered, and the shutdown is performed.
  • the carrier extraction rate is fast, which can quickly turn off the device, reduce the turn-off loss, and improve the device operation. frequency.
  • the fabrication temperature of the first semiconductor thin film layer and the second semiconductor thin film layer formed on the back surface is not higher than the melting temperature of the front metal, the high temperature annealing process is not required to activate the impurity, thereby reducing the thermal budget of the silicon wafer.
  • FIG. 3 is a schematic structural diagram of an IGBT structure according to Embodiment 3 of the present invention.
  • the substrate 1 includes a buffer layer 5, a first semiconductor thin film layer 2, and a second semiconductor.
  • the film layer 3 is covered on the buffer layer 5.
  • This buffer layer 5 can improve the withstand voltage performance of the IGBT.
  • the thickness of the first semiconductor thin film layer and the second semiconductor thin film layer are the same as that of the second semiconductor thin film layer.
  • the thickness of the first semiconductor film layer and the second semiconductor film layer are different.

Abstract

Provided are an insulated gate bipolar transistor (IGBT) rear surface manufacturing method and an IGBT structure, comprising: sequentially depositing a first semiconductor thin-film layer (2) and a dielectric layer onto a first rear surface (1), retaining only the first semiconductor thin-film layer (1) and the dielectric layer of a first area, then depositing a second semiconductor thin-film layer (3), and retaining only the second semiconductor thin-film layer (3) of a second area. The efficiency in charge carrier injection and extraction is regulated by utilizing band gap differences between the first surface (1) and respectively the first semiconductor thin-film layer (2) and the second semiconductor thin-film layer (3), thus reducing conduction voltage drop while increasing switching speed.

Description

IGBT背面制作方法及IGBT结构IGBT back fabrication method and IGBT structure
相关申请的交叉引用Cross-reference to related applications
本申请要求享有于2015年11月30日提交的名称为“IGBT背面制作方法及IGBT”的中国专利申请CN201510849344.4的优先权，该申请的全部内容通过引用并入本文中。The present application claims priority to Chinese Patent Application No. CN201510849344.4, filed on Nov. 30, 2015, which is incorporated herein by reference.
技术领域Technical field
本发明涉及半导体器件技术领域，尤其涉及一种IGBT背面制作方法及IGBT结构。The present invention relates to the field of semiconductor device technologies, and in particular, to a method for fabricating an IGBT back surface and an IGBT structure.
背景技术Background technique
绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，简称IGBT)集电极的载流子注入效率，很大程度上决定了器件的开关特性与导通压降。根据半导体理论，同质结中注入比主要取决于N区和P区的掺杂浓度比，因此一般是通过调节P型集区的掺杂浓度来调节载流子注入效率。高的P型集区的掺杂浓度可提高注入效率，降低器件导通压降，但由于导通时基区载流子过高，关断时载流子抽取速率慢，导致关断时间长，因此，通过调节P型集区的掺杂浓度来调节载流子注入效率这种方法在降低导通压降与提高开关速度间存在矛盾。The carrier injection efficiency of the collector of an insulated gate bipolar transistor (IGBT) largely determines the switching characteristics and conduction voltage drop of the device. According to the semiconductor theory, the injection ratio in the homojunction mainly depends on the doping concentration ratio of the N region and the P region, and therefore the carrier injection efficiency is generally adjusted by adjusting the doping concentration of the P-type collector. The doping concentration of the high P-type collector region can improve the implantation efficiency and reduce the on-state voltage drop of the device. However, since the carrier in the base region is too high when turned on, the carrier extraction rate is slow at the turn-off, resulting in a long turn-off time. Therefore, the method of adjusting the carrier injection efficiency by adjusting the doping concentration of the P-type collector has a contradiction between lowering the conduction voltage drop and increasing the switching speed.
目前，亟需一种IGBT制作方法及IGBT结构来实现在降低导通压降的同时提高开关速度。At present, there is a need for an IGBT fabrication method and an IGBT structure to increase the switching speed while reducing the on-state voltage drop.
发明内容Summary of the invention
本发明提供一种IGBT背面制作方法及IGBT结构，用以解决现有技术中的IGBT不能同时实现降低导通压降和提高开关速度的技术问题。The invention provides an IGBT back surface fabrication method and an IGBT structure, which are used to solve the technical problem that the IGBT in the prior art cannot simultaneously reduce the conduction voltage drop and increase the switching speed.
本发明一方面提供一种IGBT背面制作方法，包括：An aspect of the present invention provides a method for fabricating an IGBT back surface, including:
在第一背面上依次沉积第一半导体薄膜层和电介质层，并将第一背面划分成第一区域与第二区域； Depositing a first semiconductor thin film layer and a dielectric layer on the first back surface, and dividing the first back surface into a first region and a second region;
光刻和刻蚀第二区域的第一半导体薄膜层和电介质层，并保留第一区域的第一半导体薄膜层和电介质层，以获得第二背面；Photolithography and etching the first semiconductor thin film layer and the dielectric layer of the second region, and retaining the first semiconductor thin film layer and the dielectric layer of the first region to obtain a second back surface;
在第二背面沉积第二半导体薄膜层，其中，第一背面的带隙介于第一半导体薄膜层的带隙与第二半导体薄膜层的带隙之间；Depositing a second semiconductor thin film layer on the second back surface, wherein a band gap of the first back surface is between a band gap of the first semiconductor thin film layer and a band gap of the second semiconductor thin film layer;
光刻和刻蚀覆盖在第一半导体薄膜层上的第二半导体薄膜层和电介质层，并保留第二区域的第二半导体薄膜层，以获得第三背面；Photolithography and etching a second semiconductor thin film layer and a dielectric layer overlying the first semiconductor thin film layer, and retaining the second semiconductor thin film layer of the second region to obtain a third back surface;
在第三背面沉积背面金属电极。A back metal electrode is deposited on the third back side.
在一个具体的实施例中，第一半导体薄膜层为非晶硅、微晶硅、掺碳非晶硅或者掺碳微晶硅，第二半导体薄膜层为硅锗、锗或者掺锗微晶硅。In a specific embodiment, the first semiconductor thin film layer is amorphous silicon, microcrystalline silicon, carbon doped amorphous silicon or carbon doped microcrystalline silicon, and the second semiconductor thin film layer is silicon germanium, germanium or germanium doped microcrystalline silicon. .
在一个具体的实施例中，第一半导体薄膜层为硅锗、锗或者掺锗微晶硅，第二半导体薄膜层为非晶硅、微晶硅、掺碳非晶硅或者掺碳微晶硅。In a specific embodiment, the first semiconductor thin film layer is silicon germanium, germanium or germanium doped microcrystalline silicon, and the second semiconductor thin film layer is amorphous silicon, microcrystalline silicon, carbon doped amorphous silicon or carbon doped microcrystalline silicon. .
在一个具体的实施例中，在第一背面上依次沉积第一半导体薄膜层和电介质层，具体包括：In a specific embodiment, the first semiconductor thin film layer and the dielectric layer are sequentially deposited on the first back surface, and specifically include:
在第一背面上形成缓冲层，在缓冲层上依次沉积第一半导体薄膜层和电介质层。A buffer layer is formed on the first back surface, and a first semiconductor thin film layer and a dielectric layer are sequentially deposited on the buffer layer.
在一个具体的实施例中，电介质层为氧化硅、氮化硅或者氮氧化硅。In a specific embodiment, the dielectric layer is silicon oxide, silicon nitride or silicon oxynitride.
本发明另一方面提供一种IGBT结构，包括覆盖在IGBT背面衬底上的第一半导体薄膜层和第二半导体薄膜层，以及覆盖在第一半导体薄膜层和第二半导体薄膜层上的背面金属电极，其中，衬底的带隙介于第一半导体薄膜层的带隙与第二半导体薄膜层的带隙之间。Another aspect of the present invention provides an IGBT structure including a first semiconductor thin film layer and a second semiconductor thin film layer overlying a back surface substrate of an IGBT, and a back metal covering the first semiconductor thin film layer and the second semiconductor thin film layer And an electrode, wherein a band gap of the substrate is between a band gap of the first semiconductor film layer and a band gap of the second semiconductor film layer.
在一个具体的实施例中，第一半导体薄膜层为非晶硅、微晶硅、掺碳非晶硅或者掺碳微晶硅，第二半导体薄膜层为硅锗、锗或者掺锗微晶硅。In a specific embodiment, the first semiconductor thin film layer is amorphous silicon, microcrystalline silicon, carbon doped amorphous silicon or carbon doped microcrystalline silicon, and the second semiconductor thin film layer is silicon germanium, germanium or germanium doped microcrystalline silicon. .
在一个具体的实施例中，第一半导体薄膜层为硅锗、锗或者掺锗微晶硅，第二半导体薄膜层为非晶硅、微晶硅、掺碳非晶硅或者掺碳微晶硅。In a specific embodiment, the first semiconductor thin film layer is silicon germanium, germanium or germanium doped microcrystalline silicon, and the second semiconductor thin film layer is amorphous silicon, microcrystalline silicon, carbon doped amorphous silicon or carbon doped microcrystalline silicon. .
在一个具体的实施例中，衬底包括缓冲层，第一半导体薄膜层、第二半导体薄膜层覆盖在缓冲层上。In a specific embodiment, the substrate includes a buffer layer, and the first semiconductor thin film layer and the second semiconductor thin film layer are overlaid on the buffer layer.
本发明提出的IGBT背面制作方法及IGBT结构，在硅片进行完正面工艺之后，将背面减薄到所需厚度，在第一背面即衬底上依次沉积第一半导体薄膜层和 电介质层，然后光刻和刻蚀第一半导体薄膜层和电介质层，并保留第一区域的第一半导体薄膜层和电介质层，获得第二背面，在第二背面沉积第二半导体薄膜层，光刻和刻蚀第二半导体薄膜层和电介质层，并保留第二区域的第二半导体薄膜层，获得第三背面，最后在第三背面沉积背面金属电极，至此IGBT背面制作完成。由于第一半导体薄膜层的带隙比第一背面的带隙高且第二半导体薄膜层的带隙比第一背面的带隙低，或者第一半导体薄膜层的带隙比第一背面的带隙低且第二半导体薄膜层的带隙比第一背面的带隙高，即通过对第一半导体薄膜层和第二半导体薄膜层选择不同带隙的材料，利用第一半导体薄膜层和第二半导体薄膜层分别与第一背面间的带隙差来调节载流子注入效率和导通压降，当工作时，由于第一半导体薄膜层的带隙比第一背面的带隙高，载流子注入效率高，器件导通压降低，关断时，由于第二半导体薄膜层的带隙比第一背面的带隙低，载流子的抽取速率很快，可使器件快速关断，降低关断损耗，提高器件工作频率。The IGBT back surface fabrication method and the IGBT structure proposed by the present invention, after the silicon wafer is subjected to the front side process, the back surface is thinned to a desired thickness, and the first semiconductor film layer is sequentially deposited on the first back surface or the substrate. a dielectric layer, then photolithography and etching the first semiconductor thin film layer and the dielectric layer, and retaining the first semiconductor thin film layer and the dielectric layer of the first region to obtain a second back surface, and depositing a second semiconductor thin film layer on the second back surface, the light The second semiconductor film layer and the dielectric layer are etched and etched, and the second semiconductor film layer of the second region is left to obtain a third back surface, and finally the back metal electrode is deposited on the third back surface, and the IGBT back surface is completed. Since the band gap of the first semiconductor film layer is higher than the band gap of the first back surface and the band gap of the second semiconductor film layer is lower than that of the first back surface, or the band gap of the first semiconductor film layer is smaller than that of the first back surface layer The gap is low and the band gap of the second semiconductor film layer is higher than the band gap of the first back surface, that is, by selecting materials of different band gaps for the first semiconductor film layer and the second semiconductor film layer, using the first semiconductor film layer and the second The difference between the semiconductor film layer and the first back surface is to adjust the carrier injection efficiency and the conduction voltage drop. When working, since the band gap of the first semiconductor film layer is higher than the band gap of the first back surface, the current carrying current The sub-injection efficiency is high, and the on-voltage of the device is lowered. When the turn-off is performed, since the band gap of the second semiconductor thin film layer is lower than the band gap of the first back surface, the carrier extraction rate is fast, and the device can be quickly turned off and lowered. Turn off the loss and increase the operating frequency of the device.
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明的技术方案而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。Other features and advantages of the present invention will be set forth in the description which follows, and in part The objectives and other advantages of the invention may be realized and obtained by means of the structure particularly pointed in the appended claims.
附图说明DRAWINGS
附图用来提供对本申请的技术方案或现有技术的进一步理解，并且构成说明书的一部分。其中，表达本申请实施例的附图与本申请的实施例一起用于解释本申请的技术方案，但并不构成对本申请技术方案的限制。The drawings serve to provide a further understanding of the technical aspects of the present application or the prior art and form part of the specification. The drawings that express the embodiments of the present application are used to explain the technical solutions of the present application together with the embodiments of the present application, but do not constitute a limitation of the technical solutions of the present application.
图1为本发明实施例一提供的IGBT背面制作方法的流程示意图；1 is a schematic flow chart of a method for fabricating a back surface of an IGBT according to Embodiment 1 of the present invention;
图2为本发明实施例二提供的IGBT结构的结构示意图；2 is a schematic structural diagram of an IGBT structure according to Embodiment 2 of the present invention;
图3为本发明实施例三提供的IGBT结构的结构示意图。FIG. 3 is a schematic structural diagram of an IGBT structure according to Embodiment 3 of the present invention.
具体实施方式detailed description
本申请实施例以及实施例中的各个特征，在不相冲突前提下可以相互结合，所形成的技术方案均在本发明的保护范围之内。以下将结合附图及实施例来详细说明本发明的实施方式。The embodiments of the present application and the various features in the embodiments can be combined with each other without conflict, and the technical solutions formed are all within the protection scope of the present invention. Embodiments of the present invention will be described in detail below with reference to the drawings and embodiments.
实施例一 Embodiment 1
图1为根据本发明实施例一的IGBT背面制作方法的流程示意图，如图1所示，本发明提供一种IGBT背面制作方法，包括：1 is a schematic flow chart of a method for fabricating a back surface of an IGBT according to a first embodiment of the present invention. As shown in FIG. 1 , the present invention provides a method for fabricating a back surface of an IGBT, including:
步骤101，在第一背面上依次沉积第一半导体薄膜层和电介质层，并将第一背面划分成第一区域与第二区域。In step 101, a first semiconductor thin film layer and a dielectric layer are sequentially deposited on the first back surface, and the first back surface is divided into a first region and a second region.
具体的，在IGBT硅片进行完正面工艺之后，将背面减薄到所需厚度，并对IGBT硅片进行清洗处理。此处的第一背面即为IGBT的硅衬底，硅衬底可为N型掺杂也可为P型掺杂。在第一背面上依次沉积第一半导体薄膜层和电介质层，即先在第一背面上沉积第一半导体薄膜层，然后在第一半导体薄膜层上沉积电介质层，并将第一背面划分成第一区域与第二区域。Specifically, after the IGBT silicon wafer is subjected to the front surface process, the back surface is thinned to a desired thickness, and the IGBT silicon wafer is cleaned. The first back surface here is a silicon substrate of an IGBT, and the silicon substrate may be N-type doped or P-type doped. Depositing a first semiconductor thin film layer and a dielectric layer on the first back surface, that is, depositing a first semiconductor thin film layer on the first back surface, then depositing a dielectric layer on the first semiconductor thin film layer, and dividing the first back surface into One area and two areas.
进一步的，在第一背面上依次沉积第一半导体薄膜层和电介质层，具体包括：Further, the first semiconductor thin film layer and the dielectric layer are sequentially deposited on the first back surface, and specifically include:
在第一背面上形成缓冲层，在缓冲层上依次沉积第一半导体薄膜层和电介质层。A buffer layer is formed on the first back surface, and a first semiconductor thin film layer and a dielectric layer are sequentially deposited on the buffer layer.
具体的，在第一背面上首先形成缓冲层，缓冲层可为N型掺杂也可为P型掺杂，若第一背面为N型掺杂，则此处的缓冲层为N型掺杂缓冲层，若第一背面为P型掺杂，则此处的缓冲层应为P型掺杂缓冲层，缓冲层的掺杂浓度应比第一背面的掺杂浓度高，这层缓冲层可提高IGBT的耐电压性能。Specifically, a buffer layer is first formed on the first back surface, and the buffer layer may be N-type doped or P-type doped. If the first back surface is N-type doped, the buffer layer here is N-type doped. Buffer layer, if the first back surface is P-type doped, the buffer layer here should be a P-type doping buffer layer, and the doping concentration of the buffer layer should be higher than the doping concentration of the first back surface, the buffer layer can be Improve the withstand voltage performance of IGBTs.
进一步的，电介质层为氧化硅、氮化硅或者氮氧化硅。此处的电介质层可在后续步骤中的去除部分第二半导体薄膜层时，有效的保护第一半导体薄膜层不被腐蚀掉。Further, the dielectric layer is silicon oxide, silicon nitride or silicon oxynitride. The dielectric layer herein can effectively protect the first semiconductor film layer from being etched away when a portion of the second semiconductor film layer is removed in a subsequent step.
步骤102，光刻和刻蚀第二区域的第一半导体薄膜层和电介质层，并保留第一区域的第一半导体薄膜层和电介质层，获得第二背面。Step 102: Photolithography and etching the first semiconductor thin film layer and the dielectric layer of the second region, and retaining the first semiconductor thin film layer and the dielectric layer of the first region to obtain a second back surface.
具体的，光刻是指在涂满光刻胶的硅片上盖上事先做好的光刻板，然后用紫外线隔着光刻板对硅片进行一定时间的照射，原理就是利用紫外线使部分光刻胶变质，易于腐蚀。刻蚀是光刻后，用腐蚀液将变质的那部分光刻胶腐蚀掉。光刻和刻蚀第一半导体薄膜层和电介质层，并保留第一区域的第一半导体薄膜层和电介质层，获得第二背面，其中，第一区域可根据实际情况进行设置，在此不做限定，第二区域为第一背面上除去第一区域的部分。第一半导体薄膜层可根据需要进行P型掺杂或者N型掺杂，具体掺杂类型需要与第一背面的掺杂类型相反，如若第一背面为N型掺杂，那么第一半导体薄膜层则为P型掺杂。 Specifically, photolithography means that a photoresist plate is coated on a photoresist-coated silicon wafer, and then the silicon wafer is irradiated with ultraviolet rays for a certain period of time. The principle is to use ultraviolet rays to deteriorate part of the photoresist. , easy to corrode. After the etching is photolithography, the deteriorated portion of the photoresist is etched away with an etching solution. Photolithography and etching the first semiconductor thin film layer and the dielectric layer, and retaining the first semiconductor thin film layer and the dielectric layer of the first region to obtain a second back surface, wherein the first region can be set according to actual conditions, and no The second region is defined as a portion on the first back surface from which the first region is removed. The first semiconductor thin film layer may be P-type doped or N-type doped as needed, and the specific doping type needs to be opposite to the doping type of the first back surface. If the first back surface is N-type doped, the first semiconductor thin film layer Then it is P-type doping.
步骤103，在第二背面沉积第二半导体薄膜层；其中，第一背面的带隙介于第一半导体薄膜层的带隙与第二半导体薄膜层的带隙之间。 Step 103, depositing a second semiconductor thin film layer on the second back surface; wherein a band gap of the first back surface is between a band gap of the first semiconductor thin film layer and a band gap of the second semiconductor thin film layer.
具体的，可设置第一半导体薄膜层的带隙比第一背面的带隙高且第二半导体薄膜层的带隙比第一背面的带隙低，也可设置第一半导体薄膜层的带隙比第一背面的带隙低且第二半导体薄膜层的带隙比第一背面的带隙高。第一半导体薄膜层和第二半导体薄膜层本身的带隙可以通过通入气体及调整锗的含量来调整其带隙宽度，此处的气体为含碳元素的气体，如甲烷。第二半导体薄膜层可根据需要进行P型掺杂或者N型掺杂，具体掺杂类型需要与第一背面的掺杂类型相反，如若第一背面为N型掺杂，那么第二半导体薄膜层则为P型掺杂。Specifically, the band gap of the first semiconductor film layer may be higher than the band gap of the first back surface and the band gap of the second semiconductor film layer is lower than the band gap of the first back surface, and the band gap of the first semiconductor film layer may also be set. The band gap is lower than the first back surface and the band gap of the second semiconductor film layer is higher than the band gap of the first back surface. The band gap of the first semiconductor thin film layer and the second semiconductor thin film layer itself can be adjusted by the content of the gas and the enthalpy, and the gas is a carbon-containing gas such as methane. The second semiconductor thin film layer may be P-doped or N-doped as needed, and the specific doping type needs to be opposite to the doping type of the first back surface. If the first back surface is N-type doped, then the second semiconductor thin film layer Then it is P-type doping.
进一步的，第一半导体薄膜层为非晶硅、微晶硅、掺碳非晶硅或者掺碳微晶硅，第二半导体薄膜层为硅锗、锗或者掺锗微晶硅。Further, the first semiconductor thin film layer is amorphous silicon, microcrystalline silicon, carbon doped amorphous silicon or carbon doped microcrystalline silicon, and the second semiconductor thin film layer is silicon germanium, germanium or germanium doped microcrystalline silicon.
具体的，用等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，简称PECVD)沉积第一半导体薄膜层，第一半导体薄膜层为非晶硅、微晶硅、掺碳非晶硅或者掺碳微晶硅，具体可为在第一背面上，用PECVD，采用射频或微波等频率的功率发生器将硅烷(SiH4)分解，然后根据P型掺杂浓度需求，加入已硼烷(B2H6)，掺杂浓度可根据P型集区的需要进行气体流量比和工艺参数的调节，工艺参数比如有沉积压力、温度和功率等，通过调整时间和功率来控制第一半导体薄膜层的厚度。Specifically, the first semiconductor thin film layer is deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD), and the first semiconductor thin film layer is amorphous silicon, microcrystalline silicon, carbon doped amorphous silicon or carbon doped Microcrystalline silicon, specifically on the first back surface, decomposes silane (SiH4) by PECVD, using a power generator of a frequency such as radio frequency or microwave, and then adds borane (B2H6) according to the P-type doping concentration requirement. The doping concentration can be adjusted according to the needs of the P-type collector, and the process parameters such as deposition pressure, temperature and power, etc., can be controlled by adjusting the time and power to control the thickness of the first semiconductor film layer.
第二半导体薄膜层为硅锗、锗或者掺锗微晶硅，具体可为在第二背面上，用PECVD，采用射频或微波等频率的功率发生器将氟化锗(GeF4)分解，然后根据P型掺杂浓度需求，加入已硼烷(B2H6)，掺杂浓度可根据P型集区的需要进行气体流量比和工艺参数的调节，工艺参数比如有沉积压力、温度和功率等，通过调整时间和功率来控制第一半导体薄膜层的厚度。The second semiconductor film layer is silicon germanium, germanium or germanium doped microcrystalline silicon, specifically on the second back surface, by PECVD, using a power generator of radio frequency or microwave frequency to decompose the germanium fluoride (GeF4), and then according to P-type doping concentration requirement, adding borane (B2H6), the doping concentration can be adjusted according to the needs of the P-type collection area, and the process parameters such as deposition pressure, temperature and power are adjusted. Time and power to control the thickness of the first semiconductor film layer.
由于非晶硅带隙比硅衬底的带隙高，工作时，载流子注入效率高，器件导通压降低，而关断时，由于硅锗(SiGe)带隙比硅衬底的带隙更低，载流子的抽取速率很快，可使器件快速关断，降低关断损耗，提高器件工作频率。另外，由于在背面采用第一半导体薄膜层和第二半导体薄膜层的制作工艺温度不高于正面金属熔点，所以采用此种方法无需高温退火工艺来激活杂质，从而可降低硅片热预算。 Since the band gap of the amorphous silicon is higher than the band gap of the silicon substrate, the carrier injection efficiency is high, the on-voltage of the device is lowered, and the band gap of the silicon germanium (SiGe) is lower than that of the silicon substrate. The gap is lower and the carrier extraction rate is fast, which can quickly turn off the device, reduce the turn-off loss, and increase the operating frequency of the device. In addition, since the fabrication temperature of the first semiconductor thin film layer and the second semiconductor thin film layer on the back surface is not higher than the melting temperature of the front metal, the high temperature annealing process is not required to activate the impurity, thereby reducing the thermal budget of the silicon wafer.
进一步的，第一半导体薄膜层为硅锗、锗或者掺锗微晶硅，第二半导体薄膜层为非晶硅、微晶硅、掺碳非晶硅或者掺碳微晶硅。Further, the first semiconductor thin film layer is silicon germanium, germanium or germanium doped microcrystalline silicon, and the second semiconductor thin film layer is amorphous silicon, microcrystalline silicon, carbon doped amorphous silicon or carbon doped microcrystalline silicon.
具体可参见前文记载，在此不再赘述。For details, refer to the foregoing description, and details are not described herein again.
步骤104，光刻和刻蚀覆盖在第一半导体薄膜层上的第二半导体薄膜层和电介质层，并保留第二区域的第二半导体薄膜层，获得第三背面。 Step 104, photolithography and etching a second semiconductor thin film layer and a dielectric layer overlying the first semiconductor thin film layer, and retaining the second semiconductor thin film layer of the second region to obtain a third back surface.
具体的，光刻和刻蚀覆盖在第一半导体薄膜层上的第二半导体薄膜层和步骤102中保留的电介质层，保留第二区域的第二半导体薄膜层，此处第二区域为第一背面上除去第一区域的部分，即保留的第一半导体薄膜层和第二半导体薄膜层均覆盖在第一背面上。Specifically, photolithography and etching cover the second semiconductor thin film layer on the first semiconductor thin film layer and the dielectric layer remaining in step 102, and retain the second semiconductor thin film layer in the second region, where the second region is the first A portion of the back surface on which the first region is removed, that is, the remaining first semiconductor film layer and the second semiconductor film layer are overlaid on the first back surface.
步骤105，在第三背面沉积背面金属电极。 Step 105, depositing a back metal electrode on the third back side.
具体的，在第三背面沉积背面金属电极，以完成IGBT背面的制作。Specifically, a back metal electrode is deposited on the third back surface to complete the fabrication of the back surface of the IGBT.
本发明提供的IGBT背面制作方法，由于第一半导体薄膜层的带隙比第一背面的带隙高且第二半导体薄膜层的带隙比第一背面的带隙低，或者第一半导体薄膜层的带隙比第一背面的带隙低且第二半导体薄膜层的带隙比第一背面的带隙高，利用第一半导体薄膜层和第二半导体薄膜层分别与第一背面间的带隙差来调节载流子注入效率和导通压降，当工作时，由于第一半导体薄膜层的带隙比第一背面的带隙高，载流子注入效率高，器件导通压降低，关断时，由于第二半导体薄膜层的带隙比第一背面的带隙低，载流子的抽取速率很快，可使器件快速关断，降低关断损耗，提高器件工作频率。The IGBT back surface fabrication method provided by the present invention has a band gap of the first semiconductor film layer being higher than a band gap of the first back surface and a band gap of the second semiconductor film layer being lower than a band gap of the first back surface, or a first semiconductor film layer The band gap is lower than the band gap of the first back surface and the band gap of the second semiconductor film layer is higher than the band gap of the first back surface, and the band gap between the first semiconductor film layer and the second semiconductor film layer and the first back surface, respectively The difference is to adjust the carrier injection efficiency and the conduction voltage drop. When working, since the band gap of the first semiconductor film layer is higher than the band gap of the first back surface, the carrier injection efficiency is high, and the device conduction voltage is lowered, At the time of the break, since the band gap of the second semiconductor thin film layer is lower than the band gap of the first back surface, the carrier extraction rate is fast, the device can be quickly turned off, the turn-off loss is reduced, and the operating frequency of the device is improved.
实施例二 Embodiment 2
本实施例中的IGBT是根据实施例一中的IGBT背面制作方法获得的。The IGBT in this embodiment is obtained by the IGBT back surface fabrication method in the first embodiment.
图2为根据本发明实施例二的IGBT结构的结构示意图，如图2所示，本发明提供一种IGBT，包括覆盖在IGBT背面衬底1上的第一半导体薄膜层2和第二半导体薄膜层3，以及覆盖在第一半导体薄膜层2和第二半导体薄膜层3上的背面金属电极4，其中，衬底1的带隙介于第一半导体薄膜层2的带隙与第二半导体薄膜层3的带隙之间。2 is a schematic structural view of an IGBT structure according to a second embodiment of the present invention. As shown in FIG. 2, the present invention provides an IGBT including a first semiconductor thin film layer 2 and a second semiconductor thin film overlying the IGBT back substrate 1. a layer 3, and a back metal electrode 4 covering the first semiconductor film layer 2 and the second semiconductor film layer 3, wherein the band gap of the substrate 1 is between the band gap of the first semiconductor film layer 2 and the second semiconductor film Between the band gaps of layer 3.
本发明提供的IGBT，由于第一半导体薄膜层2的带隙比衬底1的带隙高且第二半导体薄膜层3的带隙比衬底1的带隙低，或者第一半导体薄膜层2的带隙 比衬底1的带隙低且第二半导体薄膜层3的带隙比衬底1的带隙高，利用第一半导体薄膜层2和第二半导体薄膜层3分别与衬底1间的带隙差来调节载流子注入效率和导通压降，当工作时，由于第一半导体薄膜层2的带隙比衬底1的带隙高，P型集区往集区注入载流子的效率高，器件导通压降低，关断时，由于第二半导体薄膜层3的带隙比衬底1的带隙低，载流子的抽取速率很快，可使器件快速关断，降低关断损耗，提高器件工作频率。The IGBT provided by the present invention has a band gap of the first semiconductor thin film layer 2 higher than that of the substrate 1 and a band gap of the second semiconductor thin film layer 3 is lower than that of the substrate 1, or the first semiconductor thin film layer 2 Band gap The band gap between the first semiconductor thin film layer 2 and the second semiconductor thin film layer 3 and the substrate 1 is different from that of the substrate 1 by the band gap of the second semiconductor thin film layer 3 being higher than that of the substrate 1. The difference is used to adjust the carrier injection efficiency and the on-state voltage drop. When operating, since the band gap of the first semiconductor thin film layer 2 is higher than the band gap of the substrate 1, the efficiency of injecting carriers into the P-type collector to the collector region High, the device's on-voltage is reduced. When turned off, since the band gap of the second semiconductor thin film layer 3 is lower than the band gap of the substrate 1, the carrier extraction rate is fast, the device can be quickly turned off, and the turn-off is reduced. Loss, increase the operating frequency of the device.
进一步的，第一半导体薄膜层2为非晶硅、微晶硅、掺碳非晶硅或者掺碳微晶硅，第二半导体薄膜层3为硅锗、锗或者掺锗微晶硅。Further, the first semiconductor thin film layer 2 is amorphous silicon, microcrystalline silicon, carbon doped amorphous silicon or carbon doped microcrystalline silicon, and the second semiconductor thin film layer 3 is silicon germanium, germanium or germanium doped microcrystalline silicon.
进一步的，第一半导体薄膜层2为硅锗、锗或者掺锗微晶硅，第二半导体薄膜层3为非晶硅、微晶硅、掺碳非晶硅或者掺碳微晶硅。Further, the first semiconductor thin film layer 2 is silicon germanium, germanium or germanium doped microcrystalline silicon, and the second semiconductor thin film layer 3 is amorphous silicon, microcrystalline silicon, carbon doped amorphous silicon or carbon doped microcrystalline silicon.
由于非晶硅、微晶硅、掺碳非晶硅或者掺碳微晶硅带隙比硅衬底的带隙高，工作时，载流子注入效率高，器件导通压降低，而关断时，由于硅锗、锗或者掺锗微晶硅的带隙比硅衬底的带隙更低，载流子的抽取速率很快，可使器件快速关断，降低关断损耗，提高器件工作频率。另外，由于在背面形成的第一半导体薄膜层和第二半导体薄膜层的制作工艺温度不高于正面金属熔点，所以采用此种方法无需高温退火工艺来激活杂质，从而可降低硅片热预算。Since the band gap of amorphous silicon, microcrystalline silicon, carbon-doped amorphous silicon or carbon-doped microcrystalline silicon is higher than that of the silicon substrate, the carrier injection efficiency is high, the device conduction voltage is lowered, and the shutdown is performed. When the band gap of silicon germanium, germanium or germanium-doped microcrystalline silicon is lower than that of the silicon substrate, the carrier extraction rate is fast, which can quickly turn off the device, reduce the turn-off loss, and improve the device operation. frequency. In addition, since the fabrication temperature of the first semiconductor thin film layer and the second semiconductor thin film layer formed on the back surface is not higher than the melting temperature of the front metal, the high temperature annealing process is not required to activate the impurity, thereby reducing the thermal budget of the silicon wafer.
进一步的，图3为根据本发明实施例三的IGBT结构的结构示意图，如图3所示，本发明提供的IGBT中，衬底1包括缓冲层5，第一半导体薄膜层2、第二半导体薄膜层3覆盖在缓冲层5上。这层缓冲层5可提高IGBT的耐电压性能。Further, FIG. 3 is a schematic structural diagram of an IGBT structure according to Embodiment 3 of the present invention. As shown in FIG. 3, in the IGBT provided by the present invention, the substrate 1 includes a buffer layer 5, a first semiconductor thin film layer 2, and a second semiconductor. The film layer 3 is covered on the buffer layer 5. This buffer layer 5 can improve the withstand voltage performance of the IGBT.
进一步的，第一半导体薄膜层与第二半导体薄膜层的厚度相同便于制作。Further, the thickness of the first semiconductor thin film layer and the second semiconductor thin film layer are the same as that of the second semiconductor thin film layer.
进一步的，第一半导体薄膜层与第二半导体薄膜层的厚度不相同。Further, the thickness of the first semiconductor film layer and the second semiconductor film layer are different.
虽然本发明所披露的实施方式如上，但所述的内容仅为便于理解本发明技术方案而采用的实施方式，并非用以限定本发明。任何本发明所属领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。 The embodiments disclosed in the present invention are as described above, but the description is only for the purpose of understanding the technical solutions of the present invention, and is not intended to limit the present invention. Any modification and variation in the form and details of the embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention. The scope defined by the appended claims shall prevail.

Claims (10)

  1. 一种IGBT背面制作方法，其中，包括：A method for fabricating an IGBT back surface, comprising:
    在第一背面上依次沉积第一半导体薄膜层和电介质层，并将第一背面划分成第一区域与第二区域；Depositing a first semiconductor thin film layer and a dielectric layer on the first back surface, and dividing the first back surface into a first region and a second region;
    光刻和刻蚀第二区域的第一半导体薄膜层和电介质层，并保留第一区域的第一半导体薄膜层和电介质层，以获得第二背面；Photolithography and etching the first semiconductor thin film layer and the dielectric layer of the second region, and retaining the first semiconductor thin film layer and the dielectric layer of the first region to obtain a second back surface;
    在第二背面沉积第二半导体薄膜层，其中，第一背面的带隙介于第一半导体薄膜层的带隙与第二半导体薄膜层的带隙之间；Depositing a second semiconductor thin film layer on the second back surface, wherein a band gap of the first back surface is between a band gap of the first semiconductor thin film layer and a band gap of the second semiconductor thin film layer;
    光刻和刻蚀覆盖在第一半导体薄膜层上的第二半导体薄膜层和电介质层，并保留第二区域的第二半导体薄膜层，以获得第三背面；Photolithography and etching a second semiconductor thin film layer and a dielectric layer overlying the first semiconductor thin film layer, and retaining the second semiconductor thin film layer of the second region to obtain a third back surface;
    在第三背面沉积背面金属电极。A back metal electrode is deposited on the third back side.
  2. 根据权利要求1所述的IGBT背面制作方法，其中，第一半导体薄膜层为非晶硅、微晶硅、掺碳非晶硅或者掺碳微晶硅，第二半导体薄膜层为硅锗、锗或者掺锗微晶硅。The method of fabricating a back surface of an IGBT according to claim 1, wherein the first semiconductor thin film layer is amorphous silicon, microcrystalline silicon, carbon-doped amorphous silicon or carbon-doped microcrystalline silicon, and the second semiconductor thin film layer is silicon germanium or germanium. Or doped with microcrystalline silicon.
  3. 根据权利要求1所述的IGBT背面制作方法，其中，第一半导体薄膜层为硅锗、锗或者掺锗微晶硅，第二半导体薄膜层为非晶硅、微晶硅、掺碳非晶硅或者掺碳微晶硅。The method of fabricating a back surface of an IGBT according to claim 1, wherein the first semiconductor thin film layer is silicon germanium, germanium or germanium doped microcrystalline silicon, and the second semiconductor thin film layer is amorphous silicon, microcrystalline silicon, carbon doped amorphous silicon. Or carbon doped microcrystalline silicon.
  4. 根据权利要求1所述的IGBT背面制作方法，其中，在第一背面上依次沉积第一半导体薄膜层和电介质层，具体包括：The IGBT back surface fabrication method according to claim 1, wherein the first semiconductor thin film layer and the dielectric layer are sequentially deposited on the first back surface, specifically comprising:
    在第一背面上形成缓冲层，在缓冲层上依次沉积第一半导体薄膜层和电介质层。A buffer layer is formed on the first back surface, and a first semiconductor thin film layer and a dielectric layer are sequentially deposited on the buffer layer.
  5. 根据权利要求1-4任一所述的IGBT背面制作方法，其中，电介质层为氧化硅、氮化硅或者氮氧化硅。The method of fabricating a back surface of an IGBT according to any one of claims 1 to 4, wherein the dielectric layer is silicon oxide, silicon nitride or silicon oxynitride.
  6. 一种IGBT结构，其中，包括覆盖在IGBT背面衬底上的第一半导体薄膜层和第二半导体薄膜层，以及覆盖在第一半导体薄膜层和第二半导体薄膜层上的背面金属电极，其中，衬底的带隙介于第一半导体薄膜层的带隙与第二半导体薄膜层的带隙之间。 An IGBT structure, comprising: a first semiconductor thin film layer and a second semiconductor thin film layer overlying a back surface substrate of the IGBT; and a back metal electrode covering the first semiconductor thin film layer and the second semiconductor thin film layer, wherein The band gap of the substrate is between the band gap of the first semiconductor film layer and the band gap of the second semiconductor film layer.
  7. 根据权利要求6所述的IGBT结构，其中，第一半导体薄膜层为非晶硅、微晶硅、掺碳非晶硅或者掺碳微晶硅，第二半导体薄膜层为硅锗、锗或者掺锗微晶硅。The IGBT structure according to claim 6, wherein the first semiconductor thin film layer is amorphous silicon, microcrystalline silicon, carbon doped amorphous silicon or carbon doped microcrystalline silicon, and the second semiconductor thin film layer is silicon germanium, germanium or doped.锗Microcrystalline silicon.
  8. 根据权利要求6所述的IGBT结构，其中，第一半导体薄膜层为硅锗、锗或者掺锗微晶硅，第二半导体薄膜层为非晶硅、微晶硅、掺碳非晶硅或者掺碳微晶硅。The IGBT structure according to claim 6, wherein the first semiconductor thin film layer is silicon germanium, germanium or germanium doped microcrystalline silicon, and the second semiconductor thin film layer is amorphous silicon, microcrystalline silicon, carbon doped amorphous silicon or doped. Carbon microcrystalline silicon.
  9. 根据权利要求6-8任一所述的IGBT结构，其特征在于，衬底包括缓冲层，第一半导体薄膜层、第二半导体薄膜层覆盖在缓冲层上。The IGBT structure according to any one of claims 6-8, wherein the substrate comprises a buffer layer, and the first semiconductor film layer and the second semiconductor film layer are overlaid on the buffer layer.
  10. 根据权利要求6-8任一所述的IGBT结构，其特征在于，第一半导体薄膜层与第二半导体薄膜层的厚度相同。 The IGBT structure according to any one of claims 6-8, wherein the first semiconductor film layer and the second semiconductor film layer have the same thickness.
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