WO2017085789A1 - Digital transmitter - Google Patents

Digital transmitter Download PDF

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Publication number
WO2017085789A1
WO2017085789A1 PCT/JP2015/082259 JP2015082259W WO2017085789A1 WO 2017085789 A1 WO2017085789 A1 WO 2017085789A1 JP 2015082259 W JP2015082259 W JP 2015082259W WO 2017085789 A1 WO2017085789 A1 WO 2017085789A1
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WIPO (PCT)
Prior art keywords
signal
circuit
modulation
digital
digital modulation
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PCT/JP2015/082259
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French (fr)
Japanese (ja)
Inventor
英之 中溝
檜枝　護重
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2017551425A priority Critical patent/JP6351871B2/en
Priority to PCT/JP2015/082259 priority patent/WO2017085789A1/en
Publication of WO2017085789A1 publication Critical patent/WO2017085789A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits

Definitions

  • the present invention relates to a digital transmitter for directly transmitting a digital modulation signal generated by a digital circuit such as a modem in a high frequency band.
  • Non-Patent Document 1 discloses a digital transmitter that directly transmits a digital modulation signal generated by a digital circuit such as a modem in a high frequency band.
  • the digital modulation signal generated by the modem is directly transmitted in the high frequency band, so that an analog circuit for converting the modulation signal in the baseband frequency band to the frequency in the high frequency band is not required, and the circuit configuration is simplified.
  • the digital modulation signal generated by the modem is delta-sigma-modulated and the digital signal after delta-sigma modulation is transmitted.
  • a ⁇ modulation circuit that outputs a modulation signal is mounted.
  • Non-Patent Document 2 below discloses a circuit configuration of a ⁇ modulation circuit.
  • the digital modulation signal generated by the modem can be transmitted directly in the high frequency band.
  • the digital modulation signal generated by the modem is delta-sigma modulated, ⁇ noise is generated in the vicinity of the desired modulation signal band. ) Deteriorated. Note that this ⁇ noise interferes with communication in adjacent channels and other communication in the adjacent frequency band, and causes deterioration in communication quality.
  • the present invention has been made to solve the above-described problems, and it is an object of the present invention to obtain a digital transmitter capable of reducing ⁇ noise accompanying delta-sigma modulation of a digital modulation signal and increasing a signal-to-noise ratio. Objective.
  • a digital transmitter modulates communication data to generate a digital modulation signal, and delta-sigma modulates the digital modulation signal generated by the modem and outputs a digital modulation signal after delta-sigma modulation.
  • the circuit configurations or operating conditions of the plurality of ⁇ modulation circuits are different, ⁇ noise associated with delta-sigma modulation of the digital modulation signal is reduced, and the signal-to-noise ratio is increased. There is an effect that can.
  • Embodiment 1 of this invention It is a block diagram which shows the digital transmitter by Embodiment 1 of this invention. It is a block diagram which shows the digital transmitter by Embodiment 2 of this invention. It is a block diagram which shows the digital transmitter by Embodiment 3 of this invention. It is a block diagram which shows the digital transmitter by Embodiment 4 of this invention. It is a block diagram which shows the delta-sigma modulation circuits 51 and 52 of the digital transmitter by Embodiment 4 of this invention. It is a block diagram which shows the delta-sigma modulation circuits 51 and 52 of the digital transmitter by Embodiment 5 of this invention. It is a block diagram which shows the modulation signal output circuit part 6 of the digital transmitter by Embodiment 6 of this invention.
  • FIG. 1 is a block diagram showing a digital transmitter according to Embodiment 1 of the present invention.
  • a modulation signal output circuit unit 1 is composed of a modem 11 and ⁇ modulation circuits 12 and 13, which modulate communication data to generate a digital modulation signal and delta-sigma modulate the digital modulation signal. It is.
  • the modem 11 modulates the communication data to generate a digital modulation signal, and outputs the digital modulation signal to the ⁇ modulation circuits 12 and 13.
  • the ⁇ modulation circuit 12 has a signal input terminal connected to a signal output terminal of the modem 11, and delta-sigma modulates the digital modulation signal output from the modem 11 and outputs a digital modulation signal after delta-sigma modulation. It is.
  • the ⁇ modulation circuit 13 has a signal input terminal connected to the signal output terminal of the modem 11 and has a circuit configuration different from that of the ⁇ modulation circuit 12, but the digital modulation output from the modem 11 is the same as the ⁇ modulation circuit 12.
  • the signal is delta-sigma modulated and a digitally modulated signal after delta-sigma modulation is output.
  • the high frequency unit 2 is a circuit composed of high frequency circuits 21 and 22 and a synthesis circuit 23.
  • the signal input terminal of the high frequency circuit 21 is connected to the signal output terminal of the ⁇ modulation circuit 12, and the signal power (signal level) of the digital modulation signal output from the ⁇ modulation circuit 12 is set to a desired power level (signal level).
  • the frequency of the digital modulation signal is converted from IF frequency (intermediate frequency) to RF frequency (radio frequency).
  • the high-frequency circuit 22 has a signal input terminal connected to a signal output terminal of the ⁇ modulation circuit 13, converts the signal power of the digital modulation signal output from the ⁇ modulation circuit 13 to a desired power level, and the digital modulation signal Is converted from IF frequency to RF frequency.
  • the high frequency circuits 21 and 22 convert the signal power of the digital modulation signal and the frequency, but either one of the signal power or the frequency conversion is converted. You can do it.
  • the high-frequency circuits 21 and 22 for example, an amplification circuit that inputs a 1-bit digital modulation signal and performs a switching operation, and a variable gain circuit that adjusts the signal power of the digital modulation signal to a desired power level
  • the circuit is composed of element circuits such as a frequency conversion circuit that converts the frequency of the digital modulation signal from IF frequency to RF frequency, and a filter circuit that suppresses unnecessary waves contained in the digital modulation signal.
  • another element circuit may be included.
  • the synthesizing circuit 23 has a first signal input terminal connected to a signal output terminal of the high frequency circuit 21 and a second signal input terminal connected to a signal output terminal of the high frequency circuit 22. The digital modulation signal and the digital modulation signal converted by the high frequency circuit 22 are combined to output a combined signal of the two digital modulation signals.
  • the modem 11 of the modulation signal output circuit unit 1 receives communication data including various kinds of information from the outside, the modem 11 modulates the communication data to generate a digital modulation signal, and the digital modulation signal is converted into the ⁇ modulation circuit 12. , 13 are output.
  • the digital modulation signal generated by the modem 11 for example, a digital modulation signal in which an amplitude value at each time of an analog modulation signal output from a general modem is represented by multiple bits can be considered.
  • the present invention is not limited to a multi-bit digital modulation signal.
  • the ⁇ modulation circuit 12 When receiving the digital modulation signal from the modem 11, the ⁇ modulation circuit 12 performs delta sigma modulation on the digital modulation signal and outputs the digital modulation signal after the delta sigma modulation to the high frequency circuit 21.
  • the ⁇ modulation circuit 13 When receiving the digital modulation signal from the modem 11, the ⁇ modulation circuit 13 performs delta sigma modulation on the digital modulation signal and outputs the digital modulation signal after the delta sigma modulation to the high frequency circuit 22.
  • the digital modulation signal after delta-sigma modulation output from the ⁇ modulation circuits 12 and 13 is a 1-bit or multi-bit digital modulation signal suitable for signal processing of the high-frequency circuits 21 and 22.
  • the characteristic of ⁇ noise generated when the ⁇ modulation circuits 12 and 13 perform delta-sigma modulation depends on the circuit configuration of the ⁇ modulation circuits 12 and 13. In the first embodiment, it is assumed that the circuit configurations of the ⁇ modulation circuit 12 and the ⁇ modulation circuit 13 are different. If the circuit configurations of the ⁇ modulation circuit 12 and the ⁇ modulation circuit 13 are different, the delta sigma is used. Since the modulation processing sequence is different, the characteristics of ⁇ noise are different. Thereby, the ⁇ noise component generated from the ⁇ modulation circuit 12 and the ⁇ noise component generated from the ⁇ modulation circuit 13 are incoherent.
  • the ⁇ modulation circuits 12 and 13 perform delta-sigma modulation on the same digital modulation signal output from the modem 11, the desired signal component of the digital modulation signal output from the ⁇ modulation circuit 12 and the ⁇ modulation are used.
  • the desired signal component of the digital modulation signal output from the circuit 13 is coherent.
  • Specific circuit configurations of the ⁇ modulation circuits 12 and 13 include a ⁇ modulation circuit in which the number of stages of a built-in ⁇ modulator described in a fourth embodiment described later is one, or a built-in circuit described in a fifth embodiment described later.
  • a ⁇ modulator circuit having two stages of ⁇ modulators is conceivable. For example, if the number of stages of the ⁇ modulator included in the ⁇ modulation circuit 12 is one and the number of stages of the ⁇ modulator included in the ⁇ modulation circuit 13 is 2, ⁇ generated from the ⁇ modulation circuit 12 The noise component and the ⁇ noise component generated from the ⁇ modulation circuit 13 become incoherent.
  • the high frequency circuit 21 When the high frequency circuit 21 receives the digital modulation signal after the delta sigma modulation from the ⁇ modulation circuit 12, the high frequency circuit 21 converts the signal power of the digital modulation signal into a desired power level and converts the frequency of the digital modulation signal from the IF frequency to the RF frequency. The frequency is converted to a frequency, and the converted digital modulation signal is output to the synthesis circuit 23.
  • the high frequency circuit 22 receives the digital modulation signal after delta-sigma modulation from the ⁇ modulation circuit 13
  • the high frequency circuit 22 converts the signal power of the digital modulation signal to a desired power level, and changes the frequency of the digital modulation signal from the IF frequency to the RF frequency.
  • the frequency is converted to a frequency, and the converted digital modulation signal is output to the synthesis circuit 23.
  • the converted digital modulation signal output from the high-frequency circuit 21 and the converted digital modulation signal output from the high-frequency circuit 22 have the same signal power and the same frequency.
  • the ⁇ noise component is incoherent, but the desired signal component of the digital modulation signal is coherent.
  • the combining circuit 23 combines the converted digital modulation signal output from the high frequency circuit 21 and the converted digital modulation signal output from the high frequency circuit 22 and outputs a combined signal of the two digital modulation signals. .
  • the desired signal components of the two digital modulation signals are coherent, the two desired signal components are voltage-added by the synthesis of the synthesis circuit 23.
  • the ⁇ noise components of the two digital modulation signals are incoherent, the ⁇ noise components of the two digital modulation signals are added by the synthesis of the synthesis circuit 23.
  • the signal-to-noise ratio which is the power ratio between the desired signal component and the ⁇ noise component in the combined signal output from the combining circuit 23, is the digital modulation signal output from each of the high frequency circuits 21 and 22.
  • the SNR of the desired signal component and the ⁇ noise component is theoretically improved by 3 dB.
  • the modem 11 that modulates communication data to generate a digital modulation signal, and the digital modulation signal generated by the modem 11 are delta-sigma modulated to produce a delta-sigma ⁇ modulation circuits 12 and 13 that output the modulated digital modulation signal, and the signal power of the digital modulation signal output from the ⁇ modulation circuits 12 and 13 is converted to a desired power level, and the frequency of the digital modulation signal is changed.
  • the high frequency circuits 21 and 22 for converting the IF frequency to the RF frequency, the digital modulation signal after the conversion by the high frequency circuit 21 and the digital modulation signal after the conversion by the high frequency circuit 22 are combined, and a combined signal of the two digital modulation signals And the circuit configuration of the ⁇ modulation circuits 12 and 13 is different. Since it is configured, by reducing the ⁇ noise associated with the delta-sigma modulation of digital modulation signals, an effect that can increase the SNR.
  • the modulation signal output circuit unit 1 includes two ⁇ modulation circuits 12 and 13 having different circuit configurations. However, the modulation signal output circuit unit 1 has a different circuit configuration.
  • the high-frequency unit 2 mounts N high-frequency circuits, and the combining circuit 23 combines the converted digital modulation signals output from the N high-frequency circuits. May be.
  • the high frequency unit 2 converts the signal power of the digital modulation signal output from the ⁇ modulation circuits 12 and 13 to a desired power level, and changes the frequency of the digital modulation signal from the IF frequency to the RF frequency.
  • the two digital modulation signals after the conversion are combined, and the digital modulation signals output from the ⁇ modulation circuits 12 and 13 are combined and then the combined signal of the two digital modulation signals. May be converted to a desired power level, and the frequency of the combined signal may be converted from the IF frequency to the RF frequency.
  • FIG. 2 is a block diagram showing a digital transmitter according to Embodiment 2 of the present invention.
  • the high frequency unit 3 is a circuit composed of a synthesis circuit 31 and a high frequency circuit 32.
  • the combining circuit 31 has a first signal input terminal connected to the signal output terminal of the ⁇ modulation circuit 12, and a second signal input terminal connected to the signal output terminal of the ⁇ modulation circuit 13.
  • the output digital modulation signal after delta sigma modulation and the digital modulation signal after delta sigma modulation output from the ⁇ modulation circuit 13 are combined, and a combined signal of the two digital modulation signals is output to the high frequency circuit 32.
  • the high frequency circuit 32 has a signal input terminal connected to a signal output terminal of the synthesis circuit 31, converts the signal power of the synthesis signal output from the synthesis circuit 31 to a desired power level, and converts the frequency of the synthesis signal to IF. Convert from frequency to RF frequency.
  • the high-frequency circuit 32 performs conversion of the signal power and frequency of the combined signal. However, any one of the conversion of signal power or frequency may be performed. Good.
  • the synthesizing circuit 31 synthesizes the digital modulation signal after the delta-sigma modulation output from the ⁇ modulation circuit 12 and the digital modulation signal after the delta-sigma modulation output from the ⁇ modulation circuit 13 to synthesize two digital modulation signals.
  • the combined signal is output.
  • the desired signal components of the two digital modulation signals are coherent, the two desired signal components are voltage-added by the synthesis of the synthesis circuit 31.
  • the synthesis of the synthesis circuit 31 causes the ⁇ noise components of the two digital modulation signals to be power addition.
  • the SNR that is the power ratio between the desired signal component and the ⁇ noise component in the combined signal output from the combining circuit 31 is equal to the desired signal component in the digital modulation signal output from each of the ⁇ modulation circuits 12 and 13 and ⁇ .
  • the theoretical improvement is 3 dB.
  • the high frequency circuit 32 When the high frequency circuit 32 receives the combined signal from the combining circuit 31, the high frequency circuit 32 converts the signal power of the combined signal into a desired power level and converts the frequency of the combined signal from the IF frequency to the RF frequency.
  • the modem 11 that modulates communication data to generate a digital modulation signal, and the digital modulation signal generated by the modem 11 are delta-sigma modulated to produce a delta-sigma ⁇ modulation circuits 12 and 13 for outputting the modulated digital modulation signal, the digital modulation signal after the delta-sigma modulation output from the ⁇ modulation circuit 12, and the digital modulation after the delta-sigma modulation output from the ⁇ modulation circuit 13 And combining the signal and outputting a combined signal of the two digital modulation signals, converting the signal power of the combined signal output from the combining circuit 31 to a desired power level, and changing the frequency of the combined signal And a high-frequency circuit 32 for converting the IF frequency to the RF frequency, and the ⁇ modulation circuits 12 and 13 have different circuit configurations.
  • the high frequency unit 3 combines the digital modulation signals output from the ⁇ modulation circuits 12 and 13 and then sets the power level and frequency of the signal power of the combined signal of the two digital modulation signals. Since conversion is performed, the number of high-frequency circuits can be reduced to one, and the circuit configuration can be simplified.
  • the modulation signal output circuit unit 1 includes two ⁇ modulation circuits 12 and 13 having different circuit configurations.
  • the modulation signal output circuit unit 1 has a different circuit configuration.
  • N number of ⁇ modulation circuits may be mounted, and the combining circuit 31 of the high-frequency unit 2 may combine the delta-sigma modulated digital modulation signals output from the N ⁇ modulation circuits.
  • Embodiment 3 the synthesis circuit 23 synthesizes the converted digital modulation signal output from the high-frequency circuit 21 and the converted digital modulation signal output from the high-frequency circuit 22 to produce two digital modulations.
  • the output of the composite signal of the signal is shown, the digital modulation signal radiated from the plurality of antennas is provided with a plurality of antennas that radiate the converted digital modulation signals output from the high-frequency circuits 21 and 22 to the space. You may make it synthesize
  • the high frequency section 4 is a circuit composed of high frequency circuits 21 and 22 and antennas 41 and 42.
  • the antenna 41 is connected to the signal output terminal of the high-frequency circuit 21 and radiates the converted digital modulation signal output from the high-frequency circuit 21 to the space.
  • the antenna 42 is connected to the signal output terminal of the high-frequency circuit 22 and radiates the converted digital modulation signal output from the high-frequency circuit 22 into space.
  • the high-frequency unit 4 When receiving the digital modulation signal after the delta-sigma modulation from the ⁇ modulation circuit 12, the high frequency circuit 21 converts the signal power of the digital modulation signal to a desired power level as well as the digital modulation signal, as in the first embodiment. The frequency of the modulation signal is converted from the IF frequency to the RF frequency, and the converted digital modulation signal is output. When receiving the digital modulation signal after the delta sigma modulation from the ⁇ modulation circuit 13, the high frequency circuit 22 converts the signal power of the digital modulation signal to a desired power level as well as the digital modulation signal, as in the first embodiment.
  • the frequency of the modulation signal is converted from the IF frequency to the RF frequency, and the converted digital modulation signal is output.
  • the converted digital modulation signal output from the high-frequency circuit 21 and the converted digital modulation signal output from the high-frequency circuit 22 have the same signal power and the same frequency.
  • the ⁇ noise component is incoherent, but the desired signal component of the digital modulation signal is coherent.
  • the antenna 41 When receiving the converted digital modulation signal from the high-frequency circuit 21, the antenna 41 radiates the digital modulation signal to space.
  • the antenna 42 receives the converted digital modulation signal from the high frequency circuit 22, the antenna 42 radiates the digital modulation signal to space.
  • the digital modulation signal radiated from the antenna 41 and the digital modulation signal radiated from the antenna 42 are combined in space.
  • the two desired signal components of the two digital modulation signals output from the high-frequency circuits 21 and 22 are coherent, the two desired signal components are voltage-added by synthesis in space.
  • the ⁇ noise components of the two digital modulation signals are incoherent, the ⁇ noise components of the two digital modulation signals are summed by combining in space.
  • the SNR which is the power ratio between the desired signal component and the ⁇ noise component in the signal synthesized in space, is the difference between the desired signal component and the ⁇ noise component in the digital modulation signal output from each of the high frequency circuits 21 and 22.
  • the theoretical improvement is 3 dB. Therefore, a receiver that is a communication target with the digital transmitter can receive a signal having a high SNR.
  • the modem 11 that modulates communication data to generate a digital modulation signal, and the digital modulation signal generated by the modem 11 are delta-sigma modulated to produce a delta-sigma ⁇ modulation circuits 12 and 13 that output the modulated digital modulation signal, and the signal power of the digital modulation signal output from the ⁇ modulation circuits 12 and 13 is converted to a desired power level, and the frequency of the digital modulation signal is changed.
  • the synthesis circuit 23 is not necessary.
  • Embodiment 4 FIG.
  • the modulation signal output circuit unit 1 is mounted with the ⁇ modulation circuits 12 and 13 having different circuit configurations.
  • the circuit configuration of the ⁇ modulation circuits 12 and 13 is provided. Therefore, the load of circuit development increases.
  • the fourth embodiment therefore, a case where a plurality of ⁇ modulation circuits having the same circuit configuration are mounted in the modulation signal output circuit section and different operating conditions are set for the plurality of ⁇ modulation circuits will be described.
  • the modulation signal output circuit unit 5 is a digital circuit including a modem 11, ⁇ modulation circuits 51 and 52, and a setting circuit 53.
  • the ⁇ modulation circuit 51 has a signal input terminal connected to the signal output terminal of the modem 11, and delta-sigma modulates the digital modulation signal output from the modem 11 and outputs a digital modulation signal after delta-sigma modulation. It is.
  • the ⁇ modulation circuit 52 is a circuit having the same circuit configuration as the ⁇ modulation circuit 51.
  • the ⁇ modulation circuit 52 has a signal input terminal connected to the signal output terminal of the modem 11, delta-sigma-modulates the digital modulation signal output from the modem 11, and outputs a digital modulation signal after delta-sigma modulation.
  • the setting circuit 53 is a circuit for setting different operating conditions for the ⁇ modulation circuits 51 and 52.
  • FIG. 5 is a block diagram showing ⁇ modulation circuits 51 and 52 of a digital transmitter according to Embodiment 4 of the present invention.
  • an initial value circuit 61 is a circuit that outputs an initial value of a digital modulation signal corresponding to the operating condition set by the setting circuit 53.
  • the setting circuit 53 sets different operating conditions for the ⁇ modulation circuits 51 and 52, the initial value output from the initial value circuit 61 of the ⁇ modulation circuit 51 and the initial value circuit 61 of the ⁇ modulation circuit 52 are It becomes a value different from the initial value to be output.
  • the PN signal generation circuit 62 is a circuit that generates a PN signal (pseudo noise signal) corresponding to the operating condition set by the setting circuit 53 and outputs the PN signal.
  • the setting circuit 53 sets different operating conditions for the ⁇ modulation circuits 51 and 52
  • the PN signal output from the PN signal generation circuit 62 of the ⁇ modulation circuit 51 and the PN signal generation circuit of the ⁇ modulation circuit 52 are set. The signal is different from the PN signal output by 62.
  • the adder 63 has a first signal input terminal connected to the signal output terminal of the modem 11, a second signal input terminal connected to the signal output terminal of the initial value circuit 61, and a third signal input terminal generating a PN signal.
  • the digital modulation signal output from the modem 11 is output from the initial value circuit 61.
  • the initial value and the pseudo noise signal output from the PN signal generation circuit 62 are added, and a digital modulation signal obtained by adding the initial value and the pseudo noise signal is output to the ⁇ modulator 64.
  • the digital noise signal output from the PN signal generation circuit 62 is added to the digital modulation signal output from the modem 11 to add the pseudo noise signal.
  • the modulation signal is output to the ⁇ modulator 64.
  • the signal input terminal of the ⁇ modulator 64 is connected to the signal output terminal of the adder 63, and the digital modulation signal output from the adder 63 is delta-sigma-modulated to output a digital modulation signal after delta-sigma modulation. It is a digital circuit.
  • the setting circuit 53 sets different operating conditions for the ⁇ modulation circuits 51 and 52.
  • the initial value circuit 61 of the ⁇ modulation circuits 51 and 52 outputs an initial value of a digital modulation signal corresponding to the operating condition to the adder 63. Since different operating conditions are set for the modulation circuits 51 and 52, the initial value output from the initial value circuit 61 of the ⁇ modulation circuit 51 is different from the initial value output from the initial value circuit 61 of the ⁇ modulation circuit 52. become.
  • any initial value may be used as long as the initial value is different, and it may be appropriately determined at the time of design.
  • the PN signal generating circuit 62 of the ⁇ modulation circuits 51 and 52 When the setting circuit 53 sets an operating condition, the PN signal generating circuit 62 of the ⁇ modulation circuits 51 and 52 generates a PN signal corresponding to the operating condition and outputs the PN signal to the adder 63. Since the circuit 53 sets different operating conditions for the ⁇ modulation circuits 51 and 52, the PN signal output from the PN signal generation circuit 62 of the ⁇ modulation circuit 51 and the PN signal generation circuit 62 of the ⁇ modulation circuit 52 output. The PN signal is different from the PN signal. In the fourth embodiment, any PN signal may be used as long as the PN signals are different, and may be appropriately determined at the time of design.
  • the adder 63 of the ⁇ modulation circuits 51 and 52 outputs the digital modulation signal output from the modem 11 from the initial value circuit 61 when the first clock of the clock group indicating the operation timing is input.
  • the initial value and the pseudo noise signal output from the PN signal generation circuit 62 are added, and a digital modulation signal obtained by adding the initial value and the pseudo noise signal is output to the ⁇ modulator 64.
  • the adder 63 of the ⁇ modulation circuits 51 and 52 receives the pseudo noise signal output from the PN signal generation circuit 62 in response to the digital modulation signal output from the modem 11. And the digital modulation signal added with the pseudo noise signal is output to the ⁇ modulator 64.
  • the ⁇ modulator 64 of the ⁇ modulation circuits 51 and 52 When receiving the digital modulation signal from the adder 63, the ⁇ modulator 64 of the ⁇ modulation circuits 51 and 52 performs delta sigma modulation on the digital modulation signal and outputs the digital modulation signal after the delta sigma modulation to the high frequency circuits 21 and 22. To do. Even if the circuit configurations of the ⁇ modulation circuits 51 and 52 are the same, if the initial value and the PN signal are different, the characteristic of ⁇ noise generated when delta-sigma modulation of the digital modulation signal output from the modem 11 is incoherent. become.
  • the desired signal component becomes coherent if the same digital modulation signal output from the modem 11 is subjected to delta sigma modulation.
  • the fourth embodiment an example is shown in which both the initial value and the PN signal are different.
  • the ⁇ noise characteristic is made incoherent and desired.
  • the signal component can be made coherent. Therefore, if the initial value output from the initial value circuit 61 of the ⁇ modulation circuit 51 and the initial value output from the initial value circuit 61 of the ⁇ modulation circuit 52 are different, the PN signal generation circuit of the ⁇ modulation circuits 51 and 52
  • the PN signals output from 62 may be the same.
  • the initial values of the ⁇ modulation circuits 51 and 52 are set.
  • the initial value output from the circuit 61 may be the same.
  • the modulation signal output circuit unit 5 is mounted with the ⁇ modulation circuits 51 and 52 having the same circuit configuration and is different from the ⁇ modulation circuits 51 and 52. Since the setting circuit 53 for setting the operating conditions is mounted, as in the first embodiment, the ⁇ noise associated with the delta-sigma modulation of the digital modulation signal can be reduced and the SNR can be increased. Compared with the case where the ⁇ modulation circuits 12 and 13 having different circuit configurations are mounted, the load required for the circuit development of the ⁇ modulation circuits 51 and 52 can be reduced.
  • Embodiment 5 the single-stage ⁇ modulation circuit in which the number of ⁇ modulators 64 included in the ⁇ modulation circuits 51 and 52 having the same circuit configuration is one is shown. However, the circuit configuration is the same.
  • the delta-sigma modulation circuits 51 and 52 may include a plurality of delta-sigma modulators having a plurality of delta-sigma modulators.
  • FIG. 6 is a block diagram showing ⁇ modulation circuits 51 and 52 of a digital transmitter according to Embodiment 5 of the present invention.
  • an initial value circuit 71 is a circuit that outputs a first initial value and a second initial value of a digital modulation signal corresponding to the operating condition set by the setting circuit 53.
  • the setting circuit 53 sets different operating conditions for the ⁇ modulation circuits 51 and 52
  • the first initial value output from the initial value circuit 71 of the ⁇ modulation circuit 51 and the initial value of the ⁇ modulation circuit 52 are set. It becomes a value different from the first initial value output from the circuit 71.
  • the second initial value output from the initial value circuit 71 of the ⁇ modulation circuit 51 is different from the second initial value output from the initial value circuit 71 of the ⁇ modulation circuit 52.
  • the PN signal generation circuit 72 generates a first PN signal and a second PN signal corresponding to the operating condition set by the setting circuit 53, and outputs the first PN signal and the second PN signal. It is. However, since the setting circuit 53 sets different operating conditions for the ⁇ modulation circuits 51 and 52, the first PN signal output from the PN signal generation circuit 72 of the ⁇ modulation circuit 51 and the PN of the ⁇ modulation circuit 52 are set. The signal is different from the first PN signal output from the signal generation circuit 72. Further, the second PN signal output from the PN signal generation circuit 72 of the ⁇ modulation circuit 51 is different from the second PN signal output from the PN signal generation circuit 72 of the ⁇ modulation circuit 52.
  • the offset generation circuit 73 is a circuit that generates an offset signal corresponding to the operating condition set by the setting circuit 53. However, since the setting circuit 53 sets different operating conditions for the ⁇ modulation circuits 51 and 52, the offset signal output from the offset generation circuit 73 of the ⁇ modulation circuit 51 and the offset generation circuit 73 of the ⁇ modulation circuit 52 It becomes a signal different from the offset signal to be output.
  • the adder 74 has a first signal input terminal connected to the signal output terminal of the modem 11, a second signal input terminal connected to the first signal output terminal of the initial value circuit 71, and a third signal input terminal
  • the digital modulation signal output from the modem 11 is A digital value obtained by adding the first initial value output from the initial value circuit 71 and the first PN signal output from the PN signal generation circuit 72 and adding the first initial value and the first PN signal.
  • the modulation signal is output to the ⁇ modulator 75.
  • the first PN signal output from the PN signal generation circuit 72 is added to the digital modulation signal output from the modem 11 to obtain the first PN signal.
  • a first adder that outputs a digital modulation signal obtained by adding to the ⁇ modulator 75.
  • the ⁇ modulator 75 has a signal input terminal connected to the signal output terminal of the adder 74, delta-sigma modulates the digital modulation signal output from the adder 74, and outputs a digital modulation signal after delta-sigma modulation. This is the first ⁇ modulator.
  • the adder 76 has a first signal input terminal connected to the signal output terminal of the ⁇ modulator 75, a second signal input terminal connected to the second signal output terminal of the initial value circuit 71, and a third signal input.
  • the terminal is connected to the second signal output terminal of the PN signal generation circuit 72, the fourth signal input terminal is connected to the offset generation circuit 73, and the first clock in the clock group indicating the operation timing is input.
  • the second PN signal output from the PN signal generation circuit 72 and the offset generation circuit 73 are output with respect to the digital modulation signal output from the ⁇ modulator 75.
  • the second adder outputs the digital modulation signal obtained by adding the offset signal and the second PN signal and the offset signal to the ⁇ modulator 77.
  • the ⁇ modulator 77 has a signal input terminal connected to the signal output terminal of the adder 76, and delta-sigma-modulates the digital modulation signal output from the adder 76 and outputs a digital modulation signal after delta-sigma modulation.
  • the adder 78 has a first signal input terminal connected to the ⁇ modulator 75 and a second signal input terminal connected to the ⁇ modulator 77, and the digital modulation signal output from the ⁇ modulator 75 and the ⁇ modulation.
  • the setting circuit 53 sets different operating conditions for the ⁇ modulation circuits 51 and 52.
  • the initial value circuit 71 of the ⁇ modulation circuits 51 and 52 adds the first initial value and the second initial value of the digital modulation signal corresponding to the operating condition to the adder 74 and
  • the first initial value output from the initial value circuit 71 of the ⁇ modulation circuit 51, and the ⁇ modulation circuit This is a value different from the first initial value output by the initial value circuit 71 of 52.
  • the second initial value output from the initial value circuit 71 of the ⁇ modulation circuit 51 is different from the second initial value output from the initial value circuit 71 of the ⁇ modulation circuit 52.
  • any initial value may be used as long as the initial value is different, and it may be appropriately determined at the time of design.
  • the PN signal generating circuit 72 of the ⁇ modulation circuits 51 and 52 When the setting circuit 53 sets an operating condition, the PN signal generating circuit 72 of the ⁇ modulation circuits 51 and 52 generates a first PN signal and a second PN signal corresponding to the operating condition, and the first PN signal is generated. The PN signal and the second PN signal are output to the adders 74 and 76, respectively. Since the setting circuit 53 sets different operating conditions for the ⁇ modulation circuits 51 and 52, the PN signal generation of the ⁇ modulation circuit 51 is performed. The first PN signal output from the circuit 72 is different from the first PN signal output from the PN signal generation circuit 72 of the ⁇ modulation circuit 52.
  • the second PN signal output from the PN signal generation circuit 72 of the ⁇ modulation circuit 51 is different from the second PN signal output from the PN signal generation circuit 72 of the ⁇ modulation circuit 52.
  • any PN signal may be used as long as the PN signals are different, and may be appropriately determined at the time of design.
  • the offset generating circuit 73 of the ⁇ modulation circuits 51 and 52 generates an offset signal corresponding to the operating condition and outputs the offset signal to the adder 76.
  • any offset signal may be used as long as the offset signals are different, and may be determined as appropriate at the time of design.
  • the adder 74 of the ⁇ modulation circuits 51 and 52 outputs the digital modulation signal output from the modem 11 from the initial value circuit 71 when the first clock of the clock group indicating the operation timing is input.
  • the first modulated initial value and the first PN signal output from the PN signal generation circuit 72 are added, and a digital modulation signal obtained by adding the first initial value and the first PN signal is added to the ⁇ modulator. Output to 75.
  • the adder 74 of the ⁇ modulation circuits 51 and 52 receives the first modulation signal output from the PN signal generation circuit 72 in response to the digital modulation signal output from the modem 11.
  • the digital modulation signal obtained by adding the PN signals and adding the first PN signal is output to the ⁇ modulator 75.
  • the ⁇ modulator 75 of the ⁇ modulation circuits 51 and 52 When receiving the digital modulation signal from the adder 74, the ⁇ modulator 75 of the ⁇ modulation circuits 51 and 52 performs delta sigma modulation on the digital modulation signal and outputs the digital modulation signal after the delta sigma modulation to the adders 76 and 78. To do.
  • the adder 76 of the ⁇ modulation circuits 51 and 52 receives an initial value circuit 71 for the digital modulation signal output from the ⁇ modulator 75 when the first clock of the clock group indicating the operation timing is input. , The second PN signal output from the PN signal generation circuit 72, and the offset signal output from the offset generation circuit 73 are added together to obtain a second initial value, A digital modulation signal obtained by adding the second PN signal and the offset signal is output to the ⁇ modulator 77. Further, when the second and subsequent clocks are input to the adder 76 of the ⁇ modulation circuits 51 and 52, the digital modulation signal output from the ⁇ modulator 75 is output from the PN signal generation circuit 72. The second PN signal and the offset signal output from the offset generation circuit 73 are added, and a digital modulation signal obtained by adding the second PN signal and the offset signal is output to the ⁇ modulator 77.
  • the ⁇ modulator 77 of the ⁇ modulation circuits 51 and 52 Upon receiving the digital modulation signal from the adder 76, the ⁇ modulator 77 of the ⁇ modulation circuits 51 and 52 performs delta sigma modulation on the digital modulation signal and outputs the digital modulation signal after the delta sigma modulation to the adder 78.
  • the adder 78 of the ⁇ modulation circuits 51 and 52 adds the digital modulation signal output from the ⁇ modulator 75 and the digital modulation signal output from the ⁇ modulator 77, and adds the added digital modulation signal to the high frequency circuit 21. , 22.
  • the first initial value, the first PN signal, the second initial value, the second PN signal, and the offset signal are all different from each other. If at least one of the first PN signal, the second initial value, the second PN signal, and the offset signal is different, the ⁇ noise characteristic is made incoherent, and the desired signal component is Can be coherent.
  • the modulation signal output circuit unit 5 is mounted with the ⁇ modulation circuits 51 and 52 having the same circuit configuration and is different from the ⁇ modulation circuits 51 and 52. Since the setting circuit 53 for setting the operating conditions is mounted, as in the first embodiment, the ⁇ noise associated with the delta-sigma modulation of the digital modulation signal can be reduced and the SNR can be increased. Compared with the case where the ⁇ modulation circuits 12 and 13 having different circuit configurations are mounted, the load required for the circuit development of the ⁇ modulation circuits 51 and 52 can be reduced.
  • the example in which the ⁇ modulators 75 and 77 having the same circuit configuration in the ⁇ modulation circuits 51 and 52 have a two-stage configuration is shown.
  • the ⁇ modulation circuits 51 and 52 are included in the internal circuit.
  • the delta-sigma modulator may have three or more stages.
  • the modulation signal output circuit unit 1 mounts one modem 11, and the modem 11 transmits the same digital modulation signal to the ⁇ modulation circuits 12, 13 (Alternatively, what is output to the ⁇ modulation circuits 51 and 52), the modulation signal output circuit unit has a plurality of modems that generate the same digital modulation signal, and a plurality of modems and a plurality of ⁇ modulations.
  • the circuits may be connected one to one.
  • the modulation signal output circuit unit 6 includes modems 11a and 11b, ⁇ modulation circuits 51 and 52, and a setting circuit 53.
  • the modem 11 a modulates communication data to generate a digital modulation signal, and outputs the digital modulation signal to the ⁇ modulation circuit 51.
  • the modem 11b modulates the communication data to generate a digital modulation signal that is the same as the digital modulation signal generated by the modem 11a, and outputs the digital modulation signal to the ⁇ modulation circuit 52.
  • FIG. 7 shows an example in which two modems are mounted, N modems and N ⁇ modulation circuits may be mounted.
  • the timing output from the ⁇ modulation circuit 51 to the high frequency circuit 21 and the ⁇ modulation circuit 52 If the output timing of the digital modulation signal from the modems 11a and 11b is controlled so that the timing output from the radio frequency circuit 22 to the high frequency circuit 22 is shifted, the radiation direction of the digital modulation signal radiated from the antennas 41 and 42 of the high frequency unit 4 is controlled. Can be controlled in any direction.
  • the modulation signal output circuit unit 6 mounts the two modems 11a and 11b, and outputs from the ⁇ modulation circuit 51 to the high frequency circuit 21 and from the ⁇ modulation circuit 52 to the high frequency circuit 22.
  • the output timing of the digital modulation signal from the modems 11a and 11b is controlled so that the timing is different from that of the modem 11a and 11b.
  • one modem 11 and the ⁇ modulation circuits 12 and 13 (or ⁇ modulation circuits 51 and 52).
  • a delay circuit may be inserted between the delay circuits to control the amount of delay of the digital modulation signal by the plurality of delay circuits.
  • the digital modulation signal radiated from the antennas 41 and 42 of the high-frequency unit 4 may be controlled.
  • the radiation direction can be controlled in an arbitrary direction.
  • FIG. 8 is a block diagram showing a modulation signal output circuit unit 7 of a digital transmitter according to Embodiment 7 of the present invention.
  • the modulation signal output circuit unit 7 includes a modem 11, ⁇ modulation circuits 51 and 52, a setting circuit 53, delay circuits 81 and 82, and a delay control circuit 83.
  • Delay circuits 81 and 82 are inserted between modem 11 and ⁇ modulation circuits 51 and 52, delay the digital modulation signal generated by modem 11, and output the delayed digital modulation signal to ⁇ modulation circuits 51 and 52. It is a circuit to do.
  • the delay control circuit 83 is a circuit that controls the delay amount of the digital modulation signal by the delay circuits 81 and 82.
  • the timing output from the ⁇ modulation circuit 51 to the high frequency circuit 21 and the ⁇ modulation circuit 52 If the delay control circuit 83 controls the amount of delay in the delay circuits 81 and 82 so that the timing output from the signal to the high-frequency circuit 22 is shifted, the digital modulation signal radiated from the antennas 41 and 42 of the high-frequency unit 4
  • the radiation direction can be controlled in an arbitrary direction.
  • Embodiment 8 FIG.
  • the modulation signal output circuit units 1, 5, 6 and 7 mount the ⁇ modulation circuits 12 and 13 (or ⁇ modulation circuits 51 and 52), and the ⁇ modulation circuits 12 and 13 (or The ⁇ modulation circuit 51 (or the ⁇ modulation circuit 51) and the ⁇ modulation circuit are used to reduce the ⁇ noise generated when the ⁇ modulation circuits 51, 52) perform delta-sigma modulation on the digital modulation signal and increase the SNR. 13 (or ⁇ modulation circuit 52) is different in circuit configuration or operating condition.
  • a pulse-width modulation circuit that performs pulse-width modulation on a digital modulation signal and outputs a PWM signal that is a digital modulation signal after pulse-width modulation is also mounted near the desired modulation signal band. Since noise is generated, the SNR that is the power ratio between the desired signal component and the noise component may deteriorate.
  • a digital transmitter capable of reducing the noise accompanying pulse width modulation of a digital modulation signal and increasing the SNR will be described.
  • FIG. 9 is a block diagram showing a digital transmitter according to Embodiment 8 of the present invention.
  • the modulation signal output circuit unit 91 includes a modem 11 and pulse width modulation circuits 101 and 102, and is a digital circuit that modulates communication data to generate a digital modulation signal and performs pulse width modulation on the digital modulation signal.
  • the pulse width modulation circuit 101 has a signal input terminal connected to a signal output terminal of the modem 11.
  • the pulse width modulation circuit 101 performs pulse width modulation on the digital modulation signal output from the modem 11, and a PWM signal which is a digital modulation signal after pulse width modulation. Is a digital circuit that outputs.
  • the pulse width modulation circuit 102 has a signal input terminal connected to the signal output terminal of the modem 11 and is different in circuit configuration from the pulse width modulation circuit 101, but is output from the modem 11 in the same manner as the pulse width modulation circuit 101.
  • the digital modulation signal is subjected to pulse width modulation, and a PWM signal which is a digital modulation signal after pulse width modulation is output.
  • the modem 11 of the modulation signal output circuit unit 91 receives communication data composed of various information from the outside, the modem 11 modulates the communication data to generate a digital modulation signal, and the digital modulation signal is converted into a pulse width modulation circuit. 101 and 102.
  • the pulse width modulation circuit 101 When the pulse width modulation circuit 101 receives the digital modulation signal from the modem 11, the pulse width modulation circuit 101 performs pulse width modulation on the digital modulation signal and outputs a PWM signal, which is a digital modulation signal after pulse width modulation, to the high frequency circuit 21.
  • the pulse width modulation circuit 102 receives the digital modulation signal from the modem 11, the pulse width modulation circuit 102 performs pulse width modulation on the digital modulation signal and outputs a PWM signal which is a digital modulation signal after pulse width modulation to the high frequency circuit 22.
  • the pulse width modulation by the pulse width modulation circuits 101 and 102 As the amplitude value of the digital modulation signal output from the modem 11 is larger, a pulse having a wider pulse width is generated and a PWM signal composed of a plurality of pulse sequences is output.
  • the characteristics of noise generated when the pulse width modulation circuits 101 and 102 perform pulse width modulation depend on the circuit configuration of the pulse width modulation circuits 101 and 102. This is the same as the characteristic of the ⁇ noise depending on the circuit configuration of the ⁇ modulation circuits 12 and 13.
  • the pulse width modulation circuit 101 and the pulse width modulation circuit 102 have different circuit configurations, and the pulse width modulation circuit 101 and the pulse width modulation circuit 102 have different circuit configurations.
  • the processing sequence of pulse width modulation is different, noise characteristics are different.
  • the noise component generated from the pulse width modulation circuit 101 and the noise component generated from the pulse width modulation circuit 102 are incoherent.
  • the pulse width modulation circuits 101 and 102 perform pulse width modulation on the same digital modulation signal output from the modem 11, a desired signal component of the digital modulation signal output from the pulse width modulation circuit 101, and The desired signal component of the digital modulation signal output from the pulse width modulation circuit 102 is coherent.
  • any circuit configuration may be used as long as the pulse width modulation circuit 101 and the pulse width modulation circuit 102 have different circuit configurations. Description of the detailed configuration is omitted. Various known configurations are known as the circuit configuration of the pulse width modulation circuit.
  • the high frequency circuit 21 When the high frequency circuit 21 receives the digital modulation signal after pulse width modulation from the pulse width modulation circuit 101, the high frequency circuit 21 converts the signal power of the digital modulation signal into a desired power level, and converts the frequency of the digital modulation signal from the IF frequency. The signal is converted into an RF frequency, and the converted digital modulation signal is output to the synthesis circuit 23.
  • the high frequency circuit 22 receives the digital modulation signal after the pulse width modulation from the pulse width modulation circuit 102, the high frequency circuit 22 converts the signal power of the digital modulation signal into a desired power level and converts the frequency of the digital modulation signal from the IF frequency. The signal is converted into an RF frequency, and the converted digital modulation signal is output to the synthesis circuit 23.
  • the converted digital modulation signal output from the high-frequency circuit 21 and the converted digital modulation signal output from the high-frequency circuit 22 have the same signal power and the same frequency.
  • the converted digital modulation signals output from the high-frequency circuits 21 and 22 also have a noise component incoherent, but a desired signal component of the digital modulation signal is coherent.
  • the synthesis circuit 23 synthesizes the converted digital modulation signal output from the high-frequency circuit 21 and the converted digital modulation signal output from the high-frequency circuit 22 to generate two signals. A composite signal of the digital modulation signal is output. At this time, since the desired signal components of the two digital modulation signals are coherent, the two desired signal components are voltage-added by the synthesis of the synthesis circuit 23. On the other hand, since the noise components of the two digital modulation signals are incoherent, the noise components of the two digital modulation signals are summed by the synthesis of the synthesis circuit 23.
  • the SNR which is the power ratio between the desired signal component and the noise component in the combined signal output from the combining circuit 23, is the desired signal component and the noise component in the digital modulation signals output from the high frequency circuits 21 and 22, respectively.
  • the theoretical improvement is 3 dB.
  • the modem 11 that modulates communication data to generate a digital modulation signal, and the pulse width modulation of the digital modulation signal generated by the modem 11
  • the pulse width modulation circuits 101 and 102 for outputting the modulated digital modulation signal, the signal power of the digital modulation signal output from the pulse width modulation circuits 101 and 102 are converted to a desired power level, and the digital modulation signal
  • the high frequency circuits 21 and 22 for converting the frequency from the IF frequency to the RF frequency, the digital modulation signal after the conversion by the high frequency circuit 21 and the digital modulation signal after the conversion by the high frequency circuit 22 are combined to generate two digital modulation signals.
  • a synthesis circuit 23 for outputting a synthesis signal and the circuit configuration of the pulse width modulation circuits 101 and 102. Since it configured to be different, to reduce the noise associated with the pulse width modulation of the digital modulation signal, an effect that can increase the SNR.
  • the modulation signal output circuit unit 91 is mounted with two pulse width modulation circuits 101 and 102 having different circuit configurations.
  • the modulation signal output circuit unit 91 has a circuit configuration.
  • the high-frequency unit 2 mounts N high-frequency circuits, and the synthesis circuit 23 synthesizes the converted digital modulation signals output from the N high-frequency circuits. You may do it.
  • the high frequency unit 2 converts the signal power of the digital modulation signal output from the pulse width modulation circuits 101 and 102 to a desired power level, and converts the frequency of the digital modulation signal from the IF frequency to the RF frequency.
  • the two digital modulation signals after the conversion are synthesized after being converted to the frequency.
  • the signal power of the combined signal may be converted to a desired power level, and the frequency of the combined signal may be converted from the IF frequency to the RF frequency.
  • FIG. 10 is a block diagram showing a digital transmitter according to Embodiment 9 of the present invention.
  • the combining circuit 31 combines the digital modulated signal after pulse width modulation output from the pulse width modulating circuit 101 and the digital modulated signal after pulse width modulation output from the pulse width modulating circuit 102 to generate two digital signals. A composite signal of the modulation signal is output. At this time, since the desired signal components of the two digital modulation signals are coherent, the two desired signal components are voltage-added by the synthesis of the synthesis circuit 31. On the other hand, since the noise components of the two digital modulation signals are incoherent, the noise components of the two digital modulation signals are summed by the synthesis of the synthesis circuit 31.
  • the SNR that is the power ratio between the desired signal component and the noise component in the combined signal output from the combining circuit 31 is the desired signal component and noise in the digital modulation signal output from each of the pulse width modulation circuits 101 and 102.
  • the SNR with the component there is a theoretical 3 dB improvement.
  • the high frequency circuit 32 When the high frequency circuit 32 receives the combined signal from the combining circuit 31, the high frequency circuit 32 converts the signal power of the combined signal into a desired power level and converts the frequency of the combined signal from the IF frequency to the RF frequency.
  • the modem 11 that modulates communication data to generate a digital modulation signal
  • Pulse width modulation circuits 101 and 102 that output a modulated digital modulation signal, a pulse width modulated digital modulation signal output from the pulse width modulation circuit 101, and a pulse width modulated output from the pulse width modulation circuit 102 are combined with each other, and a combined circuit 31 for outputting a combined signal of the two digital modulated signals is converted into a desired power level, and the combined signal output from the combined circuit 31 is converted into a desired power level.
  • a high-frequency circuit 32 for converting the frequency of IF from the IF frequency to the RF frequency, and the circuit of the pulse width modulation circuits 101 and 102 Since it is configured such that are different, by reducing the noise associated with the pulse width modulation of the digital modulation signal, an effect that can increase the SNR.
  • the high frequency unit 3 combines the digital modulation signals output from the pulse width modulation circuits 101 and 102, and then the power level and frequency of the signal power of the combined signal of the two digital modulation signals.
  • the number of high-frequency circuits can be reduced to one, and the circuit configuration can be simplified.
  • the modulation signal output circuit unit 91 is mounted with two pulse width modulation circuits 101 and 102 having different circuit configurations.
  • the modulation signal output circuit unit 91 has a circuit configuration. Different N pulse width modulation circuits may be mounted, and the synthesis circuit 31 of the high-frequency unit 2 may synthesize the pulse-modulated digital modulation signal output from the N pulse width modulation circuits.
  • the synthesis circuit 23 synthesizes the converted digital modulation signal output from the high frequency circuit 21 and the converted digital modulation signal output from the high frequency circuit 22 to generate two digital modulations.
  • the output of the combined signal is shown, antennas 41 and 42 that radiate the converted digital modulation signals output from the high-frequency circuits 21 and 22 to the space are provided, and the digital modulation radiated from the antennas 41 and 42 is provided.
  • the signals may be combined in space.
  • FIG. 11 is a block diagram showing a digital transmitter according to Embodiment 10 of the present invention.
  • the high frequency circuit 21 receives the digital modulation signal after the pulse width modulation from the pulse width modulation circuit 101, the high frequency circuit 21 converts the signal power of the digital modulation signal to a desired power level as in the eighth embodiment, and The frequency of the digital modulation signal is converted from the IF frequency to the RF frequency.
  • the high frequency circuit 22 When the high frequency circuit 22 receives the digital modulation signal after the pulse width modulation from the pulse width modulation circuit 102, the high frequency circuit 22 converts the signal power of the digital modulation signal to a desired power level as in the eighth embodiment, and The frequency of the digital modulation signal is converted from the IF frequency to the RF frequency.
  • the converted digital modulation signal output from the high-frequency circuit 21 and the converted digital modulation signal output from the high-frequency circuit 22 have the same signal power and the same frequency.
  • the converted digital modulation signals output from the high-frequency circuits 21 and 22 also have a noise component incoherent, but a desired signal component of the digital modulation signal is coherent.
  • the antenna 41 When receiving the converted digital modulation signal from the high-frequency circuit 21, the antenna 41 radiates the digital modulation signal to space.
  • the antenna 42 receives the converted digital modulation signal from the high frequency circuit 22, the antenna 42 radiates the digital modulation signal to space.
  • the digital modulation signal radiated from the antenna 41 and the digital modulation signal radiated from the antenna 42 are combined in space.
  • the two desired signal components of the two digital modulation signals output from the high-frequency circuits 21 and 22 are coherent, the two desired signal components are voltage-added by synthesis in space.
  • the noise components of the two digital modulation signals are incoherent, the noise components of the two digital modulation signals become power addition by combining in space.
  • the SNR which is the power ratio between the desired signal component and the noise component in the signal synthesized in space, is the SNR of the desired signal component and the noise component in the digital modulation signal output from each of the high frequency circuits 21 and 22.
  • 3 dB is obtained. Therefore, a receiver that is a communication target with the digital transmitter can receive a signal having a high SNR.
  • the modem 11 that modulates communication data to generate a digital modulation signal, and the pulse width modulation of the digital modulation signal generated by the modem 11
  • the pulse width modulation circuits 101 and 102 for outputting the modulated digital modulation signal, the signal power of the digital modulation signal output from the pulse width modulation circuits 101 and 102 are converted to a desired power level, and the digital modulation signal High-frequency circuits 21 and 22 for converting the frequency from IF frequency to RF frequency, and antennas 41 and 42 for radiating the converted digital modulation signals output from the high-frequency circuits 21 and 22 to the space, and a pulse width modulation circuit 101 , 102 are configured so as to have different circuit configurations, so that pulse width modulation of a digital modulation signal can be performed.
  • the synthesis circuit 23 is not necessary.
  • Embodiment 11 FIG.
  • the modulation signal output circuit unit 91 is mounted with the pulse width modulation circuits 101 and 102 having different circuit configurations. Since it is necessary to design each circuit configuration, the load of circuit development increases. Therefore, in the eleventh embodiment, a description will be given of a case where a plurality of pulse width modulation circuits having the same circuit configuration are mounted in the modulation signal output circuit section and different operating conditions are set for the plurality of pulse width modulation circuits.
  • FIG. 12 is a block diagram showing a digital transmitter according to Embodiment 11 of the present invention.
  • the modulation signal output circuit unit 92 is a digital circuit including the modem 11, pulse width modulation circuits 111 and 112, and a setting circuit 113.
  • the pulse width modulation circuit 111 has a signal input terminal connected to the signal output terminal of the modem 11.
  • the pulse width modulation circuit 111 performs pulse width modulation on the digital modulation signal output from the modem 11 and outputs a digital modulation signal after pulse width modulation.
  • the pulse width modulation circuit 112 is a circuit having the same circuit configuration as the pulse width modulation circuit 111.
  • the pulse width modulation circuit 112 has a signal input terminal connected to the signal output terminal of the modem 11.
  • the pulse width modulation circuit 112 performs pulse width modulation on the digital modulation signal output from the modem 11 and outputs a digital modulation signal after pulse width modulation.
  • the setting circuit 113 is a circuit that sets different operating conditions for the pulse width modulation circuits 111 and 112.
  • the setting circuit 113 sets different operating conditions for the pulse width modulation circuits 111 and 112.
  • the pulse width modulation circuit 111 When the pulse width modulation circuit 111 receives the digital modulation signal from the modem 11, the pulse width modulation circuit 111 performs pulse width modulation on the digital modulation signal in accordance with the operation condition set by the setting circuit 113, and converts the digital modulation signal after the pulse width modulation into a high frequency circuit. To 21.
  • the pulse width modulation circuit 112 receives the digital modulation signal from the modem 11, the pulse width modulation circuit 112 performs pulse width modulation on the digital modulation signal in accordance with the operation condition set by the setting circuit 113, and converts the digital modulation signal after the pulse width modulation into a high frequency circuit 22 to output.
  • the pulse width modulation circuit is similar to the pulse width modulation circuits 101 and 102 of FIG.
  • the noise component generated from 111 and the noise component generated from the pulse width modulation circuit 112 become incoherent.
  • the pulse width modulation circuits 111 and 112 perform pulse width modulation on the same digital modulation signal output from the modem 11, a desired signal component of the digital modulation signal output from the pulse width modulation circuit 111, and The desired signal component of the digital modulation signal output from the pulse width modulation circuit 112 becomes coherent.
  • the noise component becomes incoherent and the desired signal component becomes coherent when ⁇ modulation circuits 51 and 52 in FIG. 4 having the same circuit configuration are set with different operating conditions. This is the same as when the noise component becomes incoherent and the desired signal component becomes coherent.
  • the modulation signal output circuit unit 92 mounts the pulse width modulation circuits 111 and 112 having the same circuit configuration, and the pulse width modulation circuits 111 and 112 Since the setting circuit 113 for setting different operating conditions is mounted, the noise accompanying the pulse width modulation of the digital modulation signal can be reduced and the SNR can be increased as in the eighth embodiment. As compared with the case where the pulse width modulation circuits 101 and 102 having different circuit configurations are mounted, the load required for circuit development of the pulse width modulation circuits 111 and 112 can be reduced.
  • the modulation signal output circuit unit 91 mounts one modem 11, and the modem 11 transmits the same digital modulation signal to the pulse width modulation circuit 101, 102 (or pulse width modulation circuits 111 and 112), the modulation signal output circuit unit includes a plurality of modems that generate the same digital modulation signal, and a plurality of modems and a plurality of modems.
  • the modulation signal output circuit units may be connected one to one.
  • FIG. 13 is a block diagram showing a modulation signal output circuit section 93 of a digital transmitter according to Embodiment 12 of the present invention.
  • the modulation signal output circuit unit 93 includes modems 11a and 11b, pulse width modulation circuits 111 and 112, and a setting circuit 113.
  • FIG. 13 shows an example in which two modems are mounted, N modems and N pulse width modulation circuits may be mounted.
  • the modems 11a and 11b When the modems 11a and 11b generate the same digital modulation signal, the same operation as in the eleventh embodiment can be realized. If the pulse width modulation circuits 101 and 102 are mounted instead of the pulse width modulation circuits 111 and 112, the same operation as in the eighth to tenth embodiments can be realized. Further, when the modulation signal output circuit section 93 in FIG. 13 is connected to the high frequency section 4 in FIG.
  • the timing output from the pulse width modulation circuit 111 to the high frequency circuit 21 and the pulse width modulation If the output timing of the digital modulation signal from the modems 11a and 11b is controlled so that the timing output from the circuit 112 to the high frequency circuit 22 is shifted, the digital modulation signal radiated from the antennas 41 and 42 of the high frequency unit 4 is controlled.
  • the radiation direction can be controlled in an arbitrary direction.
  • the modulation signal output circuit unit 93 mounts the two modems 11a and 11b and outputs the timing from the pulse width modulation circuit 111 to the high frequency circuit 21, and from the pulse width modulation circuit 112 to the high frequency circuit 22.
  • the control of the output timing of the digital modulation signal from the modems 11a and 11b is shown so that the output timing is deviated, one modem 11 and the pulse width modulation circuits 101 and 102 (or the pulse width modulation circuit) are shown.
  • 111, 112) may be inserted respectively to control the amount of delay of the digital modulation signal by the plurality of delay circuits.
  • radiation is radiated from the antennas 41, 42 of the high-frequency unit 4.
  • the radiation direction of the digital modulation signal can be controlled in an arbitrary direction.
  • FIG. 14 is a block diagram showing a modulation signal output circuit unit 94 of a digital transmitter according to Embodiment 13 of the present invention.
  • the modulation signal output circuit unit 94 includes a modem 11, pulse width modulation circuits 111 and 112, a setting circuit 113, delay circuits 81 and 82, and a delay control circuit 83.
  • the timing output from the pulse width modulation circuit 111 to the high frequency circuit 21 and the pulse width modulation If the delay control circuit 83 controls the delay amount in the delay circuits 81 and 82 so that the timing output from the circuit 112 to the high-frequency circuit 22 is shifted, the digital signal radiated from the antennas 41 and 42 of the high-frequency unit 4 is controlled.
  • the radiation direction of the modulation signal can be controlled in an arbitrary direction.
  • the digital transmitter according to the present invention is suitable for a digital transmitter that needs to directly transmit a digital modulation signal generated by a digital circuit such as a modem in a high frequency band.

Abstract

A digital transmitter comprising: a modem (11) that modulates communication data to generate a digital modulated signal; ΔΣ modulation circuits (12), (13) that delta-sigma modulate the digital modulated signal generated by the modem (11) to output the digital modulated signals as delta-sigma modulated; high frequency circuits (21), (22) that convert the signal powers of the digital modulated signals outputted from the ΔΣ modulation circuits (12), (13) to a desired power level, and convert the frequencies of the digital modulated signals from IF frequencies to an RF frequency; and a synthesizing circuit (23) that synthesizes the digital modulated signal as converted by the high frequency circuit (21) with the digital modulated signal as converted by the high frequency circuit (22) to output a synthesized signal of the two digital modulated signals, wherein the circuit configurations of the ΔΣ modulation circuits (12), (13) are different from each other.

Description

ディジタル送信機Digital transmitter
　この発明は、モデムなどのディジタル回路で生成されたディジタル変調信号を直接高周波帯で送信するディジタル送信機に関するものである。 The present invention relates to a digital transmitter for directly transmitting a digital modulation signal generated by a digital circuit such as a modem in a high frequency band.
　例えば、以下の非特許文献１には、モデムなどのディジタル回路で生成されたディジタル変調信号を直接高周波帯で送信するディジタル送信機が開示されている。
　このディジタル送信機では、モデムで生成されたディジタル変調信号を直接高周波帯で送信するため、ベースバンド周波数帯の変調信号を高周波帯の周波数に変換するためのアナログ回路が不要となり、回路構成を簡素化することができる。
　なお、このディジタル送信機では、モデムで生成されたディジタル変調信号を直接高周波帯で送信できるようにするために、モデムで生成されたディジタル変調信号をデルタシグマ変調して、デルタシグマ変調後のディジタル変調信号を出力するΔΣ変調回路が実装されている。
　以下の非特許文献２には、ΔΣ変調回路の回路構成が開示されている。 For example, the following Non-Patent Document 1 discloses a digital transmitter that directly transmits a digital modulation signal generated by a digital circuit such as a modem in a high frequency band.
In this digital transmitter, the digital modulation signal generated by the modem is directly transmitted in the high frequency band, so that an analog circuit for converting the modulation signal in the baseband frequency band to the frequency in the high frequency band is not required, and the circuit configuration is simplified. Can be
In this digital transmitter, in order to directly transmit the digital modulation signal generated by the modem in the high frequency band, the digital modulation signal generated by the modem is delta-sigma-modulated and the digital signal after delta-sigma modulation is transmitted. A ΔΣ modulation circuit that outputs a modulation signal is mounted.
Non-Patent Document 2 below discloses a circuit configuration of a ΔΣ modulation circuit.
　従来のディジタル送信機は以上のように構成されているので、モデムで生成されたディジタル変調信号を直接高周波帯で送信することができる。しかし、モデムで生成されたディジタル変調信号をデルタシグマ変調する際、所望の変調信号帯域の近傍にΔΣノイズが発生するため、所望信号成分とノイズ成分との電力比である信号対雑音比（ＳＮＲ）が劣化してしまうという課題があった。なお、このΔΣノイズは、隣接チャネルでの通信や近接周波数帯の他の通信に対して干渉し、通信品質の劣化を引き起こす原因となる。 Since the conventional digital transmitter is configured as described above, the digital modulation signal generated by the modem can be transmitted directly in the high frequency band. However, when the digital modulation signal generated by the modem is delta-sigma modulated, ΔΣ noise is generated in the vicinity of the desired modulation signal band. ) Deteriorated. Note that this ΔΣ noise interferes with communication in adjacent channels and other communication in the adjacent frequency band, and causes deterioration in communication quality.
　この発明は上記のような課題を解決するためになされたもので、ディジタル変調信号のデルタシグマ変調に伴うΔΣノイズを低減して、信号対雑音比を高めることができるディジタル送信機を得ることを目的とする。 The present invention has been made to solve the above-described problems, and it is an object of the present invention to obtain a digital transmitter capable of reducing ΔΣ noise accompanying delta-sigma modulation of a digital modulation signal and increasing a signal-to-noise ratio. Objective.
　この発明に係るディジタル送信機は、通信データを変調してディジタル変調信号を生成するモデムと、モデムにより生成されたディジタル変調信号をデルタシグマ変調して、デルタシグマ変調後のディジタル変調信号を出力する複数のΔΣ変調回路と、複数のΔΣ変調回路から出力されたディジタル変調信号における信号レベル又は周波数のうち、少なくとも一方を変換してから変換後の複数のディジタル変調信号を合成、あるいは、複数のΔΣ変調回路から出力されたディジタル変調信号を合成してから、複数のディジタル変調信号の合成信号における信号レベル又は周波数のうち、少なくとも一方を変換する高周波部とを備え、複数のΔΣ変調回路の回路構成又は動作条件が異なっているようにしたものである。 A digital transmitter according to the present invention modulates communication data to generate a digital modulation signal, and delta-sigma modulates the digital modulation signal generated by the modem and outputs a digital modulation signal after delta-sigma modulation. A plurality of ΔΣ modulation circuits and a digital modulation signal output from the plurality of ΔΣ modulation circuits, at least one of the signal levels or frequencies is converted and then the plurality of converted digital modulation signals are combined, or a plurality of ΔΣ A circuit configuration of a plurality of ΔΣ modulation circuits, including a high frequency unit that synthesizes the digital modulation signals output from the modulation circuit and then converts at least one of the signal levels or frequencies in the combined signal of the plurality of digital modulation signals Alternatively, the operating conditions are different.
　この発明によれば、複数のΔΣ変調回路の回路構成又は動作条件が異なっているように構成したので、ディジタル変調信号のデルタシグマ変調に伴うΔΣノイズを低減して、信号対雑音比を高めることができる効果がある。 According to the present invention, since the circuit configurations or operating conditions of the plurality of ΔΣ modulation circuits are different, ΔΣ noise associated with delta-sigma modulation of the digital modulation signal is reduced, and the signal-to-noise ratio is increased. There is an effect that can.
この発明の実施の形態１によるディジタル送信機を示す構成図である。It is a block diagram which shows the digital transmitter by Embodiment 1 of this invention. この発明の実施の形態２によるディジタル送信機を示す構成図である。It is a block diagram which shows the digital transmitter by Embodiment 2 of this invention. この発明の実施の形態３によるディジタル送信機を示す構成図である。It is a block diagram which shows the digital transmitter by Embodiment 3 of this invention. この発明の実施の形態４によるディジタル送信機を示す構成図である。It is a block diagram which shows the digital transmitter by Embodiment 4 of this invention. この発明の実施の形態４によるディジタル送信機のΔΣ変調回路５１，５２を示す構成図である。It is a block diagram which shows the delta- sigma modulation circuits 51 and 52 of the digital transmitter by Embodiment 4 of this invention. この発明の実施の形態５によるディジタル送信機のΔΣ変調回路５１，５２を示す構成図である。It is a block diagram which shows the delta- sigma modulation circuits 51 and 52 of the digital transmitter by Embodiment 5 of this invention. この発明の実施の形態６によるディジタル送信機の変調信号出力回路部６を示す構成図である。It is a block diagram which shows the modulation signal output circuit part 6 of the digital transmitter by Embodiment 6 of this invention. この発明の実施の形態７によるディジタル送信機の変調信号出力回路部７を示す構成図である。It is a block diagram which shows the modulation signal output circuit part 7 of the digital transmitter by Embodiment 7 of this invention. この発明の実施の形態８によるディジタル送信機を示す構成図である。It is a block diagram which shows the digital transmitter by Embodiment 8 of this invention. この発明の実施の形態９によるディジタル送信機を示す構成図である。It is a block diagram which shows the digital transmitter by Embodiment 9 of this invention. この発明の実施の形態１０によるディジタル送信機を示す構成図である。It is a block diagram which shows the digital transmitter by Embodiment 10 of this invention. この発明の実施の形態１１によるディジタル送信機を示す構成図である。It is a block diagram which shows the digital transmitter by Embodiment 11 of this invention. この発明の実施の形態１２によるディジタル送信機の変調信号出力回路部９３を示す構成図である。It is a block diagram which shows the modulation signal output circuit part 93 of the digital transmitter by Embodiment 12 of this invention. この発明の実施の形態１３によるディジタル送信機の変調信号出力回路部９４を示す構成図である。It is a block diagram which shows the modulation signal output circuit part 94 of the digital transmitter by Embodiment 13 of this invention.
　以下、この発明をより詳細に説明するために、この発明を実施するための形態について、添付の図面にしたがって説明する。 Hereinafter, in order to explain the present invention in more detail, modes for carrying out the present invention will be described with reference to the accompanying drawings.
実施の形態１．
　図１はこの発明の実施の形態１によるディジタル送信機を示す構成図である。
　図１において、変調信号出力回路部１はモデム１１とΔΣ変調回路１２，１３から構成されており、通信データを変調してディジタル変調信号を生成し、そのディジタル変調信号をデルタシグマ変調するディジタル回路である。
　モデム１１は通信データを変調してディジタル変調信号を生成し、そのディジタル変調信号をΔΣ変調回路１２，１３に出力する。 Embodiment 1 FIG.
FIG. 1 is a block diagram showing a digital transmitter according to Embodiment 1 of the present invention.
In FIG. 1, a modulation signal output circuit unit 1 is composed of a modem 11 and ΔΣ modulation circuits 12 and 13, which modulate communication data to generate a digital modulation signal and delta-sigma modulate the digital modulation signal. It is.
The modem 11 modulates the communication data to generate a digital modulation signal, and outputs the digital modulation signal to the ΔΣ modulation circuits 12 and 13.
　ΔΣ変調回路１２は信号入力端子がモデム１１の信号出力端子と接続されており、モデム１１から出力されたディジタル変調信号をデルタシグマ変調して、デルタシグマ変調後のディジタル変調信号を出力するディジタル回路である。
　ΔΣ変調回路１３は信号入力端子がモデム１１の信号出力端子と接続されており、ΔΣ変調回路１２と回路構成が異なっているが、ΔΣ変調回路１２と同様に、モデム１１から出力されたディジタル変調信号をデルタシグマ変調して、デルタシグマ変調後のディジタル変調信号を出力する。 The ΔΣ modulation circuit 12 has a signal input terminal connected to a signal output terminal of the modem 11, and delta-sigma modulates the digital modulation signal output from the modem 11 and outputs a digital modulation signal after delta-sigma modulation. It is.
The ΔΣ modulation circuit 13 has a signal input terminal connected to the signal output terminal of the modem 11 and has a circuit configuration different from that of the ΔΣ modulation circuit 12, but the digital modulation output from the modem 11 is the same as the ΔΣ modulation circuit 12. The signal is delta-sigma modulated and a digitally modulated signal after delta-sigma modulation is output.
　高周波部２は高周波回路２１，２２と合成回路２３から構成されている回路である。
　高周波回路２１は信号入力端子がΔΣ変調回路１２の信号出力端子と接続されており、ΔΣ変調回路１２から出力されたディジタル変調信号の信号電力（信号レベル）を所望の電力レベル（信号レベル）に変換するとともに、そのディジタル変調信号の周波数をＩＦ周波数（中間周波数）からＲＦ周波数（無線周波数）に変換する。
　高周波回路２２は信号入力端子がΔΣ変調回路１３の信号出力端子と接続されており、ΔΣ変調回路１３から出力されたディジタル変調信号の信号電力を所望の電力レベルに変換するとともに、そのディジタル変調信号の周波数をＩＦ周波数からＲＦ周波数に変換する。
　この実施の形態１では、高周波回路２１，２２が、ディジタル変調信号の信号電力の変換と周波数の変換を行う例を示しているが、信号電力又は周波数の変換のうち、いずれか一方の変換を行うものでもよい。 The high frequency unit 2 is a circuit composed of high frequency circuits 21 and 22 and a synthesis circuit 23.
The signal input terminal of the high frequency circuit 21 is connected to the signal output terminal of the ΔΣ modulation circuit 12, and the signal power (signal level) of the digital modulation signal output from the ΔΣ modulation circuit 12 is set to a desired power level (signal level). In addition to conversion, the frequency of the digital modulation signal is converted from IF frequency (intermediate frequency) to RF frequency (radio frequency).
The high-frequency circuit 22 has a signal input terminal connected to a signal output terminal of the ΔΣ modulation circuit 13, converts the signal power of the digital modulation signal output from the ΔΣ modulation circuit 13 to a desired power level, and the digital modulation signal Is converted from IF frequency to RF frequency.
In the first embodiment, an example is shown in which the high frequency circuits 21 and 22 convert the signal power of the digital modulation signal and the frequency, but either one of the signal power or the frequency conversion is converted. You can do it.
　なお、高周波回路２１，２２の具体的な構成として、例えば、１ビットのディジタル変調信号を入力してスッチング動作する増幅回路、そのディジタル変調信号の信号電力を所望の電力レベルに調整する可変利得回路、そのディジタル変調信号の周波数をＩＦ周波数からＲＦ周波数に変換する周波数変換回路、そのディジタル変調信号に含まれている不要波を抑圧するフィルタ回路などの要素回路から構成されているものが考えられる。また、別の要素回路を含んでいてもよい。
　合成回路２３は第１の信号入力端子が高周波回路２１の信号出力端子と接続されて、第２の信号入力端子が高周波回路２２の信号出力端子と接続されており、高周波回路２１による変換後のディジタル変調信号と高周波回路２２による変換後のディジタル変調信号とを合成して、２つのディジタル変調信号の合成信号を出力する。 As specific configurations of the high- frequency circuits 21 and 22, for example, an amplification circuit that inputs a 1-bit digital modulation signal and performs a switching operation, and a variable gain circuit that adjusts the signal power of the digital modulation signal to a desired power level It can be considered that the circuit is composed of element circuits such as a frequency conversion circuit that converts the frequency of the digital modulation signal from IF frequency to RF frequency, and a filter circuit that suppresses unnecessary waves contained in the digital modulation signal. Moreover, another element circuit may be included.
The synthesizing circuit 23 has a first signal input terminal connected to a signal output terminal of the high frequency circuit 21 and a second signal input terminal connected to a signal output terminal of the high frequency circuit 22. The digital modulation signal and the digital modulation signal converted by the high frequency circuit 22 are combined to output a combined signal of the two digital modulation signals.
　次に動作について説明する。
　変調信号出力回路部１のモデム１１は、例えば、外部から各種の情報等からなる通信データを受けると、その通信データを変調してディジタル変調信号を生成し、そのディジタル変調信号をΔΣ変調回路１２，１３に出力する。
　ここで、モデム１１により生成されるディジタル変調信号としては、例えば、一般的なモデムから出力されるアナログ変調信号の各時刻における振幅値を多ビットで表しているディジタル変調信号が考えられる。ただし、多ビットのディジタル変調信号に限るものではない。 Next, the operation will be described.
For example, when the modem 11 of the modulation signal output circuit unit 1 receives communication data including various kinds of information from the outside, the modem 11 modulates the communication data to generate a digital modulation signal, and the digital modulation signal is converted into the ΔΣ modulation circuit 12. , 13 are output.
Here, as the digital modulation signal generated by the modem 11, for example, a digital modulation signal in which an amplitude value at each time of an analog modulation signal output from a general modem is represented by multiple bits can be considered. However, the present invention is not limited to a multi-bit digital modulation signal.
　ΔΣ変調回路１２は、モデム１１からディジタル変調信号を受けると、そのディジタル変調信号をデルタシグマ変調して、デルタシグマ変調後のディジタル変調信号を高周波回路２１に出力する。
　ΔΣ変調回路１３は、モデム１１からディジタル変調信号を受けると、そのディジタル変調信号をデルタシグマ変調して、デルタシグマ変調後のディジタル変調信号を高周波回路２２に出力する。
　ここで、ΔΣ変調回路１２，１３から出力されるデルタシグマ変調後のディジタル変調信号は、高周波回路２１，２２の信号処理に適している１ビット又は多ビットのディジタル変調信号である。 When receiving the digital modulation signal from the modem 11, the ΔΣ modulation circuit 12 performs delta sigma modulation on the digital modulation signal and outputs the digital modulation signal after the delta sigma modulation to the high frequency circuit 21.
When receiving the digital modulation signal from the modem 11, the ΔΣ modulation circuit 13 performs delta sigma modulation on the digital modulation signal and outputs the digital modulation signal after the delta sigma modulation to the high frequency circuit 22.
Here, the digital modulation signal after delta-sigma modulation output from the ΔΣ modulation circuits 12 and 13 is a 1-bit or multi-bit digital modulation signal suitable for signal processing of the high- frequency circuits 21 and 22.
　ΔΣ変調回路１２，１３がデルタシグマ変調する際に発生するΔΣノイズの特性は、ΔΣ変調回路１２，１３の回路構成に依存する。
　この実施の形態１では、ΔΣ変調回路１２とΔΣ変調回路１３の回路構成が異なっているものを想定しており、ΔΣ変調回路１２とΔΣ変調回路１３の回路構成が異なっていれば、デルタシグマ変調の処理シーケンスが異なるため、ΔΣノイズの特性が異なる。
　これにより、ΔΣ変調回路１２から発生するΔΣノイズの成分と、ΔΣ変調回路１３から発生するΔΣノイズの成分とはインコヒーレントである。
　一方、ΔΣ変調回路１２，１３は、モデム１１から出力された同一のディジタル変調信号をデルタシグマ変調するものであるため、ΔΣ変調回路１２から出力されるディジタル変調信号の所望信号成分と、ΔΣ変調回路１３から出力されるディジタル変調信号の所望信号成分とはコヒーレントである。 The characteristic of ΔΣ noise generated when the ΔΣ modulation circuits 12 and 13 perform delta-sigma modulation depends on the circuit configuration of the ΔΣ modulation circuits 12 and 13.
In the first embodiment, it is assumed that the circuit configurations of the ΔΣ modulation circuit 12 and the ΔΣ modulation circuit 13 are different. If the circuit configurations of the ΔΣ modulation circuit 12 and the ΔΣ modulation circuit 13 are different, the delta sigma is used. Since the modulation processing sequence is different, the characteristics of ΔΣ noise are different.
Thereby, the ΔΣ noise component generated from the ΔΣ modulation circuit 12 and the ΔΣ noise component generated from the ΔΣ modulation circuit 13 are incoherent.
On the other hand, since the ΔΣ modulation circuits 12 and 13 perform delta-sigma modulation on the same digital modulation signal output from the modem 11, the desired signal component of the digital modulation signal output from the ΔΣ modulation circuit 12 and the ΔΣ modulation are used. The desired signal component of the digital modulation signal output from the circuit 13 is coherent.
　ΔΣ変調回路１２，１３の具体的な回路構成としては、後述の実施の形態４で説明する内蔵のΔΣ変調器の段数が１段のΔΣ変調回路や、後述の実施の形態５で説明する内蔵のΔΣ変調器の段数が２段のΔΣ変調回路などが考えられる。
　例えば、ΔΣ変調回路１２が内蔵しているΔΣ変調器の段数が１段で、ΔΣ変調回路１３が内蔵しているΔΣ変調器の段数が２段であれば、ΔΣ変調回路１２から発生するΔΣノイズの成分と、ΔΣ変調回路１３から発生するΔΣノイズの成分とがインコヒーレントになる。 Specific circuit configurations of the ΔΣ modulation circuits 12 and 13 include a ΔΣ modulation circuit in which the number of stages of a built-in ΔΣ modulator described in a fourth embodiment described later is one, or a built-in circuit described in a fifth embodiment described later. A ΔΣ modulator circuit having two stages of ΔΣ modulators is conceivable.
For example, if the number of stages of the ΔΣ modulator included in the ΔΣ modulation circuit 12 is one and the number of stages of the ΔΣ modulator included in the ΔΣ modulation circuit 13 is 2, ΔΣ generated from the ΔΣ modulation circuit 12 The noise component and the ΔΣ noise component generated from the ΔΣ modulation circuit 13 become incoherent.
　高周波回路２１は、ΔΣ変調回路１２からデルタシグマ変調後のディジタル変調信号を受けると、そのディジタル変調信号の信号電力を所望の電力レベルに変換するとともに、そのディジタル変調信号の周波数をＩＦ周波数からＲＦ周波数に変換し、変換後のディジタル変調信号を合成回路２３に出力する。
　高周波回路２２は、ΔΣ変調回路１３からデルタシグマ変調後のディジタル変調信号を受けると、そのディジタル変調信号の信号電力を所望の電力レベルに変換するとともに、そのディジタル変調信号の周波数をＩＦ周波数からＲＦ周波数に変換し、変換後のディジタル変調信号を合成回路２３に出力する。
　ここでは、高周波回路２１から出力される変換後のディジタル変調信号と、高周波回路２２から出力される変換後のディジタル変調信号とは、信号電力が同一で、周波数が同一であるものとする。
　高周波回路２１，２２から出力される変換後のディジタル変調信号についても、ΔΣノイズ成分がインコヒーレントであるが、ディジタル変調信号の所望信号成分はコヒーレントである。 When the high frequency circuit 21 receives the digital modulation signal after the delta sigma modulation from the ΔΣ modulation circuit 12, the high frequency circuit 21 converts the signal power of the digital modulation signal into a desired power level and converts the frequency of the digital modulation signal from the IF frequency to the RF frequency. The frequency is converted to a frequency, and the converted digital modulation signal is output to the synthesis circuit 23.
When the high frequency circuit 22 receives the digital modulation signal after delta-sigma modulation from the ΔΣ modulation circuit 13, the high frequency circuit 22 converts the signal power of the digital modulation signal to a desired power level, and changes the frequency of the digital modulation signal from the IF frequency to the RF frequency. The frequency is converted to a frequency, and the converted digital modulation signal is output to the synthesis circuit 23.
Here, it is assumed that the converted digital modulation signal output from the high-frequency circuit 21 and the converted digital modulation signal output from the high-frequency circuit 22 have the same signal power and the same frequency.
Also for the converted digital modulation signals output from the high- frequency circuits 21 and 22, the ΔΣ noise component is incoherent, but the desired signal component of the digital modulation signal is coherent.
　合成回路２３は、高周波回路２１から出力された変換後のディジタル変調信号と、高周波回路２２から出力された変換後のディジタル変調信号とを合成して、２つのディジタル変調信号の合成信号を出力する。
　このとき、２つのディジタル変調信号の所望信号成分はコヒーレントであるため、合成回路２３の合成によって、２つの所望信号成分が電圧加算となる。一方、２つのディジタル変調信号のΔΣノイズ成分はインコヒーレントであるため、合成回路２３の合成によって、２つのディジタル変調信号のΔΣノイズ成分が電力加算となる。
　その結果、合成回路２３から出力される合成信号における所望信号成分とΔΣノイズ成分との電力比である信号対雑音比（ＳＮＲ）は、各々の高周波回路２１，２２から出力されるディジタル変調信号における所望信号成分とΔΣノイズ成分とのＳＮＲと比べて、理論的には３ｄＢ改善される。 The combining circuit 23 combines the converted digital modulation signal output from the high frequency circuit 21 and the converted digital modulation signal output from the high frequency circuit 22 and outputs a combined signal of the two digital modulation signals. .
At this time, since the desired signal components of the two digital modulation signals are coherent, the two desired signal components are voltage-added by the synthesis of the synthesis circuit 23. On the other hand, since the ΔΣ noise components of the two digital modulation signals are incoherent, the ΔΣ noise components of the two digital modulation signals are added by the synthesis of the synthesis circuit 23.
As a result, the signal-to-noise ratio (SNR), which is the power ratio between the desired signal component and the ΔΣ noise component in the combined signal output from the combining circuit 23, is the digital modulation signal output from each of the high frequency circuits 21 and 22. The SNR of the desired signal component and the ΔΣ noise component is theoretically improved by 3 dB.
　以上で明らかなように、この実施の形態１によれば、通信データを変調してディジタル変調信号を生成するモデム１１と、モデム１１により生成されたディジタル変調信号をデルタシグマ変調して、デルタシグマ変調後のディジタル変調信号を出力するΔΣ変調回路１２，１３と、ΔΣ変調回路１２，１３から出力されたディジタル変調信号の信号電力を所望の電力レベルに変換するとともに、そのディジタル変調信号の周波数をＩＦ周波数からＲＦ周波数に変換する高周波回路２１，２２と、高周波回路２１による変換後のディジタル変調信号と高周波回路２２による変換後のディジタル変調信号とを合成して、２つのディジタル変調信号の合成信号を出力する合成回路２３とを備え、ΔΣ変調回路１２，１３の回路構成が異なっているように構成したので、ディジタル変調信号のデルタシグマ変調に伴うΔΣノイズを低減して、ＳＮＲを高めることができる効果を奏する。 As is apparent from the above, according to the first embodiment, the modem 11 that modulates communication data to generate a digital modulation signal, and the digital modulation signal generated by the modem 11 are delta-sigma modulated to produce a delta-sigma ΔΣ modulation circuits 12 and 13 that output the modulated digital modulation signal, and the signal power of the digital modulation signal output from the ΔΣ modulation circuits 12 and 13 is converted to a desired power level, and the frequency of the digital modulation signal is changed. The high frequency circuits 21 and 22 for converting the IF frequency to the RF frequency, the digital modulation signal after the conversion by the high frequency circuit 21 and the digital modulation signal after the conversion by the high frequency circuit 22 are combined, and a combined signal of the two digital modulation signals And the circuit configuration of the ΔΣ modulation circuits 12 and 13 is different. Since it is configured, by reducing the ΔΣ noise associated with the delta-sigma modulation of digital modulation signals, an effect that can increase the SNR.
　この実施の形態１では、変調信号出力回路部１が、回路構成が異なる２つのΔΣ変調回路１２，１３を実装している例を示したが、変調信号出力回路部１が、回路構成が異なるＮ個のΔΣ変調回路を実装するとともに、高周波部２が、Ｎ個の高周波回路を実装し、合成回路２３が、Ｎ個の高周波回路から出力された変換後のディジタル変調信号を合成するようにしてもよい。 In the first embodiment, the modulation signal output circuit unit 1 includes two ΔΣ modulation circuits 12 and 13 having different circuit configurations. However, the modulation signal output circuit unit 1 has a different circuit configuration. In addition to mounting N ΔΣ modulation circuits, the high-frequency unit 2 mounts N high-frequency circuits, and the combining circuit 23 combines the converted digital modulation signals output from the N high-frequency circuits. May be.
実施の形態２．
　上記実施の形態１では、高周波部２が、ΔΣ変調回路１２，１３から出力されたディジタル変調信号の信号電力を所望の電力レベルに変換するとともに、そのディジタル変調信号の周波数をＩＦ周波数からＲＦ周波数に変換してから、変換後の２つのディジタル変調信号を合成するものを示したが、ΔΣ変調回路１２，１３から出力されたディジタル変調信号を合成してから、２つのディジタル変調信号の合成信号の信号電力を所望の電力レベルに変換するとともに、その合成信号の周波数をＩＦ周波数からＲＦ周波数に変換するようにしてもよい。 Embodiment 2. FIG.
In the first embodiment, the high frequency unit 2 converts the signal power of the digital modulation signal output from the ΔΣ modulation circuits 12 and 13 to a desired power level, and changes the frequency of the digital modulation signal from the IF frequency to the RF frequency. In this example, the two digital modulation signals after the conversion are combined, and the digital modulation signals output from the ΔΣ modulation circuits 12 and 13 are combined and then the combined signal of the two digital modulation signals. May be converted to a desired power level, and the frequency of the combined signal may be converted from the IF frequency to the RF frequency.
　図２はこの発明の実施の形態２によるディジタル送信機を示す構成図であり、図２において、図１と同一符号は同一または相当部分を示すので説明を省略する。
　高周波部３は合成回路３１と高周波回路３２から構成されている回路である。
　合成回路３１は第１の信号入力端子がΔΣ変調回路１２の信号出力端子と接続されて、第２の信号入力端子がΔΣ変調回路１３の信号出力端子と接続されており、ΔΣ変調回路１２から出力されたデルタシグマ変調後のディジタル変調信号と、ΔΣ変調回路１３から出力されたデルタシグマ変調後のディジタル変調信号とを合成し、２つのディジタル変調信号の合成信号を高周波回路３２に出力する。
　高周波回路３２は信号入力端子が合成回路３１の信号出力端子と接続されており、合成回路３１から出力された合成信号の信号電力を所望の電力レベルに変換するとともに、その合成信号の周波数をＩＦ周波数からＲＦ周波数に変換する。
　この実施の形態２では、高周波回路３２が、合成信号の信号電力の変換と周波数の変換を行う例を示しているが、信号電力又は周波数の変換のうち、いずれか一方の変換を行うものでもよい。 FIG. 2 is a block diagram showing a digital transmitter according to Embodiment 2 of the present invention. In FIG. 2, the same reference numerals as those in FIG.
The high frequency unit 3 is a circuit composed of a synthesis circuit 31 and a high frequency circuit 32.
The combining circuit 31 has a first signal input terminal connected to the signal output terminal of the ΔΣ modulation circuit 12, and a second signal input terminal connected to the signal output terminal of the ΔΣ modulation circuit 13. The output digital modulation signal after delta sigma modulation and the digital modulation signal after delta sigma modulation output from the ΔΣ modulation circuit 13 are combined, and a combined signal of the two digital modulation signals is output to the high frequency circuit 32.
The high frequency circuit 32 has a signal input terminal connected to a signal output terminal of the synthesis circuit 31, converts the signal power of the synthesis signal output from the synthesis circuit 31 to a desired power level, and converts the frequency of the synthesis signal to IF. Convert from frequency to RF frequency.
In the second embodiment, an example is shown in which the high-frequency circuit 32 performs conversion of the signal power and frequency of the combined signal. However, any one of the conversion of signal power or frequency may be performed. Good.
　次に動作について説明する。
　変調信号出力回路部１については、上記実施の形態１と同様であるため、ここでは、高周波部３について説明する。
　合成回路３１は、ΔΣ変調回路１２から出力されたデルタシグマ変調後のディジタル変調信号と、ΔΣ変調回路１３から出力されたデルタシグマ変調後のディジタル変調信号とを合成して、２つのディジタル変調信号の合成信号を出力する。
　このとき、２つのディジタル変調信号の所望信号成分はコヒーレントであるため、合成回路３１の合成によって、２つの所望信号成分が電圧加算となる。一方、２つのディジタル変調信号のΔΣノイズ成分はインコヒーレントであるため、合成回路３１の合成によって、２つのディジタル変調信号のΔΣノイズ成分が電力加算となる。
　その結果、合成回路３１から出力される合成信号における所望信号成分とΔΣノイズ成分との電力比であるＳＮＲは、各々のΔΣ変調回路１２，１３から出力されるディジタル変調信号における所望信号成分とΔΣノイズ成分とのＳＮＲと比べて、理論的には３ｄＢ改善される。 Next, the operation will be described.
Since the modulation signal output circuit unit 1 is the same as that of the first embodiment, only the high frequency unit 3 will be described here.
The synthesizing circuit 31 synthesizes the digital modulation signal after the delta-sigma modulation output from the ΔΣ modulation circuit 12 and the digital modulation signal after the delta-sigma modulation output from the ΔΣ modulation circuit 13 to synthesize two digital modulation signals. The combined signal is output.
At this time, since the desired signal components of the two digital modulation signals are coherent, the two desired signal components are voltage-added by the synthesis of the synthesis circuit 31. On the other hand, since the ΔΣ noise components of the two digital modulation signals are incoherent, the synthesis of the synthesis circuit 31 causes the ΔΣ noise components of the two digital modulation signals to be power addition.
As a result, the SNR that is the power ratio between the desired signal component and the ΔΣ noise component in the combined signal output from the combining circuit 31 is equal to the desired signal component in the digital modulation signal output from each of the ΔΣ modulation circuits 12 and 13 and ΔΣ. Compared to the SNR with the noise component, the theoretical improvement is 3 dB.
　高周波回路３２は、合成回路３１から合成信号を受けると、その合成信号の信号電力を所望の電力レベルに変換するとともに、その合成信号の周波数をＩＦ周波数からＲＦ周波数に変換する。 When the high frequency circuit 32 receives the combined signal from the combining circuit 31, the high frequency circuit 32 converts the signal power of the combined signal into a desired power level and converts the frequency of the combined signal from the IF frequency to the RF frequency.
　以上で明らかなように、この実施の形態２によれば、通信データを変調してディジタル変調信号を生成するモデム１１と、モデム１１により生成されたディジタル変調信号をデルタシグマ変調して、デルタシグマ変調後のディジタル変調信号を出力するΔΣ変調回路１２，１３と、ΔΣ変調回路１２から出力されたデルタシグマ変調後のディジタル変調信号と、ΔΣ変調回路１３から出力されたデルタシグマ変調後のディジタル変調信号とを合成し、２つのディジタル変調信号の合成信号を出力する合成回路３１と、合成回路３１から出力された合成信号の信号電力を所望の電力レベルに変換するとともに、その合成信号の周波数をＩＦ周波数からＲＦ周波数に変換する高周波回路３２とを備え、ΔΣ変調回路１２，１３の回路構成が異なっているように構成したので、ディジタル変調信号のデルタシグマ変調に伴うΔΣノイズを低減して、ＳＮＲを高めることができる効果を奏する。
　また、この実施の形態２では、高周波部３が、ΔΣ変調回路１２，１３から出力されたディジタル変調信号を合成してから、２つのディジタル変調信号の合成信号の信号電力の電力レベルや周波数を変換するようにしているので、高周波回路の個数を１個にすることができ、回路構成の簡単化を図ることができる効果を奏する。 As is apparent from the above, according to the second embodiment, the modem 11 that modulates communication data to generate a digital modulation signal, and the digital modulation signal generated by the modem 11 are delta-sigma modulated to produce a delta-sigma ΔΣ modulation circuits 12 and 13 for outputting the modulated digital modulation signal, the digital modulation signal after the delta-sigma modulation output from the ΔΣ modulation circuit 12, and the digital modulation after the delta-sigma modulation output from the ΔΣ modulation circuit 13 And combining the signal and outputting a combined signal of the two digital modulation signals, converting the signal power of the combined signal output from the combining circuit 31 to a desired power level, and changing the frequency of the combined signal And a high-frequency circuit 32 for converting the IF frequency to the RF frequency, and the ΔΣ modulation circuits 12 and 13 have different circuit configurations. With this configuration, it is possible to reduce the ΔΣ noise associated with the delta-sigma modulation of the digital modulation signal and increase the SNR.
In the second embodiment, the high frequency unit 3 combines the digital modulation signals output from the ΔΣ modulation circuits 12 and 13 and then sets the power level and frequency of the signal power of the combined signal of the two digital modulation signals. Since conversion is performed, the number of high-frequency circuits can be reduced to one, and the circuit configuration can be simplified.
　この実施の形態２では、変調信号出力回路部１が、回路構成が異なる２つのΔΣ変調回路１２，１３を実装している例を示したが、変調信号出力回路部１が、回路構成が異なるＮ個のΔΣ変調回路を実装するとともに、高周波部２の合成回路３１が、Ｎ個のΔΣ変調回路から出力されたデルタシグマ変調後のディジタル変調信号を合成するようにしてもよい。 In the second embodiment, the modulation signal output circuit unit 1 includes two ΔΣ modulation circuits 12 and 13 having different circuit configurations. However, the modulation signal output circuit unit 1 has a different circuit configuration. N number of ΔΣ modulation circuits may be mounted, and the combining circuit 31 of the high-frequency unit 2 may combine the delta-sigma modulated digital modulation signals output from the N ΔΣ modulation circuits.
実施の形態３．
　上記実施の形態１では、合成回路２３が、高周波回路２１から出力された変換後のディジタル変調信号と、高周波回路２２から出力された変換後のディジタル変調信号とを合成して、２つのディジタル変調信号の合成信号を出力するものを示したが、高周波回路２１，２２から出力された変換後のディジタル変調信号を空間に放射する複数のアンテナを備え、複数のアンテナから放射されたディジタル変調信号が空間で合成されるようにしてもよい。 Embodiment 3 FIG.
In the first embodiment, the synthesis circuit 23 synthesizes the converted digital modulation signal output from the high-frequency circuit 21 and the converted digital modulation signal output from the high-frequency circuit 22 to produce two digital modulations. Although the output of the composite signal of the signal is shown, the digital modulation signal radiated from the plurality of antennas is provided with a plurality of antennas that radiate the converted digital modulation signals output from the high- frequency circuits 21 and 22 to the space. You may make it synthesize | combine in space.
　図３はこの発明の実施の形態３によるディジタル送信機を示す構成図であり、図３において、図１と同一符号は同一または相当部分を示すので説明を省略する。
　高周波部４は高周波回路２１，２２とアンテナ４１，４２から構成されている回路である。
　アンテナ４１は高周波回路２１の信号出力端子と接続されており、高周波回路２１から出力された変換後のディジタル変調信号を空間に放射する。
　アンテナ４２は高周波回路２２の信号出力端子と接続されており、高周波回路２２から出力された変換後のディジタル変調信号を空間に放射する。 3 is a block diagram showing a digital transmitter according to Embodiment 3 of the present invention. In FIG. 3, the same reference numerals as those in FIG.
The high frequency section 4 is a circuit composed of high frequency circuits 21 and 22 and antennas 41 and 42.
The antenna 41 is connected to the signal output terminal of the high-frequency circuit 21 and radiates the converted digital modulation signal output from the high-frequency circuit 21 to the space.
The antenna 42 is connected to the signal output terminal of the high-frequency circuit 22 and radiates the converted digital modulation signal output from the high-frequency circuit 22 into space.
　次に動作について説明する。
　変調信号出力回路部１については、上記実施の形態１と同様であるため、ここでは、高周波部４について説明する。
　高周波回路２１は、ΔΣ変調回路１２からデルタシグマ変調後のディジタル変調信号を受けると、上記実施の形態１と同様に、そのディジタル変調信号の信号電力を所望の電力レベルに変換するとともに、そのディジタル変調信号の周波数をＩＦ周波数からＲＦ周波数に変換し、変換後のディジタル変調信号を出力する。
　高周波回路２２は、ΔΣ変調回路１３からデルタシグマ変調後のディジタル変調信号を受けると、上記実施の形態１と同様に、そのディジタル変調信号の信号電力を所望の電力レベルに変換するとともに、そのディジタル変調信号の周波数をＩＦ周波数からＲＦ周波数に変換し、変換後のディジタル変調信号を出力する。
　ここでは、高周波回路２１から出力される変換後のディジタル変調信号と、高周波回路２２から出力される変換後のディジタル変調信号とは、信号電力が同一で、周波数が同一であるものとする。
　高周波回路２１，２２から出力される変換後のディジタル変調信号についても、ΔΣノイズ成分がインコヒーレントであるが、ディジタル変調信号の所望信号成分はコヒーレントである。 Next, the operation will be described.
Since the modulation signal output circuit unit 1 is the same as that in the first embodiment, the high-frequency unit 4 will be described here.
When receiving the digital modulation signal after the delta-sigma modulation from the ΔΣ modulation circuit 12, the high frequency circuit 21 converts the signal power of the digital modulation signal to a desired power level as well as the digital modulation signal, as in the first embodiment. The frequency of the modulation signal is converted from the IF frequency to the RF frequency, and the converted digital modulation signal is output.
When receiving the digital modulation signal after the delta sigma modulation from the ΔΣ modulation circuit 13, the high frequency circuit 22 converts the signal power of the digital modulation signal to a desired power level as well as the digital modulation signal, as in the first embodiment. The frequency of the modulation signal is converted from the IF frequency to the RF frequency, and the converted digital modulation signal is output.
Here, it is assumed that the converted digital modulation signal output from the high-frequency circuit 21 and the converted digital modulation signal output from the high-frequency circuit 22 have the same signal power and the same frequency.
Also for the converted digital modulation signals output from the high- frequency circuits 21 and 22, the ΔΣ noise component is incoherent, but the desired signal component of the digital modulation signal is coherent.
　アンテナ４１は、高周波回路２１から変換後のディジタル変調信号を受けると、そのディジタル変調信号を空間に放射する。
　アンテナ４２は、高周波回路２２から変換後のディジタル変調信号を受けると、そのディジタル変調信号を空間に放射する。
　アンテナ４１から放射されたディジタル変調信号と、アンテナ４２から放射されたディジタル変調信号とは、空間で合成される。 When receiving the converted digital modulation signal from the high-frequency circuit 21, the antenna 41 radiates the digital modulation signal to space.
When the antenna 42 receives the converted digital modulation signal from the high frequency circuit 22, the antenna 42 radiates the digital modulation signal to space.
The digital modulation signal radiated from the antenna 41 and the digital modulation signal radiated from the antenna 42 are combined in space.
　このとき、高周波回路２１，２２から出力された２つのディジタル変調信号の所望信号成分はコヒーレントであるため、空間での合成によって、２つの所望信号成分が電圧加算となる。一方、２つのディジタル変調信号のΔΣノイズ成分はインコヒーレントであるため、空間での合成によって、２つのディジタル変調信号のΔΣノイズ成分が電力加算となる。
　その結果、空間で合成された信号における所望信号成分とΔΣノイズ成分との電力比であるＳＮＲは、各々の高周波回路２１，２２から出力されるディジタル変調信号における所望信号成分とΔΣノイズ成分とのＳＮＲと比べて、理論的には３ｄＢ改善される。したがって、当該ディジタル送信機との通信対象である受信機は、ＳＮＲが高い信号を受信することができる。 At this time, since the desired signal components of the two digital modulation signals output from the high- frequency circuits 21 and 22 are coherent, the two desired signal components are voltage-added by synthesis in space. On the other hand, since the ΔΣ noise components of the two digital modulation signals are incoherent, the ΔΣ noise components of the two digital modulation signals are summed by combining in space.
As a result, the SNR, which is the power ratio between the desired signal component and the ΔΣ noise component in the signal synthesized in space, is the difference between the desired signal component and the ΔΣ noise component in the digital modulation signal output from each of the high frequency circuits 21 and 22. Compared to the SNR, the theoretical improvement is 3 dB. Therefore, a receiver that is a communication target with the digital transmitter can receive a signal having a high SNR.
　以上で明らかなように、この実施の形態３によれば、通信データを変調してディジタル変調信号を生成するモデム１１と、モデム１１により生成されたディジタル変調信号をデルタシグマ変調して、デルタシグマ変調後のディジタル変調信号を出力するΔΣ変調回路１２，１３と、ΔΣ変調回路１２，１３から出力されたディジタル変調信号の信号電力を所望の電力レベルに変換するとともに、そのディジタル変調信号の周波数をＩＦ周波数からＲＦ周波数に変換する高周波回路２１，２２と、高周波回路２１，２２から出力された変換後のディジタル変調信号を空間に放射するアンテナ４１，４２とを備え、ΔΣ変調回路１２，１３の回路構成が異なっているように構成したので、ディジタル変調信号のデルタシグマ変調に伴うΔΣノイズを低減して、ＳＮＲを高めることができる効果を奏する。
　また、この実施の形態３では、合成回路２３が不要になる。 As is apparent from the above, according to the third embodiment, the modem 11 that modulates communication data to generate a digital modulation signal, and the digital modulation signal generated by the modem 11 are delta-sigma modulated to produce a delta-sigma ΔΣ modulation circuits 12 and 13 that output the modulated digital modulation signal, and the signal power of the digital modulation signal output from the ΔΣ modulation circuits 12 and 13 is converted to a desired power level, and the frequency of the digital modulation signal is changed. High- frequency circuits 21 and 22 that convert IF frequencies to RF frequencies, and antennas 41 and 42 that radiate converted digital modulation signals output from the high- frequency circuits 21 and 22 into space. Since the circuit configuration is different, ΔΣ noise associated with delta-sigma modulation of digitally modulated signals is reduced. As a result, the SNR can be increased.
In the third embodiment, the synthesis circuit 23 is not necessary.
実施の形態４．
　上記実施の形態１～３では、変調信号出力回路部１が、回路構成が異なるΔΣ変調回路１２，１３を実装しているものを示したが、この場合、ΔΣ変調回路１２，１３の回路構成をそれぞれ設計する必要があるため、回路開発の負荷が増大する。
　そこで、この実施の形態４では、回路構成が同一のΔΣ変調回路を変調信号出力回路部に複数実装し、複数のΔΣ変調回路に対して異なる動作条件を設定するものについて説明する。 Embodiment 4 FIG.
In the first to third embodiments, the modulation signal output circuit unit 1 is mounted with the ΔΣ modulation circuits 12 and 13 having different circuit configurations. In this case, the circuit configuration of the ΔΣ modulation circuits 12 and 13 is provided. Therefore, the load of circuit development increases.
In the fourth embodiment, therefore, a case where a plurality of ΔΣ modulation circuits having the same circuit configuration are mounted in the modulation signal output circuit section and different operating conditions are set for the plurality of ΔΣ modulation circuits will be described.
　図４はこの発明の実施の形態４によるディジタル送信機を示す構成図であり、図４において、図１と同一符号は同一または相当部分を示すので説明を省略する。
　図４の例では、ディジタル送信機が高周波部２を実装している例を示しているが、ディジタル送信機が図２の高周波部３や図３の高周波部４を実装しているものであってもよい。
　変調信号出力回路部５はモデム１１、ΔΣ変調回路５１，５２及び設定回路５３から構成されているディジタル回路である。 4 is a block diagram showing a digital transmitter according to Embodiment 4 of the present invention. In FIG. 4, the same reference numerals as those in FIG.
In the example of FIG. 4, an example is shown in which the digital transmitter is mounted with the high-frequency unit 2, but the digital transmitter is mounted with the high-frequency unit 3 of FIG. 2 or the high-frequency unit 4 of FIG. 3. May be.
The modulation signal output circuit unit 5 is a digital circuit including a modem 11, ΔΣ modulation circuits 51 and 52, and a setting circuit 53.
　ΔΣ変調回路５１は信号入力端子がモデム１１の信号出力端子と接続されており、モデム１１から出力されたディジタル変調信号をデルタシグマ変調して、デルタシグマ変調後のディジタル変調信号を出力するディジタル回路である。
　ΔΣ変調回路５２はΔΣ変調回路５１と回路構成が同一の回路である。ΔΣ変調回路５２は信号入力端子がモデム１１の信号出力端子と接続されており、モデム１１から出力されたディジタル変調信号をデルタシグマ変調して、デルタシグマ変調後のディジタル変調信号を出力する。
　設定回路５３はΔΣ変調回路５１，５２に対して異なる動作条件を設定する回路である。 The ΔΣ modulation circuit 51 has a signal input terminal connected to the signal output terminal of the modem 11, and delta-sigma modulates the digital modulation signal output from the modem 11 and outputs a digital modulation signal after delta-sigma modulation. It is.
The ΔΣ modulation circuit 52 is a circuit having the same circuit configuration as the ΔΣ modulation circuit 51. The ΔΣ modulation circuit 52 has a signal input terminal connected to the signal output terminal of the modem 11, delta-sigma-modulates the digital modulation signal output from the modem 11, and outputs a digital modulation signal after delta-sigma modulation.
The setting circuit 53 is a circuit for setting different operating conditions for the ΔΣ modulation circuits 51 and 52.
　図５はこの発明の実施の形態４によるディジタル送信機のΔΣ変調回路５１，５２を示す構成図である。
　図５において、初期値回路６１は設定回路５３により設定された動作条件に対応するディジタル変調信号の初期値を出力する回路である。
　ただし、設定回路５３が、ΔΣ変調回路５１，５２に対して異なる動作条件を設定するため、ΔΣ変調回路５１の初期値回路６１が出力する初期値と、ΔΣ変調回路５２の初期値回路６１が出力する初期値とは異なる値になる。
　ＰＮ信号生成回路６２は設定回路５３により設定された動作条件に対応するＰＮ信号（疑似雑音信号）を生成して、そのＰＮ信号を出力する回路である。
　ただし、設定回路５３が、ΔΣ変調回路５１，５２に対して異なる動作条件を設定するため、ΔΣ変調回路５１のＰＮ信号生成回路６２が出力するＰＮ信号と、ΔΣ変調回路５２のＰＮ信号生成回路６２が出力するＰＮ信号とは異なる信号になる。 FIG. 5 is a block diagram showing ΔΣ modulation circuits 51 and 52 of a digital transmitter according to Embodiment 4 of the present invention.
In FIG. 5, an initial value circuit 61 is a circuit that outputs an initial value of a digital modulation signal corresponding to the operating condition set by the setting circuit 53.
However, since the setting circuit 53 sets different operating conditions for the ΔΣ modulation circuits 51 and 52, the initial value output from the initial value circuit 61 of the ΔΣ modulation circuit 51 and the initial value circuit 61 of the ΔΣ modulation circuit 52 are It becomes a value different from the initial value to be output.
The PN signal generation circuit 62 is a circuit that generates a PN signal (pseudo noise signal) corresponding to the operating condition set by the setting circuit 53 and outputs the PN signal.
However, since the setting circuit 53 sets different operating conditions for the ΔΣ modulation circuits 51 and 52, the PN signal output from the PN signal generation circuit 62 of the ΔΣ modulation circuit 51 and the PN signal generation circuit of the ΔΣ modulation circuit 52 are set. The signal is different from the PN signal output by 62.
　加算器６３は第１の信号入力端子がモデム１１の信号出力端子と接続され、第２の信号入力端子が初期値回路６１の信号出力端子と接続され、第３の信号入力端子がＰＮ信号生成回路６２の信号出力端子と接続されており、動作タイミングを示すクロック群のうち、１番目のクロックが入力されると、モデム１１から出力されたディジタル変調信号に対して、初期値回路６１から出力された初期値と、ＰＮ信号生成回路６２から出力された疑似雑音信号とを加算して、初期値及び疑似雑音信号を加算したディジタル変調信号をΔΣ変調器６４に出力する。また、２番目以降のクロックが入力されると、モデム１１から出力されたディジタル変調信号に対して、ＰＮ信号生成回路６２から出力された疑似雑音信号を加算して、疑似雑音信号を加算したディジタル変調信号をΔΣ変調器６４に出力する。
　ΔΣ変調器６４は信号入力端子が加算器６３の信号出力端子と接続されており、加算器６３から出力されたディジタル変調信号をデルタシグマ変調して、デルタシグマ変調後のディジタル変調信号を出力するディジタル回路である。 The adder 63 has a first signal input terminal connected to the signal output terminal of the modem 11, a second signal input terminal connected to the signal output terminal of the initial value circuit 61, and a third signal input terminal generating a PN signal. When connected to the signal output terminal of the circuit 62 and the first clock of the clock group indicating the operation timing is input, the digital modulation signal output from the modem 11 is output from the initial value circuit 61. The initial value and the pseudo noise signal output from the PN signal generation circuit 62 are added, and a digital modulation signal obtained by adding the initial value and the pseudo noise signal is output to the ΔΣ modulator 64. When the second and subsequent clocks are input, the digital noise signal output from the PN signal generation circuit 62 is added to the digital modulation signal output from the modem 11 to add the pseudo noise signal. The modulation signal is output to the ΔΣ modulator 64.
The signal input terminal of the ΔΣ modulator 64 is connected to the signal output terminal of the adder 63, and the digital modulation signal output from the adder 63 is delta-sigma-modulated to output a digital modulation signal after delta-sigma modulation. It is a digital circuit.
　次に動作について説明する。
　変調信号出力回路部５以外は、上記実施の形態１～３と同様であるため、ここでは、変調信号出力回路部５について説明する。
　まず、設定回路５３は、ΔΣ変調回路５１，５２に対して異なる動作条件を設定する。
　ΔΣ変調回路５１，５２の初期値回路６１は、設定回路５３が動作条件を設定すると、その動作条件に対応するディジタル変調信号の初期値を加算器６３に出力するが、設定回路５３が、ΔΣ変調回路５１，５２に対して異なる動作条件を設定するため、ΔΣ変調回路５１の初期値回路６１が出力する初期値と、ΔΣ変調回路５２の初期値回路６１が出力する初期値とは異なる値になる。この実施の形態４では、初期値が異なっていれば、どのような初期値であってもよく、設計時に適宜決定されればよい。 Next, the operation will be described.
Since the configuration other than the modulation signal output circuit section 5 is the same as in the first to third embodiments, the modulation signal output circuit section 5 will be described here.
First, the setting circuit 53 sets different operating conditions for the ΔΣ modulation circuits 51 and 52.
When the setting circuit 53 sets an operating condition, the initial value circuit 61 of the ΔΣ modulation circuits 51 and 52 outputs an initial value of a digital modulation signal corresponding to the operating condition to the adder 63. Since different operating conditions are set for the modulation circuits 51 and 52, the initial value output from the initial value circuit 61 of the ΔΣ modulation circuit 51 is different from the initial value output from the initial value circuit 61 of the ΔΣ modulation circuit 52. become. In the fourth embodiment, any initial value may be used as long as the initial value is different, and it may be appropriately determined at the time of design.
　ΔΣ変調回路５１，５２のＰＮ信号生成回路６２は、設定回路５３が動作条件を設定すると、その動作条件に対応するＰＮ信号を生成して、そのＰＮ信号を加算器６３に出力するが、設定回路５３が、ΔΣ変調回路５１，５２に対して異なる動作条件を設定するため、ΔΣ変調回路５１のＰＮ信号生成回路６２が出力するＰＮ信号と、ΔΣ変調回路５２のＰＮ信号生成回路６２が出力するＰＮ信号とは異なる信号になる。この実施の形態４では、ＰＮ信号が異なっていれば、どのようなＰＮ信号であってもよく、設計時に適宜決定されればよい。 When the setting circuit 53 sets an operating condition, the PN signal generating circuit 62 of the ΔΣ modulation circuits 51 and 52 generates a PN signal corresponding to the operating condition and outputs the PN signal to the adder 63. Since the circuit 53 sets different operating conditions for the ΔΣ modulation circuits 51 and 52, the PN signal output from the PN signal generation circuit 62 of the ΔΣ modulation circuit 51 and the PN signal generation circuit 62 of the ΔΣ modulation circuit 52 output. The PN signal is different from the PN signal. In the fourth embodiment, any PN signal may be used as long as the PN signals are different, and may be appropriately determined at the time of design.
　ΔΣ変調回路５１，５２の加算器６３は、動作タイミングを示すクロック群のうち、１番目のクロックが入力されると、モデム１１から出力されたディジタル変調信号に対して、初期値回路６１から出力された初期値と、ＰＮ信号生成回路６２から出力された疑似雑音信号とを加算して、初期値及び疑似雑音信号を加算したディジタル変調信号をΔΣ変調器６４に出力する。
　また、ΔΣ変調回路５１，５２の加算器６３は、２番目以降のクロックが入力されると、モデム１１から出力されたディジタル変調信号に対して、ＰＮ信号生成回路６２から出力された疑似雑音信号を加算して、疑似雑音信号を加算したディジタル変調信号をΔΣ変調器６４に出力する。 The adder 63 of the ΔΣ modulation circuits 51 and 52 outputs the digital modulation signal output from the modem 11 from the initial value circuit 61 when the first clock of the clock group indicating the operation timing is input. The initial value and the pseudo noise signal output from the PN signal generation circuit 62 are added, and a digital modulation signal obtained by adding the initial value and the pseudo noise signal is output to the ΔΣ modulator 64.
Further, when the second and subsequent clocks are input, the adder 63 of the ΔΣ modulation circuits 51 and 52 receives the pseudo noise signal output from the PN signal generation circuit 62 in response to the digital modulation signal output from the modem 11. And the digital modulation signal added with the pseudo noise signal is output to the ΔΣ modulator 64.
　ΔΣ変調回路５１，５２のΔΣ変調器６４は、加算器６３からディジタル変調信号を受けると、そのディジタル変調信号をデルタシグマ変調し、デルタシグマ変調後のディジタル変調信号を高周波回路２１，２２に出力する。
　ΔΣ変調回路５１，５２の回路構成が同一であっても、初期値とＰＮ信号が異なれば、モデム１１から出力されたディジタル変調信号をデルタシグマ変調する際に発生するΔΣノイズの特性がインコヒーレントになる。
　一方、初期値とＰＮ信号が異なっていても、モデム１１から出力された同一のディジタル変調信号をデルタシグマ変調するものであれば、所望信号成分はコヒーレントになる。
　この実施の形態４では、初期値とＰＮ信号の双方が異なっている例を示したが、初期値又はＰＮ信号のいずれか一方が異なっていれば、ΔΣノイズの特性をインコヒーレントにして、所望信号成分をコヒーレントにすることができる。したがって、ΔΣ変調回路５１の初期値回路６１が出力する初期値と、ΔΣ変調回路５２の初期値回路６１が出力する初期値とが異なっていれば、ΔΣ変調回路５１，５２のＰＮ信号生成回路６２が出力するＰＮ信号が同一であってもよい。あるいは、ΔΣ変調回路５１のＰＮ信号生成回路６２が出力するＰＮ信号と、ΔΣ変調回路５２のＰＮ信号生成回路６２が出力するＰＮ信号とが異なっていれば、ΔΣ変調回路５１，５２の初期値回路６１が出力する初期値が同一であってもよい。 When receiving the digital modulation signal from the adder 63, the ΔΣ modulator 64 of the ΔΣ modulation circuits 51 and 52 performs delta sigma modulation on the digital modulation signal and outputs the digital modulation signal after the delta sigma modulation to the high frequency circuits 21 and 22. To do.
Even if the circuit configurations of the ΔΣ modulation circuits 51 and 52 are the same, if the initial value and the PN signal are different, the characteristic of ΔΣ noise generated when delta-sigma modulation of the digital modulation signal output from the modem 11 is incoherent. become.
On the other hand, even if the initial value and the PN signal are different, the desired signal component becomes coherent if the same digital modulation signal output from the modem 11 is subjected to delta sigma modulation.
In the fourth embodiment, an example is shown in which both the initial value and the PN signal are different. However, if either the initial value or the PN signal is different, the ΔΣ noise characteristic is made incoherent and desired. The signal component can be made coherent. Therefore, if the initial value output from the initial value circuit 61 of the ΔΣ modulation circuit 51 and the initial value output from the initial value circuit 61 of the ΔΣ modulation circuit 52 are different, the PN signal generation circuit of the ΔΣ modulation circuits 51 and 52 The PN signals output from 62 may be the same. Alternatively, if the PN signal output from the PN signal generation circuit 62 of the ΔΣ modulation circuit 51 and the PN signal output from the PN signal generation circuit 62 of the ΔΣ modulation circuit 52 are different, the initial values of the ΔΣ modulation circuits 51 and 52 are set. The initial value output from the circuit 61 may be the same.
　以上で明らかなように、この実施の形態４によれば、変調信号出力回路部５が、回路構成が同一のΔΣ変調回路５１，５２を実装するとともに、ΔΣ変調回路５１，５２に対して異なる動作条件を設定する設定回路５３を実装するように構成したので、上記実施の形態１と同様に、ディジタル変調信号のデルタシグマ変調に伴うΔΣノイズを低減して、ＳＮＲを高めることができるほか、回路構成が異なるΔΣ変調回路１２，１３を実装する場合よりも、ΔΣ変調回路５１，５２の回路開発に要する負荷を軽減することができる効果を奏する。 As is apparent from the above, according to the fourth embodiment, the modulation signal output circuit unit 5 is mounted with the ΔΣ modulation circuits 51 and 52 having the same circuit configuration and is different from the ΔΣ modulation circuits 51 and 52. Since the setting circuit 53 for setting the operating conditions is mounted, as in the first embodiment, the ΔΣ noise associated with the delta-sigma modulation of the digital modulation signal can be reduced and the SNR can be increased. Compared with the case where the ΔΣ modulation circuits 12 and 13 having different circuit configurations are mounted, the load required for the circuit development of the ΔΣ modulation circuits 51 and 52 can be reduced.
実施の形態５．
　上記実施の形態４では、回路構成が同一のΔΣ変調回路５１，５２が内蔵しているΔΣ変調器６４の個数が１個である単段構成のΔΣ変調回路について示したが、回路構成が同一のΔΣ変調回路５１，５２が内蔵しているΔΣ変調器の個数が複数である複数段構成のΔΣ変調回路であってもよい。 Embodiment 5 FIG.
In the fourth embodiment, the single-stage ΔΣ modulation circuit in which the number of ΔΣ modulators 64 included in the ΔΣ modulation circuits 51 and 52 having the same circuit configuration is one is shown. However, the circuit configuration is the same. The delta- sigma modulation circuits 51 and 52 may include a plurality of delta-sigma modulators having a plurality of delta-sigma modulators.
　図６はこの発明の実施の形態５によるディジタル送信機のΔΣ変調回路５１，５２を示す構成図である。
　図６において、初期値回路７１は設定回路５３により設定された動作条件に対応するディジタル変調信号の第一の初期値と第二の初期値を出力する回路である。
　ただし、設定回路５３が、ΔΣ変調回路５１，５２に対して異なる動作条件を設定するため、ΔΣ変調回路５１の初期値回路７１が出力する第一の初期値と、ΔΣ変調回路５２の初期値回路７１が出力する第一の初期値とは異なる値になる。また、ΔΣ変調回路５１の初期値回路７１が出力する第二の初期値と、ΔΣ変調回路５２の初期値回路７１が出力する第二の初期値とは異なる値になる。 FIG. 6 is a block diagram showing ΔΣ modulation circuits 51 and 52 of a digital transmitter according to Embodiment 5 of the present invention.
In FIG. 6, an initial value circuit 71 is a circuit that outputs a first initial value and a second initial value of a digital modulation signal corresponding to the operating condition set by the setting circuit 53.
However, since the setting circuit 53 sets different operating conditions for the ΔΣ modulation circuits 51 and 52, the first initial value output from the initial value circuit 71 of the ΔΣ modulation circuit 51 and the initial value of the ΔΣ modulation circuit 52 are set. It becomes a value different from the first initial value output from the circuit 71. Further, the second initial value output from the initial value circuit 71 of the ΔΣ modulation circuit 51 is different from the second initial value output from the initial value circuit 71 of the ΔΣ modulation circuit 52.
　ＰＮ信号生成回路７２は設定回路５３により設定された動作条件に対応する第一のＰＮ信号と第二のＰＮ信号を生成して、その第一のＰＮ信号と第二のＰＮ信号を出力する回路である。
　ただし、設定回路５３が、ΔΣ変調回路５１，５２に対して異なる動作条件を設定するため、ΔΣ変調回路５１のＰＮ信号生成回路７２が出力する第一のＰＮ信号と、ΔΣ変調回路５２のＰＮ信号生成回路７２が出力する第一のＰＮ信号とは異なる信号になる。また、ΔΣ変調回路５１のＰＮ信号生成回路７２が出力する第二のＰＮ信号と、ΔΣ変調回路５２のＰＮ信号生成回路７２が出力する第二のＰＮ信号とは異なる信号になる。
　オフセット生成回路７３は設定回路５３により設定された動作条件に対応するオフセット信号を生成する回路である。
　ただし、設定回路５３が、ΔΣ変調回路５１，５２に対して異なる動作条件を設定するため、ΔΣ変調回路５１のオフセット生成回路７３が出力するオフセット信号と、ΔΣ変調回路５２のオフセット生成回路７３が出力するオフセット信号とは異なる信号になる。 The PN signal generation circuit 72 generates a first PN signal and a second PN signal corresponding to the operating condition set by the setting circuit 53, and outputs the first PN signal and the second PN signal. It is.
However, since the setting circuit 53 sets different operating conditions for the ΔΣ modulation circuits 51 and 52, the first PN signal output from the PN signal generation circuit 72 of the ΔΣ modulation circuit 51 and the PN of the ΔΣ modulation circuit 52 are set. The signal is different from the first PN signal output from the signal generation circuit 72. Further, the second PN signal output from the PN signal generation circuit 72 of the ΔΣ modulation circuit 51 is different from the second PN signal output from the PN signal generation circuit 72 of the ΔΣ modulation circuit 52.
The offset generation circuit 73 is a circuit that generates an offset signal corresponding to the operating condition set by the setting circuit 53.
However, since the setting circuit 53 sets different operating conditions for the ΔΣ modulation circuits 51 and 52, the offset signal output from the offset generation circuit 73 of the ΔΣ modulation circuit 51 and the offset generation circuit 73 of the ΔΣ modulation circuit 52 It becomes a signal different from the offset signal to be output.
　加算器７４は第１の信号入力端子がモデム１１の信号出力端子と接続され、第２の信号入力端子が初期値回路７１の第一の信号出力端子と接続され、第３の信号入力端子がＰＮ信号生成回路７２の第一の信号出力端子と接続されており、動作タイミングを示すクロック群のうち、１番目のクロックが入力されると、モデム１１から出力されたディジタル変調信号に対して、初期値回路７１から出力された第一の初期値と、ＰＮ信号生成回路７２から出力された第一のＰＮ信号とを加算して、第一の初期値及び第一のＰＮ信号を加算したディジタル変調信号をΔΣ変調器７５に出力する。また、２番目以降のクロックが入力されると、モデム１１から出力されたディジタル変調信号に対して、ＰＮ信号生成回路７２から出力された第一のＰＮ信号を加算して、第一のＰＮ信号を加算したディジタル変調信号をΔΣ変調器７５に出力する第１の加算器である。
　ΔΣ変調器７５は信号入力端子が加算器７４の信号出力端子と接続されており、加算器７４から出力されたディジタル変調信号をデルタシグマ変調して、デルタシグマ変調後のディジタル変調信号を出力する第１のΔΣ変調器である。 The adder 74 has a first signal input terminal connected to the signal output terminal of the modem 11, a second signal input terminal connected to the first signal output terminal of the initial value circuit 71, and a third signal input terminal When connected to the first signal output terminal of the PN signal generation circuit 72 and the first clock of the clock group indicating the operation timing is input, the digital modulation signal output from the modem 11 is A digital value obtained by adding the first initial value output from the initial value circuit 71 and the first PN signal output from the PN signal generation circuit 72 and adding the first initial value and the first PN signal. The modulation signal is output to the ΔΣ modulator 75. When the second and subsequent clocks are input, the first PN signal output from the PN signal generation circuit 72 is added to the digital modulation signal output from the modem 11 to obtain the first PN signal. Is a first adder that outputs a digital modulation signal obtained by adding to the ΔΣ modulator 75.
The ΔΣ modulator 75 has a signal input terminal connected to the signal output terminal of the adder 74, delta-sigma modulates the digital modulation signal output from the adder 74, and outputs a digital modulation signal after delta-sigma modulation. This is the first ΔΣ modulator.
　加算器７６は第１の信号入力端子がΔΣ変調器７５の信号出力端子と接続され、第２の信号入力端子が初期値回路７１の第二の信号出力端子と接続され、第３の信号入力端子がＰＮ信号生成回路７２の第二の信号出力端子と接続され、第４の信号入力端子がオフセット生成回路７３と接続されており、動作タイミングを示すクロック群のうち、１番目のクロックが入力されると、ΔΣ変調器７５から出力されたディジタル変調信号に対して、初期値回路７１から出力された第二の初期値と、ＰＮ信号生成回路７２から出力された第二のＰＮ信号と、オフセット生成回路７３から出力されたオフセット信号とを加算して、第二の初期値、第二のＰＮ信号及びオフセット信号を加算したディジタル変調信号をΔΣ変調器７７に出力する。また、２番目以降のクロックが入力されると、ΔΣ変調器７５から出力されたディジタル変調信号に対して、ＰＮ信号生成回路７２から出力された第二のＰＮ信号と、オフセット生成回路７３から出力されたオフセット信号とを加算して、第二のＰＮ信号及びオフセット信号を加算したディジタル変調信号をΔΣ変調器７７に出力する第２の加算器である。 The adder 76 has a first signal input terminal connected to the signal output terminal of the ΔΣ modulator 75, a second signal input terminal connected to the second signal output terminal of the initial value circuit 71, and a third signal input. The terminal is connected to the second signal output terminal of the PN signal generation circuit 72, the fourth signal input terminal is connected to the offset generation circuit 73, and the first clock in the clock group indicating the operation timing is input. Then, with respect to the digital modulation signal output from the ΔΣ modulator 75, the second initial value output from the initial value circuit 71, the second PN signal output from the PN signal generation circuit 72, The offset signal output from the offset generation circuit 73 is added, and a digital modulation signal obtained by adding the second initial value, the second PN signal, and the offset signal is output to the ΔΣ modulator 77. When the second and subsequent clocks are input, the second PN signal output from the PN signal generation circuit 72 and the offset generation circuit 73 are output with respect to the digital modulation signal output from the ΔΣ modulator 75. The second adder outputs the digital modulation signal obtained by adding the offset signal and the second PN signal and the offset signal to the ΔΣ modulator 77.
　ΔΣ変調器７７は信号入力端子が加算器７６の信号出力端子と接続されており、加算器７６から出力されたディジタル変調信号をデルタシグマ変調して、デルタシグマ変調後のディジタル変調信号を出力する第２のΔΣ変調器である。
　加算器７８は第１の信号入力端子がΔΣ変調器７５と接続され、第２の信号入力端子がΔΣ変調器７７と接続されており、ΔΣ変調器７５から出力されたディジタル変調信号とΔΣ変調器７７から出力されたディジタル変調信号とを加算して、加算したディジタル変調信号を出力する第３の加算器である。 The ΔΣ modulator 77 has a signal input terminal connected to the signal output terminal of the adder 76, and delta-sigma-modulates the digital modulation signal output from the adder 76 and outputs a digital modulation signal after delta-sigma modulation. This is the second ΔΣ modulator.
The adder 78 has a first signal input terminal connected to the ΔΣ modulator 75 and a second signal input terminal connected to the ΔΣ modulator 77, and the digital modulation signal output from the ΔΣ modulator 75 and the ΔΣ modulation. This is a third adder that adds the digital modulation signal output from the unit 77 and outputs the added digital modulation signal.
　次に動作について説明する。
　変調信号出力回路部５以外は、上記実施の形態１～３と同様であるため、ここでは、変調信号出力回路部５について説明する。
　まず、設定回路５３は、ΔΣ変調回路５１，５２に対して異なる動作条件を設定する。
　ΔΣ変調回路５１，５２の初期値回路７１は、設定回路５３が動作条件を設定すると、その動作条件に対応するディジタル変調信号の第一の初期値と第二の初期値をそれぞれ加算器７４，７６に出力するが、設定回路５３が、ΔΣ変調回路５１，５２に対して異なる動作条件を設定するため、ΔΣ変調回路５１の初期値回路７１が出力する第一の初期値と、ΔΣ変調回路５２の初期値回路７１が出力する第一の初期値とは異なる値になる。また、ΔΣ変調回路５１の初期値回路７１が出力する第二の初期値と、ΔΣ変調回路５２の初期値回路７１が出力する第二の初期値とは異なる値になる。この実施の形態５では、初期値が異なっていれば、どのような初期値であってもよく、設計時に適宜決定されればよい。 Next, the operation will be described.
Since the configuration other than the modulation signal output circuit section 5 is the same as in the first to third embodiments, the modulation signal output circuit section 5 will be described here.
First, the setting circuit 53 sets different operating conditions for the ΔΣ modulation circuits 51 and 52.
When the setting circuit 53 sets the operating condition, the initial value circuit 71 of the ΔΣ modulation circuits 51 and 52 adds the first initial value and the second initial value of the digital modulation signal corresponding to the operating condition to the adder 74 and However, since the setting circuit 53 sets different operating conditions for the ΔΣ modulation circuits 51 and 52, the first initial value output from the initial value circuit 71 of the ΔΣ modulation circuit 51, and the ΔΣ modulation circuit This is a value different from the first initial value output by the initial value circuit 71 of 52. Further, the second initial value output from the initial value circuit 71 of the ΔΣ modulation circuit 51 is different from the second initial value output from the initial value circuit 71 of the ΔΣ modulation circuit 52. In the fifth embodiment, any initial value may be used as long as the initial value is different, and it may be appropriately determined at the time of design.
　ΔΣ変調回路５１，５２のＰＮ信号生成回路７２は、設定回路５３が動作条件を設定すると、その動作条件に対応する第一のＰＮ信号と第二のＰＮ信号を生成して、その第一のＰＮ信号と第二のＰＮ信号をそれぞれ加算器７４，７６に出力するが、設定回路５３が、ΔΣ変調回路５１，５２に対して異なる動作条件を設定するため、ΔΣ変調回路５１のＰＮ信号生成回路７２が出力する第一のＰＮ信号と、ΔΣ変調回路５２のＰＮ信号生成回路７２が出力する第一のＰＮ信号とは異なる信号になる。また、ΔΣ変調回路５１のＰＮ信号生成回路７２が出力する第二のＰＮ信号と、ΔΣ変調回路５２のＰＮ信号生成回路７２が出力する第二のＰＮ信号とは異なる信号になる。この実施の形態５では、ＰＮ信号が異なっていれば、どのようなＰＮ信号であってもよく、設計時に適宜決定されればよい。
　ΔΣ変調回路５１，５２のオフセット生成回路７３は、設定回路５３が動作条件を設定すると、その動作条件に対応するオフセット信号を生成して、そのオフセット信号を加算器７６に出力するが、設定回路５３が、ΔΣ変調回路５１，５２に対して異なる動作条件を設定するため、ΔΣ変調回路５１のオフセット生成回路７３が出力するオフセット信号と、ΔΣ変調回路５２のオフセット生成回路７３が出力するオフセット信号とは異なる信号になる。この実施の形態５では、オフセット信号が異なっていれば、どのようなオフセット信号であってもよく、設計時に適宜決定されればよい。 When the setting circuit 53 sets an operating condition, the PN signal generating circuit 72 of the ΔΣ modulation circuits 51 and 52 generates a first PN signal and a second PN signal corresponding to the operating condition, and the first PN signal is generated. The PN signal and the second PN signal are output to the adders 74 and 76, respectively. Since the setting circuit 53 sets different operating conditions for the ΔΣ modulation circuits 51 and 52, the PN signal generation of the ΔΣ modulation circuit 51 is performed. The first PN signal output from the circuit 72 is different from the first PN signal output from the PN signal generation circuit 72 of the ΔΣ modulation circuit 52. Further, the second PN signal output from the PN signal generation circuit 72 of the ΔΣ modulation circuit 51 is different from the second PN signal output from the PN signal generation circuit 72 of the ΔΣ modulation circuit 52. In the fifth embodiment, any PN signal may be used as long as the PN signals are different, and may be appropriately determined at the time of design.
When the setting circuit 53 sets an operating condition, the offset generating circuit 73 of the ΔΣ modulation circuits 51 and 52 generates an offset signal corresponding to the operating condition and outputs the offset signal to the adder 76. 53 sets different operating conditions for the ΔΣ modulation circuits 51 and 52, so that the offset signal output from the offset generation circuit 73 of the ΔΣ modulation circuit 51 and the offset signal output from the offset generation circuit 73 of the ΔΣ modulation circuit 52 Is a different signal. In the fifth embodiment, any offset signal may be used as long as the offset signals are different, and may be determined as appropriate at the time of design.
　ΔΣ変調回路５１，５２の加算器７４は、動作タイミングを示すクロック群のうち、１番目のクロックが入力されると、モデム１１から出力されたディジタル変調信号に対して、初期値回路７１から出力された第一の初期値と、ＰＮ信号生成回路７２から出力された第一のＰＮ信号とを加算して、第一の初期値及び第一のＰＮ信号を加算したディジタル変調信号をΔΣ変調器７５に出力する。
　また、ΔΣ変調回路５１，５２の加算器７４は、２番目以降のクロックが入力されると、モデム１１から出力されたディジタル変調信号に対して、ＰＮ信号生成回路７２から出力された第一のＰＮ信号を加算して、第一のＰＮ信号を加算したディジタル変調信号をΔΣ変調器７５に出力する。 The adder 74 of the ΔΣ modulation circuits 51 and 52 outputs the digital modulation signal output from the modem 11 from the initial value circuit 71 when the first clock of the clock group indicating the operation timing is input. The first modulated initial value and the first PN signal output from the PN signal generation circuit 72 are added, and a digital modulation signal obtained by adding the first initial value and the first PN signal is added to the ΔΣ modulator. Output to 75.
Further, when the second and subsequent clocks are input, the adder 74 of the ΔΣ modulation circuits 51 and 52 receives the first modulation signal output from the PN signal generation circuit 72 in response to the digital modulation signal output from the modem 11. The digital modulation signal obtained by adding the PN signals and adding the first PN signal is output to the ΔΣ modulator 75.
　ΔΣ変調回路５１，５２のΔΣ変調器７５は、加算器７４からディジタル変調信号を受けると、そのディジタル変調信号をデルタシグマ変調し、デルタシグマ変調後のディジタル変調信号を加算器７６，７８に出力する。 When receiving the digital modulation signal from the adder 74, the ΔΣ modulator 75 of the ΔΣ modulation circuits 51 and 52 performs delta sigma modulation on the digital modulation signal and outputs the digital modulation signal after the delta sigma modulation to the adders 76 and 78. To do.
　ΔΣ変調回路５１，５２の加算器７６は、動作タイミングを示すクロック群のうち、１番目のクロックが入力されると、ΔΣ変調器７５から出力されたディジタル変調信号に対して、初期値回路７１から出力された第二の初期値と、ＰＮ信号生成回路７２から出力された第二のＰＮ信号と、オフセット生成回路７３から出力されたオフセット信号とを加算して、第二の初期値、第二のＰＮ信号及びオフセット信号を加算したディジタル変調信号をΔΣ変調器７７に出力する。
　また、ΔΣ変調回路５１，５２の加算器７６は、２番目以降のクロックが入力されると、ΔΣ変調器７５から出力されたディジタル変調信号に対して、ＰＮ信号生成回路７２から出力された第二のＰＮ信号と、オフセット生成回路７３から出力されたオフセット信号とを加算して、第二のＰＮ信号及びオフセット信号を加算したディジタル変調信号をΔΣ変調器７７に出力する。 The adder 76 of the ΔΣ modulation circuits 51 and 52 receives an initial value circuit 71 for the digital modulation signal output from the ΔΣ modulator 75 when the first clock of the clock group indicating the operation timing is input. , The second PN signal output from the PN signal generation circuit 72, and the offset signal output from the offset generation circuit 73 are added together to obtain a second initial value, A digital modulation signal obtained by adding the second PN signal and the offset signal is output to the ΔΣ modulator 77.
Further, when the second and subsequent clocks are input to the adder 76 of the ΔΣ modulation circuits 51 and 52, the digital modulation signal output from the ΔΣ modulator 75 is output from the PN signal generation circuit 72. The second PN signal and the offset signal output from the offset generation circuit 73 are added, and a digital modulation signal obtained by adding the second PN signal and the offset signal is output to the ΔΣ modulator 77.
　ΔΣ変調回路５１，５２のΔΣ変調器７７は、加算器７６からディジタル変調信号を受けると、そのディジタル変調信号をデルタシグマ変調し、デルタシグマ変調後のディジタル変調信号を加算器７８に出力する。 Upon receiving the digital modulation signal from the adder 76, the ΔΣ modulator 77 of the ΔΣ modulation circuits 51 and 52 performs delta sigma modulation on the digital modulation signal and outputs the digital modulation signal after the delta sigma modulation to the adder 78.
　ΔΣ変調回路５１，５２の加算器７８は、ΔΣ変調器７５から出力されたディジタル変調信号とΔΣ変調器７７から出力されたディジタル変調信号とを加算して、加算したディジタル変調信号を高周波回路２１，２２に出力する。
　この実施の形態５では、第一の初期値と第一のＰＮ信号と第二の初期値と第二のＰＮ信号とオフセット信号の全てが異なっている例を示したが、第一の初期値、第一のＰＮ信号、第二の初期値、第二のＰＮ信号及びオフセット信号のうち、少なくともいずれか１つ以上が異なっていれば、ΔΣノイズの特性をインコヒーレントにして、所望信号成分をコヒーレントにすることができる。 The adder 78 of the ΔΣ modulation circuits 51 and 52 adds the digital modulation signal output from the ΔΣ modulator 75 and the digital modulation signal output from the ΔΣ modulator 77, and adds the added digital modulation signal to the high frequency circuit 21. , 22.
In the fifth embodiment, the first initial value, the first PN signal, the second initial value, the second PN signal, and the offset signal are all different from each other. If at least one of the first PN signal, the second initial value, the second PN signal, and the offset signal is different, the ΔΣ noise characteristic is made incoherent, and the desired signal component is Can be coherent.
　以上で明らかなように、この実施の形態５によれば、変調信号出力回路部５が、回路構成が同一のΔΣ変調回路５１，５２を実装するとともに、ΔΣ変調回路５１，５２に対して異なる動作条件を設定する設定回路５３を実装するように構成したので、上記実施の形態１と同様に、ディジタル変調信号のデルタシグマ変調に伴うΔΣノイズを低減して、ＳＮＲを高めることができるほか、回路構成が異なるΔΣ変調回路１２，１３を実装する場合よりも、ΔΣ変調回路５１，５２の回路開発に要する負荷を軽減することができる効果を奏する。 As is apparent from the above, according to the fifth embodiment, the modulation signal output circuit unit 5 is mounted with the ΔΣ modulation circuits 51 and 52 having the same circuit configuration and is different from the ΔΣ modulation circuits 51 and 52. Since the setting circuit 53 for setting the operating conditions is mounted, as in the first embodiment, the ΔΣ noise associated with the delta-sigma modulation of the digital modulation signal can be reduced and the SNR can be increased. Compared with the case where the ΔΣ modulation circuits 12 and 13 having different circuit configurations are mounted, the load required for the circuit development of the ΔΣ modulation circuits 51 and 52 can be reduced.
　この実施の形態５では、回路構成が同一のΔΣ変調回路５１，５２が内蔵しているΔΣ変調器７５，７７が２段構成である例を示したが、ΔΣ変調回路５１，５２が内蔵しているΔΣ変調器が３段構成以上であってもよいことは言うまでもない。 In the fifth embodiment, the example in which the ΔΣ modulators 75 and 77 having the same circuit configuration in the ΔΣ modulation circuits 51 and 52 have a two-stage configuration is shown. However, the ΔΣ modulation circuits 51 and 52 are included in the internal circuit. Needless to say, the delta-sigma modulator may have three or more stages.
実施の形態６．
　上記実施の形態１～５では、変調信号出力回路部１（または、変調信号出力回路部５）が１個のモデム１１を実装し、モデム１１が同一のディジタル変調信号をΔΣ変調回路１２，１３（または、ΔΣ変調回路５１，５２）に出力するものを示したが、変調信号出力回路部が、互いに同一のディジタル変調信号を生成する複数のモデムを実装し、複数のモデムと複数のΔΣ変調回路が一対一で接続されているようにしてもよい。 Embodiment 6 FIG.
In the first to fifth embodiments, the modulation signal output circuit unit 1 (or the modulation signal output circuit unit 5) mounts one modem 11, and the modem 11 transmits the same digital modulation signal to the ΔΣ modulation circuits 12, 13 (Alternatively, what is output to the ΔΣ modulation circuits 51 and 52), the modulation signal output circuit unit has a plurality of modems that generate the same digital modulation signal, and a plurality of modems and a plurality of ΔΣ modulations. The circuits may be connected one to one.
　図７はこの発明の実施の形態６によるディジタル送信機の変調信号出力回路部６を示す構成図であり、図７において、図４と同一符号は同一または相当部分を示すので説明を省略する。
　変調信号出力回路部６は、モデム１１ａ，１１ｂ、ΔΣ変調回路５１，５２及び設定回路５３から構成されている。
　モデム１１ａは通信データを変調してディジタル変調信号を生成し、そのディジタル変調信号をΔΣ変調回路５１に出力する。
　モデム１１ｂは通信データを変調することで、モデム１１ａにより生成されるディジタル変調信号と同一のディジタル変調信号を生成し、そのディジタル変調信号をΔΣ変調回路５２に出力する。
　図７では、２個のモデムが実装されている例を示しているが、Ｎ個のモデムとＮ個のΔΣ変調回路が実装されているものであってもよい。 7 is a block diagram showing a modulation signal output circuit unit 6 of a digital transmitter according to Embodiment 6 of the present invention. In FIG. 7, the same reference numerals as those in FIG.
The modulation signal output circuit unit 6 includes modems 11a and 11b, ΔΣ modulation circuits 51 and 52, and a setting circuit 53.
The modem 11 a modulates communication data to generate a digital modulation signal, and outputs the digital modulation signal to the ΔΣ modulation circuit 51.
The modem 11b modulates the communication data to generate a digital modulation signal that is the same as the digital modulation signal generated by the modem 11a, and outputs the digital modulation signal to the ΔΣ modulation circuit 52.
Although FIG. 7 shows an example in which two modems are mounted, N modems and N ΔΣ modulation circuits may be mounted.
　モデム１１ａ，１１ｂが同一のディジタル変調信号を生成する場合、上記実施の形態４，５と同様の動作を実現することができる。ΔΣ変調回路５１，５２の代わりに、ΔΣ変調回路１２，１３を実装していれば、上記実施の形態１～３と同様の動作を実現することができる。
　さらに、図７の変調信号出力回路部６が、上記実施の形態３における図３の高周波部４と接続される場合、ΔΣ変調回路５１から高周波回路２１に出力されるタイミングと、ΔΣ変調回路５２から高周波回路２２に出力されるタイミングとがずれるように、モデム１１ａ，１１ｂからのディジタル変調信号の出力タイミングを制御すれば、高周波部４のアンテナ４１，４２から放射されるディジタル変調信号の放射方向を任意の方向に制御することが可能になる。 When the modems 11a and 11b generate the same digital modulation signal, the same operation as in the fourth and fifth embodiments can be realized. If ΔΣ modulation circuits 12 and 13 are mounted instead of ΔΣ modulation circuits 51 and 52, the same operation as in the first to third embodiments can be realized.
Furthermore, when the modulation signal output circuit unit 6 of FIG. 7 is connected to the high frequency unit 4 of FIG. 3 in the third embodiment, the timing output from the ΔΣ modulation circuit 51 to the high frequency circuit 21 and the ΔΣ modulation circuit 52 If the output timing of the digital modulation signal from the modems 11a and 11b is controlled so that the timing output from the radio frequency circuit 22 to the high frequency circuit 22 is shifted, the radiation direction of the digital modulation signal radiated from the antennas 41 and 42 of the high frequency unit 4 is controlled. Can be controlled in any direction.
実施の形態７．
　上記実施の形態６では、変調信号出力回路部６が２つのモデム１１ａ，１１ｂを実装し、ΔΣ変調回路５１から高周波回路２１に出力されるタイミングと、ΔΣ変調回路５２から高周波回路２２に出力されるタイミングとがずれるように、モデム１１ａ，１１ｂからのディジタル変調信号の出力タイミングを制御するものを示したが、１つのモデム１１とΔΣ変調回路１２，１３（または、ΔΣ変調回路５１，５２）の間に遅延回路をそれぞれ挿入し、複数の遅延回路によるディジタル変調信号の遅延量を制御するようにしてもよく、この場合も、高周波部４のアンテナ４１，４２から放射されるディジタル変調信号の放射方向を任意の方向に制御することが可能になる。 Embodiment 7 FIG.
In the sixth embodiment, the modulation signal output circuit unit 6 mounts the two modems 11a and 11b, and outputs from the ΔΣ modulation circuit 51 to the high frequency circuit 21 and from the ΔΣ modulation circuit 52 to the high frequency circuit 22. In this example, the output timing of the digital modulation signal from the modems 11a and 11b is controlled so that the timing is different from that of the modem 11a and 11b. However, one modem 11 and the ΔΣ modulation circuits 12 and 13 (or ΔΣ modulation circuits 51 and 52). A delay circuit may be inserted between the delay circuits to control the amount of delay of the digital modulation signal by the plurality of delay circuits. In this case as well, the digital modulation signal radiated from the antennas 41 and 42 of the high-frequency unit 4 may be controlled. The radiation direction can be controlled in an arbitrary direction.
　図８はこの発明の実施の形態７によるディジタル送信機の変調信号出力回路部７を示す構成図であり、図８において、図４と同一符号は同一または相当部分を示すので説明を省略する。
　変調信号出力回路部７は、モデム１１、ΔΣ変調回路５１，５２、設定回路５３、遅延回路８１，８２及び遅延制御回路８３から構成されている。
　遅延回路８１，８２はモデム１１とΔΣ変調回路５１，５２の間に挿入され、モデム１１により生成されたディジタル変調信号を遅延して、遅延後のディジタル変調信号をΔΣ変調回路５１，５２に出力する回路である。
　遅延制御回路８３は遅延回路８１，８２によるディジタル変調信号の遅延量を制御する回路である。 FIG. 8 is a block diagram showing a modulation signal output circuit unit 7 of a digital transmitter according to Embodiment 7 of the present invention. In FIG. 8, the same reference numerals as those in FIG.
The modulation signal output circuit unit 7 includes a modem 11, ΔΣ modulation circuits 51 and 52, a setting circuit 53, delay circuits 81 and 82, and a delay control circuit 83.
Delay circuits 81 and 82 are inserted between modem 11 and ΔΣ modulation circuits 51 and 52, delay the digital modulation signal generated by modem 11, and output the delayed digital modulation signal to ΔΣ modulation circuits 51 and 52. It is a circuit to do.
The delay control circuit 83 is a circuit that controls the delay amount of the digital modulation signal by the delay circuits 81 and 82.
　次に動作について説明する。
　遅延回路８１，８２によるディジタル変調信号の遅延量が０である場合、上記実施の形態４，５と同様の動作を実現することができる。ΔΣ変調回路５１，５２の代わりに、ΔΣ変調回路１２，１３を実装していれば、上記実施の形態１～３と同様の動作を実現することができる。
　さらに、図８の変調信号出力回路部７が、上記実施の形態３における図３の高周波部４と接続される場合、ΔΣ変調回路５１から高周波回路２１に出力されるタイミングと、ΔΣ変調回路５２から高周波回路２２に出力されるタイミングとがずれるように、遅延制御回路８３が、遅延回路８１，８２での遅延量を制御すれば、高周波部４のアンテナ４１，４２から放射されるディジタル変調信号の放射方向を任意の方向に制御することが可能になる。 Next, the operation will be described.
When the delay amount of the digital modulation signal by the delay circuits 81 and 82 is zero, the same operation as in the fourth and fifth embodiments can be realized. If ΔΣ modulation circuits 12 and 13 are mounted instead of ΔΣ modulation circuits 51 and 52, the same operation as in the first to third embodiments can be realized.
Further, when the modulation signal output circuit unit 7 of FIG. 8 is connected to the high frequency unit 4 of FIG. 3 in the third embodiment, the timing output from the ΔΣ modulation circuit 51 to the high frequency circuit 21 and the ΔΣ modulation circuit 52 If the delay control circuit 83 controls the amount of delay in the delay circuits 81 and 82 so that the timing output from the signal to the high-frequency circuit 22 is shifted, the digital modulation signal radiated from the antennas 41 and 42 of the high-frequency unit 4 The radiation direction can be controlled in an arbitrary direction.
実施の形態８．
　上記実施の形態１～７では、変調信号出力回路部１，５，６，７がΔΣ変調回路１２，１３（または、ΔΣ変調回路５１，５２）を実装し、ΔΣ変調回路１２，１３（または、ΔΣ変調回路５１，５２）がディジタル変調信号をデルタシグマ変調する際に発生するΔΣノイズを低減して、ＳＮＲを高めるために、ΔΣ変調回路１２（または、ΔΣ変調回路５１）とΔΣ変調回路１３（または、ΔΣ変調回路５２）の回路構成又は動作条件が異なっているものを示している。
　ΔΣ変調回路の代わりに、ディジタル変調信号をパルス幅変調して、パルス幅変調後のディジタル変調信号であるＰＷＭ信号を出力するパルス幅変調回路を実装する場合も、所望の変調信号帯域の近傍にノイズが発生するため、所望信号成分とノイズ成分との電力比であるＳＮＲが劣化してしまうことがある。
　この実施の形態８では、ディジタル変調信号のパルス幅変調に伴うノイズを低減して、ＳＮＲを高めることができるディジタル送信機について説明する。 Embodiment 8 FIG.
In the first to seventh embodiments, the modulation signal output circuit units 1, 5, 6 and 7 mount the ΔΣ modulation circuits 12 and 13 (or ΔΣ modulation circuits 51 and 52), and the ΔΣ modulation circuits 12 and 13 (or The ΔΣ modulation circuit 51 (or the ΔΣ modulation circuit 51) and the ΔΣ modulation circuit are used to reduce the ΔΣ noise generated when the ΔΣ modulation circuits 51, 52) perform delta-sigma modulation on the digital modulation signal and increase the SNR. 13 (or ΔΣ modulation circuit 52) is different in circuit configuration or operating condition.
In place of the ΔΣ modulation circuit, a pulse-width modulation circuit that performs pulse-width modulation on a digital modulation signal and outputs a PWM signal that is a digital modulation signal after pulse-width modulation is also mounted near the desired modulation signal band. Since noise is generated, the SNR that is the power ratio between the desired signal component and the noise component may deteriorate.
In the eighth embodiment, a digital transmitter capable of reducing the noise accompanying pulse width modulation of a digital modulation signal and increasing the SNR will be described.
　図９はこの発明の実施の形態８によるディジタル送信機を示す構成図であり、図９において、図１と同一符号は同一または相当部分を示すので説明を省略する。
　変調信号出力回路部９１はモデム１１とパルス幅変調回路１０１，１０２から構成されており、通信データを変調してディジタル変調信号を生成し、そのディジタル変調信号をパルス幅変調するディジタル回路である。
　パルス幅変調回路１０１は信号入力端子がモデム１１の信号出力端子と接続されており、モデム１１から出力されたディジタル変調信号をパルス幅変調して、パルス幅変調後のディジタル変調信号であるＰＷＭ信号を出力するディジタル回路である。
　パルス幅変調回路１０２は信号入力端子がモデム１１の信号出力端子と接続されており、パルス幅変調回路１０１と回路構成が異なっているが、パルス幅変調回路１０１と同様に、モデム１１から出力されたディジタル変調信号をパルス幅変調して、パルス幅変調後のディジタル変調信号であるＰＷＭ信号を出力する。 FIG. 9 is a block diagram showing a digital transmitter according to Embodiment 8 of the present invention. In FIG. 9, the same reference numerals as those in FIG.
The modulation signal output circuit unit 91 includes a modem 11 and pulse width modulation circuits 101 and 102, and is a digital circuit that modulates communication data to generate a digital modulation signal and performs pulse width modulation on the digital modulation signal.
The pulse width modulation circuit 101 has a signal input terminal connected to a signal output terminal of the modem 11. The pulse width modulation circuit 101 performs pulse width modulation on the digital modulation signal output from the modem 11, and a PWM signal which is a digital modulation signal after pulse width modulation. Is a digital circuit that outputs.
The pulse width modulation circuit 102 has a signal input terminal connected to the signal output terminal of the modem 11 and is different in circuit configuration from the pulse width modulation circuit 101, but is output from the modem 11 in the same manner as the pulse width modulation circuit 101. The digital modulation signal is subjected to pulse width modulation, and a PWM signal which is a digital modulation signal after pulse width modulation is output.
　次に動作について説明する。
　変調信号出力回路部９１のモデム１１は、例えば、外部から各種の情報等からなる通信データを受けると、その通信データを変調してディジタル変調信号を生成し、そのディジタル変調信号をパルス幅変調回路１０１，１０２に出力する。 Next, the operation will be described.
For example, when the modem 11 of the modulation signal output circuit unit 91 receives communication data composed of various information from the outside, the modem 11 modulates the communication data to generate a digital modulation signal, and the digital modulation signal is converted into a pulse width modulation circuit. 101 and 102.
　パルス幅変調回路１０１は、モデム１１からディジタル変調信号を受けると、そのディジタル変調信号をパルス幅変調して、パルス幅変調後のディジタル変調信号であるＰＷＭ信号を高周波回路２１に出力する。
　パルス幅変調回路１０２は、モデム１１からディジタル変調信号を受けると、そのディジタル変調信号をパルス幅変調して、パルス幅変調後のディジタル変調信号であるＰＷＭ信号を高周波回路２２に出力する。
　パルス幅変調回路１０１，１０２によるパルス幅変調では、モデム１１から出力されたディジタル変調信号の振幅値が大きい程、パルス幅が広いパルスを生成し、複数のパルスの系列からなるＰＷＭ信号を出力することになるが、パルス幅変調回路１０１，１０２がパルス幅変調する際に発生するノイズの特性は、パルス幅変調回路１０１，１０２の回路構成に依存する。
　このことは、ΔΣノイズの特性が、ΔΣ変調回路１２，１３の回路構成に依存していることと同じである。 When the pulse width modulation circuit 101 receives the digital modulation signal from the modem 11, the pulse width modulation circuit 101 performs pulse width modulation on the digital modulation signal and outputs a PWM signal, which is a digital modulation signal after pulse width modulation, to the high frequency circuit 21.
When the pulse width modulation circuit 102 receives the digital modulation signal from the modem 11, the pulse width modulation circuit 102 performs pulse width modulation on the digital modulation signal and outputs a PWM signal which is a digital modulation signal after pulse width modulation to the high frequency circuit 22.
In the pulse width modulation by the pulse width modulation circuits 101 and 102, as the amplitude value of the digital modulation signal output from the modem 11 is larger, a pulse having a wider pulse width is generated and a PWM signal composed of a plurality of pulse sequences is output. However, the characteristics of noise generated when the pulse width modulation circuits 101 and 102 perform pulse width modulation depend on the circuit configuration of the pulse width modulation circuits 101 and 102.
This is the same as the characteristic of the ΔΣ noise depending on the circuit configuration of the ΔΣ modulation circuits 12 and 13.
　この実施の形態８では、パルス幅変調回路１０１とパルス幅変調回路１０２の回路構成が異なっているものを想定しており、パルス幅変調回路１０１とパルス幅変調回路１０２の回路構成が異なっていれば、パルス幅変調の処理シーケンスが異なるため、ノイズの特性が異なる。
　これにより、パルス幅変調回路１０１から発生するノイズの成分と、パルス幅変調回路１０２から発生するノイズの成分とはインコヒーレントである。
　一方、パルス幅変調回路１０１，１０２は、モデム１１から出力された同一のディジタル変調信号をパルス幅変調するものであるため、パルス幅変調回路１０１から出力されるディジタル変調信号の所望信号成分と、パルス幅変調回路１０２から出力されるディジタル変調信号の所望信号成分とはコヒーレントである。
　この実施の形態８では、パルス幅変調回路１０１とパルス幅変調回路１０２の回路構成が異なっていれば、どのような回路構成であっても構わないため、パルス幅変調回路１０１，１０２の具体的な構成の説明は省略する。なお、パルス幅変調回路の回路構成として、各種の公知の構成が知られている。 In the eighth embodiment, it is assumed that the pulse width modulation circuit 101 and the pulse width modulation circuit 102 have different circuit configurations, and the pulse width modulation circuit 101 and the pulse width modulation circuit 102 have different circuit configurations. For example, since the processing sequence of pulse width modulation is different, noise characteristics are different.
Thereby, the noise component generated from the pulse width modulation circuit 101 and the noise component generated from the pulse width modulation circuit 102 are incoherent.
On the other hand, since the pulse width modulation circuits 101 and 102 perform pulse width modulation on the same digital modulation signal output from the modem 11, a desired signal component of the digital modulation signal output from the pulse width modulation circuit 101, and The desired signal component of the digital modulation signal output from the pulse width modulation circuit 102 is coherent.
In the eighth embodiment, any circuit configuration may be used as long as the pulse width modulation circuit 101 and the pulse width modulation circuit 102 have different circuit configurations. Description of the detailed configuration is omitted. Various known configurations are known as the circuit configuration of the pulse width modulation circuit.
　高周波回路２１は、パルス幅変調回路１０１からパルス幅変調後のディジタル変調信号を受けると、そのディジタル変調信号の信号電力を所望の電力レベルに変換するとともに、そのディジタル変調信号の周波数をＩＦ周波数からＲＦ周波数に変換し、変換後のディジタル変調信号を合成回路２３に出力する。
　高周波回路２２は、パルス幅変調回路１０２からパルス幅変調後のディジタル変調信号を受けると、そのディジタル変調信号の信号電力を所望の電力レベルに変換するとともに、そのディジタル変調信号の周波数をＩＦ周波数からＲＦ周波数に変換し、変換後のディジタル変調信号を合成回路２３に出力する。
　ここでは、高周波回路２１から出力される変換後のディジタル変調信号と、高周波回路２２から出力される変換後のディジタル変調信号とは、信号電力が同一で、周波数が同一であるものとする。
　高周波回路２１，２２から出力される変換後のディジタル変調信号についても、ノイズ成分がインコヒーレントであるが、ディジタル変調信号の所望信号成分はコヒーレントである。 When the high frequency circuit 21 receives the digital modulation signal after pulse width modulation from the pulse width modulation circuit 101, the high frequency circuit 21 converts the signal power of the digital modulation signal into a desired power level, and converts the frequency of the digital modulation signal from the IF frequency. The signal is converted into an RF frequency, and the converted digital modulation signal is output to the synthesis circuit 23.
When the high frequency circuit 22 receives the digital modulation signal after the pulse width modulation from the pulse width modulation circuit 102, the high frequency circuit 22 converts the signal power of the digital modulation signal into a desired power level and converts the frequency of the digital modulation signal from the IF frequency. The signal is converted into an RF frequency, and the converted digital modulation signal is output to the synthesis circuit 23.
Here, it is assumed that the converted digital modulation signal output from the high-frequency circuit 21 and the converted digital modulation signal output from the high-frequency circuit 22 have the same signal power and the same frequency.
The converted digital modulation signals output from the high- frequency circuits 21 and 22 also have a noise component incoherent, but a desired signal component of the digital modulation signal is coherent.
　合成回路２３は、上記実施の形態１と同様に、高周波回路２１から出力された変換後のディジタル変調信号と、高周波回路２２から出力された変換後のディジタル変調信号とを合成して、２つのディジタル変調信号の合成信号を出力する。
　このとき、２つのディジタル変調信号の所望信号成分はコヒーレントであるため、合成回路２３の合成によって、２つの所望信号成分が電圧加算となる。一方、２つのディジタル変調信号のノイズ成分はインコヒーレントであるため、合成回路２３の合成によって、２つのディジタル変調信号のノイズ成分が電力加算となる。
　その結果、合成回路２３から出力される合成信号における所望信号成分とノイズ成分との電力比であるＳＮＲは、各々の高周波回路２１，２２から出力されるディジタル変調信号における所望信号成分とノイズ成分とのＳＮＲと比べて、理論的には３ｄＢ改善される。 Similar to the first embodiment, the synthesis circuit 23 synthesizes the converted digital modulation signal output from the high-frequency circuit 21 and the converted digital modulation signal output from the high-frequency circuit 22 to generate two signals. A composite signal of the digital modulation signal is output.
At this time, since the desired signal components of the two digital modulation signals are coherent, the two desired signal components are voltage-added by the synthesis of the synthesis circuit 23. On the other hand, since the noise components of the two digital modulation signals are incoherent, the noise components of the two digital modulation signals are summed by the synthesis of the synthesis circuit 23.
As a result, the SNR, which is the power ratio between the desired signal component and the noise component in the combined signal output from the combining circuit 23, is the desired signal component and the noise component in the digital modulation signals output from the high frequency circuits 21 and 22, respectively. Compared to the SNR, the theoretical improvement is 3 dB.
　以上で明らかなように、この実施の形態８によれば、通信データを変調してディジタル変調信号を生成するモデム１１と、モデム１１により生成されたディジタル変調信号をパルス幅変調して、パルス幅変調後のディジタル変調信号を出力するパルス幅変調回路１０１，１０２と、パルス幅変調回路１０１，１０２から出力されたディジタル変調信号の信号電力を所望の電力レベルに変換するとともに、そのディジタル変調信号の周波数をＩＦ周波数からＲＦ周波数に変換する高周波回路２１，２２と、高周波回路２１による変換後のディジタル変調信号と高周波回路２２による変換後のディジタル変調信号とを合成して、２つのディジタル変調信号の合成信号を出力する合成回路２３とを備え、パルス幅変調回路１０１，１０２の回路構成が異なっているように構成したので、ディジタル変調信号のパルス幅変調に伴うノイズを低減して、ＳＮＲを高めることができる効果を奏する。 As is apparent from the above, according to the eighth embodiment, the modem 11 that modulates communication data to generate a digital modulation signal, and the pulse width modulation of the digital modulation signal generated by the modem 11 The pulse width modulation circuits 101 and 102 for outputting the modulated digital modulation signal, the signal power of the digital modulation signal output from the pulse width modulation circuits 101 and 102 are converted to a desired power level, and the digital modulation signal The high frequency circuits 21 and 22 for converting the frequency from the IF frequency to the RF frequency, the digital modulation signal after the conversion by the high frequency circuit 21 and the digital modulation signal after the conversion by the high frequency circuit 22 are combined to generate two digital modulation signals. And a synthesis circuit 23 for outputting a synthesis signal, and the circuit configuration of the pulse width modulation circuits 101 and 102. Since it configured to be different, to reduce the noise associated with the pulse width modulation of the digital modulation signal, an effect that can increase the SNR.
　この実施の形態８では、変調信号出力回路部９１が、回路構成が異なる２つのパルス幅変調回路１０１，１０２を実装している例を示したが、変調信号出力回路部９１が、回路構成が異なるＮ個のパルス幅変調回路を実装するとともに、高周波部２が、Ｎ個の高周波回路を実装し、合成回路２３が、Ｎ個の高周波回路から出力された変換後のディジタル変調信号を合成するようにしてもよい。 In the eighth embodiment, the modulation signal output circuit unit 91 is mounted with two pulse width modulation circuits 101 and 102 having different circuit configurations. However, the modulation signal output circuit unit 91 has a circuit configuration. In addition to mounting N different pulse width modulation circuits, the high-frequency unit 2 mounts N high-frequency circuits, and the synthesis circuit 23 synthesizes the converted digital modulation signals output from the N high-frequency circuits. You may do it.
実施の形態９．
　上記実施の形態８では、高周波部２が、パルス幅変調回路１０１，１０２から出力されたディジタル変調信号の信号電力を所望の電力レベルに変換するとともに、そのディジタル変調信号の周波数をＩＦ周波数からＲＦ周波数に変換してから、変換後の２つのディジタル変調信号を合成するものを示したが、パルス幅変調回路１０１，１０２から出力されたディジタル変調信号を合成してから、２つのディジタル変調信号の合成信号の信号電力を所望の電力レベルに変換するとともに、その合成信号の周波数をＩＦ周波数からＲＦ周波数に変換するようにしてもよい。 Embodiment 9 FIG.
In the eighth embodiment, the high frequency unit 2 converts the signal power of the digital modulation signal output from the pulse width modulation circuits 101 and 102 to a desired power level, and converts the frequency of the digital modulation signal from the IF frequency to the RF frequency. In this example, the two digital modulation signals after the conversion are synthesized after being converted to the frequency. However, after the digital modulation signals output from the pulse width modulation circuits 101 and 102 are synthesized, The signal power of the combined signal may be converted to a desired power level, and the frequency of the combined signal may be converted from the IF frequency to the RF frequency.
　図１０はこの発明の実施の形態９によるディジタル送信機を示す構成図であり、図１０において、図２及び図９と同一符号は同一または相当部分を示すので説明を省略する。 FIG. 10 is a block diagram showing a digital transmitter according to Embodiment 9 of the present invention. In FIG. 10, the same reference numerals as those in FIGS.
　次に動作について説明する。
　変調信号出力回路部９１については、上記実施の形態８と同様であるため、ここでは、高周波部３について説明する。
　合成回路３１は、パルス幅変調回路１０１から出力されたパルス幅変調後のディジタル変調信号と、パルス幅変調回路１０２から出力されたパルス幅変調後のディジタル変調信号とを合成して、２つのディジタル変調信号の合成信号を出力する。
　このとき、２つのディジタル変調信号の所望信号成分はコヒーレントであるため、合成回路３１の合成によって、２つの所望信号成分が電圧加算となる。一方、２つのディジタル変調信号のノイズ成分はインコヒーレントであるため、合成回路３１の合成によって、２つのディジタル変調信号のノイズ成分が電力加算となる。
　その結果、合成回路３１から出力される合成信号における所望信号成分とノイズ成分との電力比であるＳＮＲは、各々のパルス幅変調回路１０１，１０２から出力されるディジタル変調信号における所望信号成分とノイズ成分とのＳＮＲと比べて、理論的には３ｄＢ改善される。 Next, the operation will be described.
Since the modulation signal output circuit unit 91 is the same as that of the eighth embodiment, only the high frequency unit 3 will be described here.
The combining circuit 31 combines the digital modulated signal after pulse width modulation output from the pulse width modulating circuit 101 and the digital modulated signal after pulse width modulation output from the pulse width modulating circuit 102 to generate two digital signals. A composite signal of the modulation signal is output.
At this time, since the desired signal components of the two digital modulation signals are coherent, the two desired signal components are voltage-added by the synthesis of the synthesis circuit 31. On the other hand, since the noise components of the two digital modulation signals are incoherent, the noise components of the two digital modulation signals are summed by the synthesis of the synthesis circuit 31.
As a result, the SNR that is the power ratio between the desired signal component and the noise component in the combined signal output from the combining circuit 31 is the desired signal component and noise in the digital modulation signal output from each of the pulse width modulation circuits 101 and 102. Compared to the SNR with the component, there is a theoretical 3 dB improvement.
　高周波回路３２は、合成回路３１から合成信号を受けると、その合成信号の信号電力を所望の電力レベルに変換するとともに、その合成信号の周波数をＩＦ周波数からＲＦ周波数に変換する。 When the high frequency circuit 32 receives the combined signal from the combining circuit 31, the high frequency circuit 32 converts the signal power of the combined signal into a desired power level and converts the frequency of the combined signal from the IF frequency to the RF frequency.
　以上で明らかなように、この実施の形態９によれば、通信データを変調してディジタル変調信号を生成するモデム１１と、モデム１１により生成されたディジタル変調信号をパルス幅変調して、パルス幅変調後のディジタル変調信号を出力するパルス幅変調回路１０１，１０２と、パルス幅変調回路１０１から出力されたパルス幅変調後のディジタル変調信号と、パルス幅変調回路１０２から出力されたパルス幅変調後のディジタル変調信号とを合成し、２つのディジタル変調信号の合成信号を出力する合成回路３１と、合成回路３１から出力された合成信号の信号電力を所望の電力レベルに変換するとともに、その合成信号の周波数をＩＦ周波数からＲＦ周波数に変換する高周波回路３２とを備え、パルス幅変調回路１０１，１０２の回路構成が異なっているように構成したので、ディジタル変調信号のパルス幅変調に伴うノイズを低減して、ＳＮＲを高めることができる効果を奏する。
　また、この実施の形態９では、高周波部３が、パルス幅変調回路１０１，１０２から出力されたディジタル変調信号を合成してから、２つのディジタル変調信号の合成信号の信号電力の電力レベルや周波数を変換するようにしているので、高周波回路の個数を１個にすることができ、回路構成の簡単化を図ることができる効果を奏する。 As is apparent from the above, according to the ninth embodiment, the modem 11 that modulates communication data to generate a digital modulation signal, and the pulse width modulation of the digital modulation signal generated by the modem 11 Pulse width modulation circuits 101 and 102 that output a modulated digital modulation signal, a pulse width modulated digital modulation signal output from the pulse width modulation circuit 101, and a pulse width modulated output from the pulse width modulation circuit 102 Are combined with each other, and a combined circuit 31 for outputting a combined signal of the two digital modulated signals is converted into a desired power level, and the combined signal output from the combined circuit 31 is converted into a desired power level. And a high-frequency circuit 32 for converting the frequency of IF from the IF frequency to the RF frequency, and the circuit of the pulse width modulation circuits 101 and 102 Since it is configured such that are different, by reducing the noise associated with the pulse width modulation of the digital modulation signal, an effect that can increase the SNR.
In the ninth embodiment, the high frequency unit 3 combines the digital modulation signals output from the pulse width modulation circuits 101 and 102, and then the power level and frequency of the signal power of the combined signal of the two digital modulation signals. Thus, the number of high-frequency circuits can be reduced to one, and the circuit configuration can be simplified.
　この実施の形態９では、変調信号出力回路部９１が、回路構成が異なる２つのパルス幅変調回路１０１，１０２を実装している例を示したが、変調信号出力回路部９１が、回路構成が異なるＮ個のパルス幅変調回路を実装するとともに、高周波部２の合成回路３１が、Ｎ個のパルス幅変調回路から出力されたパルス幅変調後のディジタル変調信号を合成するようにしてもよい。 In the ninth embodiment, the modulation signal output circuit unit 91 is mounted with two pulse width modulation circuits 101 and 102 having different circuit configurations. However, the modulation signal output circuit unit 91 has a circuit configuration. Different N pulse width modulation circuits may be mounted, and the synthesis circuit 31 of the high-frequency unit 2 may synthesize the pulse-modulated digital modulation signal output from the N pulse width modulation circuits.
実施の形態１０．
　上記実施の形態８では、合成回路２３が、高周波回路２１から出力された変換後のディジタル変調信号と、高周波回路２２から出力された変換後のディジタル変調信号とを合成して、２つのディジタル変調信号の合成信号を出力するものを示したが、高周波回路２１，２２から出力された変換後のディジタル変調信号を空間に放射するアンテナ４１，４２を備え、アンテナ４１，４２から放射されたディジタル変調信号が空間で合成されるようにしてもよい。 Embodiment 10 FIG.
In the eighth embodiment, the synthesis circuit 23 synthesizes the converted digital modulation signal output from the high frequency circuit 21 and the converted digital modulation signal output from the high frequency circuit 22 to generate two digital modulations. Although the output of the combined signal is shown, antennas 41 and 42 that radiate the converted digital modulation signals output from the high- frequency circuits 21 and 22 to the space are provided, and the digital modulation radiated from the antennas 41 and 42 is provided. The signals may be combined in space.
　図１１はこの発明の実施の形態１０によるディジタル送信機を示す構成図であり、図１１において、図３及び図９と同一符号は同一または相当部分を示すので説明を省略する。 FIG. 11 is a block diagram showing a digital transmitter according to Embodiment 10 of the present invention. In FIG. 11, the same reference numerals as those in FIGS.
　次に動作について説明する。
　変調信号出力回路部９１については、上記実施の形態８と同様であるため、ここでは、高周波部４について説明する。
　高周波回路２１は、パルス幅変調回路１０１からパルス幅変調後のディジタル変調信号を受けると、上記実施の形態８と同様に、そのディジタル変調信号の信号電力を所望の電力レベルに変換するとともに、そのディジタル変調信号の周波数をＩＦ周波数からＲＦ周波数に変換する。
　高周波回路２２は、パルス幅変調回路１０２からパルス幅変調後のディジタル変調信号を受けると、上記実施の形態８と同様に、そのディジタル変調信号の信号電力を所望の電力レベルに変換するとともに、そのディジタル変調信号の周波数をＩＦ周波数からＲＦ周波数に変換する。
　ここでは、高周波回路２１から出力される変換後のディジタル変調信号と、高周波回路２２から出力される変換後のディジタル変調信号とは、信号電力が同一で、周波数が同一であるものとする。
　高周波回路２１，２２から出力される変換後のディジタル変調信号についても、ノイズ成分がインコヒーレントであるが、ディジタル変調信号の所望信号成分はコヒーレントである。 Next, the operation will be described.
Since the modulation signal output circuit unit 91 is the same as that of the eighth embodiment, only the high frequency unit 4 will be described here.
When the high frequency circuit 21 receives the digital modulation signal after the pulse width modulation from the pulse width modulation circuit 101, the high frequency circuit 21 converts the signal power of the digital modulation signal to a desired power level as in the eighth embodiment, and The frequency of the digital modulation signal is converted from the IF frequency to the RF frequency.
When the high frequency circuit 22 receives the digital modulation signal after the pulse width modulation from the pulse width modulation circuit 102, the high frequency circuit 22 converts the signal power of the digital modulation signal to a desired power level as in the eighth embodiment, and The frequency of the digital modulation signal is converted from the IF frequency to the RF frequency.
Here, it is assumed that the converted digital modulation signal output from the high-frequency circuit 21 and the converted digital modulation signal output from the high-frequency circuit 22 have the same signal power and the same frequency.
The converted digital modulation signals output from the high- frequency circuits 21 and 22 also have a noise component incoherent, but a desired signal component of the digital modulation signal is coherent.
　アンテナ４１は、高周波回路２１から変換後のディジタル変調信号を受けると、そのディジタル変調信号を空間に放射する。
　アンテナ４２は、高周波回路２２から変換後のディジタル変調信号を受けると、そのディジタル変調信号を空間に放射する。
　アンテナ４１から放射されたディジタル変調信号と、アンテナ４２から放射されたディジタル変調信号とは、空間で合成される。 When receiving the converted digital modulation signal from the high-frequency circuit 21, the antenna 41 radiates the digital modulation signal to space.
When the antenna 42 receives the converted digital modulation signal from the high frequency circuit 22, the antenna 42 radiates the digital modulation signal to space.
The digital modulation signal radiated from the antenna 41 and the digital modulation signal radiated from the antenna 42 are combined in space.
　このとき、高周波回路２１，２２から出力された２つのディジタル変調信号の所望信号成分はコヒーレントであるため、空間での合成によって、２つの所望信号成分が電圧加算となる。一方、２つのディジタル変調信号のノイズ成分はインコヒーレントであるため、空間での合成によって、２つのディジタル変調信号のノイズ成分が電力加算となる。
　その結果、空間で合成された信号における所望信号成分とノイズ成分との電力比であるＳＮＲは、各々の高周波回路２１，２２から出力されるディジタル変調信号における所望信号成分とノイズ成分とのＳＮＲと比べて、理論的には３ｄＢ改善される。したがって、当該ディジタル送信機との通信対象である受信機は、ＳＮＲが高い信号を受信することができる。 At this time, since the desired signal components of the two digital modulation signals output from the high- frequency circuits 21 and 22 are coherent, the two desired signal components are voltage-added by synthesis in space. On the other hand, since the noise components of the two digital modulation signals are incoherent, the noise components of the two digital modulation signals become power addition by combining in space.
As a result, the SNR, which is the power ratio between the desired signal component and the noise component in the signal synthesized in space, is the SNR of the desired signal component and the noise component in the digital modulation signal output from each of the high frequency circuits 21 and 22. Compared to the theoretical improvement, 3 dB is obtained. Therefore, a receiver that is a communication target with the digital transmitter can receive a signal having a high SNR.
　以上で明らかなように、この実施の形態１０によれば、通信データを変調してディジタル変調信号を生成するモデム１１と、モデム１１により生成されたディジタル変調信号をパルス幅変調して、パルス幅変調後のディジタル変調信号を出力するパルス幅変調回路１０１，１０２と、パルス幅変調回路１０１，１０２から出力されたディジタル変調信号の信号電力を所望の電力レベルに変換するとともに、そのディジタル変調信号の周波数をＩＦ周波数からＲＦ周波数に変換する高周波回路２１，２２と、高周波回路２１，２２から出力された変換後のディジタル変調信号を空間に放射するアンテナ４１，４２とを備え、パルス幅変調回路１０１，１０２の回路構成が異なっているように構成したので、ディジタル変調信号のパルス幅変調に伴うノイズを低減して、ＳＮＲを高めることができる効果を奏する。
　また、この実施の形態１０では、合成回路２３が不要になる。 As is apparent from the above, according to the tenth embodiment, the modem 11 that modulates communication data to generate a digital modulation signal, and the pulse width modulation of the digital modulation signal generated by the modem 11 The pulse width modulation circuits 101 and 102 for outputting the modulated digital modulation signal, the signal power of the digital modulation signal output from the pulse width modulation circuits 101 and 102 are converted to a desired power level, and the digital modulation signal High- frequency circuits 21 and 22 for converting the frequency from IF frequency to RF frequency, and antennas 41 and 42 for radiating the converted digital modulation signals output from the high- frequency circuits 21 and 22 to the space, and a pulse width modulation circuit 101 , 102 are configured so as to have different circuit configurations, so that pulse width modulation of a digital modulation signal can be performed. By reducing cormorants noise, an effect that can increase the SNR.
In the tenth embodiment, the synthesis circuit 23 is not necessary.
実施の形態１１．
　上記実施の形態８～１０では、変調信号出力回路部９１が、回路構成が異なるパルス幅変調回路１０１，１０２を実装しているものを示したが、この場合、パルス幅変調回路１０１，１０２の回路構成をそれぞれ設計する必要があるため、回路開発の負荷が増大する。
　そこで、この実施の形態１１では、回路構成が同一のパルス幅変調回路を変調信号出力回路部に複数実装し、複数のパルス幅変調回路に対して異なる動作条件を設定するものについて説明する。 Embodiment 11 FIG.
In the above eighth to tenth embodiments, the modulation signal output circuit unit 91 is mounted with the pulse width modulation circuits 101 and 102 having different circuit configurations. Since it is necessary to design each circuit configuration, the load of circuit development increases.
Therefore, in the eleventh embodiment, a description will be given of a case where a plurality of pulse width modulation circuits having the same circuit configuration are mounted in the modulation signal output circuit section and different operating conditions are set for the plurality of pulse width modulation circuits.
　図１２はこの発明の実施の形態１１によるディジタル送信機を示す構成図であり、図１２において、図９と同一符号は同一または相当部分を示すので説明を省略する。
　図１２の例では、ディジタル送信機が高周波部２を実装している例を示しているが、ディジタル送信機が図１０の高周波部３や図１１の高周波部４を実装しているものであってもよい。
　変調信号出力回路部９２はモデム１１、パルス幅変調回路１１１，１１２及び設定回路１１３から構成されているディジタル回路である。 12 is a block diagram showing a digital transmitter according to Embodiment 11 of the present invention. In FIG. 12, the same reference numerals as those in FIG.
In the example of FIG. 12, an example is shown in which the digital transmitter is mounted with the high-frequency unit 2, but the digital transmitter is mounted with the high-frequency unit 3 of FIG. 10 and the high-frequency unit 4 of FIG. May be.
The modulation signal output circuit unit 92 is a digital circuit including the modem 11, pulse width modulation circuits 111 and 112, and a setting circuit 113.
　パルス幅変調回路１１１は信号入力端子がモデム１１の信号出力端子と接続されており、モデム１１から出力されたディジタル変調信号をパルス幅変調して、パルス幅変調後のディジタル変調信号を出力するディジタル回路である。
　パルス幅変調回路１１２はパルス幅変調回路１１１と回路構成が同一の回路である。パルス幅変調回路１１２は信号入力端子がモデム１１の信号出力端子と接続されており、モデム１１から出力されたディジタル変調信号をパルス幅変調して、パルス幅変調後のディジタル変調信号を出力する。
　設定回路１１３はパルス幅変調回路１１１，１１２に対して異なる動作条件を設定する回路である。 The pulse width modulation circuit 111 has a signal input terminal connected to the signal output terminal of the modem 11. The pulse width modulation circuit 111 performs pulse width modulation on the digital modulation signal output from the modem 11 and outputs a digital modulation signal after pulse width modulation. Circuit.
The pulse width modulation circuit 112 is a circuit having the same circuit configuration as the pulse width modulation circuit 111. The pulse width modulation circuit 112 has a signal input terminal connected to the signal output terminal of the modem 11. The pulse width modulation circuit 112 performs pulse width modulation on the digital modulation signal output from the modem 11 and outputs a digital modulation signal after pulse width modulation.
The setting circuit 113 is a circuit that sets different operating conditions for the pulse width modulation circuits 111 and 112.
　次に動作について説明する。
　変調信号出力回路部９２以外は、上記実施の形態８～１０と同様であるため、ここでは、変調信号出力回路部９２について説明する。
　設定回路１１３は、パルス幅変調回路１１１，１１２に対して異なる動作条件を設定する。 Next, the operation will be described.
Since the configuration other than the modulation signal output circuit section 92 is the same as that of the above-described eighth to tenth embodiments, the modulation signal output circuit section 92 will be described here.
The setting circuit 113 sets different operating conditions for the pulse width modulation circuits 111 and 112.
　パルス幅変調回路１１１は、モデム１１からディジタル変調信号を受けると、設定回路１１３によって設定された動作条件にしたがって、そのディジタル変調信号をパルス幅変調し、パルス幅変調後のディジタル変調信号を高周波回路２１に出力する。
　パルス幅変調回路１１２は、モデム１１からディジタル変調信号を受けると、設定回路１１３によって設定された動作条件にしたがって、そのディジタル変調信号をパルス幅変調し、パルス幅変調後のディジタル変調信号を高周波回路２２に出力する。 When the pulse width modulation circuit 111 receives the digital modulation signal from the modem 11, the pulse width modulation circuit 111 performs pulse width modulation on the digital modulation signal in accordance with the operation condition set by the setting circuit 113, and converts the digital modulation signal after the pulse width modulation into a high frequency circuit. To 21.
When the pulse width modulation circuit 112 receives the digital modulation signal from the modem 11, the pulse width modulation circuit 112 performs pulse width modulation on the digital modulation signal in accordance with the operation condition set by the setting circuit 113, and converts the digital modulation signal after the pulse width modulation into a high frequency circuit 22 to output.
　ここでは、設定回路１１３が、パルス幅変調回路１１１，１１２に対して異なる動作条件を設定しているので、回路構成が異なる図９のパルス幅変調回路１０１，１０２と同様に、パルス幅変調回路１１１から発生するノイズの成分と、パルス幅変調回路１１２から発生するノイズの成分とはインコヒーレントになる。
　一方、パルス幅変調回路１１１，１１２は、モデム１１から出力された同一のディジタル変調信号をパルス幅変調するものであるため、パルス幅変調回路１１１から出力されるディジタル変調信号の所望信号成分と、パルス幅変調回路１１２から出力されるディジタル変調信号の所望信号成分とはコヒーレントになる。
　このように、ノイズ成分がインコヒーレントになって、所望信号成分がコヒーレントになるのは、回路構成が同一である図４のΔΣ変調回路５１，５２に対して異なる動作条件を設定したとき、ΔΣノイズ成分がインコヒーレントになって、所望信号成分がコヒーレントになるのと同様である。 Here, since the setting circuit 113 sets different operating conditions for the pulse width modulation circuits 111 and 112, the pulse width modulation circuit is similar to the pulse width modulation circuits 101 and 102 of FIG. The noise component generated from 111 and the noise component generated from the pulse width modulation circuit 112 become incoherent.
On the other hand, since the pulse width modulation circuits 111 and 112 perform pulse width modulation on the same digital modulation signal output from the modem 11, a desired signal component of the digital modulation signal output from the pulse width modulation circuit 111, and The desired signal component of the digital modulation signal output from the pulse width modulation circuit 112 becomes coherent.
As described above, the noise component becomes incoherent and the desired signal component becomes coherent when ΔΣ modulation circuits 51 and 52 in FIG. 4 having the same circuit configuration are set with different operating conditions. This is the same as when the noise component becomes incoherent and the desired signal component becomes coherent.
　以上で明らかなように、この実施の形態１１によれば、変調信号出力回路部９２が、回路構成が同一のパルス幅変調回路１１１，１１２を実装するとともに、パルス幅変調回路１１１，１１２に対して異なる動作条件を設定する設定回路１１３を実装するように構成したので、上記実施の形態８と同様に、ディジタル変調信号のパルス幅変調に伴うノイズを低減して、ＳＮＲを高めることができるほか、回路構成が異なるパルス幅変調回路１０１，１０２を実装する場合よりも、パルス幅変調回路１１１，１１２の回路開発に要する負荷を軽減することができる効果を奏する。 As is apparent from the above, according to the eleventh embodiment, the modulation signal output circuit unit 92 mounts the pulse width modulation circuits 111 and 112 having the same circuit configuration, and the pulse width modulation circuits 111 and 112 Since the setting circuit 113 for setting different operating conditions is mounted, the noise accompanying the pulse width modulation of the digital modulation signal can be reduced and the SNR can be increased as in the eighth embodiment. As compared with the case where the pulse width modulation circuits 101 and 102 having different circuit configurations are mounted, the load required for circuit development of the pulse width modulation circuits 111 and 112 can be reduced.
実施の形態１２．
　上記実施の形態８～１１では、変調信号出力回路部９１（または、変調信号出力回路部９２）が１個のモデム１１を実装し、モデム１１が同一のディジタル変調信号をパルス幅変調回路１０１，１０２（または、パルス幅変調回路１１１，１１２）に出力するものを示したが、変調信号出力回路部が、互いに同一のディジタル変調信号を生成する複数のモデムを実装し、複数のモデムと複数の変調信号出力回路部が一対一で接続されているようにしてもよい。 Embodiment 12 FIG.
In the above eighth to eleventh embodiments, the modulation signal output circuit unit 91 (or the modulation signal output circuit unit 92) mounts one modem 11, and the modem 11 transmits the same digital modulation signal to the pulse width modulation circuit 101, 102 (or pulse width modulation circuits 111 and 112), the modulation signal output circuit unit includes a plurality of modems that generate the same digital modulation signal, and a plurality of modems and a plurality of modems. The modulation signal output circuit units may be connected one to one.
　図１３はこの発明の実施の形態１２によるディジタル送信機の変調信号出力回路部９３を示す構成図であり、図１３において、図１２と同一符号は同一または相当部分を示すので説明を省略する。
　変調信号出力回路部９３は、モデム１１ａ，１１ｂ、パルス幅変調回路１１１，１１２及び設定回路１１３から構成されている。
　図１３では、２個のモデムが実装されている例を示しているが、Ｎ個のモデムとＮ個のパルス幅変調回路が実装されているものであってもよい。 FIG. 13 is a block diagram showing a modulation signal output circuit section 93 of a digital transmitter according to Embodiment 12 of the present invention. In FIG. 13, the same reference numerals as those in FIG.
The modulation signal output circuit unit 93 includes modems 11a and 11b, pulse width modulation circuits 111 and 112, and a setting circuit 113.
Although FIG. 13 shows an example in which two modems are mounted, N modems and N pulse width modulation circuits may be mounted.
　モデム１１ａ，１１ｂが同一のディジタル変調信号を生成する場合、上記実施の形態１１と同様の動作を実現することができる。パルス幅変調回路１１１，１１２の代わりに、パルス幅変調回路１０１，１０２を実装していれば、上記実施の形態８～１０と同様の動作を実現することができる。
　さらに、図１３の変調信号出力回路部９３が、上記実施の形態１０における図１１の高周波部４と接続される場合、パルス幅変調回路１１１から高周波回路２１に出力されるタイミングと、パルス幅変調回路１１２から高周波回路２２に出力されるタイミングとがずれるように、モデム１１ａ，１１ｂからのディジタル変調信号の出力タイミングを制御すれば、高周波部４のアンテナ４１，４２から放射されるディジタル変調信号の放射方向を任意の方向に制御することが可能になる。 When the modems 11a and 11b generate the same digital modulation signal, the same operation as in the eleventh embodiment can be realized. If the pulse width modulation circuits 101 and 102 are mounted instead of the pulse width modulation circuits 111 and 112, the same operation as in the eighth to tenth embodiments can be realized.
Further, when the modulation signal output circuit section 93 in FIG. 13 is connected to the high frequency section 4 in FIG. 11 in the tenth embodiment, the timing output from the pulse width modulation circuit 111 to the high frequency circuit 21 and the pulse width modulation If the output timing of the digital modulation signal from the modems 11a and 11b is controlled so that the timing output from the circuit 112 to the high frequency circuit 22 is shifted, the digital modulation signal radiated from the antennas 41 and 42 of the high frequency unit 4 is controlled. The radiation direction can be controlled in an arbitrary direction.
実施の形態１３．
　上記実施の形態１２では、変調信号出力回路部９３が２つのモデム１１ａ，１１ｂを実装し、パルス幅変調回路１１１から高周波回路２１に出力されるタイミングと、パルス幅変調回路１１２から高周波回路２２に出力されるタイミングとがずれるように、モデム１１ａ，１１ｂからのディジタル変調信号の出力タイミングを制御するものを示したが、１つのモデム１１とパルス幅変調回路１０１，１０２（または、パルス幅変調回路１１１，１１２）の間に遅延回路をそれぞれ挿入し、複数の遅延回路によるディジタル変調信号の遅延量を制御するようにしてもよく、この場合も、高周波部４のアンテナ４１，４２から放射されるディジタル変調信号の放射方向を任意の方向に制御することが可能になる。 Embodiment 13 FIG.
In the twelfth embodiment, the modulation signal output circuit unit 93 mounts the two modems 11a and 11b and outputs the timing from the pulse width modulation circuit 111 to the high frequency circuit 21, and from the pulse width modulation circuit 112 to the high frequency circuit 22. Although the control of the output timing of the digital modulation signal from the modems 11a and 11b is shown so that the output timing is deviated, one modem 11 and the pulse width modulation circuits 101 and 102 (or the pulse width modulation circuit) are shown. 111, 112) may be inserted respectively to control the amount of delay of the digital modulation signal by the plurality of delay circuits. In this case as well, radiation is radiated from the antennas 41, 42 of the high-frequency unit 4. The radiation direction of the digital modulation signal can be controlled in an arbitrary direction.
　図１４はこの発明の実施の形態１３によるディジタル送信機の変調信号出力回路部９４を示す構成図であり、図１４において、図８及び図１２と同一符号は同一または相当部分を示すので説明を省略する。
　変調信号出力回路部９４は、モデム１１、パルス幅変調回路１１１，１１２、設定回路１１３、遅延回路８１，８２及び遅延制御回路８３から構成されている。 FIG. 14 is a block diagram showing a modulation signal output circuit unit 94 of a digital transmitter according to Embodiment 13 of the present invention. In FIG. 14, the same reference numerals as those in FIGS. 8 and 12 indicate the same or corresponding parts. Omitted.
The modulation signal output circuit unit 94 includes a modem 11, pulse width modulation circuits 111 and 112, a setting circuit 113, delay circuits 81 and 82, and a delay control circuit 83.
　次に動作について説明する。
　遅延回路８１，８２によるディジタル変調信号の遅延量が０である場合、上記実施の形態１１，１２と同様の動作を実現することができる。パルス幅変調回路１１１，１１２の代わりに、パルス幅変調回路１０１，１０２を実装していれば、上記実施の形態８～１０と同様の動作を実現することができる。
　さらに、図１４の変調信号出力回路部９４が、上記実施の形態１０における図１１の高周波部４と接続される場合、パルス幅変調回路１１１から高周波回路２１に出力されるタイミングと、パルス幅変調回路１１２から高周波回路２２に出力されるタイミングとがずれるように、遅延制御回路８３が、遅延回路８１，８２での遅延量を制御すれば、高周波部４のアンテナ４１，４２から放射されるディジタル変調信号の放射方向を任意の方向に制御することが可能になる。 Next, the operation will be described.
When the delay amount of the digital modulation signal by the delay circuits 81 and 82 is zero, the same operation as in the above-described eleventh and twelfth embodiments can be realized. If the pulse width modulation circuits 101 and 102 are mounted instead of the pulse width modulation circuits 111 and 112, the same operation as in the eighth to tenth embodiments can be realized.
Furthermore, when the modulation signal output circuit unit 94 in FIG. 14 is connected to the high frequency unit 4 in FIG. 11 in the tenth embodiment, the timing output from the pulse width modulation circuit 111 to the high frequency circuit 21 and the pulse width modulation If the delay control circuit 83 controls the delay amount in the delay circuits 81 and 82 so that the timing output from the circuit 112 to the high-frequency circuit 22 is shifted, the digital signal radiated from the antennas 41 and 42 of the high-frequency unit 4 is controlled. The radiation direction of the modulation signal can be controlled in an arbitrary direction.
　なお、本願発明はその発明の範囲内において、各実施の形態の自由な組み合わせ、あるいは各実施の形態の任意の構成要素の変形、もしくは各実施の形態において任意の構成要素の省略が可能である。 In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .
　この発明に係るディジタル送信機は、モデムなどのディジタル回路で生成されたディジタル変調信号を直接高周波帯で送信する必要があるものに適している。 The digital transmitter according to the present invention is suitable for a digital transmitter that needs to directly transmit a digital modulation signal generated by a digital circuit such as a modem in a high frequency band.
　１，５，６，７　変調信号出力回路部、２，３，４　高周波部、１１，１１ａ，１１ｂ　モデム、１２，１３　ΔΣ変調回路、２１，２２　高周波回路、２３　合成回路、３１　合成回路、３２　高周波回路、４１，４２　アンテナ、５１，５２　ΔΣ変調回路、５３　設定回路、６１　初期値回路、６２　ＰＮ信号生成回路、６３　加算器、６４　ΔΣ変調器、７１　初期値回路、７２　ＰＮ信号生成回路、７３　オフセット生成回路、７４　加算器（第１の加算器）、７５　ΔΣ変調器（第１のΔΣ変調器）、７６　加算器（第２の加算器）、７７　ΔΣ変調器（第２のΔΣ変調器）、７８　加算器（第３の加算器）、８１，８２　遅延回路、８３　遅延制御回路、９１，９２，９３，９４　変調信号出力回路部、１０１，１０２　パルス幅変調回路、１１１，１１２　パルス幅変調回路，１１３　設定回路。 1, 5, 6, 7 modulation signal output circuit section, 2, 3, 4 high frequency section, 11, 11a, 11b modem, 12, 13 ΔΣ modulation circuit, 21, 22 high frequency circuit, 23 synthesis circuit, 31 synthesis circuit, 32 High frequency circuit, 41, 42 antenna, 51, 52 ΔΣ modulation circuit, 53 setting circuit, 61 initial value circuit, 62 PN signal generation circuit, 63 adder, 64 ΔΣ modulator, 71 initial value circuit, 72 PN signal generation circuit, 73 offset generation circuit, 74 adder (first adder), 75 ΔΣ modulator (first ΔΣ modulator), 76 adder (second adder), 77 ΔΣ modulator (second ΔΣ modulation) ), 78 adder (third adder), 81, 82 delay circuit, 83 delay control circuit, 91, 92, 93, 94 modulation signal output circuit section, 101, 102 pulse width modulation Circuit, 111, 112 pulse width modulation circuit, 113 setting circuit.

Claims (16)

  1. 　通信データを変調してディジタル変調信号を生成するモデムと、
    　前記モデムにより生成されたディジタル変調信号をデルタシグマ変調して、デルタシグマ変調後のディジタル変調信号を出力する複数のΔΣ変調回路と、
    　前記複数のΔΣ変調回路から出力されたディジタル変調信号における信号レベル又は周波数のうち、少なくとも一方を変換してから変換後の複数のディジタル変調信号を合成、あるいは、前記複数のΔΣ変調回路から出力されたディジタル変調信号を合成してから、前記複数のディジタル変調信号の合成信号における信号レベル又は周波数のうち、少なくとも一方を変換する高周波部とを備え、
    　前記複数のΔΣ変調回路の回路構成又は動作条件が異なっていることを特徴とするディジタル送信機。     A modem that modulates communication data to generate a digitally modulated signal;
    A plurality of ΔΣ modulation circuits for delta-sigma modulating the digital modulation signal generated by the modem and outputting the digital modulation signal after delta-sigma modulation;
    Convert at least one of the signal levels or frequencies in the digital modulation signals output from the plurality of ΔΣ modulation circuits and then combine the converted digital modulation signals, or output from the plurality of ΔΣ modulation circuits. A high-frequency unit that converts at least one of the signal level or the frequency in the combined signal of the plurality of digital modulation signals after combining the digital modulation signal,
    A digital transmitter characterized in that circuit configurations or operating conditions of the plurality of ΔΣ modulation circuits are different.
  2. 　前記高周波部は、
    　前記ΔΣ変調回路から出力されたディジタル変調信号における信号レベル又は周波数のうち、少なくとも一方を変換する複数の高周波回路と、
    　前記複数の高周波回路により変換されたディジタル変調信号を合成する合成回路とから構成されていることを特徴とする請求項１記載のディジタル送信機。     The high-frequency part is
    A plurality of high-frequency circuits that convert at least one of the signal level or frequency in the digital modulation signal output from the ΔΣ modulation circuit;
    2. The digital transmitter according to claim 1, further comprising a synthesis circuit for synthesizing the digital modulation signals converted by the plurality of high frequency circuits.
  3. 　前記高周波部は、
    　前記複数のΔΣ変調回路から出力されたディジタル変調信号を合成して、前記複数のディジタル変調信号の合成信号を出力する合成回路と、
    　前記合成回路から出力された合成信号における信号レベル又は周波数のうち、少なくとも一方を変換する高周波回路とから構成されていることを特徴とする請求項１記載のディジタル送信機。     The high-frequency part is
    Combining a digital modulation signal output from the plurality of ΔΣ modulation circuits, and outputting a combined signal of the plurality of digital modulation signals;
    2. The digital transmitter according to claim 1, wherein the digital transmitter comprises a high-frequency circuit that converts at least one of a signal level and a frequency in the combined signal output from the combining circuit.
  4. 　前記高周波部は、
    　前記ΔΣ変調回路から出力されたディジタル変調信号における信号レベル又は周波数のうち、少なくとも一方を変換する複数の高周波回路と、
    　前記高周波回路により変換されたディジタル変調信号を空間に放射する複数のアンテナとから構成されており、
    　前記複数のアンテナから放射されたディジタル変調信号が空間で合成されることを特徴とする請求項１記載のディジタル送信機。     The high-frequency part is
    A plurality of high-frequency circuits that convert at least one of the signal level or frequency in the digital modulation signal output from the ΔΣ modulation circuit;
    It is composed of a plurality of antennas that radiate digitally modulated signals converted by the high-frequency circuit into space,
    2. The digital transmitter according to claim 1, wherein the digital modulation signals radiated from the plurality of antennas are combined in space.
  5. 　前記複数のΔΣ変調回路として、回路構成が同一のΔΣ変調回路が実装されており、
    　前記複数のΔΣ変調回路に対して異なる動作条件を設定する設定回路を備えたことを特徴とする請求項１記載のディジタル送信機。     The ΔΣ modulation circuit having the same circuit configuration is mounted as the plurality of ΔΣ modulation circuits,
    2. The digital transmitter according to claim 1, further comprising a setting circuit that sets different operating conditions for the plurality of ΔΣ modulation circuits.
  6. 　前記複数のΔΣ変調回路は、
    　前記設定回路により設定された動作条件に対応するディジタル変調信号の初期値を出力する初期値回路と、
    　前記設定回路により設定された動作条件に対応する疑似雑音信号を生成するＰＮ信号生成回路と、
    　動作タイミングを示すクロック群のうち、１番目のクロックが入力されると、前記モデムにより生成されたディジタル変調信号に対して、前記初期値回路から出力された初期値と、前記ＰＮ信号生成回路により生成された疑似雑音信号とを加算して、前記初期値及び前記疑似雑音信号を加算したディジタル変調信号を出力し、２番目以降のクロックが入力されると、前記モデムにより生成されたディジタル変調信号に対して、前記ＰＮ信号生成回路により生成された疑似雑音信号を加算して、前記疑似雑音信号を加算したディジタル変調信号を出力する加算器と、
    　前記加算器から出力されたディジタル変調信号をデルタシグマ変調して、デルタシグマ変調後のディジタル変調信号を出力するΔΣ変調器とから構成されていることを特徴とする請求項５記載のディジタル送信機。     The plurality of ΔΣ modulation circuits are
    An initial value circuit for outputting an initial value of a digital modulation signal corresponding to the operating condition set by the setting circuit;
    A PN signal generation circuit that generates a pseudo noise signal corresponding to the operating condition set by the setting circuit;
    When the first clock of the clock group indicating the operation timing is input, the initial value output from the initial value circuit and the PN signal generation circuit with respect to the digital modulation signal generated by the modem The generated pseudo noise signal is added to output a digital modulation signal obtained by adding the initial value and the pseudo noise signal, and when the second and subsequent clocks are input, the digital modulation signal generated by the modem In contrast, an adder that adds a pseudo noise signal generated by the PN signal generation circuit and outputs a digital modulation signal obtained by adding the pseudo noise signal;
    6. The digital transmitter according to claim 5, further comprising a delta-sigma modulator that delta-sigma-modulates the digital modulation signal output from the adder and outputs a digital modulation signal after delta-sigma modulation. .
  7. 　前記複数のΔΣ変調回路は、
    　前記設定回路により設定された動作条件に対応するディジタル変調信号の第一の初期値と第二の初期値を出力する初期値回路と、
    　前記設定回路により設定された動作条件に対応する第一の疑似雑音信号と第二の疑似雑音信号を生成するＰＮ信号生成回路と、
    　前記設定回路により設定された動作条件に対応するオフセット信号を生成するオフセット生成回路と、
    　動作タイミングを示すクロック群のうち、１番目のクロックが入力されると、前記モデムにより生成されたディジタル変調信号に対して、前記初期値回路から出力された第一の初期値と、前記ＰＮ信号生成回路により生成された第一の疑似雑音信号とを加算して、前記第一の初期値及び前記第一の疑似雑音信号を加算したディジタル変調信号を出力し、２番目以降のクロックが入力されると、前記モデムにより生成されたディジタル変調信号に対して、前記ＰＮ信号生成回路により生成された第一の疑似雑音信号を加算して、前記第一の疑似雑音信号を加算したディジタル変調信号を出力する第１の加算器と、
    　前記第１の加算器から出力されたディジタル変調信号をデルタシグマ変調して、デルタシグマ変調後のディジタル変調信号を出力する第１のΔΣ変調器と、
    　前記１番目のクロックが入力されると、前記第１のΔΣ変調器から出力されたディジタル変調信号に対して、前記初期値回路から出力された第二の初期値と、前記ＰＮ信号生成回路により生成された第二の疑似雑音信号と、前記オフセット生成回路により生成されたオフセット信号とを加算して、前記第二の初期値、前記第二の疑似雑音信号及び前記オフセット信号を加算したディジタル変調信号を出力し、前記２番目以降のクロックが入力されると、前記第１のΔΣ変調器から出力されたディジタル変調信号に対して、前記ＰＮ信号生成回路により生成された第二の疑似雑音信号と、前記オフセット生成回路により生成されたオフセット信号とを加算して、前記第二の疑似雑音信号及び前記オフセット信号を加算したディジタル変調信号を出力する第２の加算器と、
    　前記第２の加算器から出力されたディジタル変調信号をデルタシグマ変調して、デルタシグマ変調後のディジタル変調信号を出力する第２のΔΣ変調器と、
    　前記第１のΔΣ変調器から出力されたディジタル変調信号と前記第２のΔΣ変調器から出力されたディジタル変調信号とを加算して、前記加算したディジタル変調信号を出力する第３の加算器とから構成されていることを特徴とする請求項５記載のディジタル送信機。     The plurality of ΔΣ modulation circuits are
    An initial value circuit for outputting a first initial value and a second initial value of the digital modulation signal corresponding to the operating condition set by the setting circuit;
    A PN signal generation circuit for generating a first pseudo noise signal and a second pseudo noise signal corresponding to the operating conditions set by the setting circuit;
    An offset generation circuit that generates an offset signal corresponding to the operating condition set by the setting circuit;
    When the first clock of the clock group indicating the operation timing is input, the first initial value output from the initial value circuit with respect to the digital modulation signal generated by the modem, and the PN signal The first pseudo noise signal generated by the generation circuit is added to output a digital modulation signal obtained by adding the first initial value and the first pseudo noise signal, and the second and subsequent clocks are input. Then, the first pseudo noise signal generated by the PN signal generation circuit is added to the digital modulation signal generated by the modem, and the digital modulation signal obtained by adding the first pseudo noise signal is obtained. A first adder to output;
    A first ΔΣ modulator that delta-sigma-modulates the digital modulation signal output from the first adder and outputs a digital modulation signal after delta-sigma modulation;
    When the first clock is input, a second initial value output from the initial value circuit and a PN signal generation circuit are applied to the digital modulation signal output from the first ΔΣ modulator. Digital modulation obtained by adding the generated second pseudo noise signal and the offset signal generated by the offset generation circuit and adding the second initial value, the second pseudo noise signal, and the offset signal When the second and subsequent clocks are input, a second pseudo noise signal generated by the PN signal generation circuit is generated with respect to the digital modulation signal output from the first ΔΣ modulator. And the offset signal generated by the offset generation circuit are added to output a digital modulation signal obtained by adding the second pseudo noise signal and the offset signal. A second adder for,
    A second ΔΣ modulator that delta-sigma-modulates the digital modulation signal output from the second adder and outputs a digital modulation signal after delta-sigma modulation;
    A third adder that adds the digital modulation signal output from the first ΔΣ modulator and the digital modulation signal output from the second ΔΣ modulator, and outputs the added digital modulation signal; The digital transmitter according to claim 5, comprising:
  8. 　前記モデムとして、互いに同一のディジタル変調信号を生成する複数のモデムが実装されて、前記複数のモデムと前記複数のΔΣ変調回路が一対一で接続されていることを特徴とする請求項１記載のディジタル送信機。 2. The modem according to claim 1, wherein a plurality of modems that generate the same digital modulation signal are mounted as the modem, and the plurality of modems and the plurality of ΔΣ modulation circuits are connected one-to-one. Digital transmitter.
  9. 　前記複数のΔΣ変調回路の入力側に設けられ、前記モデムにより生成されたディジタル変調信号を遅延して、遅延後のディジタル変調信号を当該ΔΣ変調回路に出力する複数の遅延回路と、
    　前記複数の遅延回路によるディジタル変調信号の遅延量を制御する遅延制御回路とを備えたことを特徴とする請求項１記載のディジタル送信機。     A plurality of delay circuits that are provided on the input side of the plurality of ΔΣ modulation circuits, delay the digital modulation signal generated by the modem, and output the delayed digital modulation signal to the ΔΣ modulation circuit;
    2. The digital transmitter according to claim 1, further comprising a delay control circuit that controls a delay amount of the digital modulation signal by the plurality of delay circuits.
  10. 　通信データを変調してディジタル変調信号を生成するモデムと、
    　前記モデムにより生成されたディジタル変調信号をパルス幅変調して、パルス幅変調後のディジタル変調信号を出力する複数のパルス幅変調回路と、
    　前記複数のパルス幅変調回路から出力されたディジタル変調信号における信号レベル又は周波数のうち、少なくとも一方を変換してから変換後の複数のディジタル変調信号を合成、あるいは、前記複数のパルス幅変調回路から出力されたディジタル変調信号を合成してから、前記複数のディジタル変調信号の合成信号における信号レベル又は周波数のうち、少なくとも一方を変換する高周波部とを備え、
    　前記複数のパルス幅変調回路の回路構成又は動作条件が異なっていることを特徴とするディジタル送信機。     A modem that modulates communication data to generate a digitally modulated signal;
    A plurality of pulse width modulation circuits that pulse-modulate the digital modulation signal generated by the modem and output a digital modulation signal after pulse width modulation;
    After converting at least one of the signal levels or frequencies in the digital modulation signals output from the plurality of pulse width modulation circuits, combining the plurality of digital modulation signals after conversion, or from the plurality of pulse width modulation circuits A high-frequency unit that synthesizes the output digital modulation signal and then converts at least one of the signal level or frequency in the combined signal of the plurality of digital modulation signals;
    A digital transmitter characterized in that circuit configurations or operating conditions of the plurality of pulse width modulation circuits are different.
  11. 　前記高周波部は、
    　前記パルス幅変調回路から出力されたディジタル変調信号における信号レベル又は周波数のうち、少なくとも一方を変換する複数の高周波回路と、
    　前記複数の高周波回路により変換されたディジタル変調信号を合成する合成回路とから構成されていることを特徴とする請求項１０記載のディジタル送信機。     The high-frequency part is
    A plurality of high frequency circuits for converting at least one of the signal level or frequency in the digital modulation signal output from the pulse width modulation circuit;
    11. The digital transmitter according to claim 10, comprising a synthesis circuit for synthesizing digital modulation signals converted by the plurality of high frequency circuits.
  12. 　前記高周波部は、
    　前記複数のパルス幅変調回路から出力されたディジタル変調信号を合成して、前記複数のディジタル変調信号の合成信号を出力する合成回路と、
    　前記合成回路から出力された合成信号における信号レベル又は周波数のうち、少なくとも一方を変換する高周波回路とから構成されていることを特徴とする請求項１０記載のディジタル送信機。     The high-frequency part is
    Combining a digital modulation signal output from the plurality of pulse width modulation circuits, and outputting a combined signal of the plurality of digital modulation signals;
    11. The digital transmitter according to claim 10, wherein the digital transmitter comprises a high-frequency circuit that converts at least one of a signal level and a frequency in the combined signal output from the combining circuit.
  13. 　前記高周波部は、
    　前記パルス幅変調回路から出力されたディジタル変調信号における信号レベル又は周波数のうち、少なくとも一方を変換する複数の高周波回路と、
    　前記高周波回路により変換されたディジタル変調信号を空間に放射する複数のアンテナとから構成されており、
    　前記複数のアンテナから放射されたディジタル変調信号が空間で合成されることを特徴とする請求項１０記載のディジタル送信機。     The high-frequency part is
    A plurality of high frequency circuits for converting at least one of the signal level or frequency in the digital modulation signal output from the pulse width modulation circuit;
    It is composed of a plurality of antennas that radiate digitally modulated signals converted by the high-frequency circuit into space,
    11. The digital transmitter according to claim 10, wherein the digital modulation signals radiated from the plurality of antennas are combined in space.
  14. 　前記複数のパルス幅変調回路として、回路構成が同一のパルス幅変調回路が実装されており、
    　前記複数のパルス幅変調回路に対して異なる動作条件を設定する設定回路を備えたことを特徴とする請求項１０記載のディジタル送信機。     As the plurality of pulse width modulation circuits, a pulse width modulation circuit having the same circuit configuration is mounted,
    11. The digital transmitter according to claim 10, further comprising a setting circuit for setting different operating conditions for the plurality of pulse width modulation circuits.
  15. 　前記モデムとして、互いに同一のディジタル変調信号を生成する複数のモデムが実装されて、前記複数のモデムと前記複数のパルス幅変調回路が一対一で接続されていることを特徴とする請求項１０記載のディジタル送信機。 11. A plurality of modems that generate the same digital modulation signal are mounted as the modem, and the plurality of modems and the plurality of pulse width modulation circuits are connected one-to-one. Digital transmitter.
  16. 　前記複数のパルス幅変調回路の入力側に設けられ、前記モデムにより生成されたディジタル変調信号を遅延して、遅延後のディジタル変調信号を当該パルス幅変調回路に出力する複数の遅延回路と、
    　前記複数の遅延回路によるディジタル変調信号の遅延量を制御する遅延制御回路とを備えたことを特徴とする請求項１５記載のディジタル送信機。     A plurality of delay circuits provided on the input side of the plurality of pulse width modulation circuits, delaying the digital modulation signal generated by the modem, and outputting the delayed digital modulation signal to the pulse width modulation circuit;
    16. The digital transmitter according to claim 15, further comprising a delay control circuit that controls a delay amount of the digital modulation signal by the plurality of delay circuits.
PCT/JP2015/082259 2015-11-17 2015-11-17 Digital transmitter WO2017085789A1 (en)

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CN111510119A (en) * 2020-04-30 2020-08-07 矽力杰半导体技术(杭州)有限公司 Frequency modulation circuit and transmitter using the same
RU2758587C1 (en) * 2021-05-11 2021-11-01 Акционерное общество Научно-производственный центр "Электронные вычислительно-информационные системы" (АО НПЦ "ЭЛВИС") High-speed data transmission device using digital modulation and pseudorandom adjustment of the operating frequency (options)
WO2023199394A1 (en) * 2022-04-12 2023-10-19 三菱電機株式会社 Digital sender
WO2023223523A1 (en) * 2022-05-20 2023-11-23 三菱電機株式会社 Delta-sigma modulation circuit, digital transmission circuit, and digital transmitter

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111510119A (en) * 2020-04-30 2020-08-07 矽力杰半导体技术(杭州)有限公司 Frequency modulation circuit and transmitter using the same
CN111510119B (en) * 2020-04-30 2023-10-27 矽力杰半导体技术(杭州)有限公司 Frequency modulation circuit and transmitter using same
RU2758587C1 (en) * 2021-05-11 2021-11-01 Акционерное общество Научно-производственный центр "Электронные вычислительно-информационные системы" (АО НПЦ "ЭЛВИС") High-speed data transmission device using digital modulation and pseudorandom adjustment of the operating frequency (options)
WO2023199394A1 (en) * 2022-04-12 2023-10-19 三菱電機株式会社 Digital sender
WO2023223523A1 (en) * 2022-05-20 2023-11-23 三菱電機株式会社 Delta-sigma modulation circuit, digital transmission circuit, and digital transmitter

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