WO2017084523A1

WO2017084523A1 - Method and device for system on chip bus activity detection and computer storage medium

Info

Publication number: WO2017084523A1
Application number: PCT/CN2016/105176
Authority: WO
Inventors: 段延亮
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2015-11-17
Filing date: 2016-11-09
Publication date: 2017-05-26
Also published as: CN106708679A; CN106708671A

Abstract

A system on chip (SoC) bus activity detection method comprising: receiving a SoC bus signal, where the SoC bus signal comprises an Advanced eXtensible Interface (AXI) bus signal (100); performing at least one of the following operations on the basis of the AXI bus signal received: capturing channel data of an AXI bus or compiling statistics at least once with respect to a bus transmission parameter during AXI bus data transmission, where the captured channel data of the AXI bus comprises at least one of the following types of data: data transmitted by a write data channel of the AXI bus or data transmitted by a read data channel of the AXI bus; the bus transmission parameter for which statics are compiled each time comprises: the average delay of bus transmission or the average bandwidth occupied during a corresponding statistics time (101). Also disclosed are a SoC bus activity detection device and a computer storage medium.

Description

Method, device and computer storage medium for detecting system bus behavior

Technical field

The present invention relates to the field of System on Chip (SoC), and in particular, to a SoC bus behavior detection method, apparatus, and computer storage medium.

Background technique

The current SoC chip runs faster and faster, and its processor's main frequency has reached 2GHz or above. Therefore, the test machine cannot capture the instantaneous signal, and it is even more impossible to penetrate the chip to capture the bus signal. This requires a monitoring module. Embedded in the chip to capture bus signals in real time.

However, existing monitoring modules such as the SonicsMT and FlexNoC monitoring modules can only capture certain signals of the Advanced EXtensible Interface (AXI) bus. Specifically, the existing monitoring module can only The AXI bus address and commands are fetched, and the AXI bus data cannot be captured. In short, the existing monitoring module has a single function, which cannot meet the diversified requirements for debugging the SoC chip.

Summary of the invention

In order to solve the above technical problem, embodiments of the present invention are expected to provide a SoC bus behavior detecting method, apparatus, and computer storage medium.

The technical solution of the embodiment of the present invention is implemented as follows:

The embodiment of the invention provides a SoC bus behavior detection method, including:

Receiving a SoC bus signal, the SoC bus signal including an AXI bus signal;

Perform at least one of the following operations based on the received AXI bus signal: grab the AXI bus channel data, and perform at least one statistics on the bus transmission parameters when performing AXI bus data transmission; the captured AXI bus channel data includes at least one of the following data: The AXI bus write data channel The transmitted data, the data transmitted by the AXI bus read data channel; the bus transmission parameters of each statistics include: the average delay of the bus transmission or the average bandwidth occupied by the corresponding statistical time.

In the above solution, the capturing the AXI bus channel data includes: the signal transmitted by the write address channel (AW) in the AXI bus signal satisfies the preset first trigger condition, or the read address channel in the AXI bus signal. When the signal transmitted by (Read address channel, AR) satisfies the preset second trigger condition, the AXI bus channel data is captured.

In the above solution, the captured AXI bus channel data is data of each channel in which the enable signal of the AXI bus signal is valid.

In the above solution, the method further includes: setting a register, wherein the register is configured to store a statistical result of the bus transmission parameter;

After the statistics window is finished, the stored statistical result is read by sending an interrupt request. Once the statistics window is finished, the next statistical window is automatically entered until the statistics function is turned off, so as to implement multiple statistics of the transmission parameters during AXI data transmission.

In the above scheme, the calculation formula of the average delay of the bus transmission for each AXI bus data transmission is:

T=total_delay/n

Where T represents the average delay of the bus transmission corresponding to one statistic, Total_delay represents the sum of the time spent by each Burst transmission in the corresponding statistical time, and n represents the number of Burst transmissions occurring in the corresponding statistical time;

The calculation formula of the average bandwidth B occupied by each statistical bus transmission when performing AXI bus data transmission is:

B=total_byte/total_cycle

Where B represents the average bandwidth occupied by the corresponding one-time bus transmission, total_byte represents the sum of the amount of data transmitted by each Burst transmission in the corresponding statistical time, and total_cycle represents the number of clock cycles experienced by the corresponding statistical time.

In the above solution, the method further includes: receiving timestamp information corresponding to the AXI bus signal.

In the above solution, the SoC bus signal further includes: an AXI Coherency Extensions (ACE) bus signal;

After receiving the SoC bus signal, the method further includes: capturing the ACE bus channel data based on the received ACE bus signal.

In the above solution, the capturing the ACE bus channel data comprises: capturing the ACE bus channel data when the signal transmitted by the AC channel of the ACE bus signal satisfies a preset third trigger condition.

In the above solution, the captured ACE bus channel data is data of each channel in which the enable signal is valid in the ACE bus signal.

In the above solution, the method further includes: capturing timestamp information corresponding to the ACE bus signal.

In the above solution, the method further includes:

Monitor the occurrence of a deadlock, and when the deadlock occurs, grab the identity (ID) and address when the deadlock occurs;

And/or, monitor access to the exception address, issue an interrupt when an access exception occurs, and grab the address and ID when the exception occurred.

The embodiment of the invention further provides a SoC bus behavior detecting device, comprising: a receiving module and a detecting module; wherein

a receiving module configured to receive a SoC bus signal, where the SoC bus signal includes an AXI bus signal;

The detecting module is configured to perform at least one of the following operations based on the received AXI bus signal: grab the AXI bus channel data, and perform at least one statistics on the bus transmission parameters when performing the AXI bus data transmission; the captured AXI bus channel data includes at least one The following data: the data transmitted by the AXI bus write data channel, the data transmitted by the AXI bus read data channel; the bus transmission parameters of each statistics include: the average delay of the bus transmission in the corresponding statistical time or possession Average bandwidth.

In the above solution, the detection module is configured to transmit AW channel in the AXI bus signal. The signal satisfies the preset first trigger condition, or the AXI bus channel data is captured when the signal transmitted by the AR channel in the AXI bus signal satisfies the preset second trigger condition.

In the above solution, the detecting module further includes a register configured to store a statistical result of the bus transmission parameter;

In the above solution, the receiving module is further configured to receive an ACE bus signal;

In the above solution, the detecting module is configured to capture the ACE bus channel data when the signal transmitted by the AC channel of the ACE bus signal satisfies a preset third trigger condition.

In the above solution, the detecting module is further configured to:

Monitor the occurrence of a deadlock, and when the deadlock occurs, grab the ID and address when the deadlock occurs;

The embodiment of the invention further provides a computer storage medium, the computer storage medium comprising a set of instructions, when executed, causing at least one processor to perform the SoC bus behavior detection method described above.

The SoC bus behavior detecting method, apparatus and computer storage medium provided by the embodiments of the present invention receive a SoC bus signal, and the SoC bus signal includes an AXI bus signal; The AXI bus signal performs at least one of the following operations: grabbing AXI bus channel data, and performing at least one statistics on bus transmission parameters when performing AXI bus data transmission; the captured AXI bus channel data includes at least one of the following data: the AXI The data transmitted by the bus write data channel and the data transmitted by the AXI bus read data channel; the bus transmission parameters of each statistics include: the average delay of the bus transmission or the average bandwidth occupied by the corresponding statistical time. As such, the embodiment of the present invention supports the capture of AXI bus data and the parameter statistics of AXI bus data, and can meet the diversified requirements of SoC bus debugging.

DRAWINGS

1 is a flow chart of a first embodiment of a method for detecting a SoC bus behavior according to the present invention;

2 is a schematic diagram of a process of capturing AXI bus channel data in a first embodiment of a SoC bus behavior detection method according to the present invention;

3 is a timing diagram showing statistics of a primary bus transmission parameter in a first embodiment of a SoC bus behavior detection method according to the present invention;

4 is a schematic diagram of a process of statistical bus transmission parameters in a first embodiment of a SoC bus behavior detection method according to the present invention;

FIG. 5 is a timing diagram of performing continuous statistics in the first embodiment of the SoC bus behavior detecting method according to the present invention; FIG.

6 is a schematic diagram of a process of capturing ACE bus channel data in a first embodiment of a SoC bus behavior detection method according to the present invention;

FIG. 7 is a schematic diagram of an application scenario of a second embodiment of a SoC bus behavior detection method according to the present invention; FIG.

8 is a flow chart of bus data capture in a second embodiment of a SoC bus behavior detection method according to the present invention;

FIG. 9 is a flowchart of statistics of bus transmission parameters in a second embodiment of the SoC bus behavior detecting method according to the present invention; FIG.

10 is a schematic diagram of a first component structure of a SoC bus behavior detecting apparatus according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of a second component structure of a SoC bus behavior detecting apparatus according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings.

In various embodiments of the present invention, a SoC bus signal is received, the SoC bus signal includes an AXI bus signal, and at least one of the following operations is performed based on the received AXI bus signal: grabbing AXI bus channel data, and performing AXI bus data The bus transmission parameters are transmitted at least once; the captured AXI bus channel data includes at least one of the following: data transmitted by the AXI bus write data channel, data transmitted by the AXI bus read data channel; The bus transmission parameters include: the average delay of the bus transmission in the corresponding statistical time or the average bandwidth occupied.

1 is a flowchart of a first embodiment of a SoC bus behavior detection method according to the present invention. As shown in FIG. 1, the method includes:

Step 100: Receive a SoC bus signal, where the SoC bus signal includes an AXI bus signal.

Here, the AXI bus signal usually includes signals of at least one of the following channels: an AR channel signal, an AW channel signal, a read data channel (R) signal, a write data channel (W) signal, and a write response channel ( Write response channel, B) signal.

Further, timestamp information corresponding to the AXI bus signal can also be received, so that the time of the bus handshake and the time of responding to the handshake can be accurately learned.

In this step, in order to improve the timing between the signals of the respective channels of the AXI bus signal, the timing between the signals of the respective channels of the AXI bus signal can be adjusted before receiving the AXI bus signal, for example, using the basic logical unit slice to the AXI. The timing between the individual channel signals of the bus signal is adjusted.

In this step, the SoC bus signal can also include AXI Coherency (AXI Coherency). Extensions, ACE) bus signals; here, the ACE bus signals usually include signals of at least one of the following channels: an AC channel (snoop address channel) signal, a CR channel (snoop response channel) signal, and a CD channel (snoop data channel) signal.

Further, time stamp information corresponding to the ACE bus signal can also be received, so that the time of the bus handshake and the time of responding to the handshake can be accurately learned.

In this step, in order to improve the timing between the signals of the respective channels of the ACE bus signal, the timing between the signals of the respective channels of the ACE bus signal can be adjusted before receiving the ACE bus signal, for example, using the basic logical unit slice to the ACE. The timing between the individual channel signals of the bus signal is adjusted.

Step 101: Perform at least one of the following operations based on the received AXI bus signal: grab the AXI bus channel data, and perform at least one statistics on the bus transmission parameters when performing AXI bus data transmission; the captured AXI bus channel data includes at least one of the following: Data: the data transmitted by the AXI bus write data channel, the data transmitted by the AXI bus read data channel; the bus transmission parameters of each statistics include: the average delay of the bus transmission in the corresponding statistical time or the average occupied bandwidth.

Specifically, the capturing the AXI bus channel data includes: receiving the first data capture signal; and when the first data capture signal is valid, the data of each channel of the received AXI bus is captured, and the first data is captured. When the signal is invalid, the data acquisition process of each channel of the received AXI bus is stopped. Here, the validity of the first data capture signal may be preset, for example, the first data capture signal is a high level signal or a low level signal, and when the first data capture signal is a high level signal, indicating A data capture signal is valid; when the first data capture signal is a low level signal, it indicates that the first data capture signal is invalid.

In this step, the capturing the AXI bus channel data includes: the signal transmitted by the AW channel in the AXI bus signal satisfies a preset first trigger condition, or the signal transmitted by the AR channel in the AXI bus signal satisfies a preset second trigger. Grab the AXI bus channel data when conditions are met; at AXI total The signal transmitted by the AW channel in the line signal does not satisfy the preset first trigger condition, and the AXI bus channel data is not captured when the signal transmitted by the AR channel in the AXI bus signal does not satisfy the preset second trigger condition.

Here, the preset first trigger condition may be set according to at least one of the following elements: an AWID signal transmitted by the AW channel, an AWADDR signal transmitted by the AW channel, an AWLEN signal transmitted by the AW channel, an AWSIZE signal transmitted by the AW channel, and AWBURST transmitted by the AW channel. The preset second trigger condition may be set according to at least one of the following elements: an ARID signal transmitted by the AR channel, an ARADDR signal transmitted by the AR channel, an ARLEN signal transmitted by the AR channel, an ARSIZE signal transmitted by the AR channel, and an ARBURST transmitted by the AR channel. signal.

In this step, the captured AXI bus channel data is the data of each channel in which the enable signal of the AXI bus signal is valid. Here, the validity of the enable signal corresponding to each channel signal in the AXI bus signal can be set in advance.

In this way, by reasonably setting the first trigger condition, the second trigger condition, and the validity of the enable signal, the AXI bus channel data can be flexibly captured, and the data amount of the captured AXI bus channel data can be reduced.

Illustratively, the process of capturing AXI bus channel data is described below by way of a specific example.

The AXI protocol supports Outstanding transport access, that is, can issue multiple unfinished transactions; the AXI protocol can mark each Burst transmission with an ID, so in the first embodiment of the present invention, two register groups id_reg and id_cnt are set, wherein the register set id_reg configured to record the ID number of each Burst transmission order index register set id_cnt Burst configured to record the transmission of the same ID number reaches, here, if the same ID number a plurality of transmission Burst exists, the first i ₁ th The index of the order of arrival of the Burst transmission is denoted as i ₁ , and i ₁ is a natural number.

2 is a schematic diagram of a process of capturing AXI bus channel data in a first embodiment of a SoC bus behavior detection method according to the present invention. As shown in FIG. 2, gbal_id_reg indicates that a preset check is performed. The query order of the Burst transmissions in the order is set. The pre-set query order is the arrow order in FIG. 2 (top to bottom); the register group id_reg is composed of a plurality of storage units (slots), each slot is configured to store an ID. The register group id_cnt is also composed of multiple slots, and each slot is configured to store the value of an index.

Figure 2 depicts the capture process of AXI bus channel data from time T0 to time T4, as follows:

At time T0, the first data capture signal is changed from invalid to valid, however, there is also a Burst transmission with ID 0 not completed at this time.

At time T1, a response of a Burst transmission is received. When the response of the received Burst transmission matches the Burst transmission that is not completed at time T0, the Burst transmission indicating that the ID of 0 is not completed at time T0 has been completed at time T1. At the time of the register group id_reg and the register group id_cnt, the slot corresponding to the Burst transmission whose ID is 0 which is not completed at time T0 is invalid. In FIG. 2, the data of the invalid slot is marked as X.

At time T2, for the new Burst transmission, in the register group id_reg and the register group id_cnt, find a valid slot, and search for a slot corresponding to the Burst transmission that satisfies the preset first trigger condition or the second trigger condition, and the slot is selected. Marked as "matched"; the slot corresponding to the Burst transmission that does not satisfy the preset first trigger condition and does not satisfy the preset second trigger condition is marked as "mismatch". Here, for a "mismatch" slot, there is no need to grab the corresponding Burst transmission data. In Fig. 2, the slot labeled "matched" corresponds to the second row of the T2 timetable table, and the slot labeled "unmatched" corresponds to the third row to the fifth row of the T2 timetable table.

At time T2, for the write data operation, if the write ID tag (WID) is the same as the ID stored in the slot labeled "matched", and the value of the index stored in the corresponding slot labeled "matched" is the smallest, then It is considered that the WID matches the ID stored in the corresponding slot marked as "matched", and at this time, the write data (WDATA), the write strobe (WSTRB), the write last (WLAST), and the write ID mark (WID) are all caught. Take and send the captured data to the FIFO.

At time T2, for the read data operation, if the read ID tag (RID) is the same as the ID stored in the slot marked "matched", and the value of the index stored in the corresponding slot marked "matched" is the smallest, then The RID is considered to match the ID stored in the corresponding slot labeled "matched", at which point the read data (RDATA), the read response (RRESP), the RID, and the last read (RLAST) are all fetched and will be fetched. The subsequent data is sent to the FIFO.

At time T3, for the write data operation, if the response ID (BID) is equal to 0, if the BID is the same as the ID stored in the slot marked "matched", and the corresponding index is marked as "matched". If the value of the BID is the smallest, the BID is considered to match the ID stored in the corresponding slot marked as "matched". At this time, the Burst transmission corresponding to the slot labeled "matched" has been completed, so the Burst transmission at T3 is completed. The slot flag is invalid, and the invalid slot corresponds to the second row of the T3 time table in FIG. 2; then, in the register group id_reg and the register group id_cnt, the index value corresponding to the slot with the remaining ID equal to 0 is decremented by one, and Write response (BRESP), BID is sent to the FIFO.

At time T3, for a read data operation, if RID is equal to 0 and RLAST is valid, if the RID is the same as the ID stored in the slot labeled "matched", and the corresponding slot marked "matched" is stored If the value of the index is the smallest, it is considered that the Burst transmission corresponding to the slot marked as "matched" has been completed, so the slot in which the Burst transmission has been completed at T3 is marked as invalid; then, in the register group id_reg and the register group id_cnt, the rest The index value corresponding to the slot with ID equal to 0 is decremented by 1, and RLAST, RDATA, and RRESP are sent to the FIFO.

At time T4, for the write data operation, if the BID is equal to 0, if the BID is the same as the ID stored in the slot marked as "mismatching", and the corresponding index of the slot marked as "unmatched" stores the smallest value, The BID is considered to match the ID stored in the corresponding slot marked as “mismatched”. At this time, the Burst transmission corresponding to the slot marked as “mismatched” has been completed, and only the slot in which Burst transmission has been completed at T4 is marked as invalid. Without the data being fetched and sent, the Burst transmission does not satisfy the preset first trigger condition and the second trigger condition.

At time T4, for a read data operation, in the case where RID is equal to 0 and RLAST is valid, if the RID is the same as the ID stored in the slot marked "unmatched", and the corresponding slot marked "mismatching" is stored. If the value of the index is the smallest, it is considered that the Burst transmission corresponding to the slot marked as "unmatched" has been completed. At this time, only the slot whose Burst transmission has been completed at T4 is marked as invalid, and the slot marked as invalid corresponds to the time T4 in FIG. The third line of the table; no data grabbing is performed at time T4 because the Burst transmission does not satisfy the preset first trigger condition and the second trigger condition.

In this step, the data transmission is usually performed by using the Burst transmission mechanism when performing AXI bus data transmission, and the Burst transmission mechanism includes but is not limited to incremental bursting and rewinding bursting.

Illustratively, the average delay of each statistical bus transmission for AXI bus data transmission can be calculated according to the following formula:

T=total_delay/n

Where T represents the average delay of the bus transmission corresponding to one statistic, Total_delay represents the sum of the time spent on each Burst transmission in the corresponding statistical time, and n represents the number of Burst transmissions occurring in the corresponding statistical time; , Total_delay=T1+T2+...+Tn, T1 to Tn respectively indicate the time taken for the first Burst transmission to the nth Burst transmission in the corresponding statistical time.

The average bandwidth occupied by the bus transmission for each AXI bus data transmission can be calculated according to the following formula:

B=total_byte/total_cycle

Where B is the average bandwidth occupied by the corresponding one-time bus transmission, and total_byte is the sum of the amount of data transmitted by each Burst transmission in the corresponding statistical time. The unit is bit, and total_cycle indicates the clock period experienced by the corresponding statistical time. The number, total_cycle is a natural number; specifically, the calculation formula of total_byte is: Total_byte=(L1+L2+...+Ln)*8, where L1 to Ln respectively indicate the first Burst transmission to the nth Burst in the corresponding statistical time. The amount of data transferred by the transmission, in bytes.

3 is a timing diagram of counting a bus transmission parameter in the first embodiment of the SoC bus behavior detecting method of the present invention. As shown in FIG. 3, ACLK represents a global clock signal, AWVALID indicates that a write address is valid, and AWREADY indicates a write address preparation, AWADDR. Indicates the write address, AWSIZE indicates the maximum number of bytes of a beat data in a write transfer, AWLEN indicates how many beat data is written in one write, BVALID indicates that the write response is valid, BREADY indicates the response preparation, and BRESP indicates the write response; The meaning of T1 to Tn is explained.

Further, the at least one statistics of the bus transmission parameters when performing AXI bus data transmission include: receiving a statistical trigger signal; and when the statistical trigger signal is valid, performing bus transmission parameters for AXI bus data transmission at least once in sequence, When the statistical trigger signal is invalid, stop counting the bus transmission parameters when performing AXI bus data transmission. Here, the validity of the statistical trigger signal may be preset. For example, the statistical trigger signal is a high level signal or a low level signal. When the statistical trigger signal is a high level signal, it indicates that the statistical trigger signal is valid; otherwise, when the statistical trigger is triggered When the signal is low level, it indicates that the statistical trigger signal is invalid.

Specifically, the following two statistical modes can be used to determine the end time point of each statistic.

The first statistical mode: the starting time point of the first statistics of the bus transmission parameters when performing AXI bus data transmission is the time when the statistical trigger signal changes from invalid to valid, and the termination time point is earlier among the following two time points. Time point: The time when the trigger signal is valid from invalid to invalid, and the number of clock cycles experienced by the first statistic exceeds the preset number of clock cycles Fixed_cycle.

When j is greater than 1, the start time point of the j-th statistics of the bus transmission parameters when performing AXI bus data transmission is the termination time point of the j-1th statistic or the termination time point of the j-1th statistic. At the first successful moment, the end time point of the jth statistics of the bus transmission parameters when performing AXI bus data transmission is the earlier time point of the following two time points: the time when the statistical trigger signal is changed from valid to invalid, The number of clock cycles experienced by j statistics exceeds the preset number of clock cycles Fixed_cycle.

The second statistical mode: the first bus transmission parameters for AXI bus data transmission The starting time point of the secondary statistic is the time when the statistical trigger signal changes from invalid to valid, and the ending time point is the earlier time point of the following two time points: the time when the statistical trigger signal is changed from valid to invalid, and the first time is performed. The sum of the amount of data transmitted by each Burst transmission is greater than the preset data amount of the fixed byte.

When j is greater than 1, the start time point of the j-th statistics of the bus transmission parameters when performing AXI bus data transmission is the termination time point of the j-1th statistic or the termination time point of the j-1th statistic. At the first successful moment, the end time point of the j-th statistics of the bus transmission parameters when performing AXI bus data transmission is the earlier time point of the following two time points: the time when the statistical trigger signal is changed from valid to invalid, The sum of the amount of data transmitted by each Burst transmission at the jth count is greater than the preset data amount of the fixed byte.

Here, the first statistical mode may be referred to as a statistical mode specifying the number of clock cycles, and the second statistical mode may be referred to as a statistical mode specifying a data amount.

Illustratively, a process of statistical bus transmission parameters for AXI bus data transmission will be described below by way of a specific example.

Since the AXI protocol can mark each Burst transmission with an ID, by recording the change in the ID on the AXI bus, the delay of each Burst transmission and the total delay they spend can be calculated. Specifically, three register sets gbal_ID_reg, ID_reg, and ID_cnt are set, wherein the register set gbal_ID_reg is configured to record the ID of each Burst transmission in the entire statistical time, and the register set ID_reg is configured to record each Burst transmission in a time period in which the statistical trigger signal is valid. the ID, register set ID_cnt configured to record the sequence index Burst transmission of the same ID number reaches, here, if there is a plurality of the same ID number Burst transmissions, i ₂ the order in which the order of arrival is transmitted Burst index Recorded as i ₂ , i ₂ is a natural number.

4 is a schematic diagram of a process of statistical bus transmission parameters in a first embodiment of the SoC bus behavior detection method according to the present invention. As shown in FIG. 4, the ID numbers stored in the register group gbal_ID_reg are arranged according to a preset query order, and a preset query is performed. The order is the order of the arrows in Figure 4 (by Up to down);, the register group gbal_ID_reg is composed of multiple slots, each slot is configured to store an ID number, the register group ID_reg is composed of multiple slots, each slot is configured to store an ID number, and the register group ID_cnt is composed of multiple A slot consisting of each slot configured to store the value of an index. The register group ID_reg and the register group ID_cnt have a depth of 5. Figure 4 exemplarily describes the process of counting bus transmission parameters from time T0 to time T4, as follows:

At time T0, the statistical trigger signal is invalid, and the response of two Burst transmissions is not returned. That is, the Burst transmission response with ID 0 in the register group gbal_ID_reg in Figure 4 is not returned; here, the slot with the ID X in the register group gbal_ID_reg is Invalid slot, the invalid slot corresponds to the first line and the third line at time T0 in FIG. At time T0, the ID order of the Burst transmission without returning the response is not recorded, only the ID of the Burst transmission without returning the response is recorded; when the response of any one of the Burst transmissions is returned, the RID/BID of the corresponding Burst transmission of the return response is The ID in the register group gbal_ID_reg is compared; when the RID/BID of the corresponding Burst transmission of the corresponding response matches the ID in the register group gbal_ID_reg, the corresponding slot is invalid until all the slots in the register group gbal_ID_reg are invalid.

At time T1, the statistical trigger signal becomes invalid, and the new Burst transmission is valid. For the new Burst transmission, in the register group ID_reg and the register group ID_cnt, a valid slot is searched, and the first trigger condition or the first condition that satisfies the preset is searched. The slot corresponding to the Burst transmission of the two trigger conditions marks the slot as "matched", and the slot labeled "matched" corresponds to the second row of the T1 time table. At time T1, the slot corresponding to the Burst transmission that does not satisfy the preset first trigger condition and does not satisfy the preset second trigger condition is marked as “unmatched”. Here, for a "mismatch" slot, there is no need to grab the corresponding bus transfer data.

For Burst transmissions labeled "matched", the number of clock cycles is counted from the moment the new Burst transmission is effectively started.

It should be noted that, at time T1, when the response of the Burst transmission with ID number 0 is returned, it needs to be in the register group ID_reg and the register group ID_cnt before the valid trigger signal is valid. The slot corresponding to the Burst transmission with the ID of 0 in the register group gbal_ID_reg is invalid to avoid the influence of the Burst transmission on the statistics before the statistical trigger signal is valid. Here, the invalid slot corresponds to the third line of the T1 time table in FIG.

At time T2, when the response of the Burst transmission with ID number 0 returns, in the register group ID_reg and the register group ID_cnt, the slot corresponding to the Burst transmission with the ID of 0 in the register group gbal_ID_reg before the statistical trigger signal is valid is invalid. Avoid the statistical impact of the Burst transmission before the statistical trigger signal is valid. As can be seen from Figure 4, at this time, all Burst transmissions have been transmitted before the statistical trigger signal is valid.

At time T3, the new Burst transmission is valid. For the new Burst transmission, in the register group ID_reg and the register group ID_cnt, find a valid slot, and search for a Burst transmission corresponding to the preset first trigger condition or the second trigger condition. The slot, at time T3, marks the slot corresponding to the Burst transmission that does not satisfy the preset first trigger condition and does not satisfy the preset second trigger condition as "no match". Here, for the "mismatch" slot, it is not necessary to grab the corresponding Burst transmission data; here, the "mismatch" slot corresponds to the first row of the T3 time table in FIG.

At time T4, the response of the Burst transmission with ID 0 is returned. Since the Burst transmission before the statistical trigger signal is valid has been transmitted, at this time, in the register group ID_reg and the register group ID_cnt, the search ID is 0 and the index value is 1. The slot invalidates the slot, and the slot corresponds to the second row of the T4 time table in FIG. 4, stops counting the number of clock cycles, and obtains the time taken to complete the corresponding Burst transmission. At time T4, a new Burst transmission occurs, the Burst transmission satisfies a preset first trigger condition or a second trigger condition, and the slot corresponding to the Burst transmission is marked as "matched", and the clock is re-clocked for the new Burst transmission. The count of the number of cycles, where the slot labeled "matched" corresponds to the third row of the table at time T4 in FIG.

Further, the AXI bus can connect multiple master devices and multiple slave devices; when one master device reads data of one slave device through the AXI bus, or when one master device writes data to a slave device through the AXI bus, According to the address of any pre-configured master device, To calculate the average delay and the average bandwidth occupied by the master device when reading and writing data; similarly, it can count the data read/written data from the device according to the address of any slave device configured in advance. The average delay and the average bandwidth occupied; further, the average delay and the occupied time when the corresponding master device reads and writes the data of the corresponding slave device according to the address of any one of the pre-configured master devices and any one of the slave devices Average bandwidth.

In an embodiment, a register may be set to store the statistical result, and the statistical result can only be stored once, and after the statistics window (the duration of the valid trigger signal is valid), the statistical result is read by sending an interrupt request. Once the statistics window is finished, it will automatically enter the next statistical window until the statistics function is turned off, thus achieving multiple statistics of the transmission parameters during AXI data transmission.

It can be seen that when the bus transmission parameters are counted multiple times during the AXI bus data transmission, the continuous statistics of the bus transmission parameters in the duration of the statistical trigger signal can be realized, so that the waveform of the bus transmission parameters with time can be drawn. Figure, which helps to grasp the bus behavior more accurately.

FIG. 5 is a timing diagram of continuous statistics in the first embodiment of the SoC bus behavior detecting method according to the present invention. As shown in FIG. 5, the window represents the duration of the valid trigger signal, the ACLK represents the global clock signal, and the START represents the statistical trigger signal. When START is high, it indicates that the statistical trigger signal is valid. When START is low, it indicates that the statistical trigger signal is invalid; perf indicates the statistical result acquisition timing, and P1 to Pk respectively indicate the k obtained during the duration of the valid statistical trigger signal. Statistics result, k is greater than 1; end_flag is a high level signal or a low level signal. When end_flag is a low level signal, it indicates that a certain statistic is being performed. When end_flag becomes high level and end_flag is pulled up, it indicates A certain statistic is terminated.

Further, if the SoC bus signal further includes the ACE bus signal in step 100, in this step, the ACE bus channel data needs to be captured based on the received ACE bus signal.

Specifically, the capturing the ACE bus channel data includes: receiving the second data capture signal; When the second data capture signal is valid, the data of each channel of the received ACE bus is captured, and when the second data capture signal is invalid, the data acquisition process of each channel of the received ACE bus is stopped. Here, the validity of the second data capture signal may be preset, for example, the second data capture signal is a high level signal or a low level signal, and when the second data capture signal is a high level signal, indicating The second data capture signal is valid; otherwise, when the second data capture signal is a low level signal, it indicates that the second data capture signal is invalid.

In this step, the data of the ACE bus channel is captured: when the signal transmitted by the AC channel of the ACE bus signal satisfies the preset third trigger condition, the data of the ACE bus channel is captured; the signal transmitted by the AC channel of the ACE bus signal is not When the preset third trigger condition is met, the ACE bus channel data is not captured.

Here, the preset third trigger condition may be set according to at least one of the following elements: an ACADDR signal transmitted by the AC channel, and an ACSNOOP signal transmitted by the AC channel.

In this step, the captured ACE bus channel data is the data of each channel in which the enable signal of the ACE bus signal is valid. Here, the validity of the enable signal corresponding to each channel signal in the ACE bus signal can be set in advance.

In this way, by reasonably setting the third trigger condition and the validity of the enable signal, the ACE bus channel data can be flexibly captured, and the data amount of the captured ACE bus channel data can be reduced.

Illustratively, the process of capturing ACE bus channel data is described below by way of a specific example.

The ACE bus protocol does not support the use of ID to mark each Burst transmission. In the first embodiment of the present invention, the register sets cnt, cnt_cd, max_cnt, max_cnt_cd are set, wherein the register set cnt is configured to record the sequence of AC channel transmission, the register group cnt Including a plurality of slots, each slot is configured to store an index value indicating the sequence of transmission of the AC channel. When the signals transmitted by multiple AC channels arrive one after another, the smaller the index value indicates the corresponding AC channel transmission. The signal arrives first; the register group cnt_cd is configured to record the sequence of CD channel transmissions, The register group cnt includes a plurality of slots, and each slot is configured to store an index value indicating a sequence of transmission of the CD channel. When the signals transmitted by the plurality of CD channels arrive one after another, the smaller the index value, the corresponding The signal transmitted by the CD channel arrives first. Usually, the register group cnt and the register group cnt_cd store index values greater than or equal to one.

6 is a schematic diagram of a process of capturing ACE bus channel data in a first embodiment of a SoC bus behavior detection method according to the present invention. As shown in FIG. 6, the register group max_cnt includes at least one slot, and each slot is configured to record second data. The index value of the sequence of the AC channel transmission corresponding to a Burst transmission that is not transmitted before the capture signal is valid; the register group max_cnt_cd includes at least one slot, and each slot is configured to record that the second data capture signal is not transmitted before being valid. A Burst transmits the index value of the sequence of the corresponding CD channel transmission.

FIG. 6 exemplarily describes the process of capturing the ACE bus channel data from time T0 to time T4, which is specifically described as follows:

At time T0, the second data capture signal is invalid, and the CRRESP signal or the CDLAST signal is valid. At this time, until the index value of each slot record in the register group max_cnt and the register group max_cnt_cd is continuously decremented by 1 until the register group max_cnt and The index value of each slot record in the register group max_cnt_cd becomes 0, and all Burst transmissions are completed before the second data capture signal is valid.

At time T1, the second data capture signal is valid. If the ACE bus signal satisfies the preset third trigger condition, the corresponding slot in the register set cnt/register set cnt_cd is marked as "matched", here, labeled " The matched slot corresponds to the second row and the fourth row of the T1 time table in FIG. 6. At this time, the signal transmitted by the AC channel corresponding to the slot labeled "matched" is sent to the FIFO, and the signal transmitted by the AC channel is transmitted. At least one of the following is included: ACVALID signal, ACREADY signal, ACADDR signal, ACSNOP signal, ACPORT signal.

At time T1, if the data transmitted by the data channel/CD channel transmitted by the AC channel does not satisfy the preset third trigger condition, the corresponding slot in the register group cnt/register group cnt_cd is marked as "no". Matching, here, the slot labeled "mismatch" corresponds to the first row, the third row, and the fifth row of the T1 time table in FIG.

At time T2, the CDLAST signal is valid. At this time, the slot with the index value of 1 in the register group cnt_cd is invalid, and the remaining index values recorded in the register group cnt_cd are all decremented by 1. Here, the invalid slot is indexed in FIG. The value X indicates; at time T2, the ACE bus signal satisfies the preset third trigger condition, and the corresponding slot in the register group cnt/register group cnt_cd is marked as "matched", and at this time, it will be marked as "matched". The signal transmitted by the CD channel corresponding to the slot is sent to the FIFO, and the signal transmitted by the CD channel includes at least one of the following: a CDVALID signal, a CDREADY signal, a CDDATA signal, and a CDLAST signal.

At time T3, the CRRESP signal is valid. At this time, the slot with the index value of 1 in the register group cnt is invalid, and the remaining index values recorded in the register group cnt are all decremented by 1. Here, the invalid slot is indexed in FIG. The value X indicates; at time T3, the ACE bus signal satisfies the preset third trigger condition, and the corresponding slot in the register set cnt/register group cnt_cd is marked as "matched", and at this time, it will be marked as "matched". The signal transmitted by the CR channel corresponding to the slot is sent to the FIFO, and the signal transmitted by the CR channel includes at least one of the following: a CRVALID signal, a CRREADY signal, and a CRRESP signal.

At time T4, the CRRESP signal and the CDLAST signal are valid, the slot with the index value of 1 in the register group cnt is invalid, the slot with the index value of 1 in the register group cnt_cd is invalid, and the rest of the register group cnt_cd and the register group cnt are recorded. The index value is all decremented by one; when the ACE bus signal does not satisfy the preset third trigger condition at time T4, the corresponding slot in the register group cnt/register group cnt_cd is marked as “no match”, and at this time, the grab will not be grabbed. ACE bus channel data.

In actual application, it is also possible to monitor the occurrence of a deadlock. When a deadlock occurs, the ID and address at which the deadlock occurs are captured, and it can be inferred from which master device the deadlock is caused. It is also possible to monitor the access exception address, issue an interrupt when an access exception occurs, and grab the address at which the exception occurred. And ID, from which it can be inferred which host device is caused by the exception.

The first embodiment of the SoC bus behavior detecting method of the present invention can first capture the AXI bus data, and can obtain more accurate information than the existing technical solution that can only capture the AXI bus address and commands. Bus behavior; secondly, the ACE bus signal can be captured, which can be applied to more application scenarios; finally, the statistics of related parameters of the AXI bus transmission can be completed; thus, the first embodiment of the SoC bus behavior detection method of the present invention can Support a variety of functions to meet the diverse needs of SoC bus debugging.

Second embodiment

In order to further illustrate the object of the present invention, further exemplification will be made on the basis of the first embodiment of the present invention.

FIG. 7 is a schematic diagram of an application scenario of a second embodiment of a SoC bus behavior detection method according to the present invention. As shown in FIG. 7, the processor 700 represents a master device, and the processor 700 and the slave device 701 pass the AXI bus/ACE bus. Data transmission is performed; the detector 702 is configured to detect the behavior of bus data transmission between the processor and the slave device using the embodiment of the present invention, and the DDR memory 703 is configured to store the bus behavior detection result obtained by the detector. The detector 702 is configured to monitor the AXI bus/ACE bus by connecting the AXI bus/ACE bus from the interface; the detector 702 is connected to the DDR memory 703 through the main interface, and the monitoring of the AXI bus/ACE bus by the detector 702 is non-intrusive monitoring. Therefore, it does not interfere with bus data transfer between the processor and the slave device.

Specifically, for the above application scenario, the flow of statistics of bus data capture and bus transmission parameters is separately described.

FIG. 8 is a flowchart of bus data capture in a second embodiment of the SoC bus behavior detection method according to the present invention. As shown in FIG. 8, the process includes:

Step 800: Pre-configure the parameters of the bus data capture; configure the first data capture signal/second data capture signal to be valid, and skip to step 801.

Specifically, the parameters for pre-configuring the bus data capture include: setting a trigger condition, configuring the validity of the enable signal of each channel of the AXI bus/ACE bus, setting the timestamp capture function of the AXI bus/ACE bus signal, and configuring the AXI bus. Each channel of the /ACE bus stores space in the DDR memory, and the AXI bus/ACE bus is configured to store 1G in each DDR memory;

Further, pre-configuring various parameters of the SoC bus behavior detection includes: configuring an interrupt mask for at least one channel of the AXI bus/ACE bus, configuring an interrupt clearing and capturing an interrupt signal at the end of the data, and capturing an interrupt at the end of the data The signal is marked as drain_out. When drain_out is pulled high, it indicates that the interrupt signal at the end of the grab data is issued.

When a channel is configured with interrupt mask, the interrupt signal from the corresponding channel is ignored.

Step 801: Determine whether at least one channel of the AXI bus/ACE bus issues an interrupt signal, and if yes, skip to step 802; otherwise, skip to step 804.

Step 802: It is judged whether the channel that issues the interrupt signal is configured with an interrupt mask, and if yes, returns to step 801; if not, then to step 803.

Step 803: Read data corresponding to the channel that issues the interrupt signal in the DDR. After the data is read, the interrupt is cleared, and the process returns to step 801.

In this step, the reading of the data corresponding to the channel for issuing the interrupt signal in the DDR includes: querying the interrupt number, determining which channel the interrupt signal comes from according to the interrupt number, and then notifying the CPU to configure the corresponding DMA read mode, corresponding to The channel data is read from the DDR and the read data is stored in an external memory such as a USB.

Step 804: Determine whether to end the bus data capture. If the bus data capture is not finished, return to step 801; if the bus data capture is ended, configure the first data capture signal/second data capture signal to be invalid, skipping Go to step 805.

Here, the timing of ending the bus data capture can be determined by the user himself.

Step 805: The detector empties the residual data inside the detector, and sends out the data at the end of the grabbing. The interrupt signal reads out the data corresponding to each channel in which no interrupt mask is set in the DDR. When the data is read, the interrupt is cleared and the flow is terminated.

Specifically, the reading of the data corresponding to each channel in the DDR that is not provided with the interrupt mask includes: notifying the CPU to configure the corresponding DMA read mode based on each channel without the interrupt mask being set, and the data of the corresponding channel is from the DDR. Read out and store the read data into external memory.

It should be noted that if the interrupt mask is set for each channel of the AXI bus/ACE bus, the process ends directly after the detector empties the residual data inside itself.

FIG. 9 is a flowchart of statistics of bus transmission parameters in a second embodiment of the SoC bus behavior detecting method according to the present invention. As shown in FIG. 9, the process includes:

Step 900: Pre-configure the statistical parameters of the bus transmission parameters; configure the statistical trigger signal to be valid, and skip to step 901.

Specifically, the statistic parameter for configuring the bus transmission parameter includes: configuring an address of the at least one master device, configured to calculate an average delay of the corresponding master device in the data transmission of the bus and an average bandwidth occupied by the master device; and configuring an address of the at least one slave device, For counting the average delay of the corresponding slave device during bus data transmission and the average bandwidth occupied; pre-configuring the address of at least one master device and the address of at least one slave device for counting the correspondence between the master device and the corresponding slave device The average delay of bus data transmission and the average bandwidth occupied; configuration statistics mode.

The configuration of the statistical parameters of the bus transmission parameter may further include: configuring an interrupt mask for the statistical result of at least one channel, configuring an interrupt signal for interrupt clearing and counting at the end of the statistics.

Step 901: Determine whether the read request interrupt sent by the CPU is received. If yes, go to step 902. Otherwise, go to step 904.

Step 902: Determine whether an interrupt mask is set according to the type of the statistical result to be read, and if yes, return to step 901; if no, skip to step 903.

Step 903: Read the statistical result. After the data is read, clear the interrupt and return to the step. 901.

Step 904: Determine whether to end the statistical process. If the statistical process is not ended, return to step 901; if the statistical process is ended, the configuration statistical trigger signal is invalid, and the process proceeds to step 905.

Here, the timing of ending the statistical process can be determined by the user himself.

Step 905: Send an interrupt signal at the end of the statistics, read the statistical result, clear the interrupt, and end the process. At this time, the statistical result can be analyzed.

It should be noted that if the statistics of the acquired channels of the AXI bus are all set to interrupt masking, after step 904, the process is directly ended.

Third embodiment

For the method of the embodiment of the present invention, the embodiment of the present invention further provides an SoC bus behavior detecting apparatus.

FIG. 10 is a first schematic structural diagram of a SoC bus behavior detecting apparatus according to an embodiment of the present invention. As shown in FIG. 10, the apparatus includes: a receiving module 1000 and a detecting module 1001;

The receiving module 1000 is configured to receive a SoC bus signal, where the SoC bus signal includes an AXI bus signal.

The detecting module 1001 is configured to perform at least one of the following operations based on the received AXI bus signal: grab the AXI bus channel data, and perform at least one statistics on the bus transmission parameters when performing the AXI bus data transmission; the captured AXI bus channel data includes At least one of the following data: the data transmitted by the AXI bus write data channel, the data transmitted by the AXI bus read data channel; the bus transmission parameters of each statistics include: the average delay of the bus transmission in the corresponding statistical time or The average bandwidth occupied.

Specifically, the detecting module 1001 is configured to: when the signal transmitted by the AW channel in the AXI bus signal satisfies a preset first trigger condition, or when the signal transmitted by the AR channel in the AXI bus signal satisfies a preset second trigger condition, Grab the AXI bus channel data.

Here, the captured AXI bus channel data is valid for the enable signal in the AXI bus signal. Data for each channel.

Further, the detecting module 1001 further includes a register configured to store a statistical result of the bus transmission parameter, and the statistical result can only be stored once, and the statistical window (the duration of the valid period of the statistical trigger signal) ends, and the interrupt is sent. Request to read the statistical results, once the statistics window ends, automatically enter the next statistical window, until the statistics function is turned off, thereby achieving multiple statistics of the transmission parameters when transmitting AXI data.

Further, the receiving module 1000 is further configured to receive an ACE bus signal.

After receiving the SoC bus signal, the detection module 1001 is further configured to capture ACE bus channel data based on the received ACE bus signal.

Specifically, the detecting module 1001 is configured to capture the ACE bus channel data when the signal transmitted by the AC channel of the ACE bus signal satisfies a preset third trigger condition.

Here, the captured ACE bus channel data is the data of each channel in which the enable signal is valid in the ACE bus signal.

In actual application, the detecting module 1001 may be further configured to monitor the occurrence of a deadlock. When a deadlock occurs, the ID and address when the deadlock occurs are captured, and it can be inferred from which host device the deadlock is caused. of. The detection module 1001 can also monitor the access exception address, issue an interrupt when an access exception occurs, and grab the address and ID when the exception occurs, from which it can be inferred from which master device the exception was caused.

In a practical application, the receiving module 1000 and the detecting module 1001 can be configured by a central processing unit (CPU), a microprocessor (Micro Processor Unit (MPU), and a digital signal processor (Digital Signal) located in the terminal device. Processor, DSP), or Field Programmable Gate Array (FPGA) implementation.

Fourth embodiment

In order to further embodies the object of the present invention, the present embodiment will be further described based on the third embodiment of the present invention.

FIG. 11 is a second schematic structural diagram of a SoC bus behavior detecting apparatus according to an embodiment of the present invention. As shown in FIG. 11, the apparatus includes: a first timing adjusting unit 1100, a second timing adjusting unit 1101, an AXI bus detecting unit 1102, and an ACE. a bus detecting unit 1103, a statistic unit 1104, a configuration unit 1105, a first clearing unit 1106, a second clearing unit 1107, a data transfer unit 1108, and a third timing adjustment unit 1109;

The configuration unit 1105 is configured to configure a parameter of the bus data capture and a statistical parameter of the bus transmission parameter, and send the parameter of the configured bus data capture to the AXI bus detection unit 1102/ACE bus detection unit 1103, and configure the completed bus. The statistical parameters of the transmission parameters are sent to the statistics unit 1104. Here, the process of configuring the parameters of the bus data capture and the statistical parameters of the bus transmission parameters has been described in detail in the second embodiment of the present invention, and details are not described herein again.

Further, the configuration unit 1105 can receive configuration information from the external device and configure related parameters based on the received configuration information; the configuration unit 1105 interacts with the external device through an APB (Advanced High Performance Bus) interface.

The first timing adjustment unit 1100 is configured to receive signals of each channel of the AXI bus, perform timing adjustment on the signals of the received channels, and send signals of each channel of the timing adjustment to the AXI bus detection unit, the first clearing unit, and the first The second clearing unit and the statistical unit; here, the first timing adjusting unit 1100 can be implemented by using a basic logical unit slice; in FIG. 1, AW, AR, W, R, and B respectively represent the AXI bus AW channel, the AR channel, the W channel, and the R. Channel and B channel.

The second timing adjustment unit 1101 is configured to receive signals of each channel of the ACE bus, perform timing adjustment on the received signals of the respective channels, and send signals of each channel of the timing adjustment to the ACE bus detection unit, the first clearing unit, and the statistics respectively. Here, the second timing adjustment unit 1100 can be implemented by using a basic logical unit slice; in FIG. 1, AC, CR, and CD represent an AXI bus AC channel, a CR channel, and a CD channel, respectively.

The first clearing unit 1106 is configured to monitor AXI bus behavior and ACE bus behavior in real time. Receiving the first data capture signal and the second data capture signal, when the first data capture signal is valid, clearing data received by the AXI bus detection unit before the first data capture signal is valid; and capturing the second data in the second data capture When the signal is valid, the data received by the ACE bus detecting unit is cleared before the second data grabbing signal is valid; thus, the bus data received before the corresponding data grabbing signal is valid can be prevented from affecting the bus data grabbing.

The second clearing unit 1107 is configured to monitor the behavior of the AXI bus in real time, and receive the statistical trigger signal. When the statistical trigger signal is valid, the data received by the statistical unit before the statistical trigger signal is valid is cleared; thus, the statistical trigger signal can be prevented from being valid before the statistics are valid. The data received by the unit affects the statistical process of subsequent bus transmission parameters.

The AXI bus detecting unit 1102 is configured to: when the first data capture signal is valid, capture data of each channel of the received AXI bus, and send data of each channel that is captured to the data transmission unit. Here, the process of capturing data of each channel of the AXI bus has been described in the first embodiment of the present invention, and will not be repeated here.

The ACE bus detecting unit 1103 is configured to: when the second data capture signal is valid, capture data of each channel of the received ACE bus, and send data of each channel captured to the data transmission unit. Here, the process of capturing data of each channel of the ACE bus has been explained in the first embodiment of the present invention, and will not be repeated here.

The statistic unit 1104 is configured to perform at least one statistics on the bus transmission parameters of the AXI bus data transmission when the statistical trigger signal is valid, and send the obtained statistical result to the outside through the configuration unit. Here, the statistical process of the bus transmission parameters has been explained in the first embodiment of the present invention and will not be repeated here.

The data transmission unit 1108 is configured to perform packet processing on the received data, and send the packed data to the third timing adjustment unit.

Specifically, the data transmission unit 1108 includes a first input first output (FIFO) subunit and a data processing subunit; wherein the FIFO subunit is configured to receive from AXI The data of the bus detecting unit 1102 and the ACE bus detecting unit 1103, when the data of the received at least one channel reaches the corresponding channel threshold, initiates a write operation, and sends data reaching the channel threshold to the data processing subunit; exemplarily, when When the FIFO depth is 16, the channel threshold of the AW channel, the AR channel, and the AC channel is 4, and the thresholds of the W channel, the R channel, the B channel, the CD channel, and the CR channel are 8. Here, if the data of the plurality of channels reaches the corresponding channel threshold at the same time in the FIFO subunit, the data of the corresponding multiple channels is sent to the data processing subunit by using a preset polling order polling.

The data processing sub-unit is configured to assemble and receive the received data according to the agreed data structure. Here, in order to reduce the development difficulty and the verification complexity, the data width of the output data of the SoC bus behavior detecting device is specified to be 64 bits, so that the data width of the data outputted by the data processing subunit needs to be a constant value. That is, the data processing sub-unit combines the received data into fixed-length data and outputs it to the outside; in particular, when the data capture process of each channel of the AXI bus ends, if at least one of the FIFO sub-units The data does not reach the corresponding channel threshold. At this time, redundant data is added to the data of the corresponding channel to reach the corresponding channel threshold, which is beneficial to the data processing process of the data processing subunit.

In order to efficiently transfer data, two state machines are set in the data processing sub-unit occupation, one is an address state machine, configured to generate and split addresses (for example, when transmitting across 4K, a complete data structure needs to be played. The other is the address state machine, configured for data merging and splitting. Illustratively, when the data width of the AXI bus channel data is 32 bits, the data processing subunit needs to merge the two AXI bus channel data. Outward output; when the data width of the channel data of the AXI bus is 32 bits, the data processing subunit splits the channel data of one AXI bus into two sets of data and outputs it outward; thus, the data processing subunit merges through the data. Splitting can greatly improve the efficiency of data transmission.

The third timing adjustment unit 1109 is configured to perform timing adjustment on the received data, and send the time-aligned data to an external storage unit; here, the third timing adjustment unit 1109 It can be implemented in the basic logical unit slice.

Further, in order to solve the problem that the amount of data captured is large and the external storage unit cannot be accessed, a limited address space is set for each channel of data in the external storage unit, and the address space granularity is 1K. The write operation is performed on the block address space. When the data amount of the data of one channel captured reaches half of the address space of the corresponding channel, an interrupt is issued, and the CPU is notified to read the data of the corresponding channel that is captured.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on the computer or other programmable device to produce the computer The implemented processing, such as instructions executed on a computer or other programmable device, provides steps for implementing the functions specified in one or more blocks of the flowchart or in a block or blocks of the flowchart.

Based on this, an embodiment of the present invention further provides a computer storage medium, the computer storage medium comprising a set of instructions, when executed, causing at least one processor to execute the SoC bus behavior detection method.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

detailed description

The solution provided by the embodiment of the present invention receives a SoC bus signal, where the SoC bus signal includes an AXI bus signal; and performs at least one of the following operations based on the received AXI bus signal: grabbing AXI bus channel data, and performing AXI bus data transmission The bus transmission parameters are analyzed at least once; the captured AXI bus channel data includes at least one of the following: data transmitted by the AXI bus write data channel, data transmitted by the AXI bus read data channel; The transmission parameters include: the average delay of the bus transmission in the corresponding statistical time or the average bandwidth occupied. In this way, the AXI bus data can be captured, and the parameters of the AXI bus data can be counted, thereby meeting the diversified needs of the SoC bus debugging.

Claims

A method for detecting a SoC bus behavior of a system on a chip, the method comprising:

Receiving a SoC bus signal, the SoC bus signal including a SoC advanced scalable interface AXI bus signal;

Perform at least one of the following operations based on the received AXI bus signal: grab the AXI bus channel data, and perform at least one statistics on the bus transmission parameters when performing AXI bus data transmission; the captured AXI bus channel data includes at least one of the following data: The data transmitted by the AXI bus write data channel and the data transmitted by the AXI bus read data channel; the bus transmission parameters of each statistics include: an average delay of the bus transmission or an average bandwidth occupied by the corresponding statistical time.
The method of claim 1, wherein the capturing the AXI bus channel data comprises: the signal transmitted by the AW channel in the AXI bus signal satisfies a preset first trigger condition, or the AR channel transmission in the AXI bus signal When the signal meets the preset second trigger condition, the AXI bus channel data is captured.
The method according to claim 1 or 2, wherein the captured AXI bus channel data is data of each channel in which the enable signal is valid in the AXI bus signal.
The method of claim 1 wherein the method further comprises: setting a register configured to store a statistical result of a bus transmission parameter;

After the statistics window is finished, the stored statistical result is read by sending an interrupt request. Once the statistics window is finished, the next statistical window is automatically entered until the statistics function is turned off, so as to implement multiple statistics of the transmission parameters during AXI data transmission.
The method according to claim 1 or 4, wherein the calculation formula of the average delay of each statistical bus transmission when performing AXI bus data transmission is:

T=total_delay/n

Where T represents the average delay of the bus transmission corresponding to one statistic, Total_delay represents the sum of the time spent by each Burst transmission in the corresponding statistical time, and n represents the corresponding statistical time. The number of Burst transmissions occurring within;

The calculation formula of the average bandwidth B occupied by each statistical bus transmission when performing AXI bus data transmission is:

B=total_byte/total_cycle

Where B represents the average bandwidth occupied by the corresponding one-time bus transmission, total_byte represents the sum of the amount of data transmitted by each Burst transmission in the corresponding statistical time, and total_cycle represents the number of clock cycles experienced by the corresponding statistical time.
The method of claim 1, 2 or 4, wherein the method further comprises receiving timestamp information corresponding to the AXI bus signal.
The method of claim 1 wherein said SoC bus signal further comprises: an AXI coherent extended ACE bus signal;

After receiving the SoC bus signal, the method further includes: capturing the ACE bus channel data based on the received ACE bus signal.
The method of claim 7, wherein the fetching the ACE bus channel data comprises: grabbing the ACE bus channel data when the signal transmitted by the ACE bus signal AC channel satisfies a preset third trigger condition.
The method according to claim 7 or 8, wherein the captured ACE bus channel data is data of each channel in which the enable signal is valid in the ACE bus signal.
The method of claim 7 or 8, wherein the method further comprises: capturing timestamp information corresponding to the ACE bus signal.
The method of claim 1 further comprising:

Monitor the occurrence of a deadlock, and when the deadlock occurs, grab the ID and address when the deadlock occurs;

And/or, monitor access to the exception address, issue an interrupt when an access exception occurs, and grab the address and ID when the exception occurred.
A SoC bus behavior detecting device, the device comprising: a receiving module and a detecting module; wherein

a receiving module configured to receive a SoC bus signal, where the SoC bus signal includes an AXI bus signal;

The detecting module is configured to perform at least one of the following operations based on the received AXI bus signal: grab the AXI bus channel data, and perform at least one statistics on the bus transmission parameters when performing the AXI bus data transmission; the captured AXI bus channel data includes at least one The following data: the data transmitted by the AXI bus write data channel, the data transmitted by the AXI bus read data channel; the bus transmission parameters of each statistics include: the average delay of the bus transmission in the corresponding statistical time or possession Average bandwidth.
The method according to claim 12, wherein the detecting module is configured to: the signal transmitted by the AW channel in the AXI bus signal satisfies a preset first trigger condition, or the signal transmitted by the AR channel in the AXI bus signal satisfies a preset When the second trigger condition is met, the AXI bus channel data is captured.
The method according to claim 12 or 13, wherein the captured AXI bus channel data is data of each channel in which the enable signal is valid in the AXI bus signal.
The apparatus of claim 11 wherein said detection module further comprises a register configured to store a statistical result of a bus transmission parameter;

After the statistics window is finished, the stored statistical result is read by sending an interrupt request. Once the statistics window is finished, the next statistical window is automatically entered until the statistics function is turned off, so as to implement multiple statistics of the transmission parameters during AXI data transmission.
The apparatus of claim 11, wherein the receiving module is further configured to receive an ACE bus signal;

The detection module is further configured to capture ACE bus channel data based on the received ACE bus signal after receiving the SoC bus signal.
The apparatus according to claim 16, wherein the detecting module is configured to capture an ACE when a signal transmitted by the AC channel of the ACE bus signal satisfies a preset third trigger condition Bus channel data.
The apparatus according to claim 16 or 17, wherein the captured ACE bus channel data is data of respective channels in which an enable signal is valid in the ACE bus signal.
The apparatus according to claim 12, wherein the detecting module is further configured to:

Monitor the occurrence of a deadlock, and when the deadlock occurs, grab the ID and address when the deadlock occurs;

And/or, monitor access to the exception address, issue an interrupt when an access exception occurs, and grab the address and ID when the exception occurred.
A computer storage medium comprising a set of instructions that, when executed, cause at least one processor to perform the SoC bus behavior detection method of any one of claims 1 to 11.