WO2017080793A3 - Verfahren zum betrieb eines mehrkernprozessors - Google Patents

Verfahren zum betrieb eines mehrkernprozessors Download PDF

Info

Publication number
WO2017080793A3
WO2017080793A3 PCT/EP2016/075381 EP2016075381W WO2017080793A3 WO 2017080793 A3 WO2017080793 A3 WO 2017080793A3 EP 2016075381 W EP2016075381 W EP 2016075381W WO 2017080793 A3 WO2017080793 A3 WO 2017080793A3
Authority
WO
WIPO (PCT)
Prior art keywords
processor cores
error detection
computing
lane
computing operations
Prior art date
Application number
PCT/EP2016/075381
Other languages
English (en)
French (fr)
Other versions
WO2017080793A2 (de
Inventor
Michael Armbruster
Martin Bischoff
Christian Buckl
Ludger Fiege
Andreas Zirkler
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Priority to US15/773,774 priority Critical patent/US20180322001A1/en
Priority to KR1020187016720A priority patent/KR20180072829A/ko
Priority to CN201680066047.5A priority patent/CN108351815A/zh
Priority to EP16790913.4A priority patent/EP3338189A2/de
Priority to JP2018524403A priority patent/JP2019500682A/ja
Publication of WO2017080793A2 publication Critical patent/WO2017080793A2/de
Publication of WO2017080793A3 publication Critical patent/WO2017080793A3/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1497—Details of time redundant execution on a single processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0736—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function
    • G06F11/0739—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function in a data processing system embedded in automotive or aircraft systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2035—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant without idle spare hardware

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)

Abstract

Erfindungsgemäß werden mindestens zwei Prozessorkerne eines Mehrkernprozessors dazu genutzt, eine sicherheitskritische Applikation zweikanalig zu berechnen. Dabei werden die Rechenoperationen nicht in jedem Rechenzyklus auf beiden Prozessorkernen redundant berechnet, sondern beide Prozessorkerne werden in verschiedenen Arbeitszyklen mit verschiedenen Applikationen ausgelastet. Somit wird eine Verdoppelung der benötigten Rechenkapazität in vorteilhafter Weise vermieden. Um eine gegenseitige Überwachung der Prozessorkerne zu erreichen, werden die Rechenoperationen abwechselnd auf beiden Prozessorkernen zur berechnet. Durch die beschriebenen Fehlererkennungsmechanismen können zufällige Fehler erkannt werden. Zwar liegt die Güte der erfindungsgemäßen Fehlererkennung etwas unter dem bei einem aus dem Stand der Technik bekannten »Dual-Lane-Betrieb« mit einer parallel-redundanten mehrkanaligen Berechnung. Die Güte der Fehlererkennung kann allerdings gegenüber dem Erfordernis eines geringeren Aufwands an Rechenleistung hintanstehen, insbesondere wenn für das Steuersystem eine wirtschaftliche Verwirklichung gefordert ist. Die Erfindung vereinigt somit Anforderungen an eine hinreichend sichere Fehlererkennung mit einer ökonomischen Auslegung der Rechenleistung.
PCT/EP2016/075381 2015-11-12 2016-10-21 Verfahren zum betrieb eines mehrkernprozessors WO2017080793A2 (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US15/773,774 US20180322001A1 (en) 2015-11-12 2016-10-21 Methods for operating multicore processors
KR1020187016720A KR20180072829A (ko) 2015-11-12 2016-10-21 멀티코어 프로세서를 동작시키기 위한 방법
CN201680066047.5A CN108351815A (zh) 2015-11-12 2016-10-21 用于运行多核处理器的方法
EP16790913.4A EP3338189A2 (de) 2015-11-12 2016-10-21 Verfahren zum betrieb eines mehrkernprozessors
JP2018524403A JP2019500682A (ja) 2015-11-12 2016-10-21 マルチコアプロセッサの操作方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102015222321.3 2015-11-12
DE102015222321.3A DE102015222321A1 (de) 2015-11-12 2015-11-12 Verfahren zum Betrieb eines Mehrkernprozessors

Publications (2)

Publication Number Publication Date
WO2017080793A2 WO2017080793A2 (de) 2017-05-18
WO2017080793A3 true WO2017080793A3 (de) 2017-08-17

Family

ID=57233400

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2016/075381 WO2017080793A2 (de) 2015-11-12 2016-10-21 Verfahren zum betrieb eines mehrkernprozessors

Country Status (7)

Country Link
US (1) US20180322001A1 (de)
EP (1) EP3338189A2 (de)
JP (1) JP2019500682A (de)
KR (1) KR20180072829A (de)
CN (1) CN108351815A (de)
DE (1) DE102015222321A1 (de)
WO (1) WO2017080793A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7400222B2 (ja) 2019-06-14 2023-12-19 マツダ株式会社 外部環境認識装置
JP7419157B2 (ja) * 2020-05-13 2024-01-22 株式会社日立製作所 プログラム生成装置、並列演算デバイス、及び、並列演算デバイスに並列演算を実行させるためのコンピュータプログラム
KR102403767B1 (ko) 2020-11-25 2022-05-30 현대제철 주식회사 초고강도 냉연강판 및 그 제조방법
CN114201332A (zh) * 2022-02-21 2022-03-18 岚图汽车科技有限公司 一种冗余控制方法、装置、芯片及存储介质

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006056506A1 (de) * 2004-11-26 2006-06-01 Nokia Siemens Networks Gmbh & Co. Kg Verfahren zum nachweis der verfügbarkeit von systemkomponenten eines redundanten kommunikationssystems
EP2055607A2 (de) * 2007-10-29 2009-05-06 GM Global Technology Operations, Inc. Verfahren und Vorrichtung zur Überwachung des Netzbremsbetriebs in einem hybriden Antriebsstrang-System
WO2013100604A1 (en) * 2011-12-29 2013-07-04 Korea Electronics Technology Institute Ecu monitoring system and monitoring method
US20130204493A1 (en) * 2011-11-16 2013-08-08 Flextronics Ap, Llc Duplicated processing in vehicles
US9015536B1 (en) * 2011-08-31 2015-04-21 Amazon Technologies, Inc. Integration based anomaly detection service

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008148625A1 (en) * 2007-06-05 2008-12-11 Siemens Aktiengesellschaft Method and device for scheduling a predictable operation of an algorithm on a multi-core processor
JP4709268B2 (ja) * 2008-11-28 2011-06-22 日立オートモティブシステムズ株式会社 車両制御用マルチコアシステムまたは内燃機関の制御装置
US20150212570A1 (en) * 2012-09-03 2015-07-30 Hitachi, Ltd. Computer system and control method for computer system
JP6069104B2 (ja) * 2013-05-31 2017-01-25 富士重工業株式会社 制御装置および制御装置の異常検出方法
JP6324127B2 (ja) * 2014-03-14 2018-05-16 三菱電機株式会社 情報処理装置、情報処理方法及びプログラム

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006056506A1 (de) * 2004-11-26 2006-06-01 Nokia Siemens Networks Gmbh & Co. Kg Verfahren zum nachweis der verfügbarkeit von systemkomponenten eines redundanten kommunikationssystems
EP2055607A2 (de) * 2007-10-29 2009-05-06 GM Global Technology Operations, Inc. Verfahren und Vorrichtung zur Überwachung des Netzbremsbetriebs in einem hybriden Antriebsstrang-System
US9015536B1 (en) * 2011-08-31 2015-04-21 Amazon Technologies, Inc. Integration based anomaly detection service
US20130204493A1 (en) * 2011-11-16 2013-08-08 Flextronics Ap, Llc Duplicated processing in vehicles
WO2013100604A1 (en) * 2011-12-29 2013-07-04 Korea Electronics Technology Institute Ecu monitoring system and monitoring method

Also Published As

Publication number Publication date
JP2019500682A (ja) 2019-01-10
US20180322001A1 (en) 2018-11-08
CN108351815A (zh) 2018-07-31
KR20180072829A (ko) 2018-06-29
EP3338189A2 (de) 2018-06-27
WO2017080793A2 (de) 2017-05-18
DE102015222321A1 (de) 2017-05-18

Similar Documents

Publication Publication Date Title
WO2017080793A3 (de) Verfahren zum betrieb eines mehrkernprozessors
GB2524218A (en) Extended link aggregation (LAG) for use in multiple switches
GB2490823A (en) A data processing apparatus and method for switching a workload between first and second processing circuitry
WO2015018708A3 (de) Verfahren zum betrieb eines navigationssystems in einem fahrzeug und entsprechendes steuerungssystem sowie computerprogrammprodukt
FI20185283L (fi) Menetelmä ja järjestelmä tehtävien osoittamiseksi kaivos- ja/tai työkoneille
EP3398166A4 (de) Verfahren für struktur aus bewegungsverarbeitung in einem computersichtsystem
JP2012232363A5 (ja) ロボット制御システム及びロボットシステム
WO2013184675A3 (en) Automated disaster recovery and data migration
WO2014116861A3 (en) Parallel processing with proactive solidarity cells
WO2014199070A3 (fr) Système de commande de vol électrique pour aéronef
GB2499535A (en) Multiple modeling paradigm for predictive analytics
WO2014100791A3 (en) Assigning jobs to heterogeneous processing modules
EP4329422A3 (de) Steuerschaltung für ein dampfbereitstellungssystem
WO2014198464A9 (en) Multicore processor fault detection for safety critical software applications
WO2014001370A3 (de) Vorrichtung und verfahren für eine sicherheitskritische anwendung
WO2013036824A3 (en) Parallel processing development environment extensions
WO2014165208A3 (en) Meter reading data validation
WO2016033629A3 (de) Computersystem und verfahren für sicherheitskritische anwendungen
GB2506048A (en) Unified, adaptive RAS for hybrid systems
WO2014160556A3 (en) Populating localized fast bulk storage in a multi-node computer system
WO2012051089A3 (en) Autonomous machine control system
JP2014035644A5 (de)
BR112015025254A2 (pt) sistema de acionamento híbrido para uma colheitadeira, seu método de operação e programa de computador
JP2014116519A5 (ja) アライメント装置、貼り合わせ装置および位置合わせ方法
WO2013053643A3 (de) Verfahren zum betreiben eines steuerungsnetzwerk und steuerungsnetzwerk

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16790913

Country of ref document: EP

Kind code of ref document: A2

WWE Wipo information: entry into national phase

Ref document number: 2016790913

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 15773774

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 2018524403

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20187016720

Country of ref document: KR

Kind code of ref document: A