WO2017080014A1 - 一种Mura补偿数据写入装置及方法 - Google Patents

一种Mura补偿数据写入装置及方法 Download PDF

Info

Publication number
WO2017080014A1
WO2017080014A1 PCT/CN2015/097679 CN2015097679W WO2017080014A1 WO 2017080014 A1 WO2017080014 A1 WO 2017080014A1 CN 2015097679 W CN2015097679 W CN 2015097679W WO 2017080014 A1 WO2017080014 A1 WO 2017080014A1
Authority
WO
WIPO (PCT)
Prior art keywords
interface
write
memory
read
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/097679
Other languages
English (en)
French (fr)
Inventor
张华�
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/905,239 priority Critical patent/US10276076B2/en
Publication of WO2017080014A1 publication Critical patent/WO2017080014A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0204—Compensation of DC component across the pixels in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/02—Graphics controller able to handle multiple formats, e.g. input or output formats
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/16—Calculation or use of calculated indices related to luminance levels in display data

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a device and method for writing Mura compensation data.
  • a Mura compensation method that is, a Mura form in which a grayscale image (a pure white image with different brightness) is captured by a camera, and the surrounding area of the LCD panel is calculated by comparing the brightness of the center position of the LCD panel.
  • the difference from the brightness of the center position, and then by offset compensation of the grayscale value of the Mura position the LCD panel as a whole achieves a relatively uniform brightness. For example, in a region brighter than the center position, the grayscale value is lowered to darken the luminance of the region; in a region darker than the central position, the grayscale value is increased, thereby brightening the luminance of the region.
  • the Full High Definition (FHD) resolution (1920 ⁇ 1080) Timing Controller (TCON) chip is supported on the market, and the Mura compensation function is not integrated. Therefore, in the FHD resolution LCD panel, most of them are matched with the TCON chip through a separate Mura compensation chip to complete the Mura compensation function.
  • the Mura compensation chip calculates the difference between the brightness of the area around the LCD panel and the center position, and reads the corresponding Mura compensation from the FLASH memory. The data, in turn, controls the TCON chip to output Mura compensated grayscale data to achieve Mura compensation for the LCD panel.
  • the Mura compensation chip needs to be paired with two data memories: an Electrically Erasable Programmable Read-Only Memory (EEPROM) for I2C (Inter-Integrated Circuit) interface for storage.
  • EEPROM Electrically Erasable Programmable Read-Only Memory
  • I2C Inter-Integrated Circuit
  • Mura compensation The chip's setting parameters; the other is the Serial Peripheral Interface (SPI) FLASH memory, which is used to store the Mura compensation data.
  • SPI Serial Peripheral Interface
  • the present invention provides a Mura compensation data writing device, which realizes the setting parameters of the Mura compensation chip and the writing of the Mura compensation data by multiplexing one connector, thereby simplifying the Mura compensation data.
  • the writing process improves data writing efficiency and reduces production costs.
  • the present invention also provides a Mura compensation data writing method.
  • a Mura compensation data writing device includes a Mura compensation chip, a first memory, a second memory, a connector, and a control circuit, wherein the Mura compensation chip is electrically connected to the first memory, the second memory, and the connector, The connector is electrically connected to the first memory, and is electrically connected to the second memory through the control circuit, and the first memory and the second memory respectively include a write enable state and a write protection state.
  • the control circuit is configured to control the second memory to be in a different working state from the first memory
  • the connector is configured to: when the first memory enters an allowable write state A memory writes the first data, and when the second memory enters the allowable write state, the second data is written to the second memory by the Mura compensation chip.
  • the Mura compensation chip includes a first communication interface, the first memory includes a first read/write interface and a first protection interface, and the connector includes a data input interface and a read/write control interface; the first communication interface The data input interface is connected to the first communication interface and the first read/write interface; and the read/write control interface is connected to the first protection interface.
  • the Mura compensation chip further includes a second communication interface, the second memory includes a second read/write interface and a second protection interface, and the second communication interface is connected to the second read/write interface, the reading The write control interface is connected to the second protection interface through the control circuit, and the control circuit is configured to control the second memory to be in a different working state from the first memory.
  • control circuit comprises a transistor, a first resistor and a second resistor, the transistor comprising a gate, a source and a drain, wherein the gate is connected to the read/write control interface; the source is used to access a first level control signal; and the first resistor is connected to the source at one end The other end is connected to the read/write control interface; the drain is connected to the second protection interface; one end of the second resistor is connected to the drain and the second protection interface, and the other end is grounded.
  • the transistor is a P-type metal-oxide semiconductor field effect transistor.
  • the first read/write interface is configured to write the first data to the first memory; the first protection interface is used to access a first level or a second level of control signals.
  • the first protection interface accesses the first level control signal, the first memory enters an allowable write state, and when the first protection interface accesses the second level control signal, the first memory Enter the write protection state.
  • the read/write control interface when the read/write control interface outputs a control signal of a first level, the first memory enters a write enable state, the second memory enters a write protection state; and the data input interface inputs the first data The first data is written into the first memory through the first read/write interface.
  • the second read/write interface is configured to write the second data to the second memory; the second protection interface is configured to access a control signal of a first level or a second level.
  • the second protection interface accesses the first level control signal, the second memory enters an allowable write state, and when the second protection interface accesses the second level control signal, the second memory Enter the write protection state.
  • the read/write control interface when the read/write control interface outputs a second level control signal, the first memory enters a write protection state, the second memory enters an allowable write state; and the data input interface inputs the second data
  • the second data is transmitted to the Mura compensation chip through the first communication interface, and is output by the second communication interface to the second read/write interface, and then written by the second read/write interface.
  • the second memory when the read/write control interface outputs a second level control signal, the first memory enters a write protection state, the second memory enters an allowable write state; and the data input interface inputs the second data
  • the second data is transmitted to the Mura compensation chip through the first communication interface, and is output by the second communication interface to the second read/write interface, and then written by the second read/write interface.
  • a method for writing Mura compensation data comprising:
  • the read/write control port of the connector outputs a first level control signal to control the first memory to enter an allowable write state
  • the control circuit converts the control signal of the first level into a control signal of a second level, and controls the second memory to enter a write protection state
  • the data input interface of the connector inputs the first data, and the first data is written into the first memory through the first read/write interface;
  • the read/write control port of the connector outputs a second level control signal to control the first memory to enter the write Into the protection state;
  • the control circuit converts the control signal of the second level into a control signal of a first level, and controls the second memory to enter an allowable write state
  • the data input interface of the connector inputs the second data, and the second data is transmitted to the Mura compensation chip through the first communication interface;
  • the Mura compensation chip outputs the second data to the second read/write interface through the second communication interface, and writes the second memory by the second read/write interface.
  • the Mura compensation chip includes a first communication interface, the first memory includes a first read/write interface and a first protection interface, and the connector includes a data input interface and a read/write control interface; the first communication interface The data input interface is connected to the first communication interface and the first read/write interface; and the read/write control interface is connected to the first protection interface.
  • the Mura compensation chip further includes a second communication interface, the second memory includes a second read/write interface and a second protection interface, and the second communication interface is connected to the second read/write interface, the reading The write control interface is connected to the second protection interface through the control circuit, and the control circuit is configured to control the second memory to be in a different working state from the first memory.
  • the control circuit includes a transistor, a first resistor and a second resistor, the transistor includes a gate, a source and a drain, the gate is connected to the read/write control interface; and the source is used for connection a first level of control signal; one end of the first resistor being connected to the source, the other end being connected to the read/write control interface; the drain being connected to the second protection interface; the second One end of the resistor is connected to the drain and the second protection interface, and the other end is grounded.
  • the transistor is a P-type metal-oxide semiconductor field effect transistor.
  • the first read/write interface is configured to write the first data to the first memory; the first protection interface is used to access a first level or a second level of control signals.
  • the first protection interface accesses the first level control signal, the first memory enters an allowable write state, and when the first protection interface accesses the second level control signal, the first memory Enter the write protection state.
  • the read/write control interface when the read/write control interface outputs a control signal of a first level, the first memory enters a write enable state, the second memory enters a write protection state; and the data input interface inputs the first data The first data is written into the first memory through the first read/write interface.
  • the second read/write interface is configured to write the second data to the second memory;
  • the second protection interface is configured to access a control signal of the first level or the second level, and when the second protection interface is connected to the control signal of the first level, the second memory enters an allowable write state, When the second protection interface accesses the second level control signal, the second memory enters a write protection state.
  • the read/write control interface when the read/write control interface outputs a second level control signal, the first memory enters a write protection state, the second memory enters an allowable write state; and the data input interface inputs the second data
  • the second data is transmitted to the Mura compensation chip through the first communication interface, and is output by the second communication interface to the second read/write interface, and then written by the second read/write interface.
  • the second memory when the read/write control interface outputs a second level control signal, the first memory enters a write protection state, the second memory enters an allowable write state; and the data input interface inputs the second data
  • the second data is transmitted to the Mura compensation chip through the first communication interface, and is output by the second communication interface to the second read/write interface, and then written by the second read/write interface.
  • the Mura compensation data writing device is controlled by the control circuit by setting the connector to be electrically connected to the first memory and electrically connecting to the second memory through the control circuit
  • the first memory and the second memory are in different working states, and the first data is written to the first memory by the connector when the first memory enters the allowable write state, and in the When the two memories enter the allowable write state, the second data is written to the second memory by the Mura compensation chip, thereby implementing multiplexing of the connector, simplifying the structure of the Mura compensation data writing device and Mura compensates for the data writing process, which helps to improve data writing efficiency and reduce production costs.
  • FIG. 1 is a block diagram showing an implementation principle of a Mura compensation function in the prior art
  • FIG. 2 is a schematic diagram of comparison of original gray scale data and Mura compensation data shown in FIG. 1;
  • FIG. 3 is a schematic structural diagram of a device for writing Mura compensation data in the prior art
  • FIG. 4 is a schematic structural diagram of a device for writing Mura compensation data according to an embodiment of the present invention.
  • FIG. 5 is a schematic flowchart diagram of a method for writing Mura compensation data according to an embodiment of the present invention.
  • an embodiment of the present invention provides a Mura compensation data writing device 100, which is applied to a liquid crystal display (LCD) to implement Mura compensation of an LCD and improve brightness uniformity of the LCD.
  • LCD liquid crystal display
  • the Mura compensation data writing device 100 includes a Mura compensation chip 110, a first memory 130, a second memory 150, a connector 170, and a control circuit 190.
  • the Mura compensation chip 110 is electrically connected to the first memory 130, the second memory 150, and the connector 170.
  • the connector 170 is electrically connected to the first memory 130 and passes through the control circuit 190 and the second memory.
  • the reservoir 150 is electrically connected.
  • the first memory 130 and the second memory 150 each include two working states of a write enable state and a write protection state.
  • the control circuit 190 is configured to control the second memory 150 to be in a different working state from the first memory 130, for example, to control the second memory 150 when the first memory 130 enters a write protection state. Enter the allowable write state.
  • the connector 170 is configured to write first data to the first memory 130 when the first memory 130 enters a write enable state; and control the second memory 150 to enter write enable at the control circuit 190 When the state is entered, the second data is written to the second memory 150 by the Mura compensation chip 110.
  • the Mura compensation chip 110 includes a first communication interface 111 and a second communication interface 113.
  • the first memory 130 includes a first read/write interface 131 and a first protection interface 133.
  • the first read/write interface 131 is configured to write the first data to the first memory 130 or write the first data. Reading the first data in the first memory 130 of a data; the first protection interface 133 is configured to access a control signal of a first level or a second level, when the first protection interface 133 is connected.
  • the first memory 130 enters a write enable state when the first level of the control signal is received, and the first memory 130 enters the write protection when the first protection interface 133 is connected to the second level control signal status.
  • the second memory 150 includes a second read/write interface 151 and a second protection interface 153.
  • the second read/write interface 151 is configured to write the second data to the second memory 150 or Reading the second data in the second memory 150 of the two data;
  • the second protection interface 153 is configured to access the control signal of the first level or the second level, when the second protection interface 153 is connected When the first level of the control signal, the second memory 150 enters the write enable state, and when the second protection interface 153 is connected to the second level control signal, the second memory 150 enters the write protection status.
  • the connector 170 includes a data input interface 171 and a read/write control interface 173; the data input interface 171 is configured to input the first data or the second data; and the read/write control interface 173 is configured to output the first Level or second level control signal.
  • the data input interface 171 is connected to the first communication interface 111 and the first read/write interface 131; the read/write control interface 173 is connected to the first protection interface 133, and the control circuit 190 is used to The second protection interface 153 is connected; the control circuit 190 is configured to convert the first level control signal output by the read/write control interface 173 into a second level control signal, or output the read/write control interface The second level of control signal is converted to a first level of control signal.
  • the first read/write interface 131 is connected to the first communication interface 111; the second communication interface 113 is connected to the second read/write interface 151.
  • the first electric The flat control signal is a high level voltage signal, such as a 3.3V voltage signal; the second level control signal is a low level voltage signal, such as a 0V voltage signal.
  • the control signal of the first level may also be a voltage signal of a low level, and correspondingly, the control signal of the second level may also be a voltage signal of a high level.
  • the first communication interface 111 is an Inter-Integrated Circuit (I2C) interface
  • the second communication interface 113 is a Serial Peripheral Interface (SPI);
  • the first memory 130 The first read/write interface 131 is an I2C interface
  • the first data is the setting of the Mura compensation chip 110.
  • the first read/write interface 131 is an I2C interface.
  • the first data is used to set an operating parameter of the Mura compensation chip 110;
  • the second memory 150 is a FLASH memory of an SPI interface, and the second read/write interface 151 is an SPI interface;
  • the second data is Mura compensation data, and the second data is used to provide gray scale data compensation for the LCD having the Mura defect;
  • the connector 170 is an I2C connector, and the data input interface 171 is an I2C interface. As shown in FIG.
  • the first communication interface 111, the first read/write interface 131, and the data input interface 171 are connected by a data line SDA and a clock line SCL, and the data line SDA is used for transmitting data, such as the first Data or second data, the clock line SCL is used to transmit a data read/write clock signal; between the second communication interface 113 and the second read/write interface 151, an output data line SPI_SDO, an input data line SPI_SDI, a clock
  • the line SPI_SCK is connected to the enable signal line SPI_CS for outputting the second data to the second memory 150, and the input data line SPI_SDI is for reading the second data from the second memory 150.
  • the clock line SPI_SCK is used to transmit a data read/write clock signal
  • the enable signal line SPI_CS is used to transmit a read/write enable signal.
  • the control circuit 190 includes a transistor Q1, a first resistor R1, and a second resistor R2.
  • the transistor Q1 is a P-type Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and includes a gate G, a source S and a drain D, and the gate G and the gate
  • the read/write control interface 173 is connected; the source S is used to access a first level control signal (a voltage signal of 3.3V in this embodiment); one end of the first resistor R1 is connected to the source S The other end is connected to the read/write control interface 173; the drain D is connected to the second protection interface 153; and one end of the second resistor R2 is connected to the drain D and the second protection interface 153. The other end is grounded.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • the read/write control interface 173 When the read/write control interface 173 outputs a control signal of a first level (3.3V), the gate G and the source S voltage are equal, the transistor Q1 is turned off, and the first protection interface 133 is connected. a first level of control signal, the first memory 130 enters a write enable state, the second protection interface 153 is a control signal for accessing a second level, and the second memory 150 enters a write protection state;
  • the data input interface 171 inputs first data, and the first data is written into the first memory 130 through the first read/write interface 131. After the first data is written, the read/write control interface 173 outputs a control signal of a second level (0V), the voltage of the gate G is 0V, and the voltage of the source S is 3.3V.
  • the transistor Q1 is turned on, the first protection interface 133 is connected to the second level control signal, the first memory 130 enters a write protection state, and the second protection interface 153 is connected to the first power. a flat control signal, the second memory 150 enters an allowable write state; the data input interface 171 inputs second data, and the second data is transmitted to the Mura compensation chip 110 through the first communication interface 111, And being output to the second read/write interface 151 by the second communication interface 113, and then writing to the second memory 150 through the second read/write interface 151.
  • an embodiment of the present invention further provides a method for writing Mura compensation data, where the method includes at least the following steps:
  • Step S201 The read/write control port of the connector outputs a first level control signal, and controls the first memory to enter an allowable write state;
  • Step S202 The control circuit converts the control signal of the first level into a control signal of a second level, and controls the second memory to enter a write protection state;
  • Step S203 The data input interface of the connector inputs the first data, and the first data is written into the first memory through the first read/write interface;
  • Step S204 The read/write control port of the connector outputs a second level control signal, and controls the first memory to enter a write protection state;
  • Step S205 The control circuit converts the control signal of the second level into a control signal of a first level, and controls the second memory to enter an allowable write state;
  • Step S206 The data input interface of the connector inputs the second data, and the second data is transmitted to the Mura compensation chip through the first communication interface;
  • Step S207 The Mura compensation chip outputs the second data to the second read/write interface through the second communication interface, and writes the second memory by the second read/write interface.
  • the Mura compensation chip includes a first communication interface, the first memory includes a first read/write interface and a first protection interface, and the connector includes a data input interface and a read/write control interface; the first communication interface The data input interface is connected to the first communication interface and the first read/write interface; and the read/write control interface is connected to the first protection interface.
  • the Mura compensation chip further includes a second communication interface, the second memory includes a second read/write interface and a second protection interface, and the second communication interface is connected to the second read/write interface, the reading The write control interface is connected to the second protection interface through the control circuit, and the control circuit is configured to control the second memory to be in a different working state from the first memory.
  • the control circuit includes a transistor, a first resistor and a second resistor, the transistor includes a gate, a source and a drain, the gate is connected to the read/write control interface; and the source is used for connection a first level of control signal; one end of the first resistor being connected to the source, the other end being connected to the read/write control interface; the drain being connected to the second protection interface; the second One end of the resistor is connected to the drain and the second protection interface, and the other end is grounded.
  • the transistor is a P-type metal-oxide semiconductor field effect transistor.
  • the first read/write interface is configured to write the first data to the first memory; the first protection interface is used to access a first level or a second level of control signals.
  • the first protection interface accesses the first level control signal, the first memory enters an allowable write state, and when the first protection interface accesses the second level control signal, the first memory Enter the write protection state.
  • the read/write control interface when the read/write control interface outputs a control signal of a first level, the first memory enters a write enable state, the second memory enters a write protection state; and the data input interface inputs the first data The first data is written into the first memory through the first read/write interface.
  • the second read/write interface is configured to write the second data to the second memory; the second protection interface is configured to access a control signal of a first level or a second level.
  • the second protection interface accesses the first level control signal, the second memory enters an allowable write state, and when the second protection interface accesses the second level control signal, the second memory Enter the write protection state.
  • the read/write control interface when the read/write control interface outputs a second level control signal, the first memory enters a write protection state, the second memory enters an allowable write state; and the data input interface inputs the second data
  • the second data is transmitted to the Mura compensation chip through the first communication interface, and is output by the second communication interface to the second read/write interface, and further through the second read/write interface Write to the second memory.
  • the Mura compensation data writing device is controlled by the control circuit by setting the connector to be electrically connected to the first memory and electrically connecting to the second memory through the control circuit
  • the first memory and the second memory are in different working states, and the first data is written to the first memory by the connector when the first memory enters the allowable write state, and in the When the two memories enter the allowable write state, the second data is written to the second memory by the Mura compensation chip, thereby implementing multiplexing of the connector, simplifying the structure of the Mura compensation data writing device and Mura compensates for the data writing process, which helps to improve data writing efficiency and reduce production costs.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Read Only Memory (AREA)
  • Storage Device Security (AREA)

Abstract

一种Mura补偿数据写入装置，包括Mura补偿芯片（110）、第一存储器（130）、第二存储器（150）、连接器（170）及控制电路（190）。该Mura补偿芯片（110）与第一存储器（130）、第二存储器（150）及连接器（170）连接，连接器（170）与第一存储器（130）电性连接，并通过控制电路（190）与第二存储器（150）电性连接，第一存储器（130）与第二存储器（150）均包括允许写入和写入保护两种状态，控制电路（190）用于控制第二存储器（150）与第一存储器（130）处于不同的工作状态，连接器（170）用于在第一存储器（130）进入允许写入状态时向第一存储器（130）写入第一数据，并在第二存储器（150）进入允许写入状态时，通过Mura补偿芯片（110）向第二存储器（150）写入第二数据。另，还公开了一种Mura补偿数据写入方法。该Mura补偿数据写入装置可以简化Mura补偿数据写入过程并提升写入效率。

Description

一种Mura补偿数据写入装置及方法
本发明要求2015年11月11日递交的发明名称为“一种Mura补偿数据写入装置及方法”的申请号(201510764877.2)的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种Mura补偿数据写入装置及方法。
背景技术
由于液晶显示器(Liquid Crystal Display，LCD)制程上的瑕疵，可能会导致生产出来的LCD面板亮度不均匀，形成各种各样的Mura(斑纹)缺陷。为了提升LCD面板亮度均匀性，目前已有Mura补偿方法，即通过相机拍摄出灰阶画面(不同亮度的纯白画面)的Mura形态，通过对比LCD面板中心位置的亮度，计算出LCD面板四周区域与中心位置亮度的差异，然后通过反向补偿Mura位置的灰阶值，使LCD面板整体达到比较一致的亮度。例如，在比中心位置亮的区域，降低灰阶值，从而使该区域的亮度变暗；在比中心位置暗的区域，提高灰阶值，从而使该区域的亮度变亮。
目前市面上支持全高清(Full High Definition，FHD)分辨率(1920×1080)的时序控制(Timing Controller，TCON)芯片，并未整合Mura补偿功能。因此，在FHD分辨率LCD面板中，大都是通过一颗独立的Mura补偿芯片与TCON芯片相配合来完成Mura补偿功能。如图1和图2所示，通过对Mura补偿芯片输入LCD面板的原始灰阶数据，Mura补偿芯片计算出LCD面板四周区域与中心位置亮度的差异，并从FLASH存储器中读取相应的Mura补偿数据，进而控制所述TCON芯片输出Mura补偿后的灰阶数据，实现对LCD面板的Mura补偿。在上述方案中，Mura补偿芯片需要搭配两颗数据存储器：一颗为I2C(Inter-Integrated Circuit)接口的电可擦可编程只读存储器(Electrically Erasable Programmable Read-Only Memory，EEPROM)，用于存储Mura补偿 芯片的设定参数；另一颗为串行外设接口(Serial Peripheral Interface，SPI)的FLASH存储器，用于存储Mura补偿数据。如图3所示，在对所述两颗数据存储器进行数据写入时，需要采用两个不同的连接器及两个不同的数据文档来对所述两颗数据存储器分别进行数据写入，使得数据写入过程复杂，且耗时较长。
发明内容
鉴于现有技术中存在的上述问题，本发明提供一种Mura补偿数据写入装置，通过复用一个连接器，实现Mura补偿芯片的设定参数及Mura补偿数据的写入，以简化Mura补偿数据写入过程，提升数据写入效率，并降低生产成本。
另，本发明还提供一种Mura补偿数据写入方法。
一种Mura补偿数据写入装置，包括Mura补偿芯片、第一存储器、第二存储器、连接器及控制电路，所述Mura补偿芯片与所述第一存储器、第二存储器及连接器电性连接，所述连接器与所述第一存储器电性连接，并通过所述控制电路与所述第二存储器电性连接，所述第一存储器与第二存储器均包括允许写入状态和写入保护状态两种工作状态，所述控制电路用于控制所述第二存储器与所述第一存储器处于不同的工作状态，所述连接器用于在所述第一存储器进入允许写入状态时向所述第一存储器写入第一数据，并在所述第二存储器进入允许写入状态时，通过所述Mura补偿芯片向所述第二存储器写入第二数据。
其中，所述Mura补偿芯片包括第一通信接口，所述第一存储器包括第一读写接口及第一保护接口，所述连接器包括数据输入接口及读写控制接口；所述第一通信接口与所述第一读写接口连接；所述数据输入接口与所述第一通信接口及第一读写接口连接；所述读写控制接口与所述第一保护接口连接。
其中，所述Mura补偿芯片还包括第二通信接口，所述第二存储器包括第二读写接口及第二保护接口，所述第二通信接口与所述第二读写接口连接，所述读写控制接口通过所述控制电路与所述第二保护接口连接，所述控制电路用于控制所述第二存储器与所述第一存储器处于不同的工作状态。
其中，所述控制电路包括晶体管、第一电阻及第二电阻，所述晶体管包括 栅极、源极及漏极，所述栅极与所述读写控制接口连接；所述源极用于接入第一电平的控制信号；所述第一电阻一端与所述源极连接，另一端与所述读写控制接口连接；所述漏极与所述第二保护接口连接；所述第二电阻一端与所述漏极及所述第二保护接口连接，另一端接地。
其中，所述晶体管为P型金属-氧化物半导体场效应晶体管。
其中，所述第一读写接口用于向所述第一存储器写入所述第一数据；所述第一保护接口用于接入第一电平或第二电平的控制信号，当所述第一保护接口接入第一电平的控制信号时，所述第一存储器进入允许写入状态，当所述第一保护接口接入第二电平的控制信号时，所述第一存储器进入写入保护状态。
其中，当所述读写控制接口输出第一电平的控制信号时，所述第一存储器进入允许写入状态，所述第二存储器进入写入保护状态；所述数据输入接口输入第一数据，所述第一数据通过所述第一读写接口写入所述第一存储器。
其中，所述第二读写接口用于向所述第二存储器写入所述第二数据；所述第二保护接口用于接入第一电平或第二电平的控制信号，当所述第二保护接口接入第一电平的控制信号时，所述第二存储器进入允许写入状态，当所述第二保护接口接入第二电平的控制信号时，所述第二存储器进入写入保护状态。
其中，当所述读写控制接口输出第二电平的控制信号时，所述第一存储器进入写入保护状态，所述第二存储器进入允许写入状态；所述数据输入接口输入第二数据，所述第二数据通过所述第一通信接口传输到所述Mura补偿芯片，并由所述第二通信接口输出给所述第二读写接口，进而通过所述第二读写接口写入所述第二存储器。
一种Mura补偿数据写入方法，包括：
连接器的读写控制端口输出第一电平的控制信号，控制第一存储器进入允许写入状态；
控制电路将所述第一电平的控制信号转换为第二电平的控制信号，控制所述第二存储器进入写入保护状态；
连接器的数据输入接口输入第一数据，所述第一数据通过第一读写接口写入所述第一存储器；
连接器的读写控制端口输出第二电平的控制信号，控制第一存储器进入写 入保护状态；
控制电路将所述第二电平的控制信号转换为第一电平的控制信号，控制所述第二存储器进入允许写入状态；
连接器的数据输入接口输入第二数据，所述第二数据通过第一通信接口传输到Mura补偿芯片；
所述Mura补偿芯片将所述第二数据通过第二通信接口输出给第二读写接口，并由所述第二读写接口写入所述第二存储器。
其中，所述Mura补偿芯片包括第一通信接口，所述第一存储器包括第一读写接口及第一保护接口，所述连接器包括数据输入接口及读写控制接口；所述第一通信接口与所述第一读写接口连接；所述数据输入接口与所述第一通信接口及第一读写接口连接；所述读写控制接口与所述第一保护接口连接。
其中，所述Mura补偿芯片还包括第二通信接口，所述第二存储器包括第二读写接口及第二保护接口，所述第二通信接口与所述第二读写接口连接，所述读写控制接口通过所述控制电路与所述第二保护接口连接，所述控制电路用于控制所述第二存储器与所述第一存储器处于不同的工作状态。
其中，所述控制电路包括晶体管、第一电阻及第二电阻，所述晶体管包括栅极、源极及漏极，所述栅极与所述读写控制接口连接；所述源极用于接入第一电平的控制信号；所述第一电阻一端与所述源极连接，另一端与所述读写控制接口连接；所述漏极与所述第二保护接口连接；所述第二电阻一端与所述漏极及所述第二保护接口连接，另一端接地。
其中，所述晶体管为P型金属-氧化物半导体场效应晶体管。
其中，所述第一读写接口用于向所述第一存储器写入所述第一数据；所述第一保护接口用于接入第一电平或第二电平的控制信号，当所述第一保护接口接入第一电平的控制信号时，所述第一存储器进入允许写入状态，当所述第一保护接口接入第二电平的控制信号时，所述第一存储器进入写入保护状态。
其中，当所述读写控制接口输出第一电平的控制信号时，所述第一存储器进入允许写入状态，所述第二存储器进入写入保护状态；所述数据输入接口输入第一数据，所述第一数据通过所述第一读写接口写入所述第一存储器。
其中，所述第二读写接口用于向所述第二存储器写入所述第二数据；所述 第二保护接口用于接入第一电平或第二电平的控制信号，当所述第二保护接口接入第一电平的控制信号时，所述第二存储器进入允许写入状态，当所述第二保护接口接入第二电平的控制信号时，所述第二存储器进入写入保护状态。
其中，当所述读写控制接口输出第二电平的控制信号时，所述第一存储器进入写入保护状态，所述第二存储器进入允许写入状态；所述数据输入接口输入第二数据，所述第二数据通过所述第一通信接口传输到所述Mura补偿芯片，并由所述第二通信接口输出给所述第二读写接口，进而通过所述第二读写接口写入所述第二存储器。
所述Mura补偿数据写入装置通过将所述连接器设置为与所述第一存储器电性连接，并通过所述控制电路与所述第二存储器电性连接，由所述控制电路控制所述第一存储器与所述第二存储器处于不同的工作状态，进而通过所述连接器在所述第一存储器进入允许写入状态时向所述第一存储器写入第一数据，并在所述第二存储器进入允许写入状态时，通过所述Mura补偿芯片向所述第二存储器写入第二数据，从而实现所述连接器的复用，简化了所述Mura补偿数据写入装置的结构及Mura补偿数据写入过程，有利于提升数据写入效率，并降低生产成本。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中Mura补偿功能的实现原理框图；
图2为图1所示原始灰阶数据与Mura补偿数据的对比示意图；
图3为现有技术中Mura补偿数据写入装置的结构示意图；
图4为本发明实施例提供的Mura补偿数据写入装置的结构示意图；
图5为本发明实施例提供的Mura补偿数据写入方法的流程示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
为便于描述，这里可以使用诸如“在…之下”、“在…下面”、“下”、“在…之上”、“上”等空间相对性术语来描述如图中所示的一个元件或特征与另一个(些)元件或特征的关系。可以理解，当一个元件或层被称为在另一元件或层“上”、“连接到”或“耦接到”另一元件或层时，它可以直接在另一元件或层上、直接连接到或耦接到另一元件或层，或者可以存在居间元件或层。相反，当一个元件被称为“直接在”另一元件或层上、“直接连接到”或“直接耦接到”另一元件或层时，不存在居间元件或层。
可以理解，这里所用的术语仅是为了描述特定实施例，并非要限制本发明。在这里使用时，除非上下文另有明确表述，否则单数形式“一”和“该”也旨在包括复数形式。进一步地，当在本说明书中使用时，术语“包括”和/或“包含”表明所述特征、整体、步骤、操作、元件和/或组件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、组件和/或其组合的存在或增加。
除非另行定义，这里使用的所有术语(包括技术术语和科学术语)都具有本发明所属领域内的普通技术人员所通常理解的相同含义。将进一步理解，诸如通用词典中所定义的术语，否则应当被解释为具有与它们在相关领域的语境中的含义相一致的含义，而不应被解释为理想化或过度形式化的意义，除非在此明确地如此定义。
请参阅图4，本发明实施例提供一种Mura补偿数据写入装置100，其应用于液晶显示器(Liquid Crystal Display，LCD)中，以实现LCD的Mura补偿，提升LCD的亮度均匀性。
所述Mura补偿数据写入装置100包括Mura补偿芯片110、第一存储器130、第二存储器150、连接器170及控制电路190。所述Mura补偿芯片110与所述第一存储器130、第二存储器150及连接器170电性连接。所述连接器170与所述第一存储器130电性连接，并通过所述控制电路190与所述第二存 储器150电性连接。所述第一存储器130与第二存储器150均包括允许写入状态和写入保护状态两种工作状态。所述控制电路190用于控制所述第二存储器150与所述第一存储器130处于不同的工作状态，例如，在所述第一存储器130进入写入保护状态时，控制所述第二存储器150进入允许写入状态。所述连接器170用于在所述第一存储器130进入允许写入状态时向所述第一存储器130写入第一数据；并在所述控制电路190控制所述第二存储器150进入允许写入状态时，通过所述Mura补偿芯片110向所述第二存储器150写入第二数据。
具体地，所述Mura补偿芯片110包括第一通信接口111及第二通信接口113。所述第一存储器130包括第一读写接口131及第一保护接口133；所述第一读写接口131用于向所述第一存储器130写入所述第一数据或者从已经写入第一数据的所述第一存储器130中读出第一数据；所述第一保护接口133用于接入第一电平或第二电平的控制信号，当所述第一保护接口133接入第一电平的控制信号时，所述第一存储器130进入允许写入状态，当所述第一保护接口133接入第二电平的控制信号时，所述第一存储器130进入写入保护状态。所述第二存储器150包括第二读写接口151及第二保护接口153；所述第二读写接口151用于向所述第二存储器150写入所述第二数据或者从已经写入第二数据的所述第二存储器150中读出第二数据；所述第二保护接口153用于接入第一电平或第二电平的控制信号，当所述第二保护接口153接入第一电平的控制信号时，所述第二存储器150进入允许写入状态，当所述第二保护接口153接入第二电平的控制信号时，所述第二存储器150进入写入保护状态。所述连接器170包括数据输入接口171及读写控制接口173；所述数据输入接口171用于输入所述第一数据或第二数据；所述读写控制接口173用于输出所述第一电平或第二电平的控制信号。所述数据输入接口171与所述第一通信接口111及第一读写接口131连接；所述读写控制接口173与所述第一保护接口133连接，并通过所述控制电路190与所述第二保护接口153连接；所述控制电路190用于将所述读写控制接口173输出的第一电平的控制信号转换为第二电平的控制信号，或者将所述读写控制接口输出的第二电平的控制信号转换为第一电平的控制信号。所述第一读写接口131与所述第一通信接口111连接；所述第二通信接口113与所述第二读写接口151连接。在本实施例中，所述第一电 平的控制信号为高电平的电压信号，例如3.3V的电压信号；所述第二电平的控制信号为低电平的电压信号，如0V的电压信号。可以理解，所述第一电平的控制信号也可以为低电平的电压信号，相应地，所述第二电平的控制信号也可以为高电平的电压信号。
在本实施例中，所述第一通信接口111为I2C(Inter-Integrated Circuit)接口，所述第二通信接口113为串行外设接口(Serial Peripheral Interface，SPI)；所述第一存储器130为I2C接口的电可擦可编程只读存储器(Electrically Erasable Programmable Read-Only Memory，EEPROM)，所述第一读写接口131为I2C接口；所述第一数据为所述Mura补偿芯片110的设定参数，所述第一数据用于设定所述Mura补偿芯片110的工作参数；所述第二存储器150为SPI接口的FLASH存储器，所述第二读写接口151为SPI接口；所述第二数据为Mura补偿数据，所述第二数据用于为存在Mura缺陷的LCD提供灰阶数据补偿；所述连接器170为I2C连接器，所述数据输入接口171为I2C接口。如图4所示，所述第一通信接口111、第一读写接口131及数据输入接口171之间通过数据线SDA及时钟线SCL连接，所述数据线SDA用于传输数据，如第一数据或第二数据，所述时钟线SCL用于传输数据读写时钟信号；所述第二通信接口113与所述第二读写接口151之间通过输出数据线SPI_SDO、输入数据线SPI_SDI、时钟线SPI_SCK及使能信号线SPI_CS连接，所述输出数据线SPI_SDO用于输出第二数据至所述第二存储器150，所述输入数据线SPI_SDI用于从所述第二存储器150读取第二数据，所述时钟线SPI_SCK用于传输数据读写时钟信号，所述使能信号线SPI_CS用于传输读写使能信号。
所述控制电路190包括晶体管Q1、第一电阻R1及第二电阻R2。所述晶体管Q1为P型金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)，包括栅极G、源极S及漏极D，所述栅极G与所述读写控制接口173连接；所述源极S用于接入第一电平的控制信号(本实施例中为3.3V的电压信号)；所述第一电阻R1一端与所述源极S连接，另一端与所述读写控制接口173连接；所述漏极D与所述第二保护接口153连接；所述第二电阻R2一端与所述漏极D及所述第二保护接口153连接，另一端接地。
当所述读写控制接口173输出第一电平(3.3V)的控制信号时，所述栅极G与源极S电压相等，则所述晶体管Q1截止，所述第一保护接口133接入第一电平的控制信号，所述第一存储器130进入允许写入状态，所述第二保护接口153为接入第二电平的控制信号，所述第二存储器150进入写入保护状态；所述数据输入接口171输入第一数据，所述第一数据通过所述第一读写接口131写入所述第一存储器130。当所述第一数据写入完毕后，所述读写控制接口173输出第二电平(0V)的控制信号，所述栅极G的电压为0V，所述源极S的电压为3.3V，则所述晶体管Q1导通，所述第一保护接口133接入第二电平的控制信号，所述第一存储器130进入写入保护状态，所述第二保护接口153接入第一电平的控制信号，所述第二存储器150进入允许写入状态；所述数据输入接口171输入第二数据，所述第二数据通过所述第一通信接口111传输到所述Mura补偿芯片110，并由所述第二通信接口113输出给所述第二读写接口151，进而通过所述第二读写接口151写入所述第二存储器150。
请参阅图5，本发明实施例还提供一种Mura补偿数据写入方法，所述方法至少包括如下步骤：
步骤S201：连接器的读写控制端口输出第一电平的控制信号，控制第一存储器进入允许写入状态；
步骤S202：控制电路将所述第一电平的控制信号转换为第二电平的控制信号，控制所述第二存储器进入写入保护状态；
步骤S203：连接器的数据输入接口输入第一数据，所述第一数据通过第一读写接口写入所述第一存储器；
步骤S204：连接器的读写控制端口输出第二电平的控制信号，控制第一存储器进入写入保护状态；
步骤S205：控制电路将所述第二电平的控制信号转换为第一电平的控制信号，控制所述第二存储器进入允许写入状态；
步骤S206：连接器的数据输入接口输入第二数据，所述第二数据通过第一通信接口传输到Mura补偿芯片；
步骤S207：所述Mura补偿芯片将所述第二数据通过第二通信接口输出给第二读写接口，并由所述第二读写接口写入所述第二存储器。
其中，所述Mura补偿芯片包括第一通信接口，所述第一存储器包括第一读写接口及第一保护接口，所述连接器包括数据输入接口及读写控制接口；所述第一通信接口与所述第一读写接口连接；所述数据输入接口与所述第一通信接口及第一读写接口连接；所述读写控制接口与所述第一保护接口连接。
其中，所述Mura补偿芯片还包括第二通信接口，所述第二存储器包括第二读写接口及第二保护接口，所述第二通信接口与所述第二读写接口连接，所述读写控制接口通过所述控制电路与所述第二保护接口连接，所述控制电路用于控制所述第二存储器与所述第一存储器处于不同的工作状态。
其中，所述控制电路包括晶体管、第一电阻及第二电阻，所述晶体管包括栅极、源极及漏极，所述栅极与所述读写控制接口连接；所述源极用于接入第一电平的控制信号；所述第一电阻一端与所述源极连接，另一端与所述读写控制接口连接；所述漏极与所述第二保护接口连接；所述第二电阻一端与所述漏极及所述第二保护接口连接，另一端接地。
其中，所述晶体管为P型金属-氧化物半导体场效应晶体管。
其中，所述第一读写接口用于向所述第一存储器写入所述第一数据；所述第一保护接口用于接入第一电平或第二电平的控制信号，当所述第一保护接口接入第一电平的控制信号时，所述第一存储器进入允许写入状态，当所述第一保护接口接入第二电平的控制信号时，所述第一存储器进入写入保护状态。
其中，当所述读写控制接口输出第一电平的控制信号时，所述第一存储器进入允许写入状态，所述第二存储器进入写入保护状态；所述数据输入接口输入第一数据，所述第一数据通过所述第一读写接口写入所述第一存储器。
其中，所述第二读写接口用于向所述第二存储器写入所述第二数据；所述第二保护接口用于接入第一电平或第二电平的控制信号，当所述第二保护接口接入第一电平的控制信号时，所述第二存储器进入允许写入状态，当所述第二保护接口接入第二电平的控制信号时，所述第二存储器进入写入保护状态。
其中，当所述读写控制接口输出第二电平的控制信号时，所述第一存储器进入写入保护状态，所述第二存储器进入允许写入状态；所述数据输入接口输入第二数据，所述第二数据通过所述第一通信接口传输到所述Mura补偿芯片，并由所述第二通信接口输出给所述第二读写接口，进而通过所述第二读写接口 写入所述第二存储器。
可以理解，本实施例中所述的Mura补偿数据写入方法的各个步骤的具体执行还可以参照图4所示装置实施例中的描述，此处不再赘述。
所述Mura补偿数据写入装置通过将所述连接器设置为与所述第一存储器电性连接，并通过所述控制电路与所述第二存储器电性连接，由所述控制电路控制所述第一存储器与所述第二存储器处于不同的工作状态，进而通过所述连接器在所述第一存储器进入允许写入状态时向所述第一存储器写入第一数据，并在所述第二存储器进入允许写入状态时，通过所述Mura补偿芯片向所述第二存储器写入第二数据，从而实现所述连接器的复用，简化了所述Mura补偿数据写入装置的结构及Mura补偿数据写入过程，有利于提升数据写入效率，并降低生产成本。
以上所揭露的仅为本发明的较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (18)

  1. 一种Mura补偿数据写入装置，包括Mura补偿芯片、第一存储器和第二存储器，其中，所述装置还包括连接器及控制电路，所述Mura补偿芯片与所述第一存储器、第二存储器及连接器电性连接，所述连接器与所述第一存储器电性连接，并通过所述控制电路与所述第二存储器电性连接，所述第一存储器与第二存储器均包括允许写入状态和写入保护状态两种工作状态，所述控制电路用于控制所述第二存储器与所述第一存储器处于不同的工作状态，所述连接器用于在所述第一存储器进入允许写入状态时向所述第一存储器写入第一数据，并在所述第二存储器进入允许写入状态时，通过所述Mura补偿芯片向所述第二存储器写入第二数据。
  2. 如权利要求1所述的装置，其中，所述Mura补偿芯片包括第一通信接口，所述第一存储器包括第一读写接口及第一保护接口，所述连接器包括数据输入接口及读写控制接口；所述第一通信接口与所述第一读写接口连接；所述数据输入接口与所述第一通信接口及第一读写接口连接；所述读写控制接口与所述第一保护接口连接。
  3. 如权利要求2所述的装置，其中，所述Mura补偿芯片还包括第二通信接口，所述第二存储器包括第二读写接口及第二保护接口，所述第二通信接口与所述第二读写接口连接，所述读写控制接口通过所述控制电路与所述第二保护接口连接。
  4. 如权利要求3所述的装置，其中，所述控制电路包括晶体管、第一电阻及第二电阻，所述晶体管包括栅极、源极及漏极，所述栅极与所述读写控制接口连接；所述源极用于接入第一电平的控制信号；所述第一电阻一端与所述源极连接，另一端与所述读写控制接口连接；所述漏极与所述第二保护接口连接；所述第二电阻一端与所述漏极及所述第二保护接口连接，另一端接地。
  5. 如权利要求4所述的装置，其中，所述晶体管为P型金属-氧化物半导体场效应晶体管。
  6. 如权利要求3所述的装置，其中，所述第一读写接口用于向所述第一存储器写入所述第一数据；所述第一保护接口用于接入第一电平或第二电平的控制信号，当所述第一保护接口接入第一电平的控制信号时，所述第一存储器进入允许写入状态，当所述第一保护接口接入第二电平的控制信号时，所述第一存储器进入写入保护状态。
  7. 如权利要求6所述的装置，其中，当所述读写控制接口输出第一电平的控制信号时，所述第一存储器进入允许写入状态，所述第二存储器进入写入保护状态；所述数据输入接口输入第一数据，所述第一数据通过所述第一读写接口写入所述第一存储器。
  8. 如权利要求3所述的装置，其中，所述第二读写接口用于向所述第二存储器写入所述第二数据；所述第二保护接口用于接入第一电平或第二电平的控制信号，当所述第二保护接口接入第一电平的控制信号时，所述第二存储器进入允许写入状态，当所述第二保护接口接入第二电平的控制信号时，所述第二存储器进入写入保护状态。
  9. 如权利要求8所述的装置，其中，当所述读写控制接口输出第二电平的控制信号时，所述第一存储器进入写入保护状态，所述第二存储器进入允许写入状态；所述数据输入接口输入第二数据，所述第二数据通过所述第一通信接口传输到所述Mura补偿芯片，并由所述第二通信接口输出给所述第二读写接口，进而通过所述第二读写接口写入所述第二存储器。
  10. 一种Mura补偿数据写入方法，其中，所述方法包括：
    连接器的读写控制端口输出第一电平的控制信号，控制第一存储器进入允许写入状态；
    控制电路将所述第一电平的控制信号转换为第二电平的控制信号，控制所述第二存储器进入写入保护状态；
    连接器的数据输入接口输入第一数据，所述第一数据通过第一读写接口写入所述第一存储器；
    连接器的读写控制端口输出第二电平的控制信号，控制第一存储器进入写入保护状态；
    控制电路将所述第二电平的控制信号转换为第一电平的控制信号，控制所述第二存储器进入允许写入状态；
    连接器的数据输入接口输入第二数据，所述第二数据通过第一通信接口传输到Mura补偿芯片；
    所述Mura补偿芯片将所述第二数据通过第二通信接口输出给第二读写接口，并由所述第二读写接口写入所述第二存储器。
  11. 如权利要求10所述的方法，其中，所述Mura补偿芯片包括第一通信接口，所述第一存储器包括第一读写接口及第一保护接口，所述连接器包括数据输入接口及读写控制接口；所述第一通信接口与所述第一读写接口连接；所述数据输入接口与所述第一通信接口及第一读写接口连接；所述读写控制接口与所述第一保护接口连接。
  12. 如权利要求11所述的方法，其中，所述Mura补偿芯片还包括第二通信接口，所述第二存储器包括第二读写接口及第二保护接口，所述第二通信接口与所述第二读写接口连接，所述读写控制接口通过所述控制电路与所述第二保护接口连接，所述控制电路用于控制所述第二存储器与所述第一存储器处于不同的工作状态。
  13. 如权利要求12所述的方法，其中，所述控制电路包括晶体管、第一电阻及第二电阻，所述晶体管包括栅极、源极及漏极，所述栅极与所述读写控制接口连接；所述源极用于接入第一电平的控制信号；所述第一电阻一端与所述源极连接，另一端与所述读写控制接口连接；所述漏极与所述第二保护接口 连接；所述第二电阻一端与所述漏极及所述第二保护接口连接，另一端接地。
  14. 如权利要求13所述的方法，其中，所述晶体管为P型金属-氧化物半导体场效应晶体管。
  15. 如权利要求12所述的方法，其中，所述第一读写接口用于向所述第一存储器写入所述第一数据；所述第一保护接口用于接入第一电平或第二电平的控制信号，当所述第一保护接口接入第一电平的控制信号时，所述第一存储器进入允许写入状态，当所述第一保护接口接入第二电平的控制信号时，所述第一存储器进入写入保护状态。
  16. 如权利要求15所述的方法，其中，当所述读写控制接口输出第一电平的控制信号时，所述第一存储器进入允许写入状态，所述第二存储器进入写入保护状态；所述数据输入接口输入第一数据，所述第一数据通过所述第一读写接口写入所述第一存储器。
  17. 如权利要求12所述的方法，其中，所述第二读写接口用于向所述第二存储器写入所述第二数据；所述第二保护接口用于接入第一电平或第二电平的控制信号，当所述第二保护接口接入第一电平的控制信号时，所述第二存储器进入允许写入状态，当所述第二保护接口接入第二电平的控制信号时，所述第二存储器进入写入保护状态。
  18. 如权利要求17所述的方法，其中，当所述读写控制接口输出第二电平的控制信号时，所述第一存储器进入写入保护状态，所述第二存储器进入允许写入状态；所述数据输入接口输入第二数据，所述第二数据通过所述第一通信接口传输到所述Mura补偿芯片，并由所述第二通信接口输出给所述第二读写接口，进而通过所述第二读写接口写入所述第二存储器。
PCT/CN2015/097679 2015-11-11 2015-12-17 一种Mura补偿数据写入装置及方法 Ceased WO2017080014A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/905,239 US10276076B2 (en) 2015-11-11 2015-12-17 Mura offset data input device and method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510764877.2A CN105280149B (zh) 2015-11-11 2015-11-11 一种Mura补偿数据写入装置及方法
CN201510764877.2 2015-11-11

Publications (1)

Publication Number Publication Date
WO2017080014A1 true WO2017080014A1 (zh) 2017-05-18

Family

ID=55149049

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/097679 Ceased WO2017080014A1 (zh) 2015-11-11 2015-12-17 一种Mura补偿数据写入装置及方法

Country Status (3)

Country Link
US (1) US10276076B2 (zh)
CN (1) CN105280149B (zh)
WO (1) WO2017080014A1 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105957490B (zh) * 2016-07-13 2019-03-01 武汉华星光电技术有限公司 驱动电路及具有该驱动电路的液晶显示器
CN106960653A (zh) * 2017-04-25 2017-07-18 武汉精测电子技术股份有限公司 一种模组色斑修复装置及方法
CN106991987B (zh) * 2017-05-15 2019-10-11 深圳市华星光电技术有限公司 提升获取LCD面板原始mura准确度的方法
US10540942B2 (en) * 2017-08-25 2020-01-21 HKC Corporation Limited Optimization method and pre-stage device for brightness compensation
CN108008553A (zh) * 2017-11-22 2018-05-08 深圳市华星光电技术有限公司 一种Mura检测校正方法和系统
CN108538264B (zh) * 2018-04-04 2020-06-30 深圳市华星光电技术有限公司 显示面板的mura补偿方法及装置
KR102528980B1 (ko) * 2018-07-18 2023-05-09 삼성디스플레이 주식회사 표시 장치 및 이의 얼룩 보정 방법
US10969991B2 (en) * 2018-08-15 2021-04-06 Macronix International Co., Ltd. Multi-chip package, controlling method of multi-chip package and security chip
CN109272956B (zh) * 2018-11-06 2020-12-29 惠科股份有限公司 显示面板中存储单元的保护电路及显示装置
CN109637431B (zh) * 2019-02-25 2022-04-01 武汉天马微电子有限公司 一种显示面板的显示补偿方法
CN110930920B (zh) * 2019-11-21 2022-07-12 Tcl华星光电技术有限公司 一种显示装置及其驱动方法
CN114765015A (zh) * 2021-01-13 2022-07-19 敦泰电子股份有限公司 显示驱动电路系统

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090135211A1 (en) * 2007-11-26 2009-05-28 Tpo Displays Corp. Image displaying system and method for eliminating mura defect
CN103761933A (zh) * 2013-12-30 2014-04-30 深圳市华星光电技术有限公司 液晶显示面板的不良显示修复系统及修复方法
CN104992657A (zh) * 2015-07-27 2015-10-21 京东方科技集团股份有限公司 mura补偿模块和方法、显示装置和方法

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100606974B1 (ko) * 2004-08-09 2006-08-01 엘지.필립스 엘시디 주식회사 액정 표시 장치의 구동 회로
US7839409B2 (en) * 2004-10-18 2010-11-23 Ali Noorbakhsh Acquisition of extended display identification data (EDID) using inter-IC (I2C) protocol
KR101100335B1 (ko) * 2006-01-19 2011-12-30 삼성전자주식회사 표시장치
KR20070118371A (ko) * 2006-06-12 2007-12-17 삼성전자주식회사 디스플레이장치 및 그 제어방법
US7730253B2 (en) * 2006-11-27 2010-06-01 Research In Motion Limited System and method for controlling access to a memory device of an electronic device
TW200847087A (en) * 2007-05-18 2008-12-01 Beyond Innovation Tech Co Ltd Method and system for protecting information between a master terminal and a slave terminal
US20090083486A1 (en) * 2007-09-20 2009-03-26 Inventec Corpration Testing device of card reading interface and testing method thereof
US8890877B2 (en) * 2008-02-28 2014-11-18 Standard Microsystems Corporation Updating firmware in a display device using a serial bus
US7899967B2 (en) * 2008-11-24 2011-03-01 Mediatek Inc. Systems for accessing memory card and methods for accessing memory card by a control unit
TWI451424B (zh) * 2009-04-17 2014-09-01 Mstar Semiconductor Inc 應用於快閃記憶體之保護電路及電源系統
JP5530269B2 (ja) * 2010-06-28 2014-06-25 ラピスセミコンダクタ株式会社 通信インタフェース装置及び通信方法
US20110317067A1 (en) * 2010-06-29 2011-12-29 Ming-Han Hsieh Device having functions of high definition conversion and audio supporting
TW201218202A (en) * 2010-10-28 2012-05-01 Unigrand Ltd wherein the method includes setting a write-in prevention voltage and changing a system voltage to be higher or lower than the write-in prevention voltage
US8914569B2 (en) * 2011-02-24 2014-12-16 Winbond Electronics Corp. Flash memory apparatus with serial interface and reset method thereof
US8909852B1 (en) * 2011-12-30 2014-12-09 Google Inc. Disabling write protection on a serial peripheral interface chip
KR101923157B1 (ko) * 2012-02-22 2018-11-28 삼성전자주식회사 메모리 시스템 및 그것의 프로그램 방법
US9519164B2 (en) * 2012-06-08 2016-12-13 Apple Inc. Systems and methods for mura calibration preparation
US9761201B2 (en) * 2012-09-28 2017-09-12 Sharp Kabushiki Kaisha Liquid-crystal display device and drive method thereof
KR102025251B1 (ko) * 2012-10-31 2019-09-25 삼성전자주식회사 메모리 시스템 및 그것의 프로그램 방법
KR101957758B1 (ko) * 2012-11-06 2019-03-14 엘지디스플레이 주식회사 유기발광표시장치 및 그 구동방법
KR101958634B1 (ko) * 2012-12-13 2019-03-15 엘지디스플레이 주식회사 디스플레이 장치의 무라 검출 장치 및 방법
CN103107575B (zh) * 2013-01-18 2015-07-29 华为终端有限公司 充电方法、移动设备、充电设备与充电系统
CN103077692B (zh) * 2013-02-05 2015-09-09 深圳市华星光电技术有限公司 液晶显示器驱动方法及使用该方法的液晶显示控制电路
CN104679699A (zh) * 2013-11-26 2015-06-03 英业达科技有限公司 电子装置
KR102154186B1 (ko) * 2013-12-03 2020-09-10 삼성전자 주식회사 테스트 효율성을 향상한 타이밍 콘트롤러, 소스 드라이버, 디스플레이 구동회로 및 디스플레이 구동회로의 동작방법
KR20150078857A (ko) * 2013-12-31 2015-07-08 엘지디스플레이 주식회사 메모리 보호회로 및 이를 포함하는 액정표시장치
CN104064141B (zh) * 2014-06-12 2016-12-14 京东方科技集团股份有限公司 显示面板光学补偿装置、显示面板和光学补偿方法
JP2016004388A (ja) * 2014-06-16 2016-01-12 富士通株式会社 通信システム及び電子回路
CN204178073U (zh) * 2014-08-15 2015-02-25 宏祐图像科技(上海)有限公司 一种用于液晶显示面板二次开发的独用Mura修复架构
KR102285749B1 (ko) * 2014-11-10 2021-08-05 삼성전자주식회사 세마포어 기능을 갖는 시스템 온 칩 및 그것의 세마포어 구현 방법
KR20160065556A (ko) * 2014-12-01 2016-06-09 삼성전자주식회사 디스플레이 구동 집적 회로 및 이를 포함하는 디스플레이 장치

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090135211A1 (en) * 2007-11-26 2009-05-28 Tpo Displays Corp. Image displaying system and method for eliminating mura defect
CN103761933A (zh) * 2013-12-30 2014-04-30 深圳市华星光电技术有限公司 液晶显示面板的不良显示修复系统及修复方法
CN104992657A (zh) * 2015-07-27 2015-10-21 京东方科技集团股份有限公司 mura补偿模块和方法、显示装置和方法

Also Published As

Publication number Publication date
US20170256187A1 (en) 2017-09-07
CN105280149A (zh) 2016-01-27
CN105280149B (zh) 2017-11-17
US10276076B2 (en) 2019-04-30

Similar Documents

Publication Publication Date Title
WO2017080014A1 (zh) 一种Mura补偿数据写入装置及方法
CN107705769B (zh) 显示装置驱动系统及方法和显示装置
CN103137088B (zh) 用于驱动液晶显示设备的电路
KR101279124B1 (ko) 액정표시장치와 그 ｆｐｇａ 초기화 방법
US10262742B2 (en) Memory protection circuit and liquid crystal display including same
US8244925B2 (en) Circuit board and liquid crystal display includes changing EDID information
WO2021072806A1 (zh) 显示面板驱动装置及其配置方法
CN103514854B (zh) 公共电极电压补偿控制电路及方法、阵列基板、显示装置
KR101773354B1 (ko) Rgbw 동적 컬러 충실도 제어
CN106847224A (zh) Lcd面板数据烧录治具并联方法及系统
WO2016197408A1 (zh) 可进行插黑的显示装置
WO2019134610A1 (zh) 液晶显示装置及其驱动方法
TWI424422B (zh) 液晶顯示裝置及驅動該裝置的方法
WO2018010412A1 (zh) I2c传输电路及显示装置
KR20180043442A (ko) 표시 장치 및 이의 구동 방법
KR20160053076A (ko) 표시 장치 및 이의 구동 방법
US8587568B2 (en) Integrated circuit device, electronic apparatus and method for manufacturing of electronic apparatus
CN103927959B (zh) 显示装置的电压调节电路、显示装置
US20160275848A1 (en) Voltage output control system and voltage output system
CN101625846B (zh) 显示数据通道接口电路
KR20190095637A (ko) 액정 표시 패널 구동 방법 및 이를 채용한 액정 표시 장치
KR102149752B1 (ko) 메모리 제어회로 및 이를 포함하는 액정표시장치
WO2013159323A1 (zh) 一种液晶显示驱动模组、液晶显示装置及一种驱动方法
CN100399402C (zh) 有外部传输接口的时序控制器及应用该控制器的电子产品
KR101957296B1 (ko) 전원공급장치와 이를 구비한 액정표시장치, 및 전원공급방법

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14905239

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15908144

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15908144

Country of ref document: EP

Kind code of ref document: A1