WO2017079947A1 - 一种支持引脚交换的加法器布线方法 - Google Patents

一种支持引脚交换的加法器布线方法 Download PDF

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WO2017079947A1
WO2017079947A1 PCT/CN2015/094492 CN2015094492W WO2017079947A1 WO 2017079947 A1 WO2017079947 A1 WO 2017079947A1 CN 2015094492 W CN2015094492 W CN 2015094492W WO 2017079947 A1 WO2017079947 A1 WO 2017079947A1
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input
full adder
output
lookup table
adder
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PCT/CN2015/094492
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English (en)
French (fr)
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耿嘉
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京微雅格（北京）科技有限公司
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Priority to CN201580001650.0A priority Critical patent/CN107005240B/zh
Priority to PCT/CN2015/094492 priority patent/WO2017079947A1/zh
Publication of WO2017079947A1 publication Critical patent/WO2017079947A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components

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  • the present invention relates to the field of integrated circuit technology, and in particular, to an adder wiring method that supports pin swap.
  • FPGA Field-Programmable Gate Array
  • FIG. 1 is a schematic diagram of a logical structure of a full adder in the prior art.
  • the full adder includes a lookup table LUT (Look-Up Table), a gate and an exclusive OR gate. That is to say, the full adder in the prior art is composed of a lookup table and an adder.
  • LUT Look-Up Table
  • the present invention provides an adder wiring method supporting pin swap, characterized in that the method comprises: locking a full adder, and determining that at least one input of the full adder needs to be received from outside the PLB Input signal; determining whether the first lookup table has an unused input; in some cases, exchanging input signals from outside the PLB to unused inputs of the first lookup table; and connecting the output of the lookup table At least one input to the full adder.
  • the output of the lookup table is mapped to an input that is not used by the lookup table.
  • the lookup table is a multiple output lookup table, and the lookup table includes a plurality of lookup tables that are single output independent inputs.
  • the input pins of the lookup table can be interchanged, and the input end is outputted by the output end corresponding to the input end.
  • the output signal output by the lookup table is the same as the input signal of the full adder accessed by the lookup table.
  • the wiring method provided by the embodiment of the present invention extends the pin-switching technology to the full adder based on the C1 chip architecture.
  • the logic resources are saved, and the chip utilization rate is effectively improved.
  • the pin-interchange technology improves the bypass and fmax of the full adder, as well as the full adder.
  • the path of the selectable wiring expands the solution space of the wiring and reduces the overall power consumption of the chip.
  • FIG. 1 is a schematic diagram of a logical structure of a full adder in the prior art
  • FIG. 2 is a schematic structural diagram of a programmable logic module in a C1 architecture according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a full adder according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a pin swapping process of the full adder of FIG. 3;
  • Figure 5 is a schematic structural view of the lookup table LUT1 of Figure 1;
  • FIG. 6 is a schematic structural diagram of a five-input and two-output lookup table according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a combination of an input end of a full adder and a lookup table according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of another combination of an input end of a full adder and a lookup table according to an embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a combination of two input ends and a lookup table of a full adder according to an embodiment of the present invention.
  • C1 is the first chip in the cloud series in the FPGA chip, mainly used in the field of high-speed communication. As shown in FIG.
  • the a1 end of the full adder ADD1 can input the signal m accessed from outside the PLB, the signal n from the output of the front LUTx, or The constant 0/1 of the access; the b1 input can input the signal k that is f5 from the outside of the PLB, the signal p of the xy output of the front LUT, or the access constant 1: it can be seen that only a small number of input signals are externally connected from the PLB. In, that is, only a small number of winding paths can be accessed from the XBAR, so the more cumbersome winding method will affect the operating frequency of the overall module.
  • the following describes an adder wiring method based on the support of the FPGA chip in the FPGA chip provided by the present invention.
  • FIG. 3 is a schematic diagram of a logical structure of a full adder according to an embodiment of the present invention.
  • the full adder in the embodiment includes an exclusive OR gate A, an exclusive OR gate B and a gate, and the input signal enters the full adder through the input pins a and b of the exclusive OR gate A, when the input pins a and b
  • the input signal of the gate strobe input pin a is used as the output signal of the carry output c1, that is, the condition of the gate strobe a is the output of the exclusive OR gate is 0; when the input pins a and b
  • the full adder in this embodiment does not need to use the LUT to drive each logic gate, and the chip is effectively improved due to the small chip use area of each logic gate in the
  • the input control pin of the LUT in front of the full adder has no more than four input pins
  • the input signal of one of the input terminals (such as port a) of the full adder can be connected to the LUT.
  • the unused input port drives the full adder through the output port of the LUT.
  • any two single-output and independent inputs can be used, and the total number of pins is less than five.
  • the look-up table is packaged. During the packaging process, the mask value of the corresponding pin port needs to be modified according to the design requirements. .
  • the lookup table in the C1 architecture is described in detail below by taking two identical five-input single-output lookup tables as an example.
  • FIG. 5 is a schematic structural view of the lookup table LUT1 of FIG. 1.
  • the LUT 1 includes two identical five-input single-output lookup tables lut_0 and lut_1, a strobe A, and a strobe B.
  • the lookup table LUT1 includes two sets of input pins f[5] and f[4:0], and an output pin x and an output pin xy. Among them, the input pin f[5] corresponds to the highest address.
  • the gate A strobe configuration 1 is used to select two internal inputs of lut_1 and lut_0. Find the output of the table.
  • LUT1 in the embodiment is a combination of two single output independent input lookup tables into one two output Look up the table and modify the mask value of the corresponding pin.
  • FIG. 6 is a schematic structural diagram of a five-input two-output lookup table according to an embodiment of the present invention.
  • the same input pin of the lut_0 and lut_1 input pins f[4:0] is connected to the same input signal, so that LUT1 is changed.
  • gate A strobes configuration 0 is not used.
  • the LUT1 internal lookup table receives no more than four input pins of the control signal
  • the input signal of one of the input terminals (such as port a) of the full adder can be connected.
  • changing the mask value of the unused port of LUT1, so that the corresponding output terminal outputs the input signal of the original full adder; changing the mask value of LUT1 can determine the output port of the output signal.
  • FIG. 7 is a schematic structural diagram of a combination of an input end of a full adder and a lookup table according to an embodiment of the present invention.
  • the input signal of the input end of the full adder a is m
  • the input signal of the b input end is n
  • the F0-F3 port of the LUT1 receives the control signal
  • the F4 port is not used
  • the output signal is output by the output terminal xy.
  • the output terminal x of the LUT1 outputs the original input signal m, and drives the full adder to operate.
  • the output terminal xy outputs the output signal of the F0-F3 port operation, the output terminal x outputs the output signal of the F4 port operation, or the output terminal x outputs the F0.
  • the output signal of the F3 port is running, and the output terminal xy is outputting the output signal of the F4 port operation.
  • the input signal of the F4 port is the same as its output signal; by changing the mask value, the pins of the LUT1 input port F0-F4 can be interchanged.
  • FIG. 8 is a schematic structural diagram of another combination of an input end of a full adder and a lookup table according to an embodiment of the present invention.
  • the pins of the input of the full adder a and the pins of the b input are interchangeable.
  • the input signal of the input end of the full adder a is m
  • the input signal of the input end of the b is n.
  • the input signal of the input end of the input terminal is n
  • the input signal of the input end of the b is m.
  • the F0-F3 port of LUT1 receives the control signal, its F4 port is not used, and the output signal is output by the output terminal xy.
  • the pin of the input of the full adder a is connected to the LUT1.
  • the output terminal x is placed on the pin, and the input signal is changed to be input by the F4 port of the LUT1.
  • the output terminal x of the LUT1 is outputted to output the original input signal m, and the full adder is driven to work.
  • the output terminal xy outputs the output signal of the F0-F3 port operation, the output terminal x outputs the output signal of the F4 port operation, or the output terminal x outputs the output signal of the F0-F3 port operation, and the output terminal xy outputs the output signal of the F4 port operation.
  • FIG. 9 is a schematic structural diagram of a combination of two input ends and a lookup table of a full adder according to an embodiment of the present invention.
  • the pins of the input of the full adder a and the pins of the b input are interchangeable. Changing the mask value of the input port of LUT1 allows the output signal to be equal to the input signal.
  • the LUT1 in front of the full adder is not used as a whole, the LUT1 has no input and no output at this time, and the input signals of the input of the full adder a and the input of the b input can be input through any two input ports of the F0-F4 port of the LUT1. Or input by the F0-F4 port resource sharing, and output the output signal to the full adder through the output terminal x and the output terminal xy of the LUT1.
  • the wiring method provided by the embodiment of the present invention extends the pin-switching technology to the full adder based on the C1 chip architecture.
  • the logic resources are saved, and the chip utilization rate is effectively improved.
  • the pin-interchange technology improves the bypass and fmax of the full adder, as well as the full adder.
  • the path of the selectable wiring expands the solution space of the wiring and reduces the overall power consumption of the chip.
  • the steps of the method or algorithm described in connection with the embodiments disclosed herein may be implemented in hardware, processing The software module executed by the device, or a combination of the two.
  • the software module can be placed in random access memory (RAM), memory, read only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or technical field. Any other form of storage medium known.

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Abstract

一种支持引脚交换的加法器布线方法，该方法包括：锁定全加器，并且确定全加器中的至少一个输入端需要接收来自PLB外的输入信号（m）；确定第一查找表（LUT1）是否有未使用的输入端（F4）；在有的情况下，将来自PLB外的输入信号（m）交换到第一查找表（LUT1）未使用的输入端（F4）；并且将查找表的输出端（x）连接到全加器中的至少一个输入端（a）。该布线方法是基于C1的芯片架构把引脚交换技术延伸到全加器上，通过使用全加器节省了逻辑资源，有效的提高了芯片利用率，同时借助全加器的两输入端口引脚的可互换性与前端LUT的未使用的输入输出端口，并通过引脚互换技术提高了全加器的绕通性与fmax，以及全加器可选择布线的通路扩大了布线的解空间，降低了芯片整体功耗。

Description

一种支持引脚交换的加法器布线方法 技术领域
本发明涉及集成电路技术领域，尤其涉及一种支持引脚交换的加法器布线方法。
背景技术
现场可编程门阵列(Field－Programmable Gate Array，FPGA)是一种具有丰富硬件资源、强大并行处理能力和灵活可重配置能力的逻辑器件。这些特征使得FPGA在数据处理、通信、网络等很多领域得到了越来越多的广泛应用。
加法作为一种基本运算，大量运用在数字信号处理和数字通信的各种算法中。由于加法器使用频繁，因此其速度往往影响着整个系统的运行速率。在FPGA内部，加法器通常由进位链(carry chain)实现。图1为现有技术中全加器的逻辑结构示意图，如图1所示，该全加器包括查找表LUT(Look-Up Table)，选通器和异或门。也就是说，现有技术中的全加器是由查找表和加法器组成的。
在FPGA芯片中，由于FPGA芯片和该全加器的硬件架构的限制，通常只有比较少的绕线通路可以从XBAR连接过来，使输入信号的数量产生局限性，同时也会增加布线时的复杂度，降低布线的成功率。
因此，设计一种优选的布线方式，提高可布通路，从而提升布局布线成功率的方法，是亟待解决的问题。
发明内容
为实现上述目的，本发明提供了一种支持引脚交换的加法器布线方法，其特征在于，该方法包括：锁定全加器，并且确定全加器中的至少一个输入端需要接收来自PLB外的输入信号；确定第一查找表是否有未使用的输入端；在有的情况下，将来自PLB外的输入信号交换到第一查找表未使用的输入端；并且将查找表的输出端连接到所述全加器中的至少一个输入端。
进一步的，查找表的输出端与查找表未使用的输入端相映射。
进一步的，查找表是一个多输出查找表，查找表包括多个单输出独立输入的查找表。
进一步的，通过修改查找表中输入端的掩码值，查找表的输入端引脚可进行互换，同时将输入端由输入端对应的输出端输出。
进一步的，所述查找表输出的所述输出信号与所述查找表接入的所述全加器的所述输入信号相同。
本发明实施例提供的布线方法是基于C1的芯片架构把引脚交换技术延伸到全加器上，通过使用实施例中的全加器，节省了逻辑资源，有效的提高了芯片利用率，同时借助全加器的两输入端口引脚的可互换性与前端LUT的未使用的输入输出端口，并通过引脚互换技术，提高了全加器的绕通性与fmax，以及全加器可选择布线的通路扩大了布线的解空间，降低了芯片整体功耗。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为现有技术中全加器的逻辑结构示意图；
图2为本发明实施例提供的C1架构中可编程逻辑模块的结构示意图；
图3为本发明实施例提供的全加器逻辑结构示意图；
图4为图3中全加器的引脚互换过程示意图；
图5为图1中查找表LUT1的结构示意图；
图6为本发明实施例提供的一种五输入两输出查找表的结构示意图
图7为本发明实施例提供的一种全加器一输入端与查找表组合的结构示意图；
图8为本发明实施例提供的另一种全加器一输入端与查找表组合的结构示意图；
图9为本发明实施例提供的一种全加器的两输入端与查找表组合的结构示意图。
具体实施方式
下面通过附图和实施例，对本发明的技术方案做进一步的详细描述。
本发明下述实施例中的方法是基于FPGA芯片中cloud系列第一款芯片C1实现的。图2为本发明实施例提供的C1架构中可编程逻辑模块的结构示意图。C1是FPGA芯片中cloud系列的第一款芯片，主要用于高速通信领域。如图2所示，在PLB(Programmable Logic Block，可编程逻辑模块,)的结构中，全加器ADD1的a1端能输入从PLB外接入的信号m、从前方LUTx输出端的信号n，或者接入的常数0/1；其b1输入端能输入f5从PLB外接入的信号k、前方LUT的xy输出的信号p，或者接入常数1：可见只有较少的输入信号从PLB外接入，也就是说只有较少的绕线通路可以从XBAR接入进来，这样较繁琐的绕线方式会影响到整体模块的工作频率。
下面通过实施例，对本发明提供的基于FPGA芯片内支持引脚交换的加法器布线方法加以说明。
图3为本发明实施例提供的全加器逻辑结构示意图。如图3所示，本实 施例中的全加器包括异或门A、异或门B和选通器，输入信号通过异或门A的输入引脚a与b进入全加器，当输入引脚a与b上的输入信号相同时，选通器选通输入引脚a的输入信号作为进位输出c1的输出信号，即选通器选通a的条件为异或门的输出为0；当输入引脚a与b上的输入信号不同时，选通器选通前级进位c0的信号作为进位输出c1的输出信号。与上述图2所示的全加器相比较，本实施例中的全加器不需要使用LUT来驱动各个逻辑门，并且由于结构中各个逻辑门的芯片使用面积较少，有效的提高了芯片利用率。
由图3中全加器的结构图可知，输入端引脚a的和输入端引脚b是完全等价的，可进行类似于LUT的引脚互换，如图4所示，该过程为实施例全加器的引脚互换过程。
由于C1架构的结构限制，当全加器前面的LUT的接收控制信号的输入引脚不多于4个时，可将全加器其中一个输入端(如a端口)的输入信号，连接到LUT未使用的输入端口，再通过LUT的输出端口驱动全加器。对于C1架构中五输入两输出的LUT可由任意两个单输出且独立输入，同时引脚总数不超过五个的查找表打包形成，打包过程中需要根据设计需要修改相应引脚端口的掩码值。
下面以两个相同的五输入单输出的查找表为例，对C1架构中的查找表进行详细说明。
图5为图1中查找表LUT1的结构示意图。如图5所示，LUT1包括两个相同的五输入单输出的查找表lut_0和lut_1、选通器A和选通器B。结合图2所示的C1的架构，查找表LUT1包括f[5]和f[4:0]两组输入引脚，以及输出引脚x和输出引脚xy。其中，输入引脚f[5]对应的是最高位地址，当LUT1作为六输入一输出的查找表使用时，选通器A选通配置1端，用来选择内部lut_1与lut_0两个五输入查找表的输出结果。
需要说明的是，为了节省逻辑资源，提高芯片的最高工作频率fMax。实施例中的LUT1是通过将两个单输出独立输入的查找表打包合并为一个两输出 查找表，同时修改相应引脚的掩码值。
图6为本发明实施例提供的一种五输入两输出查找表的结构示意图。如图6所示，通过改变掩码值，在图5所示的LUT1中，将lut_0和lut_1输入引脚f[4:0]中相同的输入引脚接入相同的输入信号，使LUT1变成一个五输入两输出的查找表，由于选通器A选通配置0端，此时f[5]不使用。
结合图3和图6所示的结构，当LUT1内部查找表接收控制信号的输入引脚不多于4个时，可将全加器其中一个输入端(如a端口)的输入信号，接入到LUT1未使用的端口，再通过LUT1的相应的输出端口驱动全加器。其中，改变LUT1未使用端口的掩码值，使相应输出端输出原全加器接入的输入信号；改变LUT1的掩码值可决定输出信号的输出端口。
图7为本发明实施例提供的一种全加器一输入端与查找表组合的结构示意图。如图7所示，全加器a输入端的输入信号为m，b输入端的输入信号为n，LUT1的F0-F3端口接收控制信号，其F4端口未被使用，输出信号由输出端xy输出。在这种情况下，将全加器a输入端的引脚连接到LUT1的输出端x的引脚上，将输入信号为m改由LUT1的F4端口输入，通过修改F4端口的掩码值，实现LUT1的输出端x输出原输入信号m，驱动全加器进行工作，其中，输出端xy输出F0-F3端口运行的输出信号，输出端x输出F4端口运行的输出信号，或者输出端x输出F0-F3端口运行的输出信号，输出端xy输出F4端口运行的输出信号。需要说明的是，F4端口的输入信号与其输出信号相同；通过改变掩码值，LUT1输入端口F0-F4的引脚可以进行互换。
图8为本发明实施例提供的另一种全加器一输入端与查找表组合的结构示意图。由图8结合图3可知，全加器a输入端的引脚与b输入端的引脚可互换。全加器a输入端的输入信号为m，b输入端的输入信号为n，a输入端的引脚和b输入端的引脚互换后，a输入端的输入信号为n，b输入端的输入信号为m，LUT1的F0-F3端口接收控制信号，其F4端口未被使用，输出信号由输出端xy输出，在这种情况下，将全加器a输入端的引脚连接到LUT1的 输出端x放入引脚上，将输入信号为m改由LUT1的F4端口输入，通过修改F4端口的掩码值，实现LUT1的输出端x输出原输入信号m，驱动全加器进行工作，输出端xy输出F0-F3端口运行的输出信号，输出端x输出F4端口运行的输出信号，或者输出端x输出F0-F3端口运行的输出信号，输出端xy输出F4端口运行的输出信号。。
图9为本发明实施例提供的一种全加器的两输入端与查找表组合的结构示意图。由图9结合图7和图8可知，全加器a输入端的引脚与b输入端的引脚可互换。改变LUT1的输入端口的掩码值可实现输出信号与输入信号相等。当全加器前面的LUT1整体未被使用时，此时LUT1无输入无输出，可将全加器a输入端和b输入端的输入信号都通过LUT1的F0-F4端口中任意两输入端端口输入或由F0-F4端口资源共享的方式输入，并通过LUT1的输出端x和输出端xy输出，将输出信号输入到全加器。
本发明实施例提供的布线方法是基于C1的芯片架构把引脚交换技术延伸到全加器上，通过使用实施例中的全加器，节省了逻辑资源，有效的提高了芯片利用率，同时借助全加器的两输入端口引脚的可互换性与前端LUT的未使用的输入输出端口，并通过引脚互换技术，提高了全加器的绕通性与fmax，以及全加器可选择布线的通路扩大了布线的解空间，降低了芯片整体功耗。
专业人员应该还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
结合本文中所公开的实施例描述的方法或算法的步骤可以用硬件、处理 器执行的软件模块，或者二者的结合来实施。软件模块可以置于随机存储器(RAM)、内存、只读存储器(ROM)、电可编程ROM、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、CD-ROM、或技术领域内所公知的任意其它形式的存储介质中。
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施方式而已，并不用于限定本发明的保护范围，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (5)

  1. 一种支持引脚交换的加法器布线方法，其特征在于，所述方法包括：
    锁定全加器，并且确定全加器中的至少一个输入端需要接收来自PLB外的输入信号；
    确定第一查找表是否有未使用的输入端；
    在有的情况下，将所述来自PLB外的输入信号交换到所述第一查找表未使用的所述输入端；并且将所述第一查找表的输出端连接到所述全加器中的所述至少一个输入端。
  2. 根据权利要求1所述的方法，其特征在于，所述第一查找表的所述输出端与所述第一查找表未使用的所述输入端相映射。
  3. 根据权利要求1所述的方法，其特征在于，所述第一查找表是一个多输出查找表，所述第一查找表包括多个单输出独立输入的查找表。
  4. 根据权利要求2所述的方法，其特征在于，通过修改所述第一查找表中所述输入端的掩码值，所述第一查找表的所述输入端引脚可进行互换，同时将所述输入端由所述输入端对应的输出端输出。
  5. 根据权利要求1所述的方法，其特征在于，所述第一查找表输出的所述输出信号与所述第一查找表接入的所述全加器的所述输入信号相同。
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