WO2017067351A1

WO2017067351A1 - Black level cancellation method and system, and image sensor having system

Info

Publication number: WO2017067351A1
Application number: PCT/CN2016/098893
Authority: WO
Inventors: 裴学用; 郭先清
Original assignee: 比亚迪股份有限公司
Priority date: 2015-10-23
Filing date: 2016-09-13
Publication date: 2017-04-27
Also published as: CN106612402B; CN106612402A

Abstract

Disclosed is a black level cancellation method, comprising: receiving a first level signal and a second level signal that are outputted by an effective pixel unit; starting first counting when receiving the first level signal and a ramp signal, and stopping the first counting when the amplitude of the ramp signal is equal to that of the first level signal, to obtain a first count value; performing timing when receiving the second level signal and the ramp signal, starting second counting after delaying for the preset quantity of clock periods, and stopping the second counting when the amplitude of the ramp signal is equal to that of the second level signal, to obtain a second count value, wherein the preset quantity is a black level value of a non-luminous pixel unit; and obtaining a digital signal according to the first count value and the second count value. The method cancels a black level during conversion of a second level signal, and saves the time needed by subtracting a black level value from an analysis result of an effective pixel unit in a digital circuit.

Description

Black level elimination method, system and image sensor having the same

Cross-reference to related applications

The present application claims the priority of the Chinese Patent Application No. 20151069818, filed on Jan. 23, 2015, the entire disclosure of which is hereby incorporated by reference.

Technical field

The present invention relates to the field of image processing technologies, and in particular, to a black level cancellation method, a black level cancellation system, and an image sensor having a black level cancellation system.

Background technique

Since CIS (CMOS Image Sensors) have low power consumption and can integrate sensors and processing circuits on the same chip, they are increasingly used in image processing.

Generally, the CIS is composed of a pixel unit array and corresponding processing circuits, and the pixel units in the pixel unit array convert the optical signals into electrical signals and transmit them to corresponding processing circuits for processing. Among them, the pixel unit array is generally divided into three categories: dummy pixel, dark pixel, and active pixel, and the virtual pixel unit is used to reduce process error, and is used for a matte pixel unit. The noise of the pixel unit is simulated under the absence of light, and the effective pixel unit is an effective pixel unit.

In the image processing process, usually in one frame image, all the signals of the matte pixel unit are first parsed, and the average of the parsing results of all the matte pixel unit signals is calculated to obtain the black level value (Black) Level), then subtracting the black level value when parsing the signal of the effective pixel unit to eliminate a part of the noise caused by the effective pixel unit.

In the related art, the black level is removed by averaging the signal analysis results of all the matte pixel units to obtain a black level value, and storing the black level value. Then, the signals of all the effective pixel units are parsed, and the parsing result is stored. Further, the analysis result of the effective pixel unit signal is subtracted from the black level value in the digital circuit to remove the black level. However, since it takes a certain time to subtract the analysis result of the effective pixel unit signal from the black level value in the digital circuit, the conventional method of removing the black level has a relatively slow processing speed.

Summary of the invention

The present invention aims to solve at least one of the technical problems in the related art to some extent. Accordingly, it is an object of the present invention to provide a black level erasing method which subtracts a black level value during the conversion of the second level signal, thereby eliminating the level signal conversion while achieving Black level, eliminating the need for effective implementation in digital circuits The time required for the resolution of the pixel unit to be subtracted from the black level value.

Another object of the present invention is to provide a black level cancellation system. It is still another object of the present invention to provide an image sensor.

In order to achieve the above object, a black level erasing method according to an embodiment of the present invention includes the following steps: receiving a level signal output by an effective pixel unit, wherein a level signal output by the effective pixel unit includes a a level signal and a second level signal; starting the first counting when the first level signal and the ramp signal are received, and when the amplitude of the ramp signal is the first level signal Stopping the first count when the amplitudes are equal, obtaining a first count value; timing when receiving the second level signal and the ramp signal, and starting after delaying a predetermined number of clock cycles Secondary counting, and stopping the second counting when the amplitude of the ramp signal is equal to the amplitude of the second level signal, to obtain a second count value, wherein the predetermined number is matte a black level value of the pixel unit; and a digital signal corresponding to an output signal of the effective pixel unit after the black level is removed according to the first count value and the second count value.

In the black level elimination method of the embodiment of the present invention, the black level value is used as the number of cycles of the delayed clock cycle. When the signal signal output by the effective pixel unit is converted, the control terminal CNT_Syn that starts counting is compared with the counter. The control terminal Ramp_En of the ramp signal output from the ramp generator is delayed by a predetermined number of clock cycles to subtract the black level value during the conversion of the signal signal, thereby eliminating the conversion of the signal signal. The black level eliminates the time required to subtract the resolution result of the effective pixel unit from the black level value and then subtract it in the digital circuit.

In order to achieve the above object, a black level cancellation system according to another embodiment of the present invention includes: a receiving module, configured to receive a level signal output by an effective pixel unit, wherein a level signal output by the effective pixel unit a first level signal and a second level signal; a ramp generator for generating a ramp signal based on the ramp control signal; a comparator for using the amplitude of the ramp signal and the first And outputting a count stop signal when the amplitudes of the flat signals are equal and the amplitude of the ramp signal is equal to the amplitude of the second level signal; and the counter is configured to receive the first count control signal and the second count respectively When the signal is controlled, the counting starts, and when the counting stop signal is received, the counting is stopped, and the corresponding first counting value and the second counting value are obtained, and the blackening is obtained according to the first counting value and the second counting value. a digital signal corresponding to an output signal of the effective pixel unit after the level; a controller configured to generate the ramp control signal, and receive the first level signal and the Generating the first count control signal when the wave signal is received, and generating the second count control after delaying a predetermined number of clock cycles when the comparator receives the second level signal and the ramp signal a signal, wherein the predetermined number is a black level value of the matte pixel unit.

In the black level elimination system of the embodiment of the present invention, the black level value is used as the number of cycles of the delayed clock cycle. When the signal signal output by the effective pixel unit is converted, the control terminal CNT_Syn that starts counting the counter is compared with The control terminal Ramp_En of the ramp signal output from the ramp generator is delayed by a predetermined number of clock cycles to The black level value is subtracted during the conversion of the signal signal, thereby realizing the elimination of the black level while the signal signal is being converted, eliminating the need to store the analysis result of the effective pixel unit and the black level value in the digital circuit. The time required to subtract.

Furthermore, embodiments of the present invention also propose an image sensor comprising the black level cancellation system described above.

Furthermore, embodiments of the present invention also provide a computer readable storage medium comprising computer instructions that, when executed, cause the black level cancellation method to be performed.

In the image sensor of the embodiment of the present invention, the black level value is used as the number of cycles of the delayed clock cycle, and when the signal signal output from the effective pixel unit is converted, the control terminal CNT_Syn that starts counting from the counter is compared with the ramp generator. The control terminal Ramp_En at which the output ramp signal starts to fall is delayed by a predetermined number of clock cycles to subtract the black level value during the conversion of the signal signal, thereby realizing the elimination of the black level while the signal signal is being converted. The time required to subtract the analysis result of the effective pixel unit from the black level value and subtract it in the digital circuit is omitted.

DRAWINGS

1 is a flow chart of a method of eliminating a black level according to an embodiment of the present invention;

The topology of an analog to digital converter for each column of effective pixel cells in a pixel cell array is shown in FIG. 2;

3 is a timing diagram of parsing signals of effective pixel cells in accordance with one embodiment of the present invention;

4 is a flow chart of a black level removal method in accordance with an embodiment of the present invention;

5 is a timing diagram of parsing signals of a matte pixel unit, in accordance with one embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a black level erasing system according to an embodiment of the present invention.

detailed description

The embodiments of the present invention are described in detail below, and the examples of the embodiments are illustrated in the drawings, wherein the same or similar reference numerals are used to refer to the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the drawings are intended to be illustrative of the invention and are not to be construed as limiting.

A black level erasing method, a black level canceling system, and an image sensor having the black level canceling system according to an embodiment of the present invention will be described below with reference to the accompanying drawings.

1 is a flow chart of a method of eliminating black levels in accordance with an embodiment of the present invention. As shown in FIG. 1, the method for eliminating the black level includes the following steps:

S1. Receive a level signal output by the effective pixel unit, wherein the level signal includes a first level signal and a second level signal.

Specifically, when parsing the signal of the effective pixel unit, in order to eliminate the fixed mode caused by the effective pixel unit Noise PFN, CIS generally needs to use the double sampling technique, which is simply to analyze the level signals of the two effective pixel unit outputs, that is, the first level signal and the second level signal. Wherein, the first level signal is a reset signal (abbreviated as Vr), the second level signal is a signal signal (abbreviated as Vs), and the difference between the signal signal and the reset signal (Vs-Vr) is an effective pixel unit. output signal.

S2, starting the first counting when receiving the first level signal and the ramp signal, and stopping the first counting when the amplitude of the ramp signal is equal to the amplitude of the first level signal, obtaining the first count value.

Specifically, the analog-to-digital converter ADC is configured to convert a level signal output by the effective pixel unit into a digital signal to generate an image. For example, a column-level analog-to-digital converter (column level ADC) may be employed, wherein, preferably, a single-slope column-level analog-to-digital converter may be employed, and since the structure of the single-slope column-level analog-to-digital converter is simple and easy to implement, during image processing This analog to digital converter is usually used.

In particular, the topology of an analog to digital converter for each column of effective pixel cells in a pixel cell array is shown in FIG. As shown in FIG. 2, the effective pixel unit outputs a reset signal Vr and a signal signal Vs. All the effective pixel units in the pixel unit array share a ramp generator, and the ramp generator is used to output the ramp signal Vramp. Ramp_En is a control signal for the ramp signal Vramp to start falling, and the ramp signal Vramp starts to fall when the rising edge of the Ramp_En signal comes. The comparator is used to compare the level signal Vout (Vr/Vs) outputted by the effective pixel unit with the magnitude (amplitude) of the ramp signal Vramp, and the magnitude of the ramp signal Vramp and the level signal Vout (Vr/Vs) When they are equal, the output signal is inverted. The counter is used to quantize the fall time required for the ramp signal Vramp to be equal in magnitude to the level signal Vout (Vr/Vs), expressed as a binary value. CNT_Syn is the control signal for the counter to start counting, and the counter starts counting when the rising edge of the CNT_Syn signal comes. CNT_Clk provides a clock signal to the counter. The latch is used to latch the output result of the counter, wherein the level signal Vout output by the effective pixel unit is the first level signal Vr or the second level signal Vs.

As shown in FIG. 3, in the embodiment of the present invention, when parsing the signal of the effective pixel unit, first, the effective pixel unit outputs a reset signal Vr, and the ramp generator outputs a ramp signal Vramp, and the ramp wave occurs at this time. The ramp signal Vramp output by the device is its initial voltage Vramp_ini. Then, when the first rising edge of the Ramp_En signal occurs, the ramp signal Vramp begins to fall, and when the first rising edge of the CNT_Syn signal occurs, the counter starts counting. Then, when the ramp signal Vramp falls to the same level as the reset signal Vr, the counter stops counting. At this time, the reset signal Vr is converted, and the counter obtains the first count value.

S3, timing when receiving the second level signal and the ramp signal, and starting the second counting after delaying a predetermined number of clock cycles, and when the amplitude of the ramp signal and the amplitude of the second level signal When the second time is equal, the second count is stopped, and the second count value is obtained, wherein the predetermined number is the black level value of the matte pixel unit.

Specifically, as shown in FIG. 3, after the conversion of the reset signal Vr is completed, the effective pixel unit outputs the signal signal Vs, and the ramp signal Vramp outputted by the ramp generator returns to its initial voltage Vramp_ini. Then at When the second rising edge of the Ramp_En signal occurs, the ramp signal Vramp begins to fall, and after a delay of n clock cycles, the second rising edge of the CNT_Syn signal appears and the counter starts counting. The number n of delayed clock cycles is a black level value obtained by calculating an average value from the analysis result of the matte pixel unit. Further, when the ramp signal Vramp falls to be equal to the magnitude of the signal signal Vs, the counter stops counting. At this point, the signal signal Vs conversion is completed, and the counter obtains the second count value.

It should be understood that the manner of calculating the black level value can be implemented in an existing manner, and in order to avoid redundancy, it is not duplicated here.

S4. Obtain a digital signal corresponding to an output signal of the effective pixel unit after the black level is removed according to the first count value and the second count value.

Specifically, the counter is further configured to calculate a difference between the conversion result of the signal signal Vs and the conversion result of the reset signal Vr, that is, calculate a difference between the second count value and the first count value, and at this time, the switch S is turned on, and the The difference between the second count value and the first count value is written into the latch.

In the black level erasing method of the embodiment of the present invention, the black level value is used as the number of periods of the delayed clock period, and when the signal signal output from the effective pixel unit is converted, the control signal CNT_Syn at which the counter starts counting is compared with The control signal Ramp_En of the ramp signal output from the ramp generator is delayed by a predetermined number of clock cycles to subtract the black level value during the conversion of the signal signal, thereby eliminating the signal signal conversion while eliminating The black level eliminates the time required to subtract the resolution result of the effective pixel unit from the black level value and then subtract it in the digital circuit.

4 is a flow chart of a black level cancellation method in accordance with an embodiment of the present invention. As shown in FIG. 4, before the step S1, steps S5 and S6 may be further included; specifically, the black level elimination method includes the following steps:

S5. Receive a level signal output by the matte pixel unit, and convert the level signal output by the matte pixel unit into a digital signal of the matte pixel unit.

Specifically, when parsing the level signal of the matte pixel unit, it is also necessary to parse the level signal of the output of the matte pixel unit twice. For convenience of explanation, the third level signal output by the matte pixel unit is simply abbreviated as Vr', the fourth level signal output by the matte pixel unit is abbreviated as Vs'.

In particular, the topology of the analog to digital converter shown in Figure 2 is equally applicable to matte pixel units. As shown in Fig. 2, the matte pixel unit outputs a reset signal Vr' and a signal signal Vs'. All the matte pixel units in the pixel unit array share a ramp generator, and the ramp generator is used to output the ramp signal Vramp. Ramp_En is a control signal for the ramp signal Vramp to start falling, and the ramp signal Vramp starts to fall when the rising edge of the Ramp_En signal comes. The comparator is used to compare the level signal Vout' (Vr'/Vs') outputted by the matte pixel unit with the magnitude (amplitude) of the ramp signal Vramp, and the ramp signal Vramp and the level signal Vout' (Vr) When '/Vs' is equal, the output signal is inverted. The counter is used to quantize the ramp signal Vramp and the level signal Vout' (Vr'/Vs') The fall time required to be equal in size, expressed as a binary value. CNT_Syn is the control signal for the counter to start counting, and the counter starts counting when the rising edge of the CNT_Syn signal comes. CNT_Clk provides a clock signal to the counter. The latch is used to latch the output of the counter. The level signal Vout' outputted by the matte pixel unit is the third level signal Vr' or the fourth level signal Vs'.

As shown in FIG. 5, in the embodiment of the present invention, when parsing the signal of the matte pixel unit, first, the matte pixel unit outputs a reset signal Vr', and the ramp generator outputs the ramp signal Vramp, and at this time The ramp signal Vramp output by the ramp generator is its initial voltage Vramp_ini. Then, when the first rising edge of the Ramp_En signal occurs, the ramp signal Vramp begins to fall, and when the first rising edge of the CNT_Syn signal occurs, the counter starts counting. Then, when the ramp signal Vramp falls to the same level as the reset signal Vr', the counter stops counting. At this time, the reset signal Vr' is converted, and the counter obtains the third count value.

Further, after the conversion of the reset signal Vr' is completed, the matte pixel unit outputs the signal signal Vs', and the ramp signal Vramp output from the ramp generator returns to its initial voltage Vramp_ini. Then, when the second rising edge of the Ramp_En signal occurs, the ramp signal Vramp begins to fall, and when the second rising edge of the Ramp_En signal occurs, the second rising edge of the CNT_Syn signal appears simultaneously, and the counter starts counting. Further, when the ramp signal Vramp falls to the same level as the signal signal Vs', the counter stops counting. At this time, the signal signal Vs' conversion is completed, and the counter obtains the fourth count value.

Further, in the counter, the difference between the conversion result of the signal signal Vs' and the conversion result of the reset signal Vr' is calculated, that is, the difference between the fourth count value and the third count value is calculated, and at this time, the switch S is turned on, and the fourth is The difference between the count value and the third count value is written into the latch.

S6. Calculate an average value of the digital signals of the plurality of matte pixel units, and use the average value as the black level value of the matte pixel unit.

Specifically, the above operation is repeated for all the matte pixel units, the digital signals of each matte pixel unit are obtained, and the average value of the digital signals of all the matte pixel units is calculated to obtain a black level value, that is, a plurality of matte The average value of the difference between the fourth count value and the third count value of the level signal output by the pixel unit is a black level value.

S4, corresponding to the output signal of the effective pixel unit after the black level is removed according to the first count value and the second count value Digital signal.

In the black level erasing method of the embodiment of the present invention, the black level value is calculated according to the analysis result of the matte pixel unit, and the black level value is used as the period number of the delayed clock period, and the signal is output to the effective pixel unit. When the signal is converted, the control signal CNT_Syn at which the counter starts counting is delayed by a predetermined number of clock cycles with respect to the control signal Ramp_En at which the ramp signal output from the ramp generator starts to decrease, to subtract black during the conversion of the signal signal. The level value, thus achieving the elimination of the black level while the signal signal is being converted, eliminates the time required to subtract the resolution result of the effective pixel unit from the black level value and then subtract it in the digital circuit. In order to implement the above embodiment, the present invention also proposes a black level cancellation system.

FIG. 6 is a schematic structural diagram of a black level erasing system according to an embodiment of the present invention. As shown in FIG. 6, the black level cancellation system includes a receiving module 100, a ramp generator 200, a comparator 300, a counter 400, a controller 500, a switch module 600, and a latch 700.

Specifically, the receiving module 100 is configured to receive a level signal output by the effective pixel unit, wherein the level signal includes a first level signal and a second level signal. Wherein, when parsing the signal of the effective pixel unit, it is necessary to parse the level signals output by the two effective pixel units, that is, the first level signal and the second level signal. Wherein, the first level signal is a reset signal (abbreviated as Vr), the second level signal is a signal signal (abbreviated as Vs), and the difference between the signal signal and the reset signal (Vs-Vr) is an effective pixel unit. output signal.

The ramp generator 200 is for generating a ramp signal based on the ramp control signal. The comparator 300 is configured to output a count stop signal when the amplitude of the ramp signal is equal to the amplitude of the first level signal and the amplitude of the ramp signal is equal to the amplitude of the second level signal. The counter 400 is configured to start counting when receiving the first counting control signal and the second counting control signal, respectively, and stop counting when receiving the counting stop signal, to obtain a corresponding first counting value and second counting value, and according to the A count value and a second count value obtain a digital signal corresponding to an output signal of the effective pixel unit after the black level is eliminated.

The controller 500 is configured to generate a ramp control signal, and generate a first count control signal when the comparator receives the first level signal and the ramp signal, and receive the second level signal and the ramp signal at the comparator The second count control signal is generated after a predetermined number of clock cycles are delayed, wherein the predetermined number is a black level value of the matte pixel unit.

Specifically, as shown in FIG. 3, in the embodiment of the present invention, when parsing the signal of the effective pixel unit, first, the effective pixel unit outputs a reset signal Vr, and the controller 500 controls the ramp generator 200 to output the ramp signal. Vramp, at this time, the ramp signal Vramp outputted by the ramp generator 200 is its initial voltage Vramp_ini. Then, when the first rising edge of the Ramp_En signal occurs, the ramp signal Vramp begins to fall, and when the first rising edge of the CNT_Syn signal occurs, the controller 500 controls the counter 400 to start counting. Then, when the comparator 300 compares the ramp signal Vramp to the same level as the reset signal Vr, the counter 400 stops counting. At this time, the reset signal Vr conversion is completed, and the counter 400 obtains the first count value.

Further, after the conversion of the reset signal Vr is completed, the effective pixel unit outputs the signal signal Vs, and the controller 500 controls the ramp signal Vramp output from the ramp generator 200 to return to its initial voltage Vramp_ini. Then, when the second rising edge of the Ramp_En signal occurs, the ramp signal Vramp starts to fall, and after a delay of n clock cycles, the second rising edge of the CNT_Syn signal appears, and the controller 500 controls the counter 400 to start counting. The number n of delayed clock cycles is a black level value obtained by calculating an average value from the analysis result of the matte pixel unit. Further, when the comparator 300 compares the ramp signal Vramp to be equal to the magnitude of the signal signal Vs, the counter 400 stops counting. At this time, the signal signal Vs conversion is completed, and the counter 400 obtains the second count value.

Further, the switch module 600 is turned on after the counter 400 obtains the digital signal after the level signal conversion, and the latch 700 stores the digital signal after the level signal conversion. That is to say, the counter 400 calculates the difference between the conversion result of the signal signal Vs and the conversion result of the reset signal Vr, that is, calculates the difference between the second count value and the first count value, at which time the switch module 600 is turned on, and the control is second. The difference between the count value and the first count value is written into the latch 700.

In the black level elimination system of the embodiment of the present invention, the black level value is used as the number of cycles of the delayed clock cycle. When the signal signal output by the effective pixel unit is converted, the control terminal CNT_Syn that starts counting the counter is compared with The control terminal Ramp_En of the ramp signal output from the ramp generator is delayed by a predetermined number of clock cycles to subtract the black level value during the conversion of the signal signal, thereby eliminating the conversion of the signal signal. The black level eliminates the time required to subtract the resolution result of the effective pixel unit from the black level value and then subtract it in the digital circuit.

In an embodiment of the present invention, the receiving module 100 is further configured to receive a level signal output by the invalid pixel unit, wherein the level signal output by the invalid pixel unit includes a third level signal and a fourth level signal; 300 is further configured to output a count stop signal when the amplitude of the ramp signal is equal to the amplitude of the third level signal and the amplitude of the ramp signal is equal to the amplitude of the fourth level signal; the counter 400 is further configured to respectively Counting is started when the third counting control signal and the fourth counting control signal are received, and counting is stopped when the counting stop signal is received, and the corresponding third counting value and fourth counting value are obtained, and according to the third counting value and the The fourth count value obtains a digital signal of the matte pixel unit corresponding to the level signal output by the matte pixel unit; and calculates an average value of the digital signals of the plurality of matte pixel units, and uses the average value as the matte pixel a black level value of the unit; the controller 500 is further configured to generate a third count control signal when the comparator receives the third level signal and the ramp signal, and receive the fourth at the comparator When the level signal and a ramp signal, generating a fourth counting control signal. Specifically, when parsing the level signal of the matte pixel unit, it is also necessary to parse the level signal of the output of the matte pixel unit twice. For convenience of explanation, the third level signal output by the matte pixel unit is simply abbreviated as Vr', the fourth level signal output by the matte pixel unit is abbreviated as Vs'.

As shown in FIG. 5, when parsing the signal of the matte pixel unit, first, the matte pixel unit outputs a reset signal Vr', and the controller 500 controls the ramp generator 200 to output the ramp signal Vramp, and the ramp wave occurs at this time. The ramp signal Vramp output by the device 200 is its initial voltage Vramp_ini. Then on the first of the Ramp_En signal When the rising edge occurs, the ramp signal Vramp begins to fall, and when the first rising edge of the CNT_Syn signal occurs, the controller 500 controls the counter 400 to start counting. Then, when the comparator 300 compares the ramp signal Vramp to the same level as the reset signal Vr', the counter 400 stops counting. At this time, the reset signal Vr' conversion is completed, and the counter 400 obtains the third count value.

Further, after the conversion of the reset signal Vr' is completed, the matte pixel unit outputs the signal signal Vs', and the controller 500 controls the ramp signal Vramp output from the ramp generator 200 to return to its initial voltage Vramp_ini. Then, when the second rising edge of the Ramp_En signal occurs, the ramp signal Vramp starts to fall, and when the second rising edge of the Ramp_En signal occurs, the second rising edge of the CNT_Syn signal appears simultaneously, and the controller 500 controls the counter 400 to start. count. Further, when the comparator 300 compares the ramp signal Vramp to be equal to the magnitude of the signal signal Vs', the counter 400 stops counting. At this time, the signal signal Vs' conversion is completed, and the counter 400 obtains the fourth count value.

Further, the counter 400 calculates a difference between the conversion result of the signal signal Vs' and the conversion result of the reset signal Vr', that is, calculates a difference between the fourth count value and the third count value, and at this time, the switch module 600 is turned on, and will be fourth. The difference between the count value and the third count value is written into the latch 700.

In the black level elimination system of the embodiment of the present invention, the black level value is calculated according to the analysis result of the matte pixel unit, and the black level value is used as the period number of the delayed clock period, and the signal output to the effective pixel unit is When the signal is converted, the control signal CNT_Syn at which the counter starts counting is delayed by a predetermined number of clock cycles with respect to the control signal Ramp_En at which the ramp signal output from the ramp generator starts to decrease, to subtract black during the conversion of the signal signal. The level value, thus achieving the elimination of the black level while the signal signal is being converted, eliminates the time required to subtract the resolution result of the effective pixel unit from the black level value and then subtract it in the digital circuit.

In order to implement the above embodiments, the present invention also proposes an image sensor comprising the black level cancellation system of the embodiment of the present invention.

In the image sensor of the embodiment of the present invention, the black level value is used as the number of cycles of the delayed clock cycle, and when the signal signal output from the effective pixel unit is converted, the control signal CNT_Syn that starts counting from the counter is compared with the ramp generator. The output ramp signal begins to fall, and the control signal Ramp_En is delayed by a predetermined number of clock cycles to subtract the black level value during the conversion of the signal signal, thereby realizing the elimination of the black level while the signal signal is being converted. The time required to subtract the analysis result of the effective pixel unit from the black level value and subtract it in the digital circuit is omitted.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " After, "Left", "Right", "Vertical", "Horizontal", "Top", "Bottom", "Inside", "Outside", "Clockwise", "Counterclockwise", "Axial", The orientation or positional relationship of the "radial", "circumferential" and the like is based on the orientation or positional relationship shown in the drawings, and is merely for the convenience of describing the present invention and simplifying the description, rather than indicating or implying The device or component referred to must have a particular orientation, is constructed and operated in a particular orientation, and thus is not to be construed as limiting the invention.

Moreover, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining "first" or "second" may include at least one of the features, either explicitly or implicitly. In the description of the present invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless specifically defined otherwise.

In the present invention, the terms "installation", "connected", "connected", "fixed" and the like shall be understood broadly, and may be either a fixed connection or a detachable connection, unless explicitly stated and defined otherwise. , or integrated; can be mechanical or electrical connection; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of two elements or the interaction of two elements, unless otherwise specified Limited. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.

In the present invention, the first feature "on" or "under" the second feature may be a direct contact of the first and second features, or the first and second features may be indirectly through an intermediate medium, unless otherwise explicitly stated and defined. contact. Moreover, the first feature "above", "above" and "above" the second feature may be that the first feature is directly above or above the second feature, or merely that the first feature level is higher than the second feature. The first feature "below", "below" and "below" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely that the first feature level is less than the second feature.

In the description of the present specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like means a specific feature described in connection with the embodiment or example. A structure, material or feature is included in at least one embodiment or example of the invention. In the present specification, the schematic representation of the above terms is not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, various embodiments or examples described in the specification, as well as features of various embodiments or examples, may be combined and combined.

Although the embodiments of the present invention have been shown and described, it is understood that the above-described embodiments are illustrative and are not to be construed as limiting the scope of the invention. The embodiments are subject to variations, modifications, substitutions and variations.

Claims

A method for eliminating a black level, comprising the steps of:

Receiving a level signal output by the effective pixel unit, wherein the level signal output by the effective pixel unit includes a first level signal and a second level signal;

The first counting is started when the first level signal and the ramp signal are received, and the first time is stopped when the amplitude of the ramp signal is equal to the amplitude of the first level signal Counting to obtain the first count value;

Timing is performed when the second level signal and the ramp signal are received, and a second count is started after a predetermined number of clock cycles are delayed, and when the amplitude of the ramp signal is the second Stopping the second counting when the amplitudes of the level signals are equal, and obtaining a second counting value, wherein the predetermined number is a black level value of the matte pixel unit;

And obtaining, according to the first count value and the second count value, a digital signal corresponding to an output signal of the effective pixel unit after the black level is eliminated.
The black level removing method according to claim 1, further comprising:

Receiving a level signal output by the matte pixel unit, and converting the level signal output by the matte pixel unit into a digital signal of the matte pixel unit;

Calculating an average value of the digital signals of the plurality of matte pixel units, and using the average value as a black level value of the matte pixel unit.
The black level removing method according to claim 1 or 2, wherein the level signal output by the matte pixel unit comprises a third level signal and a fourth level signal;

The converting the level signal output by the matte pixel unit into a digital signal of the matte pixel unit includes:

The third counting is started when the third level signal and the ramp signal are received, and the third time is stopped when the amplitude of the ramp signal is equal to the amplitude of the third level signal Counting to obtain a third count value;

The fourth counting is started when the fourth level signal and the ramp signal are received, and is stopped when the amplitude of the ramp signal is equal to the amplitude of the fourth level signal Counting four times to obtain a fourth count value;

And obtaining a digital signal of the matte pixel unit according to the third count value and the fourth count value.
The black level removing method according to any one of claims 1 to 3, characterized in that, according to the first count value and the second count value, an output signal of the effective pixel unit after the black level is removed is obtained. The corresponding digital signal specifically includes:

The second count value and the first count value are subtracted to obtain a digital signal corresponding to an output signal of the effective pixel unit after the black level is eliminated.
A black level cancellation system, comprising:

a receiving module, configured to receive a level signal output by the effective pixel unit, where the effective pixel unit outputs The level signal includes a first level signal and a second level signal;

a ramp generator for generating a ramp signal based on the ramp control signal;

a comparator for outputting a count when an amplitude of the ramp signal is equal to an amplitude of the first level signal and an amplitude of the ramp signal is equal to an amplitude of the second level signal Stop signal

a counter, configured to start counting when receiving the first count control signal and the second count control signal, respectively, and stop counting when receiving the count stop signal, to obtain a corresponding first count value and a second count value, and And obtaining, according to the first count value and the second count value, a digital signal corresponding to an output signal of the effective pixel unit after eliminating the black level;

a controller, configured to generate the ramp control signal, and generate the first count control signal when the comparator receives the first level signal and the ramp signal, and in the comparing The receiver receives the second level signal and the ramp signal, and generates the second count control signal after delaying a predetermined number of clock cycles, wherein the predetermined number is a black level value of the matte pixel unit .
A black level removing system according to claim 5, wherein

The receiving module is further configured to receive a level signal output by the invalid pixel unit, where the level signal output by the invalid pixel unit includes a third level signal and a fourth level signal;

The comparator is further configured to: when the amplitude of the ramp signal is equal to the amplitude of the third level signal and the amplitude of the ramp signal is equal to the amplitude of the fourth level signal Output count stop signal;

The counter is further configured to start counting when receiving the third counting control signal and the fourth counting control signal, respectively, and stop counting when receiving the counting stop signal, to obtain a corresponding third counting value and fourth counting value. And obtaining, according to the third count value and the fourth count value, a digital signal of the matte pixel unit corresponding to the level signal output by the matte pixel unit; and calculating the number of the plurality of matt pixel units An average value of the signal, and the average value is used as a black level value of the matte pixel unit;

The controller is further configured to generate the third count control signal when the comparator receives the third level signal and the ramp signal, and receive the fourth at the comparator The fourth count control signal is generated when the level signal and the ramp signal are used.
The black level removing system according to claim 5 or 6, wherein the counter obtains an output signal of the effective pixel unit after the black level is removed according to the first count value and the second count value. Corresponding digital signals, including:

The second count value and the first count value are subtracted to obtain a digital signal corresponding to an output signal of the effective pixel unit after the black level is eliminated.
The black level elimination system according to any one of claims 5-7, further comprising:

a switch module, configured to: the number corresponding to the output signal of the effective pixel unit after the counter is blackened After the word signal is turned on;

A latch for storing a digital signal corresponding to an output signal of the effective pixel unit after the black level is removed.
An image sensor, comprising: the black level cancellation system according to any one of claims 5-8.
A computer readable storage medium comprising computer instructions that, when executed, cause a black level removal method according to any one of claims 1-4.