WO2017063240A1 - 一种ltps阵列基板以及液晶显示面板 - Google Patents

一种ltps阵列基板以及液晶显示面板 Download PDF

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Publication number
WO2017063240A1
WO2017063240A1 PCT/CN2015/093873 CN2015093873W WO2017063240A1 WO 2017063240 A1 WO2017063240 A1 WO 2017063240A1 CN 2015093873 W CN2015093873 W CN 2015093873W WO 2017063240 A1 WO2017063240 A1 WO 2017063240A1
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Prior art keywords
layer
common electrode
array substrate
electrode layer
insulating layer
Prior art date
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PCT/CN2015/093873
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English (en)
French (fr)
Inventor
李亚锋
林建宏
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Wuhan China Star Optoelectronics Technology Co Ltd
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/897,777 priority Critical patent/US20180217453A1/en
Publication of WO2017063240A1 publication Critical patent/WO2017063240A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
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    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
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    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
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    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
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    • H10D30/6745—Polycrystalline or microcrystalline silicon
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G—PHYSICS
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F2202/104—Materials and properties semiconductor poly-Si

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to an LTPS array substrate and a liquid crystal display panel.
  • LTPS-TFT LCD Low Temperature Poly-Silicon
  • LTPS-TFT LCD Low Temperature Poly-Silicon
  • the array substrate of the existing LTPS-TFT LCD has a problem that the transmittance at the edge position of the adjacent sub-pixel is significantly lower than that at other positions, which affects the display effect of the liquid crystal display panel.
  • an embodiment of the present invention first provides an LTPS array substrate, which includes:
  • a passivation layer formed on the first common electrode layer, wherein the passivation layer is formed with a first via hole;
  • the second common electrode layer is electrically connected to the first common electrode layer through the first via.
  • the array substrate further includes:
  • the first common electrode layer is formed on the flat layer.
  • the second common electrode layer is formed directly above the data line.
  • the first material layer comprises:
  • a first insulating layer formed on the light transmissive substrate and the light shielding layer.
  • the data line is formed on the first insulating layer and directly above the light shielding layer.
  • the array substrate further includes:
  • a fourth insulating layer formed on the gate layer and the third insulating layer
  • a source drain layer formed on the fourth insulating layer, the source drain layer being electrically connected to the polysilicon layer through a second via formed in the third insulating layer and the fourth insulating layer;
  • the first common electrode layer is formed on the flat layer.
  • the second common electrode layer is electrically connected to a common electrode of the first sub-pixel of the two adjacent sub-pixels through the first via.
  • a pixel electrode of a second sub-pixel of the two adjacent sub-pixels is formed by A third via in the passivation layer and the planar layer is electrically connected to the source drain layer.
  • the second common electrode layer and the pixel electrode layer are on the same horizontal plane.
  • the invention also provides a liquid crystal display panel comprising:
  • the array substrate provided by the present invention bridges the common electrode through the via hole at the position of the adjacent pixel electrode, and the bridged common electrode and the pixel electrode are at the same horizontal plane, so that the electric field intensity at the region is significantly enhanced, and further Increased penetration in this area. At the same time, for a single sub-pixel, its overall penetration rate will also increase.
  • FIG. 1 is a schematic structural view of a TFT switch of a conventional LTPS liquid crystal display panel
  • FIG. 2 is a schematic structural view of a data line of a conventional LTPS liquid crystal display panel
  • FIG. 3 is a plan view showing a sub-pixel of a conventional LTPS liquid crystal display panel
  • FIG. 4 is a schematic structural view of a TFT switch of an LTPS liquid crystal display panel according to an embodiment of the present invention
  • FIG. 5 is a schematic structural view of a data line of an LTPS liquid crystal display panel according to an embodiment of the present invention.
  • FIG. 6 is a plan view showing a sub-pixel of a LTPS liquid crystal display panel according to an embodiment of the present invention.
  • FIG. 7 is a comparison diagram of transmittance of an LTPS liquid crystal display panel and an existing LTPS liquid crystal display panel provided by the present invention.
  • FIG. 1 is a schematic view showing the structure of a TFT switch of a conventional LTPS liquid crystal display panel.
  • the existing LTPS liquid crystal display panel includes an array substrate 101, a color filter 102, and a liquid crystal layer 103 filled between the array substrate 101 and the color filter 102.
  • the color filter 102 includes a transparent substrate 201, a black matrix 202, a color resist layer 203, a flat layer 204, and a film pillar 205.
  • the black matrix 202 is formed on the transparent substrate 201, and the color resist layer 203 is covered on the black matrix 202 and the transparent substrate 201.
  • the black matrix 202 is located at the boundary of two adjacent sub-pixel units in the color resist layer 203.
  • a flat layer 204 is formed on the color resist layer 203, and a film pillar 205 is formed on the flat layer 204.
  • the film column 205 includes a main film column and a auxiliary film column for supporting the color filter plate 102 when the liquid crystal display panel is assembled.
  • the light shielding layer 302 is formed on the transparent substrate 301 at the TFT switch of the array substrate 101.
  • the second insulating layer 303 is formed on the light shielding layer 302 and the transparent substrate 301 and covers the light shielding layer 302 and the transparent substrate 301.
  • An active layer (i.e., polysilicon layer) 304 is formed on the second insulating layer 303 and directly above the light shielding layer 302.
  • a third insulating layer 305 is formed on the active layer 304 and the second insulating layer 303 and covers the active layer 304 and the second insulating layer 303.
  • the gate layer 306 is formed on the third insulating layer 305 and directly above the polysilicon layer 304 such that the third insulating layer 305 achieves electrical isolation between the gate layer 306 and the polysilicon layer 304.
  • a fourth insulating layer 307 is formed on the gate layer 306 and the third insulating layer 305, and a source/drain layer (ie, an SD layer) 308 is formed on the fourth insulating layer 307.
  • a second via hole is formed in the third insulating layer 305 and the fourth insulating layer 307, and the source/drain layer 308 is electrically connected to the polysilicon layer 304 through the second via hole.
  • a flat layer 309 is formed on the fourth insulating layer 307 and the source/drain layer 308, and a common electrode layer 310 is formed on the flat layer 309.
  • the common electrode in the common electrode layer 310 corresponds to the two sub-pixels, respectively, and there is a certain interval between the two common electrodes.
  • a passivation layer 311 is formed on the common electrode layer 310. Since the common electrode layer 310 does not completely cover the flat layer 309 at the TFT switch position of the array substrate 101, the passivation layer 311 also covers the partial flat layer 309 as shown in FIG.
  • the pixel electrode layer 312 is formed on the passivation layer 311, and the pixel electrode layer 312 is electrically connected to the source/drain layer 308 through a third via formed in the passivation layer 311 and the flat layer 309.
  • FIG. 2 is a schematic view showing the structure of a data line of a conventional LTPS liquid crystal display panel.
  • the data line of the conventional LTPS liquid crystal display panel also includes an array substrate 101, a color filter 102, and a liquid crystal layer 103 filled between the array substrate 101 and the color filter 102.
  • the color filter and the liquid crystal layer have the same structure as the color filter and the liquid crystal layer shown in FIG. 1, for the sake of simplicity of description, the structure of the color filter and the liquid crystal layer will not be described here. Only the structure of the array substrate 101 at the data line will be further explained.
  • a first material layer is formed on the light-transmitting substrate 301.
  • the first material layer comprises a light shielding layer 302 and a first insulating layer.
  • the first insulating layer is further formed by stacking a plurality of insulating layers. As shown in FIG. 2, the first insulating layer further includes a second insulating layer 303, a third insulating layer 305, and a fourth insulating layer 307 which are sequentially stacked.
  • the data line 313 is formed on the fourth insulating layer 307 directly above the light shielding layer 302, the flat layer 309 is formed on the data line 313 and the fourth insulating layer 307, and the common electrode layer 310 is formed on the passivation layer 311 and the flat layer 309. Between the pixel electrode layers 312 is formed on the passivation layer 311.
  • the array substrate in the conventional LTPS liquid crystal display panel mainly forms a fringe electric field by the upper and lower ITO electrodes (ie, the pixel electrode and the common electrode). To drive the liquid crystal to rotate in the plane, thereby controlling the direction of rotation of the light.
  • the geometry of the TFT switch can be designed very small during pixel design, which is beneficial to the design of higher PPI products.
  • the electric field between the two electrodes ie, the pixel electrode and the common electrode
  • the electric field strength itself is consumed, and thus adjacent At the edge position of the sub-pixel, the electric field strength is significantly weakened, and this causes the transmittance corresponding to this portion (at the edge position of the adjacent sub-pixel) to also decrease.
  • the present embodiment provides a new LTPS array substrate and an LTPS liquid crystal display panel.
  • the pixel electrode spacing of adjacent sub-pixels should be kept at a certain interval (for example, about 10 um).
  • the LTPS array substrate provided by the present invention is that in the interval region of adjacent sub-pixels, the common electrode is bridged through the via hole, and an additional common electrode layer is formed at a position at the same level as the pixel electrode layer, thereby Effectively increasing the electric field strength at the edge position of the adjacent sub-pixels, thereby increasing the transmittance of the array substrate at the region.
  • FIG. 4 is a schematic view showing the structure of the TFT switch position of the liquid crystal display panel provided by the embodiment.
  • the LTPS liquid crystal display panel provided in this embodiment has substantially the same structure as the LTPS liquid crystal display panel shown in FIG. 1.
  • the purpose of the present invention and the original purpose are more clearly explained for the sake of simplicity of description. And the advantages, the following only describes the differences in detail.
  • the present embodiment is different from the LTPS liquid crystal display panel shown in FIG.
  • a second common electrode layer 314 is further disposed in the array substrate 101 of the liquid crystal display panel provided.
  • the second common electrode layer 314 is formed on the passivation layer 311 and between the pixel electrodes of two adjacent sub-pixels in the pixel electrode layer 312, that is, in the same material layer as the pixel electrode layer 312.
  • a predetermined interval is maintained between the second common electrode layer 314 and each of the pixel electrode layers 312 to ensure electrical isolation between the second common electrode layer 314 and each of the pixel electrode layers 312.
  • the second common electrode layer 314 is electrically connected to the first common electrode layer 310 through the first via formed in the passivation layer 311. Specifically, as shown in FIG. 4, the second common electrode layer 314 is electrically connected to the common electrode of the first sub-pixel of the two adjacent sub-pixels through the first via. The pixel electrodes of the second sub-pixels of the two adjacent sub-pixels are electrically connected to the source/drain layer 308 through the third via holes formed in the passivation layer 311 and the flat layer 309.
  • the second common electrode layer 314 is preferably at the same level as the pixel electrode layer 312.
  • the second common electrode layer 314 may not be at the same level as the pixel electrode layer 312 according to actual needs or requirements of the manufacturing process, and the present invention is not limited thereto.
  • FIG. 5 is a schematic structural view showing the position of the data line of the LTPS liquid crystal display panel provided by the embodiment.
  • the LTPS liquid crystal display panel provided in this embodiment is substantially the same as the LTPS liquid crystal display panel shown in FIG. 2 at the position of the data line, and the description is simple and clear. The objects, principles, and advantages of the invention are set forth in detail below.
  • the present embodiment is different from the LTPS liquid crystal display panel shown in FIG.
  • the array substrate 101 of the liquid crystal display panel is provided with a second common electrode layer 314.
  • the second common electrode layer 314 at the position of the data line is also formed between the pixel electrodes of two adjacent sub-pixels in the pixel electrode layer 312 and is identical to the pixel electrode layer 312, like the second common electrode at the position of the TFT switch.
  • a predetermined interval is maintained between the second common electrode layer 314 and each pixel electrode in the pixel electrode layer 312, thereby ensuring The second common electrode layer 314 is electrically isolated from each of the pixel electrode layers 312.
  • the second common electrode layer 314 is electrically connected to the first common electrode layer 310 through the first via formed in the passivation layer 311.
  • the liquid crystal display panel provided in this embodiment is at the data line position, and the second common electrode layer 314 is preferably at the same level as the pixel electrode layer 312.
  • the second common electrode layer 314 may not be the same as the pixel electrode layer 312 according to actual needs or requirements of the manufacturing process. On a horizontal plane, the invention is not limited thereto.
  • each insulating layer is realized by a silicon oxynitride layer.
  • the constituent materials of the respective material layers may adopt other reasonable materials, and the present invention is not limited thereto.
  • the array substrate provided in this embodiment bridges the common electrode through the via hole at the position of the adjacent pixel electrode, and the bridged common electrode and the pixel electrode are in the same horizontal plane, thereby making the region
  • the electric field strength at the location is significantly enhanced, thereby increasing the transmittance of the array substrate at the region.
  • its overall penetration rate will also increase.
  • the present embodiment compares the transmittance of the conventional LTPS array substrate with the LTPS array substrate provided by the embodiment.
  • FIG. 7 shows a comparison of transmittances of the two array substrates. As can be seen from FIG. 7, the transmittance of the array substrate provided by the present embodiment is significantly improved compared to the conventional LTPS array substrate. .

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Abstract

一种LTPS阵列基板（101）及液晶显示面板，该基板（101）包括：第一公共电极层（310）及其上的钝化层（311），钝化层（311）中有第一过孔，其上形成有像素电极层（312）；第二公共电极层（314）形成于钝化层（311）上，其处于两个相邻子像素的像素电极之间，与像素电极层（312）电隔离，并通过第一过孔与第一公共电极层（310）电连接。

Description

一种LTPS阵列基板以及液晶显示面板
相关技术的交叉引用
本申请要求享有2015年10月14日提交的名称为：“一种LTPS阵列基板以及液晶显示面板”的中国专利申请CN 201510659235.6的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及液晶显示技术领域，具体地说，涉及一种LTPS阵列基板以及液晶显示面板。
背景技术
低温多晶硅(Low Temperature Poly-Silicon，简称为LTPS)薄膜晶体管液晶显示器(即LTPS-TFT LCD)有别与传统的非晶硅薄膜晶体管液晶显示器，其具有分辨率高、反应速度快、亮度高以及开口率高等优点，因此，LTPS-TFT LCD得到了越来越广泛的应用。
然而，现有LTPS-TFT LCD的阵列基板存在相邻子像素边缘位置处的穿透率明显低于其他位置处的穿透率的问题，这影响了液晶显示面板的显示效果。
基于上述情况，亟需一种能够保证相邻子像素边缘位置处的穿透率的LTPS阵列基板。
发明内容
本发明所要解决的技术问题是为了提高LTPS阵列基板中相邻子像素边缘位置处的穿透率。为解决上述问题，本发明的一个实施例首先提供了一种LTPS阵列基板，其包括：
第一公共电极层；
钝化层，其形成在所述第一公共电极层上，所述钝化层中形成有第一过孔；
像素电极层，其形成在所述钝化层上；
第二公共电极层，其形成在所述钝化层上并处于所述像素电极层中两个相邻子像素 的像素电极之间，且与所述像素电极层保持电隔离，所述第二公共电极层通过所述第一过孔与所述第一公共电极层电连接。
根据本发明的一个实施例，在所述阵列基板的数据线位置处，所述阵列基板还包括：
透光基板；
第一材料层，其形成在所述透光基板上；
数据线，其形成在所述第一材料层上；
平坦层，其形成在所述数据线和第一材料层上；
其中，所述第一公共电极层形成在所述平坦层上。
根据本发明的一个实施例，所述第二公共电极层形成在所述数据线的正上方。
根据本发明的一个实施例，所述第一材料层包括：
遮光层，其形成在所述透光基板上；
第一绝缘层，其形成在所述透光基板和遮光层上。
根据本发明的一个实施例，所述数据线形成在所述第一绝缘层上并处于所述遮光层的正上方。
根据本发明的一个实施例，在所述阵列基板的TFT开关位置处，所述阵列基板还包括：
透光基板；
遮光层，其形成在所述透光基板上；
第二绝缘层，其形成在所述遮光层和透光基板上；
多晶硅层，其形成在所述第二绝缘层上并处于所述遮光层的正上方；
第三绝缘层，其形成在所述多晶硅层和第二绝缘层上；
栅极层，其形成在所述第三绝缘层上并处于所述遮光层的正上方；
第四绝缘层，其形成在所述栅极层和第三绝缘层上；
源漏层，其形成在所述第四绝缘层上，所述源漏层通过形成在所述第三绝缘层和第四绝缘层中的第二过孔与所述多晶硅层电连接；
平坦层，其形成在所述源漏层和第四绝缘层上；
其中，所述第一公共电极层形成在所述平坦层上。
根据本发明的一个实施例，所述第二公共电极层通过所述第一过孔与所述两个相邻子像素中第一子像素的公共电极电连接。
根据本发明的一个实施例，所述两个相邻子像素中第二子像素的像素电极通过形成 在所述钝化层和平坦层中的第三过孔与所述源漏层电连接。
根据本发明的一个实施例，所述第二公共电极层与所述像素电极层处于同一水平面上。
本发明还提供了一种液晶显示面板，其包括：
如上任一项所述的LTPS阵列基板；
彩色滤光板；
以及，设置在所述LTPS阵列基板与彩色滤光板之间的液晶层。
本发明所提供的阵列基板在相邻的像素电极位置处，通过过孔将公共电极桥接出来，桥接出的公共电极与像素电极处于同一水平面，从而使得该区域处的电场强度得到明显加强，进而提高了该区域出的穿透率。同时，对于单个子像素来说，其整体穿透率也会提高。
此外，在相邻子像素的边缘区域中，由于公共的电极与像素电极处于同一层别，因而不存在材料层数目增加的问题。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要的附图做简单的介绍：
图1是现有的LTPS液晶显示面板TFT开关处的结构示意图；
图2是现有的LTPS液晶显示面板数据线处的结构示意图；
图3是现有的LTPS液晶显示面板中子像素的平面结构图；
图4是根据本发明一个实施例的LTPS液晶显示面板TFT开关处的结构示意图；
图5是根据本发明一个实施例的LTPS液晶显示面板数据线处的结构示意图；
图6是根据本发明一个实施例的LTPS液晶显示面板中子像素的平面结构图；
图7是本发明所提供的LTPS液晶显示面板与现有的LTPS液晶显示面板的穿透率对比图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技 术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
同时，在以下说明中，出于解释的目的而阐述了许多具体细节，以提供对本发明实施例的彻底理解。然而，对本领域的技术人员来说显而易见的是，本发明可以不用这里的具体细节或者所描述的特定方式来实施。
图1示出了现有的LTPS液晶显示面板TFT开关处的结构示意图。
从图1中可以看出，在TFT开关处，现有的LTPS液晶显示面板包括：阵列基板101、彩色滤光板102以及填充在阵列基板101与彩色滤光板102之间的液晶层103。其中，彩色滤光板102包括：透光基板201、黑矩阵202、色阻层203、平坦层204以及膜柱205。其中，黑矩阵202形成在透光基板201上，色阻层203覆盖在黑矩阵202和透光基板201上。黑矩阵202位于色阻层203中两个相邻的亚像素单元的交界位置处。平坦层204形成在色阻层203上，膜柱205形成在平坦层204上。本实施例中，膜柱205包括主膜柱和辅膜柱，其用于在液晶显示面板装配时支撑彩色滤光板102。
在阵列基板101的TFT开关处，遮光层302形成在透光基板301上，第二绝缘层303形成在遮光层302以及透光基板301上并覆盖遮光层302和透光基板301。主动层(即多晶硅层)304形成在第二绝缘层303上并处于遮光层302的正上方。第三绝缘层305形成在主动层304和第二绝缘层303上并覆盖主动层304和第二绝缘层303。栅极层306形成在第三绝缘层305上并处于多晶硅层304正上方，这样第三绝缘层305便实现了栅极层306与多晶硅层304之间的电隔离。
第四绝缘层307形成在栅极层306和第三绝缘层305上，而源漏层(即SD层)308则形成在第四绝缘层307上。其中，第三绝缘层305和第四绝缘层307中形成有第二过孔，源漏层308通过第二过孔与多晶硅层304实现电连接。
平坦层309形成在第四绝缘层307以及源漏层308上，公共电极层310形成在平坦层309上。从图1中可以看出，对于相邻的两个子像素来说，公共电极层310中的公共电极分别对应于这两个子像素，并且这两个公共电极之间存在一定间隔。
钝化层311形成在公共电极层310上。由于在阵列基板101的TFT开关位置处，公共电极层310并未完全覆盖平坦层309，因此如图1所示，钝化层311同样覆盖了部分平坦层309。
像素电极层312形成在钝化层311上，像素电极层312通过形成在钝化层311以及平坦层309中的第三过孔与源漏层308电连接。
图2示出了现有的LTPS液晶显示面板数据线处的结构示意图。
如图2所示，现有的LTPS液晶显示面板数据线处同样包含阵列基板101、彩色滤光板102以及填充在阵列基板101与彩色滤光板102之间的液晶层103。其中，由于此处彩色滤光板以及液晶层与图1所示的彩色滤光板以及液晶层的结构相同，因此为了描述的简便，在此不再对彩色滤光板以及液晶层的结构进行赘述，以下仅对阵列基板101在数据线处的结构作进一步地阐述。
在阵列基板101的数据线位置处，第一材料层形成在透光基板301上。其中，第一材料层包括遮光层302和第一绝缘层。具体地，本实施例中，第一绝缘层又由多个绝缘层叠加而成。如图2所示，第一绝缘层还包括依次叠加的第二绝缘层303、第三绝缘层305和第四绝缘层307。
数据线313形成在第四绝缘层307上并处于遮光层302的正上方，平坦层309形成在数据线313和第四绝缘层307上，公共电极层310形成在钝化层311与平坦层309之间，像素电极层312则形成在钝化层311上。
同时，结合图3所示的传统的LTPS液晶显示面板的子像素的平面结构示意图可知，传统的LTPS液晶显示面板中阵列基板主要靠上下两层ITO电极(即像素电极和公共电极)形成边缘电场来驱动液晶在平面内转动，进而控制光的旋转方向。
由于LTPS具有高迁移率的优点，因此在进行像素设计时TFT开关的几何尺寸也就可以设计得很小，这也就有利于实现更高PPI产品的设计。然而，对于传统的LTPS液晶显示面板来说，由于两层电极(即像素电极和公共电极)之间的电场要穿过中间的钝化层，这对电场强度本身会有消耗，因此在相邻子像素的边缘位置处，电场强度明显减弱，而这则会导致这部分区域(相邻子像素的边缘位置处)所对应的穿透率也随之降低。
针对现有的LTPS液晶显示面板所存在的上述问题，本实施例提供了一种新的LTPS阵列基板以及LTPS液晶显示面板。对于传统的LTPS液晶显示面板来说，为了保证相邻的子像素不至于出现混色现象，相邻子像素的像素电极间距要保持一定间隔(例如10um左右)。而本发明所提供的LTPS阵列基板则是在相邻子像素的间隔区域中，通过过孔将公共电极桥接出来，并在与像素电极层处于同一水平面的位置处形成额外的公共电极层，从而有效增加相邻子像素的边缘位置处的电场强度，进而提高该区域处的阵列基板的穿透率。
图4示出了本实施例所提供的液晶显示面板TFT开关位置处的结构示意图。
对比图1和图4可以看出，本实施例所提供的LTPS液晶显示面板与图1所示的LTPS液晶显示面板的结构大致相同，为了描述的简便以及更加清楚地阐述本发明的目的、原 理以及优点，以下仅对不同之处进行详细地阐述。
如图4所示，与图1所示的LTPS液晶显示面板相比，除设置在钝化层311与平坦层309之间的公共电极层(即第一公共电极层)310外，本实施例所提供的液晶显示面板的阵列基板101中还设置有第二公共电极层314。第二公共电极层314形成在钝化层311上，并处于像素电极层312中的两个相邻子像素的像素电极之间，即与像素电极层312处于同一材料层中。其中，第二公共电极层314与像素电极层312中的各个像素电极之间保持预设间隔，从而保证第二公共电极层314与像素电极层312中的各个像素电极之间保持电隔离。
本实施例中，第二公共电极层314通过形成在钝化层311中的第一过孔与第一公共电极层310电连接。具体地，如图4所示，第二公共电极层314通过第一过孔与两个相邻子像素中第一子像素的公共电极电连接。而这两个相邻子像素中第二子像素的像素电极则通过形成在钝化层311和平坦层309中的第三过孔与源漏层308电连接。
本实施例中，第二公共电极层314优选地与像素电极层312处于同一水平面上。当然，在本发明的其他实施例中，根据实际需要或制造工艺的要求或限制，第二公共电极层314还可以与像素电极层312不处于同一水平面上，本发明不限于此。
图5示出了本实施例所提供的LTPS液晶显示面板的数据线位置处的结构示意图。
对比图2和图5可以看出，在数据线位置处，本实施例提供的LTPS液晶显示面板与图2所示的LTPS液晶显示面板的结构大致相同，为了描述的简便以及更加清楚地阐述本发明的目的、原理以及优点，以下仅对不同之处进行详细地阐述。
如图5所示，与图2所示的LTPS液晶显示面板相比，除设置在钝化层311与平坦层309之间的公共电极(即第一公共电极层)310外，本实施例所提供的液晶显示面板的阵列基板101还设置有第二公共电极层314。与TFT开关位置处的第二公共电极相同，数据线位置处的第二公共电极层314同样形成在像素电极层312中两个相邻子像素的像素电极之间并与像素电极层312处于同一材料层中。其中，结合图6所示的LTPS液晶显示面板中子像素所对应的平面结构图可以看出，第二公共电极层314与像素电极层312中的各个像素电极之间保持预设间隔，从而保证第二公共电极层314与像素电极层312中的各个像素电极之间保持电隔离。
本实施例中，第二公共电极层314通过形成在钝化层311中的第一过孔与第一公共电极层310电连接。同样，本实施例所提供的液晶显示面板在数据线位置处，第二公共电极层314优选地与像素电极层312处于同一水平面上。当然，在本发明的其他实施例中，根据实际需要或制造工艺的要求，第二公共电极层314还可以与像素电极层312不处于同 一水平面上，本发明不限于此。
需要指出的是，在本实施例所提供的LTPS阵列基板以及LTPS液晶显示面板中，各个绝缘层均采用氮氧化硅合层来实现。当然，在本发明的其他实施例中，各个材料层的构成材料均可以采用其他合理材料，本发明不限于此。
从上述描述中可以看出，本实施例所提供的阵列基板在相邻的像素电极位置处，通过过孔将公共电极桥接出来，桥接出的公共电极与像素电极处于同一水平面，从而使得该区域处的电场强度得到明显加强，进而提高了该区域处阵列基板的穿透率。同时，对于单个子像素来说，其整体穿透率也会提高。
此外，在该区域中，由于公共的电极与像素电极处于同一层别，因而不存在材料层数目增加的问题。
为了更加清楚地显示本实施例所提供的阵列基板的优点，本实施例还将传统的LTPS阵列基板与本实施例所提供的LTPS阵列基板的穿透率进行了比较。图7示出了这两种阵列基板的穿透率对比图，从图7中可以看出，相较于传统的LTPS阵列基板，本实施例所提供的阵列基板的穿透率得到的明显提高。
应该理解的是，本发明所公开的实施例不限于这里所公开的特定结构或材料，而应当延伸到相关领域的普通技术人员所理解的这些特征的等同替代。还应当理解的是，在此使用的术语仅用于描述特定实施例的目的，而并不意味着限制。
说明书中提到的“一个实施例”或“实施例”意指结合实施例描述的特定特征、结构或特性包括在本发明的至少一个实施例中。因此，说明书通篇各个地方出现的短语“一个实施例”或“实施例”并不一定均指同一个实施例。
在一个或多个应用中的原理，但对于本领域的技术人员来说，在不背离本发明的原理和思想的情况下，明显可以在形式上、用法及实施的细节上作各种修改而不用付出创造性劳动。因此，本发明由所附的权利要求书来限定。

Claims (18)

  1. 一种LTPS阵列基板，其中，包括：
    第一公共电极层；
    钝化层，其形成在所述第一公共电极层上，所述钝化层中形成有第一过孔；
    像素电极层，其形成在所述钝化层上；
    第二公共电极层，其形成在所述钝化层上并处于所述像素电极层中两个相邻子像素的像素电极之间，且与所述像素电极层保持电隔离，所述第二公共电极层通过所述第一过孔与所述第一公共电极层电连接。
  2. 如权利要求1所述的LTPS阵列基板，其中，在所述阵列基板的数据线位置处，所述阵列基板还包括：
    透光基板；
    第一材料层，其形成在所述透光基板上；
    数据线，其形成在所述第一材料层上；
    平坦层，其形成在所述数据线和第一材料层上；
    其中，所述第一公共电极层形成在所述平坦层上。
  3. 如权利要求2所述的LTPS阵列基板，其中，所述第二公共电极层形成在所述数据线的正上方。
  4. 如权利要求2所述的LTPS阵列基板，其中，所述第一材料层包括：
    遮光层，其形成在所述透光基板上；
    第一绝缘层，其形成在所述透光基板和遮光层上。
  5. 如权利要求4所述的LTPS阵列基板，其中，所述数据线形成在所述第一绝缘层上并处于所述遮光层的正上方。
  6. 如权利要求1所述的LTPS阵列基板，其中，在所述阵列基板的TFT开关位置处，所述阵列基板还包括：
    透光基板；
    遮光层，其形成在所述透光基板上；
    第二绝缘层，其形成在所述遮光层和透光基板上；
    多晶硅层，其形成在所述第二绝缘层上并处于所述遮光层的正上方；
    第三绝缘层，其形成在所述多晶硅层和第二绝缘层上；
    栅极层，其形成在所述第三绝缘层上并处于所述遮光层的正上方；
    第四绝缘层，其形成在所述栅极层和第三绝缘层上；
    源漏层，其形成在所述第四绝缘层上，所述源漏层通过形成在所述第三绝缘层和第四绝缘层中的第二过孔与所述多晶硅层电连接；
    平坦层，其形成在所述源漏层和第四绝缘层上；
    其中，所述第一公共电极层形成在所述平坦层上。
  7. 如权利要求6所述的LTPS阵列基板，其中，所述第二公共电极层通过所述第一过孔与所述两个相邻子像素中第一子像素的公共电极电连接。
  8. 如权利要求7所述的LTPS阵列基板，其中，所述两个相邻子像素中第二子像素的像素电极通过形成在所述钝化层和平坦层中的第三过孔与所述源漏层电连接。
  9. 如权利要求1所述的LTPS阵列基板，其中，所述第二公共电极层与所述像素电极层处于同一水平面上。
  10. 一种液晶显示面板，其中，包括：
    LTPS阵列基板；
    彩色滤光板；
    以及，设置在所述LTPS阵列基板与彩色滤光板之间的液晶层；
    其中，所述LTPS阵列基板包括：
    第一公共电极层；
    钝化层，其形成在所述第一公共电极层上，所述钝化层中形成有第一过孔；
    像素电极层，其形成在所述钝化层上；
    第二公共电极层，其形成在所述钝化层上并处于所述像素电极层中两个相邻子像素的像素电极之间，且与所述像素电极层保持电隔离，所述第二公共电极层通过所述第一过孔与所述第一公共电极层电连接。
  11. 如权利要求10所述的液晶显示面板，其中，在所述阵列基板的数据线位置处，所述阵列基板还包括：
    透光基板；
    第一材料层，其形成在所述透光基板上；
    数据线，其形成在所述第一材料层上；
    平坦层，其形成在所述数据线和第一材料层上；
    其中，所述第一公共电极层形成在所述平坦层上。
  12. 如权利要求11所述的液晶显示面板，其中，所述第二公共电极层形成在所述数据线的正上方。
  13. 如权利要求11所述的液晶显示面板，其中，所述第一材料层包括：
    遮光层，其形成在所述透光基板上；
    第一绝缘层，其形成在所述透光基板和遮光层上。
  14. 如权利要求13所述的液晶显示面板，其中，所述数据线形成在所述第一绝缘层上并处于所述遮光层的正上方。
  15. 如权利要求10所述的液晶显示面板，其中，在所述阵列基板的TFT开关位置处，所述阵列基板还包括：
    透光基板；
    遮光层，其形成在所述透光基板上；
    第二绝缘层，其形成在所述遮光层和透光基板上；
    多晶硅层，其形成在所述第二绝缘层上并处于所述遮光层的正上方；
    第三绝缘层，其形成在所述多晶硅层和第二绝缘层上；
    栅极层，其形成在所述第三绝缘层上并处于所述遮光层的正上方；
    第四绝缘层，其形成在所述栅极层和第三绝缘层上；
    源漏层，其形成在所述第四绝缘层上，所述源漏层通过形成在所述第三绝缘层和第四绝缘层中的第二过孔与所述多晶硅层电连接；
    平坦层，其形成在所述源漏层和第四绝缘层上；
    其中，所述第一公共电极层形成在所述平坦层上。
  16. 如权利要求15所述的液晶显示面板，其中，所述第二公共电极层通过所述第一过孔与所述两个相邻子像素中第一子像素的公共电极电连接。
  17. 如权利要求16所述的液晶显示面板，其中，所述两个相邻子像素中第二子像素的像素电极通过形成在所述钝化层和平坦层中的第三过孔与所述源漏层电连接。
  18. 如权利要求10所述的液晶显示面板，其中，所述第二公共电极层与所述像素电极层处于同一水平面上。
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