WO2017062002A1 - Circuits permettant d'effectuer des opérations rram à faible marge - Google Patents

Circuits permettant d'effectuer des opérations rram à faible marge Download PDF

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Publication number
WO2017062002A1
WO2017062002A1 PCT/US2015/054531 US2015054531W WO2017062002A1 WO 2017062002 A1 WO2017062002 A1 WO 2017062002A1 US 2015054531 W US2015054531 W US 2015054531W WO 2017062002 A1 WO2017062002 A1 WO 2017062002A1
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WIPO (PCT)
Prior art keywords
rram
current
circuit
phase
transistor
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Application number
PCT/US2015/054531
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English (en)
Inventor
Luke WHITAKER
James S. Ignowski
Yoocharn Jeon
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Hewlett-Packard Development Company, L.P.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Hewlett-Packard Development Company, L.P. filed Critical Hewlett-Packard Development Company, L.P.
Priority to PCT/US2015/054531 priority Critical patent/WO2017062002A1/fr
Publication of WO2017062002A1 publication Critical patent/WO2017062002A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/06—Sense amplifier related aspects
    • G11C2207/068—Integrator type sense amplifier

Definitions

  • Resistive random-access memory technologies, such as memory based on memristors, store one or more bits of data based on resistance values of memory elements.
  • Arrays of resistive memory can be associated with issues such as sneak path currents, which potentially can be generated across non-addressed memory cells and negatively affect the ability to accurately read the logic values of the memory elements.
  • F!G. 1 is a block diagram of a device including a first circuit according to an example.
  • FIG. 2 is a block diagram of a device including a first circuit according to an example.
  • FIG. 3 is a block diagram of a device including a first circuit according to an example.
  • FIG. 4 is a block diagram of a system including a first circuit and a second circuit according to an example.
  • FIG. 5 is a block diagram of a system including a first circuit, a second circuit, and a third circuit according to an example.
  • FIG. 6 is a block diagram of a system including a first circuit, a second circuit, and a third circuit according to an example.
  • FIG. 7 is a flow chart based on isolating RRAM current for performing RRAM operations according to an example.
  • FIG. 8 is a flow chart based on performing RRAM operations according to an example.
  • examples described herein enable low-headroom operations, enabling sampling of the sneak current and voltage clamping of a RRAM array at voltages down to on the order of 0.5 V or lower.
  • This enables the sensing of RRAM arrays at very low voltages, improving voltage overhead.
  • transimpedance amplifier (TIA)-based clamping may be used for the sampling of sneak currents and RRAM element currents.
  • the sampled sneak current can be subtracted from the sampled current of the RRAM element, and the subtracted result can be compared to a threshold current for resolving a logic value for a RRAM element cell.
  • Examples may be operated at low clamp voltages, e.g., at or below 0.5 V, including on the order of 0.2 V. This enables the RRAM array to be operated with more headroom, in view of using a low-headroom current or voltage sensing approach.
  • examples enable approaches for low headroom clamping, sneak current subtraction, and sensing for memory elements such as memristors.
  • RRAM includes references to any resistive- based memory technologies, such as memristors, phase-change memory and the like. Furthermore, examples are described herein with reference to various RRAM operations in greater detail, such as sneak current subtraction, sensing, and clamping. However, examples are also applicable to other RRAM operations, such as writing, forming, and reading RRAM cells, as well as other operations that can benefit from the example low-headroom sample and hold operations.
  • FIG. 1 is a block diagram of a device 100 including a first circuit 1 10 according to an example.
  • the device 100 is to receive a total current 106 from a selected RRAM 109 of a RRAM array 101 .
  • the first circuit 1 10 includes an amplifier 1 19 and a transistor 1 15 to isolate the RRAM current 108 from the sneak current 104 of the total current 106, for sensing the RRAM current 108.
  • the RRAM array 101 can include a one dimensional array of resistive memory cells, a two dimensional array of resistive memory cells, and/or a three dimensional array of resistive memory cells.
  • a memory element of RRAM array 101 can be a RRAM, such as selected RRAM 109.
  • a memory element may include a memristor, a phase change memory ceil, a programmable metallization cell, or other suitable resistive memory cell.
  • references to RRAM are to include such types of memory ceils.
  • RRAM array 101 uses the resistance value of each memory element to store one or more bits of data.
  • the device 100 is to perform low-headroom RRAM operations.
  • the first circuit 1 10 of device 100 includes amplifier 1 19 and transistor 1 15. A gate of the transistor 1 15 is controlled by output of the amplifier 1 19.
  • the first circuit 1 10 is to sample and hold, during a first phase of operation of the device 100, the sneak current 109 of the RRAM array 101 based on sample and holding a gate potential of the transistor 1 15.
  • the phases of operation for the device 100 may be established by the interaction between circuits, e.g., based on a switch(es) selectively electrically coupling the first circuit 1 10 to other circuit(s).
  • the first circuit 1 10 is to subtract off, during a second phase, the sneak current 104 from the total current 106 of the selected RRAM 109, to isolate the RRAM current 108 for sensing.
  • the device 100 may be used to enable various operations in first and/or second phases.
  • An example first operation is to force a known voltage onto the RRAM array 101 via clamping.
  • An example second operation is to sample the sneak current 109 of the RRAM array 101 .
  • An example third operation is to sample the total current 106 of the selected RRAM 109 and subtract the held sneak current 109. These operations can collectively be referred to as sneak current subtraction.
  • An example fourth operation is to compare the RRAM current 108 to a threshold current, and resolve a logic value based on the difference ( ⁇ or ⁇ '). This operation is known as sensing.
  • the first circuit 1 10 may perform sample and hold operations on the gate of the transistor 1 15 to enable low-voltage sample and holding. Examples also enable sensing the status of the selected RRAM 109 based on voltage sensing, and/or current sensing. The sensing may be performed using a transimpedance amplifier (TIA) to sense currents using a resistor, as well as other approaches to sense voltages.
  • TIA transimpedance amplifier
  • the example circuit topologies described herein can operate with low voltage headroom, targeting on the order of 0.5 V and lower (e.g., 0.2 V).
  • the operational headroom enables more voltage drop/headroom across the RRAM array 101 .
  • example circuits can incorporate sneak current subtraction info an amplifier, avoiding a need for a two-stage amplifier.
  • device 100 enables low headroom clamping, sneak current subtraction, and sensing circuit topologies, enabling optimized usage of the limited voltage across the RRAM array 101 . More headroom across the RRAM array 101 enables voltages to be applied to improve the fidelity of memory element ceils (thereby reducing bit error rate (BER)), and/or to reduce the overall power required by the device 100.
  • BER bit error rate
  • FIG. 2 is a block diagram of a system 200 including a first circuit 210 according to an example.
  • a RRAM array 201 is coupled to a RRAM array node
  • the first circuit 210 includes an amplifier 219 coupled to a reference voltage
  • the amplifier 219 also is selectively coupled, via a first switch 213 (SW3), to a first node 212.
  • the first node 212 also is coupled to a capacitor 214 and a gate 218 of a transistor 215.
  • the first circuit 210 is coupled to the RRAM array node 202 via a drain 217 of transistor 215, whose source 218 is coupled to ground.
  • System 200 includes the transistor 215 (M2) and capacitor 214 connected to an output of the operational amplifier (op-amp) 219.
  • the amplifier 219 is to control the gate 218 of the transistor 215, for sample and hold operations while reducing headroom.
  • Use of these components in the illustrated arrangement enables reduction of voltage at the RRAM array node 202, to a low value to support such circuitry, enabling operation of the entire RRAM array 201 with a lower voltage on RRAM array node 202 (e.g., on the order of 0.5 volts and lower), for low-headroom operation of the system 200 (e.g., the drain 217 of the transistor 215 is coupled to the RRAM array node 202).
  • the system 20(3 uses a single-stage amplifier 219 followed by the sneak current subtraction NMOS transistor 215 (M2) with its drain 217 voltage in feedback.
  • switch SW3 In operation, during a first phase to sample sneak current, switch SW3 is closed/ON.
  • the amplifier 219 holds the RRAM array node 202 at VREF 203, and the gate voltage of transistor 215 (M2) is controlled such that the current passing through the transistor 215 is the summation of at least a portion of the source current (12) and the RRAM array sneak current, if the input impedance of the amplifier is high (i.e., for CMOS approaches), then a large majority, or all of, the source current will pass through the transistor 215 (M2).
  • the first switch 213 (SW3) is open/OFF.
  • the capacitor 214 holds the voltage of the gate 216 of transistor 215 (M2), which causes transistor 215 (M2) to sink the summation of the source current (12) and the sneak current from the RRAM array 201 , thus performing sneak current subtraction. Furthermore, the output of the drain 217 of transistor 215 (M2), when in feedback, is going to assume a value substantially equal to reference voltage 203 (Vref). When disconnected via the first switch 213 (SW3), more current is sourced across the transistor 215 (M2), and the drain 217 of transistor 215 (M2) will rise.
  • FIG. 3 is a block diagram of a system 300 including a first circuit 310 according to an example.
  • the first circuit 310 is selectively coupled, via a first switch 313 (SW3), to a RRAM array node 302.
  • a RRAM array 301 is also coupled to the RRAM array node 302.
  • the first circuit 310 includes a first node 312 coupled to a gate 316 of a transistor 315.
  • the first node 312 is also coupled to a capacitor 314 and the first switch 313, which is coupled to the RRAM array node 302.
  • the first circuit 310 also is coupled to the RRA array node 302 via a drain 317 of transistor 315', whose source 318 is coupled to ground.
  • the first circuit 310 includes at least a portion that can operate as an amplifier 319, which is coupled to reference voltage 303 and source current 31 1 .
  • the transistor 315' whose drain 317 is coupled to the RRAM array node 302, and whose source 318 is coupled to ground, can provide low- headroom operation of the device 300, based on enabling sampling of the RRAM array 301 at voltages on the order of 0.5 volts and lower.
  • the transistors 315 (M2) and 315' (M4) can work together to enable low-headroom sample and hold operation.
  • the first circuit 310 is based on a topology to provide low headroom, e.g., enabling clamping and sampling based on the drain-source voltage (VDS) drop associated with the transistor 315' (M4). Such a drop may be on the order of 200 mV. Such a low value provides the transistor 315' with ample headroom to operate in saturation.
  • VDS drain-source voltage
  • a selected RRAM of the RRAM array 301 is enabled, e.g., by tying the corresponding RRAM's switches from V2 to V1 in the RRAM array 301 .
  • the first circuit 310 Prior to enabling the selected RRAM, the first circuit 310 is to open the first switch 313 (SW3), and hold the voltage at the first node 312, i.e., the voltage corresponding to the sneak current from the RRAM array 301 that was passing though the transistor 315' (M4).
  • the first circuit 310 can hold the voltage at the first node 312 using the capacitor 314, thereby avoiding leakage-induced voltage droop (e.g., due to gate leakage of transistor 315 (M2) and the first switch 1 13 (SW3)) and effectively subtracting the sneak current through the transistor 315' (M4).
  • leakage-induced voltage droop e.g., due to gate leakage of transistor 315 (M2) and the first switch 1 13 (SW3)
  • switch SW3 is closed/ON.
  • the differential pair formed from the transistors M1 , M2, M3, and M4 holds the RRAM array node 302 at a voltage value corresponding to VREF 303, and the gate voltage of transistor 315 (M2) is controlled such that the current passing through transistor 315' (M4) is the summation of at least a portion of source current 31 1 (12) and the sneak current of the RRAM array 301 . in this way, the sneak current subtraction function is built into the differential pair single stage amplifier 319 of the first circuit 310 (i.e., the transistor 315' forms a portion of the amplifier 319).
  • switch SW3 is open/OFF, and the capacitor 314 holds the voltage of the gate 318 of transistor 315 ( 2), which causes transistor 315' (M4) to sink the summation of a portion of the source current 31 1 (12) and the sneak current of the RRAM array 301 , thus performing sneak current subtraction.
  • FIG. 4 is a block diagram of a system 400 including a first circuit 410 and a second circuit 420 according to an example.
  • the first circuit 410 is selectively coupled, via a first switch 413 (SW3), to a RRAM array node 402.
  • the second circuit 420 is selectively coupled, via a switch (SW2), to the RRAM array node 402.
  • the second circuit 420 includes a threshold current 422, and is selectively coupled to reference voltage 403 via a switch (SW1 ).
  • a RRAM array 401 is also coupled to the RRAM array node 402.
  • the first circuit 410 includes a first node 412 coupled to a gate 416 of a transistor 415.
  • the first node 412 is also coupled to a capacitor 414 and the first switch 413, which is coupled to the RRAM array node 402.
  • the first circuit 410 also is coupled to the RRAM array node 402 via a drain 417 of transistor 415', whose source 418 is coupled to ground.
  • the first circuit 410 includes at least a portion that can operate as an amplifier 419, which is coupled to reference voltage 403 and source current 41 1 .
  • Status of the system 400 such as RRAM current of a selected RRAM of the RRAM array 401 , can be sensed based on voltages Vsensel (coupled to the first node 412) and Vsense2 (coupled to the RRAM array node 402).
  • the first circuit 410 includes the transistor 415', whose drain 417 is coupled to the RRAM array node 402 of the RRAM array 401 .
  • the source 418 of the transistor 415' is coupled to ground.
  • transistor 415' can provide low- headroom operation of the device 400, based on enabling sampling of the RRAM array 401 at voltages on the order of 0.5 volts and lower.
  • the first circuit 410 is based on a topology to provide low headroom, e.g., enabling clamping and sampling based on the drain-source voltage (VDS) drop associated with the transistor 415' (M4). Such a drop may be on the order of 200 mV. Such a low value provides the transistor 415' with ample headroom to operate in saturation.
  • VDS drain-source voltage
  • a selected RRAM of the RRAM array 401 is enabled, e.g., by tying the corresponding RRAM's switches from V2 to V1 in the RRAM array 401 .
  • the first circuit 410 Prior to enabling the selected RRA , the first circuit 410 is to open the first switch 413 (SW3), and hold the voltage at the first node 412, i.e., the voltage corresponding to the sneak current from the RRAM array 401 that was passing though the transistor 415' (M4).
  • the first circuit 410 can hold the voltage at the first node 412 using the capacitor 414, thereby avoiding leakage-induced voltage droop (e.g., due to gate leakage of transistor 415 (M2) and the first switch 1 13 (SW3)) and effectively subtracting the sneak current through the transistor 415' (M4).
  • leakage-induced voltage droop e.g., due to gate leakage of transistor 415 (M2) and the first switch 1 13 (SW3)
  • the first circuit 410 is operated to sample the sneak current of the RRAM array 401 .
  • the first circuit 410 is operated to sense voltage and/or current corresponding to determining a state of a selected RRAM of the RRAM array 401 .
  • switches SW1 and SW3 are closed/ON, while switch SW2 is open/OFF.
  • the differential pair formed from the transistors M1 , M2, M3, and M4 holds the RRAM array node 402 at a voltage value corresponding to VREF 403, and the gate voltage of transistor 415 (M2) is controlled such that the current passing through transistor 415' (M4) is the summation of at least a portion of source current 41 1 (12) and the sneak current of the RRAM array 401 .
  • the sneak current subtraction function is built into the differential pair single stage amplifier of the first circuit 410.
  • the threshold current 422 (1TH) is tied to VREF 403 through switch SW1 .
  • switches SW1 and SW3 are open/OFF, and SW2 is closed/ON.
  • the capacitor 414 holds the voltage of the gate 416 of transistor 415 (M2), which causes transistor 415' (M4) to sink the summation of a portion of the source current 41 1 (12) and the sneak current of the RRAM array 401 , thus performing sneak current subtraction.
  • a third circuit may be coupled to the first circuit 410 to perform current sensing (e.g., a T!A using a resistor to sense current per FIGS. 5 and 8).
  • the voltages Vsensel and Vsense2 may be monitored to perform voltage mode sensing, e.g., in applications where the sneak current is low or somewhat on the order of the selected RRAM's current. The sneak current will likely change as the voltage at Vsense2 (RRAM array node 402) changes, which can affect the ability to sense depending on whether the current is greater than or less than threshold current 422 (ITH),
  • FIG. 4 is compatible with the use of a variety of different sense amp approaches, including a TIA-based approach and other variations.
  • a latched comparator may be used to sense the voltages at Vsensel and Vsense2. If voltages at the sensing nodes change, the change may be used as a sensing signal to detect voltage sensing, even without monitoring for current changes/sensing.
  • the first circuit 410 does not need an additional circuit for clamping (such as a TIA circuit), because the samp!e-and- hold operation provided at the first node 412 provides a clamping function. Slight deviations from that clamping voltage may be sensed as a sensing signal to identify the RRAM status.
  • the examples illustrated in FIGS. 2-6 include topologies that may be operated according to the same first and second timing phases.
  • the first phase is to sample sneak current of the RRAM array 401 .
  • the second phase is to sample the selected RRAM current, in which the sneak current is subtracted from the selected RRAM's total current, and the resulting value is compared to a reference current (i.e. sensed).
  • the voltages of the nodes such as VREF, Vsensel , Vsense2 can then be sent to a latched comparator or other third circuit (not shown in FIG. 4) for conversion to digital logic levels.
  • examples described herein may combine the two functions of clamping and sample and holding when sensing, e.g., by controlling the gate voltage of transistor 415 by an amplifier 419, thereby reducing the voltage level and headroom compared to having to perform such functions separately.
  • FIG. 5 is a block diagram of a system 500 including a first circuit 510, a second circuit 520, and a third circuit 530 according to an example.
  • a RRAM array 501 is coupled to a RRAM array node 502.
  • the first circuit 510 includes an amplifier 519 coupled to a reference voltage 503.
  • the amplifier 519 also is selectively coupled, via a first switch 513 (SW3), to a first node 512.
  • the first node 512 also is coupled to a capacitor 514 and a gate 516 of a transistor 51 5.
  • the first circuit 510 is coupled to the RRAM array node 502 via a drain 517 of transistor 515, whose source 518 is coupled to ground.
  • the second circuit 520 is selectively coupled, via a switch (SW2), to the RRAM array node 502.
  • the second circuit 520 includes a threshold current 522, and is selectively coupled to reference voltage 503 via a switch (SW1 ).
  • the third circuit 530 includes resistor 534, selectively coupied to the first circuit 510 via a second switch 538 (SW4).
  • the third circuit 530 also includes a reference voltage 503. Status of the system 500, such as RRAM current of a selected RRAM of the RRAM array 501 , can be sensed based on sense voltage 532 (Vsense).
  • System 500 includes the transistor 515 (M2) and capacitor 514 connected to an output of the operational amplifier (op-amp) 519.
  • Use of these components in the illustrated arrangement enables reduction of voltage at the RRAM array node 502, to a low value to support such circuitry, enabling operation of the entire RRAM array 501 at a lower voltage on the order of 0.5 volts and lower, for low-headroom operation of the system 5(30 (e.g., the drain 517 of the transistor 515 is coupied to the RRAM array node 502).
  • the system 500 uses a single-stage amplifier 519 followed by the sneak current subtraction NMOS transistor 515 (M2) with its drain 517 voltage in feedback.
  • the system 500 can obtain multiple uses from the illustrated TIA amplifier arrangement, to sample and then cancel the sneak current using the unique application of the TIA. For example, in a first phase based on the arrangement of switches SW1 -SW5, the circuits of system 500 can sample the sneak current, and in a second phase the circuits are to operate as a TIA using the resistor 534 to sense the current. When switching the first and second modes with the 2 ⁇ stage op-amp, ringing may result in taking longer to stabilize. Thus, examples may also use some compensation capacitors (not shown in FIG. 5) to improve stability of the total feedback loop. Compensation may be achieved using relatively large capacitances as needed, and/or using Miller compensation. For example, a capacitor may be coupled from the Vsense node 532 out to the output of the amplifier 519 (e.g., the gate of M2 or M1 ).
  • switches SW1 , SW3, and SW5 are closed/ON, while SW2 and SW4 are open/OFF.
  • the amplifier 519 holds the RRAM array node 502 at VREF 503, and the gate voltage of transistor 515 (M2) is controlled such that the current passing through the transistor 515 is the summation of at least a portion of the source current (12) and the RRAM array sneak current. If the input impedance of the amplifier is high (i.e., for CMOS approaches), then a large majority, or all of, the source current will pass through the transistor 515 (M2).
  • the threshold current 522 (ITH), is tied to reference voltage 503 (VREF) through SW1 , and the VSENSE node 532 is held at the reference voltage 503 (VREF) through switch SW5.
  • switches SW1 , 8 3, and SW5 are open/OFF, and switches SW2 and SW4 are closed/ON.
  • the capacitor 514 holds the voltage of the gate 516 of transistor 515 (M2), which causes transistor 515 (M2) to sink the summation of the source current (12) and the sneak current from the RRAM array 501 , thus performing sneak current subtraction.
  • the feedback network is now configured as a TIA, in which the difference between the threshold current (ITH) and the selected RRAM device current is driven across resistor R 534, thus performing current sensing.
  • ITH threshold current
  • the output at Vsense 532 will drive lower than the reference voltage 5(33 (VREF), and the opposite is true when the difference is negative.
  • the Vsense 532 voltage output will change by an amount set by the difference current multiplied by resistor R 534.
  • the system 500 enables the circuits 510, 520, and/or 530 to operate as a TIA in the second phase, when the second switch 536 (SW4) is closed.
  • SW4 When the second switch 536 (SW4) is open/OFF, and the first switch 513 (SW3) is closed/ON, then system 500 can operate in a 2-stage amplifier arrangement.
  • the second circuit 520 provides switches SW1 and SW2 and the threshold current 522.
  • the RRAM current can be compared to the threshold current 522, and the difference in current can be sensed by the TIA.
  • the threshold current 522 is equal to the RRAM current, then no current will pass across the resistor 534, and effectively the reference voltage 503 (Vref) and the sense node 532 (Vsense) will be equal, if there is a difference between the values, the difference current will flow across the resistor 534. if lower, the difference current will flow in the opposite direction across the resistor 534, resulting in a decrease in voltage.
  • an additional circuit (not shown), such as a latched comparator, can be used to sense Vref and Vsense, based on the system 500.
  • FIG. 6 is a block diagram of a system 600 including a first circuit 610, a second circuit 620, and a third circuit according to an example.
  • the first circuit 610 is selectively coupled, via a first switch 613 (SW3), to a RRA array node 602.
  • the second circuit 620 is selectively coupled, via a switch (SW2), to the RRAM array node 602.
  • the second circuit 620 includes a threshold current 622, and is selectively coupled to reference voltage 603 via a switch (8W1 ).
  • a RRAM array 601 is also coupled to the RRAM array node 602.
  • the first circuit 610 includes a first node 612 coupled to a gate 616 of a transistor 615.
  • the first node 612 is also coupled to a capacitor 614 and the first switch 613, which is coupled to the RRAM array node 602.
  • the first circuit 610 also is coupled to the RRAM array node 602 via a drain 617 of transistor 615', whose source 618 is coupled to ground.
  • the first circuit 610 includes at least a portion that can operate as an amplifier 619, which is coupled to reference voltage 603 and source current 61 1 .
  • the third circuit 630 includes resistor 634, selectively coupled to the first circuit 610 and the RRAM array node 602 via a second switch 636 (SW4).
  • the third circuit 630 also includes a reference voltage 603. Status of the system 600, such as RRAM current of a selected RRAM of the RRAM array 601 , can be sensed based on sense voltage 632 (Vsense).
  • Vsense sense voltage 632
  • the third circuit 630 can be operated as a TIA, based on the differential amp arrangement of transistors M5-M8 and the operation of the resistor 634 (R).
  • the third circuit 630 is thus a replica circuit (of the first circuit 610) having a TIA feedback resistor R. Similar to the operations described above with respect to transistor M4, the sneak current will pass through transistor 615' (M4), and the remaining portion of the selected RRAM current is passes across the resistor 634 to be sensed by the TiA third circuit 630.
  • the first circuit 610 and the third circuit 630 thus may be matched in an arrangement where they are very tightly coupled in layout and in design, having low offsets, to operate as matched amplifiers.
  • the first circuit 610 and the third circuit 630 can operate as a single-stage amplifier, which operates unconditionally stable based on one dominant pole at the output.
  • the first circuit 610 integrates the sneak current subtraction NMOS transistor 615' into the single-stage amplifier itself, thus eliminating the need for a two-stage amplifier configuration and enabling a topology that is stable even with large capacitances on the RRAM array node 602.
  • switches 8W1 and SW3 are c!osed/ON, while switches SW2 and SW4 are open/OFF.
  • the differential pair formed by transistors M1 , M2, M3, and M4 holds the RRAM array node 6(32 at reference voltage 603 (VREF), and the voltage of the gate 616 of the transistor 615 (M2) is controlled such that the current going through transistor 615' (M4) is the summation of at least a portion of the source current 61 1 (12) and the RRAM array sneak current.
  • the sneak current subtraction function is built into the differential pair single-stage amplifier 619.
  • the threshold current 622 (1TH) is tied to the reference voltage 603 (VREF) through SW1 , and the sense voltage node 632 (VSENSE) node is held at the reference voltage 603 (VREF) via the differential pair formed by transistors M5, M6, M7, and M8.
  • switches SW1 and SW3 are open/OFF, and switches SW2 and SW4 are ciosed/ON.
  • the capacitor 614 holds the voltage of the gate 616 of the transistor 615 (M2), which causes transistor 615' (M4) to sink the summation of at least a portion of source current 61 1 (12) and the RRAM array sneak current, thus performing sneak current subtraction.
  • M7 and M8 is now configured as a TIA, in which the difference between the threshold current 622 (ITH) and the selected RRAM current is driven across the resistor 634, thus performing current sensing.
  • ITH threshold current 622
  • VSENSE sense node 632
  • VREF reference voltage 603
  • VSENSE sense node 623
  • the first circuit 610 when the first switch 613 (SW3) is closed, can operate as a unify gain buffer to clamp the RRAM array node 602 to the reference voltage 603 (VREF).
  • the drain of transistor 615' (M4) which is tied to the RRAM array node 602, can serve as a type of feedback node with the gate 616 of transistor 615 (M2) serving as the negative terminal.
  • the first circuit 610 can operate as a unity gain amplifier in feedback, basically holding the first node 612 at the reference voltage 603,
  • the transistor 615 (M2) will be diode-connected, so the current will be steered through the branch M2, M4. such that its output is at Vref 603.
  • M3 sets the current of transistor 615' (M4), establishing what proportion of the source current 61 1 (12) goes down that branch of the amplifier 619, resulting in a difference pair type of balance between the left and right branches with the output equal to the reference voltage 603 (VREF).
  • the third circuit 630 may operate as a TiA, when the first switch 613 (SW3) turns off and the second switch 636 (SW4) turns on, because it is a replica amplifier with the addition of the feedback resistor 634.
  • the feedback resistor 634 converts the current into a voltage through the transimpedance of the resistance.
  • the output voltage sense voltage 632 VSENSE
  • the transimpedance amplifier of the third circuit 630 thereby provides damping, amplification, and sensing.
  • a latched comparator or similar approach may be used to compare the sense node voltage 632 (Vsense) to the reference voltage 603 (Vref). Depending on the result, it can be determined whether the selected RRA is in the low resistance state or high resistance state. Further, similar to the devices 300 and 400 of FIGS. 3 and 4, the sneak current subtraction NMOS transistor is incorporated in the amplifier, avoiding a need for a relatively less stable two-stage amplifier topology.
  • FIG. 7 and 8 flow diagrams are illustrated in accordance with various examples of the present disclosure.
  • the flow diagrams represent processes that may be utilized in conjunction with various systems and devices as discussed with reference to the preceding figures. While illustrated in a particular order, the disclosure is not intended to be so limited. Rather, it is expressly contemplated that various processes may occur in different orders and/or simultaneously with other processes than those illustrated.
  • FIG. 7 is a flow chart 700 based on isolating RRAM current for sensing according to an example.
  • a first circuit is to sample and hold, during a first phase, a sneak current of a RRAM array and at least a portion of a source current, wherein the first circuit includes an amplifier and a transistor whose gate is controlled by output of the amplifier, coupled to a RRAM array node.
  • an amplifier coupled to a gate of a transistor may set a voltage at the gate of the transistor, which is held by a capacitor.
  • the transistor may be coupled to a RRAM array node to receive the sneak current and/or the selected memristor current.
  • the first circuit is to subtract off, during a second phase, the sneak current and at least the portion of the source current from a total current of a selected RRAM to isolate the RRAM current for sensing.
  • the capacitor on the gate of the transistor can cause the amplifier to operate by subtracting the sneak current from the current of the selected RRAM.
  • a second circuit is to selectively provide, to the first circuit, a threshold current to be compared with the RRAM current for sensing based on electrically coupling the threshold current to the first circuit during the second phase.
  • a threshold current selectively may be coupled, via a switch, to the first circuit based on whether the system is operating according to a first phase or a second phase.
  • the second circuit is to isolate the threshold current from the first circuit during the first phase.
  • the switch coupling the threshold current to the first circuit may be open during the first phase (and closed during the second phase).
  • FIG. 8 is a flow chart 800 based on sensing RRAM current according to an example
  • a RRAM current is isolated based on first and second phases of a first circuit, including sampling/holding and subtracting off a sneak current.
  • the sneak current can be sampled and held during the first phase, and subtracted off during the second phase.
  • a third circuit is selectively coupled to the first circuit, based on a second switch closed during the second phase and open during the first phase, to sense the RRAM current of the selected RRAM.
  • the third circuit may be a TIA including a resistor to serve as a repiica circuit tightly coupled in layout and design to operate as a matched amplifier to the first circuit
  • a voltage is clamped at a RRAM array node, associated with the RRAM array, to a value on the order of 0.5 volts and lower.
  • a transistor of the first circuit may provide a VDS voltage from ground to the RRAM array node.
  • the RRAM current is sensed by the third circuit based on a comparison of a sense voltage of the third circuit and a reference voltage.
  • the third circuit may rely on a resistor to pass a current corresponding to the difference between a threshold voltage of a second circuit, and the isolated RRAM current.

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

Conformément à un aspect de l'invention, un dispositif donné à titre d'exemple pour effectuer des opérations RRAM à faible marge comprend un premier circuit comprenant un amplificateur et un transistor dont la grille est commandée par la sortie de l'amplificateur pour échantillonner et maintenir, pendant une première phase, un courant de fuite d'une matrice RRAM et au moins une partie d'un courant source d'après l'échantillonnage et le maintien d'un potentiel de grille du transistor. Le premier circuit est conçu pour soustraire, durant une seconde phase, le courant de fuite et au moins la partie du courant source d'un courant total d'une RRAM sélectionnée afin d'isoler le courant RRAM pour des opérations RRAM.
PCT/US2015/054531 2015-10-07 2015-10-07 Circuits permettant d'effectuer des opérations rram à faible marge WO2017062002A1 (fr)

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CN110556141A (zh) * 2018-06-01 2019-12-10 台湾积体电路制造股份有限公司 存储器电路和对rram器件执行写入操作的方法

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US20060250871A1 (en) * 2004-09-01 2006-11-09 Micron Technology, Inc. Sample and hold memory sense amplifier
US20110286259A1 (en) * 2010-05-24 2011-11-24 Hewlett-Packard Development Company, L.P. Reading Memory Elements Within a Crossbar Array
US20130100726A1 (en) * 2011-10-21 2013-04-25 Wei Yi Multi-level memory cell with continuously tunable switching
US20140211535A1 (en) * 2013-01-30 2014-07-31 Hewlett-Packard Development Company, L.P. Mitigation of inoperable low resistance elements in programable crossbar arrays

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Publication number Priority date Publication date Assignee Title
US20040090852A1 (en) * 2002-11-13 2004-05-13 Smith Kenneth Kay Power-saving reading of magnetic memory devices
US20060250871A1 (en) * 2004-09-01 2006-11-09 Micron Technology, Inc. Sample and hold memory sense amplifier
US20110286259A1 (en) * 2010-05-24 2011-11-24 Hewlett-Packard Development Company, L.P. Reading Memory Elements Within a Crossbar Array
US20130100726A1 (en) * 2011-10-21 2013-04-25 Wei Yi Multi-level memory cell with continuously tunable switching
US20140211535A1 (en) * 2013-01-30 2014-07-31 Hewlett-Packard Development Company, L.P. Mitigation of inoperable low resistance elements in programable crossbar arrays

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110556141A (zh) * 2018-06-01 2019-12-10 台湾积体电路制造股份有限公司 存储器电路和对rram器件执行写入操作的方法

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