WO2017048240A1

WO2017048240A1 - Silicon controlled rectifier with propagating trigger

Info

Publication number: WO2017048240A1
Application number: PCT/US2015/050221
Authority: WO
Inventors: Steven S. Poon; Nathan D. Jack
Original assignee: Intel Corporation
Priority date: 2015-09-15
Filing date: 2015-09-15
Publication date: 2017-03-23

Abstract

A silicon controlled rectifier may be used to protect an integrated circuit from excessive voltage encountered during an electrostatic discharge (ESD) event. An ESD protected circuit may be conductively coupled to an anode of a first silicon controlled rectifier (SCR) and to an anode and gate of a second SCR disposed proximate and on the same substrate as the first SCR. A trigger current may be used to trigger and latch-up the first SCR in the event of an ESD. A stray current may develop in the substrate responsive to the first SCR latching-up. This stray current may cause a charge accumulation at an N-well (i.e., gate) of the second SCR and may be used to sympathetically trigger and latch-up the second SCR in the absence of an externally supplied trigger current to the second SCR.

Description

SILICON CONTROLLED RECTIFIER WITH PROPAGATING TRIGGER

STEVEN S. POON

NATHAN D. JACK

TECHNICAL FIELD

The present disclosure relates to electrostatic discharge protection of integrated

BACKGROUND

Electrostatic discharges (ESDs) can range from tens of volts to thousands of volts.

Even relatively low voltage ESD events can damage or destroy an integrated circuit. With the ubiquity of portable electronic devices such as smartphones, handheld computers, and wearable computers, ESD events have become commonplace and the system design incorporates some level of ESD handling to protect sensitive system components. Some system manufacturers now require a "fail-safe" type of input/output in which integrated circuit "pins" must maintain a high impedance state even when power is removed from the integrated circuit. Many current ESD protection systems fail to satisfy the fail-safe I/O requirement in that a low impedance path exists when a power supply is unpowered.

Typically, a forward-biased series of diodes provides a trigger circuit for low voltage I/O (e.g. , 1.8V or less) applications. However, at higher operating voltages (e.g. , 3V to 5V), the leakage through such as forward biased diode string may be excessive. For higher voltage applications, a grounded gate N-type metal oxide semiconductor (ggNMOS) may be used as a low-leakage trigger circuit. In such instances, the ggNMOS replaces the diodes in the ESD protection circuit. The ggNMOS is a voltage triggered device that, upon reaching a trigger voltage, transitions from a high-impedance state to a low-impedance or high-current state. While the applied trigger voltage is greater than the operating voltage by a sufficient margin, the ggNMOS remains in a high-impedance state while providing a safe current path if an ESD event occurs. Unfortunately, the ggNMOS fails to provide adequate protection against ESD events for the latest finned field-effect transistor (FinFET) devices. With the latest 14 nm FinFET processes, ggNMOS device have been found unable to meet area and current leakage specification targets when used as the sole protection against ESD events.

Silicon controlled rectifiers (SCRs) may be used in place of ggNMOS devices to provide a measure of ESD protection. The SCR is also a voltage-triggered device that relies upon the parasitic bipolar junction transistors inherent in bulk CMOS processes. The trigger voltage and current of an SCR must be specified and become an integral part of the design for the SCR. BRIEF DESCRIPTION OF THE DRAWINGS

Features and advantages of various embodiments of the claimed subject matter will become apparent as the following Detailed Description proceeds, and upon reference to the Drawings, wherein like numerals designate like parts, and in which:

FIG. 1 is a partial schematic diagram of an illustrative electrostatic discharge (ESD) protection system, in accordance with at least one embodiment of the present disclosure;

FIG. 2 A is an illustrative die layout using a first silicon controlled rectifier (SCR), a plurality second SCRs, and a plurality of third SCRs, in accordance with at least one embodiment of the present disclosure.

FIG. 2B is another illustrative die layout using a first silicon controlled rectifier (SCR), a plurality second SCRs, and a plurality of third SCRs, in accordance with at least one embodiment of the present disclosure.

FIG. 3 is a high-level flow diagram of an illustrative method of triggering a number of second silicon controlled rectifiers (SCRs) using a stray current formed in a substrate by the triggering and latching-up of a first SCR using an externally supplied trigger current, in accordance with at least one embodiment of the present disclosure;

FIG. 4 is a high-level flow diagram of an illustrative method of triggering a number of third silicon controlled rectifiers (SCRs) based, at least in part, on a charge accumulation in the N-well of each of the number of third SCRs caused by a second stray current formed in a substrate by the triggering and latching-up of the second SCR, in accordance with at least one embodiment of the present disclosure.

FIG. 5 is a high-level flow diagram of an illustrative method of safely dissipating an overvoltage condition, such as that cause by an electrostatic discharge (ESD) event, via a first SCR and a number of second SCRs, in accordance with at least one embodiment of the present disclosure.

FIG. 6 is a high-level flow diagram of an illustrative method of safely dissipating an overvoltage condition, such as that cause by an electrostatic discharge (ESD) event by directing, via a first SCR and a number of second SCRs, the overvoltage condition for dissipation by a low potential structure, in accordance with at least one embodiment of the present disclosure. Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications and variations thereof will be apparent to those skilled in the art. DETAILED DESCRIPTION

The trigger current per unit cell of a silicon controlled rectifier plays a significant role in determining the operating efficiency and reliability of the SCR device. Maintaining a low trigger current per unit cell reduces the leakage power per cell and reduces the die area required for the SCR structure. If an SCR is intrinsically difficult to trigger, one option is to increase the size of the trigger circuitry (to improve the current handling capability of the circuit) which is often undesirable and may not even be possible if the trigger current is excessive. It has been observed that latch-up of an SCR generates a stray current within the SCR substrate. It has been further observed that, upon latch-up of the SCR , the stray current may be used to sympathetically trigger additional SCR s that are physically proximate the latched-up SCR .

When a P-N junction is forward biased in a bulk complementary metal oxide semiconductor (CMOS) device, minority carriers tend to diffuse toward the collector. At high levels, the current provided by these minority carriers may de-bias the P-well and/or N- well, thereby causing forward biasing of additional P-N junctions. This chain of events may lead to triggering parasitic PNPN devices that subsequently latch-up. It has been observed using failure-isolation techniques such as Infra-Red Emission Microscopy (IREM) that such latch-up phenomenon has a tendency to spread spatially. Since triggering an SCR is essentially identical to such latch-up phenomenon, such spatial spreading phenomenon may be relied upon to trigger an SCR.

In such instances, a first SCR may be positioned proximate or adjacent to any number of second SCR s. The first SCR is conventionally triggered, for example by providing a current signal to the gate of the first SCR. Upon latch-up of the first SCR, the substrate or stray current generated by the first SCR may be used to trigger one or more of the proximate or adjacent second SCR s. The stray current generated by the latch-up of the first SCR may be collected by the N-well tap of the second SCR. This stray current may de-bias the N-well and trigger latch-up of the second SCR. It is possible to accomplish such a sympathetic triggering using a flow of electrons or a flow of electron acceptors (i.e. , "holes"). In such an embodiment, the stray current may be generated by the PNP collector current. After latch-up occurs, stray current from both the NPN and PNP BJTs may inject in all directions and thus, particles having both negative (i.e., electrons) and positive (i.e., holes) polarities tend to contribute to the propagating triggering.

An electrostatic discharge (ESD) protection system is provided. The ESD protection system may include a first silicon controlled rectifier (SCR) and at least one second SCR proximately disposed on a substrate. The system may also include a trigger circuit conductively coupled to a gate of the first SCR. The ESD protection system may also include an ESD protected circuit conductively coupled to an anode of the first SCR and an anode and a gate of the second SCR wherein the gate of the second SCR includes a gate triggerable by a stray current carried by the substrate and a low potential structure conductively coupled to a cathode of the first SCR and to a cathode of the second SCR.

An electrostatic discharge (ESD) protection method is provided. The ESD protection method may include causing a stray current to flow through a substrate responsive to triggering and latching-up a first silicon controlled rectifier (SCR). The ESD protection method may include de-biasing an N-well of each of a number of second SCRs disposed on the substrate and proximate the first SCR. The ESD protection method may include autonomously triggering and latching-up each respective one of the number of second SCR s responsive to the de-biasing of the N-well of the respective second SCR.

An electrostatic discharge (ESD) protection system is provided. The ESD protection system may include a means for causing a stray current to flow through a substrate responsive to triggering and latching-up a first silicon controlled rectifier (SCR). The ESD protection system may additionally include a means for de -biasing an N-well of each of a number of second SCRs disposed on the substrate and proximate the first SCR and a means for autonomously triggering and latching-up each respective one of the number of second SCR s responsive to the de-biasing of the N-well of the respective second SCR.

FIG. 1 is a partial schematic diagram of an illustrative electrostatic discharge (ESD) protection system 100, in accordance with at least one embodiment of the present disclosure. The system 100 includes a first silicon controlled rectifier (SCR) 110A and a second SCR HOB. Although only a single second SCR 110B is shown in FIG. 1 for clarity, it is understood that any number of similar second SCRs HOB may be disposed proximate or adjacent to the first SCR 110A.

The first SCR 110A includes an N-well 120A and a P-well 130A. The N-well 120A includes P-doped regions 122A and 126A and an N-well tap 124A. The P-well 130A includes N-doped regions 132A and 136A and a P-well tap 134A. Within the N-well 120 A, a PNP bipolar junction transistor (BJT) 128 A is formed by the various P-N interfaces in the first SCR 110A. The emitter of the PNP BJT 128A is conductively coupled to the P-doped region 126A in the N-well 120 A. The collector of the PNP BJT 128 A is conductively coupled to the P-well tap 134A via the P-well 130A. The base of the PNP BJT is formed by the bulk N-well 120 A and is conductively coupled to the N-well tap 124A via the N-well 120A.

Within the P-well 130 A, an NPN BJT 138A is formed at the various P-N interfaces in the first SCR 110A. The emitter of the NPN BJT 138A is conductively coupled to the N- doped region 132A in the P-well 130A. The collector of the NPN BJT 138 A is conductively coupled to the N-doped region 124A in the N-well 120A. The base of the NPN BJT 138 A is conductively coupled to the P-well tap 134A via the P-well 130A.

The P-doped region 126A in the N-Well 120A provides the anode for the first SCR and is conductively coupled to an ESD protected circuit 102. In at least some

implementations, the ESD protected circuit 102 may include one or more input/output circuits conductively coupled to one or more integrated circuits. In some implementations, the ESD protected circuit 102 may include one or more input/output circuits conductively coupled to a power supply such that the first SCR 120A provides ESD protection even when the power supply is in an unpowered state.

The N-doped region 132A in the P-well 130A provides the cathode for the first SCR and is conductively coupled to a low potential structure 106. In some implementations, the low potential structure 106 may include one or more structures at a potential less than the operating potential of the ESD protected circuit 102. In some implementations, the low potential structure 106 may include an earth ground.

The first SCR 110A is configured such that a trigger current 104 supplied to the N- doped region of the N-well 120A causes the PNP BJT 128A to transition to a low-impedance (i.e., high-current) state. Once the PNP BJT 128 A enters a low- impedance state, the PNP BJT 138 A also enters a low-impedance state and latches-up the first SCR 110A. A current 142A flows from the NPN BJT 138A to the N-well tap 124A. A current 144 A flows from the PNP BJT 128 A to the P-well tap 134A. The first SCR 110A will remain in the low- impedance state regardless of the presence or absence of the trigger signal at the N-well tap 124A and will only return to a high- impedance state when the voltage at the P-doped region 126A falls below a defined threshold voltage value, such as 0.1V, 0.3V, 0.5, 1.0V, 1.8V, 3V, Each second SCR HOB includes an N-well 120B and a P-well 130B. The N-well 120B includes P-doped regions 122B and 126B and an N-well tap 124B. The P-well 130B includes N-doped regions 132B and 136B and a P-well tap 134B. Within the N-well 120B, a PNP BJT 128B is formed by the various P-N interfaces in the first SCR HOB. The emitter of the PNP BJT 128B is conductively coupled to the P-doped region 126B in the N-well 120B. The collector of the PNP BJT 128B is conductively coupled to the P-well tap 134B. The base of the PNP BJT is formed by the bulk N-well 120B and is conductively coupled to the N-well tap 124B.

Within the P-well 130B, an NPN BJT 138B is formed at the various P-N interfaces in the first SCR 110B. The emitter of the NPN BJT 138B is conductively coupled to the N- doped region 132B in the P-well 130B. The collector of the NPN BJT 138B is conductively coupled to the N-well tap 124B in the N-well 120B. The base of the NPN BJT 138B is conductively coupled to the P-well tap 134B.

The second SCR 11 OB is configured differently from the first SCR 110A. Instead of a trigger current 104 supplied to the N-doped region of the N-well 120B, the second SCR HOB may be triggered by a stray current 160 that flows through a substrate on which both the first SCR 110A and the second SCR 110B are formed. In at least some implementations, the stray current 160 may at least partially result from the first SCR 110A "latching-up" in response to the presence of a trigger current 104 at the N-well tap 124 A. Once the PNP BJT 128B enters a low-impedance state, the PNP BJT 138B also enters a low-impedance state and latches-up the second SCR 110B. A current 142Bflows from the NPN BJT 138B to the N- well tap 124B. A current 144B flows from the PNP BJT 128B to the P-well tap 134B.

The second SCR HOB will remain in the low-impedance state regardless of the presence or absence of the trigger signal at the N-well tap 124A of the first SCR 110A and/or the presence of the stray current 160 and will only return to a high-impedance state when the voltage at the P-doped region 126B falls below a defined threshold voltage value.

Advantageously, the stray current 160 caused by the latching-up of the first SCR 110A reduces or eliminates the use of a trigger current in the at least one second SCR 110B. For example, assuming a trip current of Ι^_Ρ for each of "N" SCRs 110, the required trip current using the configuration depicted in FIG. 1 is I_tn_P versus "N" times Ι^_Ρ (i.e., N * I_tdp) for a conventional layout in which each SCR 110 is individually supplied with a trip current. This reduction in trip current may permit the use of physically smaller trigger circuitry. The use of physically smaller circuitry beneficially reduces the leakage power and also permits greater component density for a given die size. In addition, by conductively coupling the ESD protected circuit 102 to the gate 124B on each of the non-externally triggered second SCRs HOB, provides protection in the event of a "negative polarity" high voltage event in which the ESD protected circuit 102 generates the voltage surge. When the ESD protected circuit 102 generates a high voltage event, the substrate-N-well junction may become forward biased. It is therefore possible to provide reverse polarity ESD protection without requiring the use of additional components (e.g., a separate diode to provide negative polarity protection). Such a reduction in component count permits a more compact die layout, greater efficiency, and reduced capacitance.

FIG. 2A and FIG. 2B depict illustrative layouts using a first silicon controlled rectifier (SCR) 110A, a plurality second SCRs HOB, and a plurality of third SCRs 205, in accordance with at least one embodiment of the present disclosure. As discussed above, a trigger current 104 may be supplied to a number of first SCRs 110A. The trigger current 104 may be supplied by a trigger circuit 210 that includes any number or combination of devices capable of generating a current signal of sufficient magnitude and duration to trip and latch-up the first SCRs 110A. Example trigger circuits 210 may include, but are not limited to, one or more grounded gate N-type metal oxide semiconductors (ggNMOS), one or more diodes, or combinations thereof. The trigger circuit 210 may supply the trigger current 104 to the gate (i.e. , the N-well tap 124A) of each of at least some of the first SCRs 110A. The trigger circuit 210 may generate the trigger current 104 upon detecting an occurrence of an overvoltage event such as an electrostatic discharge event occurring at some point on the ESD protected circuit or an overvoltage event occurring within an integrated circuit communicably coupled to the ESD protected circuit.

At least some of the first SCRs 110A are tripped and latch-up upon receipt of the trigger current 104. In some implementations, the trigger circuit 210 provides the trigger current 104 to the gate of the first SCRs 110A. Upon latch-up, a stray current 160 forms in the substrate supporting the first SCRs 110A, the second SCRs HOB, and the third SCRs 220. The stray current 160 may be collected by the N-well tap 124B of the second SCRs HOB, de-bias the N-well and trigger latch-up in at least some of the second SCRs 110B.

Upon latch-up of at least some of the second SCRs 110B, a second stray current 230 may form in the substrate. The stray current 160 and the second stray current 230 contributed by the second SCRs 110B may, in turn, be collected by the N-well tap of the third SCRs 220, de-bias the third SCR 220 N-well and trigger latch-up in at least some of the third SCRs 220. Although limited to three SCRs for brevity, this type of "chain-reaction" N-well de-biasing leading to triggering and latch-up of SCRs not conductively coupled to an external trigger current may continue to grow or otherwise propagate throughout some or all of the ESD protection SCRs included in the die. Thus, a single SCR coupled to an external trigger circuit 210 may be able to beneficially trigger and latch-up a large number of SCRs that are not conductively coupled to the trigger circuit.

FIG. 3 is a high-level flow diagram of an illustrative method 300 of triggering a number of second silicon controlled rectifiers (SCRs) HOB using a stray current 160 formed in a substrate by the triggering and latching-up of a first SCR 110A using an externally supplied trigger current 104, in accordance with at least one embodiment of the present disclosure. One or more ESD protected circuits 102 may be conductively coupled to any number of second SCRs HOB. The second SCRs HOB may be conductively coupled to a low potential structure 106, such as an earth or chassis ground. An overvoltage event at the ESD protected circuit 102 may be safely dissipated to the low potential structure 106 by transitioning at least some of the number of second SCRs HOB from a high-impedance state to a low-impedance state.

In embodiments, the transition from a high-impedance state to a low-impedance state may occur when sufficient charge accumulates at the N-well tap 124B of the second SCR HOB. In embodiments, the second SCRs 110B may trigger and latch-up based on a charge accumulation caused by stray currents in the substrate and not based on the presence of an externally supplied trigger current 104. Such stray currents may include at least the stray current 160 produced by the first SCR 110A. Such stray currents may additionally or alternatively include a second stray current 230 that may be produced upon triggering and latching-up of one or more neighboring second SCRs HOB. In embodiments, the stray current 160 and/or the second stray current 230 may de-bias the N-wells 124B in any number of second SCRs 110B, causing at least some of the second SCRs 110B to trigger and latch- up. The method 300 commences at 302.

At 304, the triggering and latching-up of the first SCR 11 OA may cause, create, generate, or otherwise produce a stray current 160 in the substrate beneath the respective first SCR 11 OA. In embodiments, the stray current 160 may flow through the substrate responsive to the triggering and latching-up of the respective second SCR HOB.

A number of second SCRs HOB may be disposed proximate at least a portion of the number of first SCRs 110A. In some instances, the die area occupied by at least some of the number of second SCRs HOB may be physically adjacent the die area occupied by at least some of the number of first SCRs 110A. Thus, in embodiments, the first SCR 110A and the number of second SCRs HOB may all occupy respective areas of a common die (i.e. , all of the SCRs 110A and 110B may be formed on the same, contiguous, substrate).

In embodiments, the stray current 160 produced by at least some of the number of first SCRs 110A may take the form of a flow of electrons through the substrate. At least a portion of the stray current 160 may result in a net charge imbalance or accumulation at the N-well 124B of one or more second SCRs HOB. In embodiments, the stray current 160 may take the form of a flow of holes or electron acceptors through the substrate, at least a portion of which may result in a net charge imbalance or accumulation at the N-well 124B of one or more second SCRs HOB.

At 306, the stray current 160 produced by the triggered and latched-up first SCR

HOB de-biases the N-well 124B of at least one of a number of second SCRs HOB. The at least one second SCR 110B may be disposed on the same substrate as the first SCR 110A and is located proximate the first SCR 110A. In embodiments, at least a portion of the stray current 160 may collect or otherwise accumulate at the N-well tap 124B of the second SCR HOB.

At 308, the charge accumulation at the N-well tap 124B caused, at least in part by the stray current 160 may de-bias the N-well tap 124B of the second SCR HOB. De-biasing the N-well 124B of the second SCR HOB may result in autonomous triggering and latching-up the respective second SCR HOB. Triggering and latching-up of the second SCR HOB provides a low-impedance path conductively coupling the ESD protected circuit 102 to the low potential structure 106. The existence of a low-impedance path between the ESD protected circuit 102 and the low potential structure 106 permits the overvoltage in the ESD protected circuit to safely pass through the second SCR HOB and dissipate within the low potential structure 106. The method 300 concludes at 310.

FIG. 4 is a high-level flow diagram of an illustrative method 400 of triggering a number of third silicon controlled rectifiers (SCRs) 220 based, at least in part, on a charge accumulation in the N-well of each of the number of third SCRs 220 caused by a second stray current 230 formed in a substrate by the triggering and latching-up of the second SCR HOB, in accordance with at least one embodiment of the present disclosure. One or more ESD protected circuits 102 may be conductively coupled to any number of third SCRs 220. The third SCRs 220 may be conductively coupled to a low potential structure 106, such as an earth or chassis ground. An overvoltage event at the ESD protected circuit 102 may be safely dissipated to the low potential structure 106 by transitioning the third SCR 220 from a high- impedance state to a low-impedance state. In embodiments, the transition from a high-impedance state to a low-impedance state may occur when sufficient charge accumulates at the N-well tap of the third SCR 220. In embodiments, the third SCRs 220 may trigger and latch-up based on a charge accumulation caused by stray currents in the substrate and not based on the presence of an externally supplied trigger current 104. Such stray currents may include the stray current 160 produced by the first SCR 110A. Such stray currents may additionally or alternatively include a second stray current 230 that may be produced upon triggering and latching-up of the second SCR HOB. In embodiments, the stray current 160 and/or the second stray current 230 may de-bias the N-wells in any number of third SCRs 220, causing at least some of the third SCRs 230 to trigger and latch-up. The method 400 commences at 402.

At 404, the triggering and latching-up of the second SCR HOB may cause, create, generate, or otherwise produce a second stray current 230. In embodiments, the second stray current 230 may flow through the substrate responsive to the triggering and latching-up of the respective second SCR HOB.

A number of third SCRs 220 may be disposed proximate at least a portion of the number of second SCRs HOB. In some instances, the die area occupied by at least some of the number of third SCRs 220 may be physically adjacent the die area occupied by at least some of the number of second SCRs HOB. Thus, in embodiments, the first SCR 110A, the number of second SCRs HOB, and the number of third SCRs 220 may all occupy respective areas of a common die (i.e. , all of the SCRs 110A, 110B, and 220 may be formed on the same, contiguous, substrate).

In embodiments, the second stray current 230 produced by at least some of the number of second SCRs HOB may take the form of a flow of electrons through the substrate. At least a portion of the second stray current 230 may result in a net charge imbalance or accumulation at the N-well of one or more third SCRs 220. In embodiments, the second stray current 230 may take the form of a flow of holes or electron acceptors through the substrate, at least a portion of which may result in a net charge imbalance or accumulation at the N-well of one or more third SCRs 220.

At 406, the second stray current 230 from the second SCR 110B de-biases the N-well of at least one of a number of third SCRs 220. In at least some implementations, the stray current 160 caused by the triggering and latching-up of the first SCR 11 OA may also contribute to the charge accumulation at and subsequent de-biasing of the N-well of the at least one of the number of third SCRs 220. The at least one third SCR 220 may be disposed on the same substrate as the second SCR 110B and the first SCR 110A and is located proximate the second SCR HOB. In embodiments, at least a portion of the stray current 160 and/or second stray current 230 may be collected at the N-well tap of the third SCR 220.

At 408, the charge accumulation at the N-well tap caused, at least in part by the stray current 160 and/or the second stray current 230, may de-bias the N-well of the third SCR 220. De-biasing the N-well of the third SCR 220 may result in autonomous triggering and latching-up the at least one third SCR 220. Triggering and latching-up of the third SCR 220 provides a low-impedance path conductively coupling the ESD protected circuit 102 to the low potential structure 106. The existence of a low-impedance path between the ESD protected circuit 102 and the low potential structure 106 permits the overvoltage in the ESD protected circuit to safely dissipate within the low potential structure 106. The method 400 concludes at 410.

FIG. 5 is a high-level flow diagram of an illustrative method 500 of safely dissipating an overvoltage condition, such as that cause by an electrostatic discharge (ESD) event, via a first SCR 110A and a number of second SCRs 110B, in accordance with at least one embodiment of the present disclosure. A silicon controlled rectifier includes an anode, a cathode, and a gate. In the absence of a current input to the gate or a voltage at the anode exceeding the breakthrough voltage of the SCR, an SCR presents a high impedance pathway between the anode and cathode that permits very little current flow through the SCR.

However, when tripped, the SCR latches-up and maintains a low-impedance pathway between the anode and cathode that only transitions back to the high-impedance state when the voltage at the anode falls below a defined threshold voltage value. The method 500 commences at 502.

At 504, an ESD protected circuit 102 is conductively coupled to a P-doped region 126A that functions as the anode of the first SCR 110A.

At 506, the ESD protected circuit 102 is conductively coupled to a P-doped region

126B that functions as the anode of the second SCR HOB. The ESD protected circuit 102 is also conductively coupled to an N-well tap 124B that functions as the gate of the second SCR HOB. The method 500 concludes at 508.

FIG. 6 is a high-level flow diagram of an illustrative method 600 of safely dissipating an overvoltage condition, such as that cause by an electrostatic discharge (ESD) event by directing, via a first SCR 110A and a number of second SCRs 110B, the overvoltage condition for dissipation by a low potential structure 106, in accordance with at least one embodiment of the present disclosure. The first SCR 110A and the second SCR HOB may be conductively coupled to the same low potential structure 106 or any number of different low potential structures 130. In embodiments, the low potential structure 106 may include one or more systems, devices or combinations thereof that are maintained at a low potential, for example a chassis ground. In embodiments, the low potential structure 106 may include an earth ground. The method 600 commences at 602.

At 604, a P-well 134A and an N-doped region 132A that function as the cathode for the first SCR 110A may be conductively coupled to a low potential structure 106.

Additionally, a P-well 134B and an N-doped region 132B that function as the cathode of the second SCR 110B may be conductively coupled to a low potential structure 106. The method 600 concludes at 606.

The following examples pertain to embodiments that employ some or all of the described reverse breakdown diode trigger circuit apparatuses, systems, and methods described herein. The enclosed examples should not be considered exhaustive, nor should the enclosed examples be construed to exclude other combinations of the systems, methods, and apparatuses disclosed herein and which are not specifically enumerated herein.

According to example 1 there is provided an electrostatic discharge (ESD) protection system. The ESD protection system may include a first silicon controlled rectifier (SCR) and at least one second SCR proximately disposed on a substrate and a trigger circuit conductively coupled to a gate of the first SCR. The ESD protection system may additionally include an ESD protected circuit conductively coupled to an anode of the first SCR and an anode and a gate of the second SCR wherein the gate of the second SCR includes a gate triggerable by a stray current carried by the substrate and a low potential structure conductively coupled to a cathode of the first SCR and to a cathode of the second SCR.

Example 2 may include elements of example 1 where the at least one second SCR comprises a plurality of second SCR s positioned proximate the first SCR.

Example 3 may include elements of example 1 the gate of the second SCR may include a gate triggerable by a stray current caused at least in part by a flow of electrons from an N-P-N bipolar junction transistor (BJT) in the first SCR.

Example 4 may include the elements of example 1 where the gate of the second SCR may include a gate triggerable by a stray current caused at least in part by a flow of holes from a P-N-P bipolar junction transistor (BJT) in the first SCR.

Example 5 may include the elements of example 1 where the gate of the second SCR may include a gate triggerable by a stray current caused at least in part by at least one of: a flow of electrons from an N-P-N bipolar junction transistor (BJT) in the first SCR, a flow of holes from a P-N-P BJT in the first SCR , or any combination thereof. Example 6 may include the elements of any of examples 1 through 5 where the ESD protected circuit includes an input/output (I/O) circuit of and integrated circuit (IC).

Example 7 may include the elements of any of examples 1 through 5 and may additionally include at least one third SCR disposed proximate the at least one second SCR on the common substrate. An anode and a gate of the at least one third SCR may conductively couple to the ESD protected circuit and the gate of the at least one third SCR may include a gate triggerable by a stray current carried by the substrate. A cathode of the at least one third SCR may conductively couple to the low potential structure.

According to example 8 there is provided an electrostatic discharge (ESD) protection method. The ESD protection method may include causing a stray current to flow through a substrate responsive to triggering and latching-up a first silicon controlled rectifier (SCR). The ESD protection method may additionally include de-biasing an N-well of each of a number of second SCRs disposed on the substrate and proximate the first SCR. The ESD protection method may further include autonomously triggering and latching-up each respective one of the number of second SCR s responsive to the de -biasing of the N-well of the respective second SCR.

Example 9 may include elements of example 8 where causing a stray current to flow through a substrate responsive to triggering and latching-up a first silicon controlled rectifier (SCR) may include causing a stray current to flow through the substrate responsive to receiving an externally supplied trigger current at a gate of the first SCR, the externally supplied trigger current sufficient to cause an autonomous triggering and latching-up of the first SCR.

Example 10 may include elements of example 8 where de-biasing an N-well of each of a number of second SCRs may include de-biasing, by the stray current, the N-well of each of the number of second SCRs.

Example 11 may include elements of example 10 and may further include causing a second stray current to flow through the substrate responsive to triggering and latching-up at least one of the number of second SCRs. The ESD protection method may additionally include de-biasing an N-well of each of a number of third SCRs, each of the number of third SCRs disposed on the substrate and proximate the at least one of the number of second SCRs and autonomously triggering and latching-up each respective one of the number of third SCRs responsive to de -biasing the N-well of the respective third SCR.

Example 12 may include elements of example 8 and may additionally include conductively coupling an ESD protected circuit to an anode of the first SCR and conductively coupling the ESD protected circuit to an anode and the gate of each respective one of the number of second SCRs.

Example 13 may include elements of example 8 and may further include conductively coupling a cathode of the first SCR and a cathode of each of the number of second SCRs to a low potential structure.

Example 14 may include elements any of examples 8 through 13 where causing a stray current to flow through a substrate responsive to triggering and latching-up a first silicon controlled rectifier (SCR) may include causing a stray current that includes a flow of electrons from an N-P-N bipolar junction transistor (BJT) in the first SCR to flow through the substrate responsive to triggering and latching-up the first SCR.

Example 15 may include elements of any of examples 8 through 13 where causing a stray current to flow through a substrate responsive to triggering and latching-up a first silicon controlled rectifier (SCR) may include causing a stray current that includes a flow of holes from a P-N-P bipolar junction transistor (BJT) in the first SCR to flow through the substrate responsive to triggering and latching-up the first SCR.

Example 16 may include elements of any of examples 8 through 13 where causing a stray current to flow through a substrate responsive to triggering and latching-up a first silicon controlled rectifier (SCR) may include causing a stray current that includes at least one of: a flow of electrons from an N-P-N bipolar junction transistor (BJT) in the first SCR, a flow of holes from a P-N-P BJT in the first SCR, or a combination thereof.

According to example 17, there is provided an electrostatic discharge (ESD) protection system. The ESD protection system may include a means for causing a stray current to flow through a substrate responsive to triggering and latching-up a first silicon controlled rectifier (SCR). The ESD protection system may further include a means for de- biasing an N-well of each of a number of second SCRs disposed on the substrate and proximate the first SCR and a means for autonomously triggering and latching-up each respective one of the number of second SCR s responsive to the de -biasing of the N-well of the respective second SCR may include elements of example 16 and may additionally include removing at least a portion of the silicon substrate from the completed GaN layer to expose at least a portion of a surface of the completed GaN layer.

Example 18 may include the elements of example 17 where the means for causing a stray current to flow through a substrate responsive to triggering and latching-up a first silicon controlled rectifier (SCR) may include a means for causing a stray current to flow through the substrate responsive to receiving an externally supplied trigger current at a gate of the first SCR, the externally supplied trigger current sufficient to cause an autonomous triggering and latching-up of the first SCR.

Example 19 may include elements of example 17 where the means for de-biasing an N-well of each of a number of second SCRs may include a means for de-biasing, by the stray current, the N-well of each of the number of second SCRs.

Example 20 may include elements of example 19 and may additionally include a means for causing a second stray current to flow through the substrate responsive to triggering and latching-up at least one of the number of second SCRs, a means for de -biasing an N-well of each of a number of third SCRs disposed on the substrate and proximate the at least one of the number of second SCRs, and a means for autonomously triggering and latching-up each respective one of the number of third SCR s responsive to the de -biasing of the N-well of the respective third SCR.

Example 21 may include elements of example 17 and may additionally include a means for conductively coupling an ESD protected circuit to an anode of the first SCR and a means for conductively coupling the ESD protected circuit to an anode and the gate of each respective one of the at least one second SCRs.

Example 22 may include elements of example 17 and may additionally include a means for conductively coupling a cathode of the first SCR and a cathode of each of the number of second SCRs to a low potential structure.

Example 23 may include elements of any of examples 17 through 22 where the means for causing a stray current to flow through a substrate responsive to triggering and latching- up a first SCR may include a means for causing a stray current that includes a flow of electrons from an N-P-N bipolar junction transistor (BJT) in the first SCR to flow through the substrate responsive to triggering and latching-up the first SCR.

Example 24 may include elements of any of examples 17 through 22 where the means for causing a stray current to flow through a substrate responsive to triggering and latching- up a first silicon controlled rectifier (SCR) may include a means for causing a stray current that includes a flow of holes from a P-N-P bipolar junction transistor (BJT) in the first SCR to flow through the substrate responsive to triggering and latching-up the first SCR.

Example 25 may include elements of any of examples 17 through 22 where the means for causing a stray current to flow through a substrate responsive to triggering and latching- up a first silicon controlled rectifier (SCR) may include a means for causing a stray current that includes at least one of: a flow of electrons from an N-P-N bipolar junction transistor (BJT) in the first SCR through the substrate responsive to triggering and latching-up the first SCR, a flow of holes from a P-N-P BJT in the first SCR through the substrate responsive to triggering and latching-up the first SCR, or a combination thereof.

The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Accordingly, the claims are intended to cover all such equivalents.

Claims

WHAT IS CLAIMED:

1. An electrostatic discharge (ESD) protection system, comprising:

a first silicon controlled rectifier (SCR) and at least one second SCR proximately disposed on a substrate;

a trigger circuit conductively coupled to a gate of the first SCR;

an ESD protected circuit conductively coupled to an anode of the first SCR and an anode and a gate of the second SCR; and

a low potential structure conductively coupled to a cathode of the first SCR and to a cathode of the second SCR.

2. The ESD protection system of claim 1 wherein the gate of the second SCR includes a gate triggerable by a stray current carried by the substrate.

3. The ESD protection system of claim 2 wherein the gate of the second SCR includes a gate triggerable by a stray current that includes:

a stray current caused at least in part by a flow of electrons from an N-P-N bipolar junction transistor (BJT) in the first SCR.

4. The ESD protection system of claim 2 wherein the gate of the second SCR includes a gate triggerable by a stray current that includes:

a stray current caused at least in part by a flow of holes from a P-N-P bipolar junction transistor (BJT) in the first SCR.

5. The ESD protection system of claim 1 wherein the gate of the second SCR includes a gate triggerable by a stray current that includes:

a stray current caused at least in part by at least one of: a flow of electrons from an N- P-N bipolar junction transistor (BJT) in the first SCR, a flow of holes from a P-N-P BJT in the first SCR , or any combination thereof.

6. The ESD protection system of any of claims 1 through 5 wherein the ESD protected circuit includes an input/output (I/O) circuit of and integrated circuit (IC).

7. The ESD protection system of any of claims 1 through 5, further comprising: at least one third SCR disposed proximate the at least one second SCR on the common substrate;

wherein an anode and a gate of the at least one third SCR conductively couple to the ESD protected circuit and the gate of the at least one third SCR includes a gate triggerable by a stray current carried by the substrate; and

wherein a cathode of the at least one third SCR conductively couples to the low potential structure.

8. An electrostatic discharge (ESD) protection method, comprising:

causing a stray current to flow through a substrate responsive to triggering and latching-up a first silicon controlled rectifier (SCR);

de-biasing an N-well of each of a number of second SCRs disposed on the substrate and proximate the first SCR; and

autonomously triggering and latching-up each respective one of the number of second

SCR s responsive to the de-biasing of the N-well of the respective second SCR.

9. The ESD protection method of claim 8 wherein causing a stray current to flow through a substrate responsive to triggering and latching-up a first silicon controlled rectifier (SCR) comprises:

causing a stray current to flow through the substrate responsive to receiving an externally supplied trigger current at a gate of the first SCR, the externally supplied trigger current sufficient to cause an autonomous triggering and latching-up of the first SCR.

10. The ESD protection method of claim 8 wherein de -biasing an N-well of each a number of second SCRs comprises:

de-biasing, by the stray current, the N-well of each of the number of second SCRs.

11. The ESD protection method of claim 10, further comprising:

causing a second stray current to flow through the substrate responsive to triggering and latching-up at least one of the number of second SCRs;

de-biasing an N-well of each of a number of third SCRs, each of the number of third

SCRs disposed on the substrate and proximate the at least one of the number of second SCRs; and autonomously triggering and latching-up each respective one of the number of third SCRs responsive to de -biasing the N-well of the respective third SCR.

12. The ESD protection method of claim 8, further comprising:

conductively coupling an ESD protected circuit to an anode of the first SCR; and conductively coupling the ESD protected circuit to an anode and the gate of each respective one of the number of second SCRs.

13. The ESD protection method of claim 8, further comprising:

conductively coupling a cathode of the first SCR and a cathode of each of the number of second SCRs to a low potential structure.

14. The ESD protection method of any of claims 8 through 13 wherein causing a stray current to flow through a substrate responsive to triggering and latching-up a first silicon controlled rectifier (SCR) comprises:

causing a stray current that includes a flow of electrons from an N-P-N bipolar junction transistor (BJT) in the first SCR to flow through the substrate responsive to triggering and latching-up the first SCR.

15. The ESD protection method of any of claims 8 through 13 wherein causing a stray current to flow through a substrate responsive to triggering and latching-up a first silicon controlled rectifier (SCR) comprises:

causing a stray current that includes a flow of holes from a P-N-P bipolar junction transistor (BJT) in the first SCR to flow through the substrate responsive to triggering and latching-up the first SCR.

16. The ESD protection method of any of claims 8 through 13 wherein causing a stray current to flow through a substrate responsive to triggering and latching-up a first silicon controlled rectifier (SCR) comprises:

causing a stray current that includes at least one of: a flow of electrons from an N-P-N bipolar junction transistor (BJT) in the first SCR, a flow of holes from a P-N-P BJT in the first SCR, or a combination thereof.

17. An electrostatic discharge (ESD) protection system, comprising:

a means for causing a stray current to flow through a substrate responsive to triggering and latching-up a first silicon controlled rectifier (SCR);

a means for de-biasing an N-well of each of a number of second SCRs disposed on the substrate and proximate the first SCR; and

a means for autonomously triggering and latching-up each respective one of the number of second SCR s responsive to the de-biasing of the N-well of the respective second SCR.

18. The ESD protection system of claim 17 wherein the means for causing a stray current to flow through a substrate responsive to triggering and latching-up a first silicon controlled rectifier (SCR) comprises:

a means for causing a stray current to flow through the substrate responsive to receiving an externally supplied trigger current at a gate of the first SCR, the externally supplied trigger current sufficient to cause an autonomous triggering and latching-up of the first SCR.

19. The ESD protection system of claim 17 wherein the means for de-biasing N-well of each of a number of second SCRs comprises:

a means for de-biasing, by the stray current, the N-well of each of the number of second SCRs.

20. The ESD protection system of claim 19, further comprising:

a means for causing a second stray current to flow through the substrate responsive to triggering and latching-up at least one of the number of second SCRs;

a means for de-biasing an N-well of each of a number of third SCRs disposed on the substrate and proximate the at least one of the number of second SCRs; and

a means for autonomously triggering and latching-up each respective one of the number of third SCR s responsive to the de-biasing of the N-well of the respective third SCR.

21. The ESD protection system of claim 17, further comprising:

a means for conductively coupling an ESD protected circuit to an anode of the first SCR; and a means for conductively coupling the ESD protected circuit to an anode and the gate of each respective one of the at least one second SCRs.

22. The ESD protection system of claim 17, further comprising:

a means for conductively coupling a cathode of the first SCR and a cathode of each of the number of second SCRs to a low potential structure.

23. The ESD protection system of any of claims 17 through 22 wherein the means for causing a stray current to flow through a substrate responsive to triggering and latching- up a first SCR comprises:

a means for causing a stray current that includes a flow of electrons from an N-P-N bipolar junction transistor (BJT) in the first SCR to flow through the substrate responsive to triggering and latching-up the first SCR.

24. The ESD protection system of any of claims 17 through 22 wherein the means for causing a stray current to flow through a substrate responsive to triggering and latching- up a first silicon controlled rectifier (SCR) comprises:

a means for causing a stray current that includes a flow of holes from a P-N-P bipolar junction transistor (BJT) in the first SCR to flow through the substrate responsive to triggering and latching-up the first SCR.

25. The ESD protection method of any of claims 17 through 22 wherein the means for causing a stray current to flow through a substrate responsive to triggering and latching- up a first silicon controlled rectifier (SCR) comprises:

a means for causing a stray current that includes at least one of: a flow of electrons from an N-P-N bipolar junction transistor (BJT) in the first SCR through the substrate responsive to triggering and latching-up the first SCR, a flow of holes from a P-N-P BJT in the first SCR through the substrate responsive to triggering and latching-up the first SCR, or a combination thereof.