WO2017046931A1 - Liquid crystal display device - Google Patents

Liquid crystal display device Download PDF

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Publication number
WO2017046931A1
WO2017046931A1 PCT/JP2015/076590 JP2015076590W WO2017046931A1 WO 2017046931 A1 WO2017046931 A1 WO 2017046931A1 JP 2015076590 W JP2015076590 W JP 2015076590W WO 2017046931 A1 WO2017046931 A1 WO 2017046931A1
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Prior art keywords
electrode
data line
liquid crystal
display device
crystal display
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PCT/JP2015/076590
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French (fr)
Japanese (ja)
Inventor
貢祥 平田
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堺ディスプレイプロダクト株式会社
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Priority to PCT/JP2015/076590 priority Critical patent/WO2017046931A1/en
Publication of WO2017046931A1 publication Critical patent/WO2017046931A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to a liquid crystal display device that displays an image using a liquid crystal panel, and more particularly to a horizontal electric field type liquid crystal display device such as an IPS method.
  • One of the display methods of the liquid crystal display device is an IPS (In-Plane Switching) method.
  • IPS liquid crystal display device liquid crystal is sandwiched between a color filter substrate on which a color filter is formed and a circuit substrate on which an active matrix circuit is formed, and the circuit substrate includes an electric field including a component parallel to the circuit substrate. To drive the liquid crystal.
  • FIG. 9 is a schematic circuit diagram showing a part of an active matrix circuit in the conventional IPS system.
  • FIG. 9 shows a portion of the active matrix circuit corresponding to each of a plurality of pixels constituting an image displayed on the liquid crystal display device.
  • a gate line (scanning line) 51 and a data line 52 are arranged so as to intersect with each other, and a comb-like pixel electrode 55 and a common electrode 54 are formed.
  • the common electrode 54 is connected to a common wiring 53 to which a common signal is supplied, and the common wiring 53 is disposed so as to intersect the data line 52.
  • the pixel electrode 55 is connected to the data line 52 and the gate line 51 through a TFT (thin film) transistor 56 which is an active element.
  • TFT thin film
  • the plurality of data lines 52 and the gate lines 51 are arranged in a grid pattern, and portions corresponding to the pixels of the circuit board are arranged in a matrix pattern.
  • the TFT 56 is turned on, an electric field is generated between the pixel electrode 55 and the common electrode 54, the direction of the liquid crystal is changed, and the pixel is displayed.
  • the data line 52 is provided with the common electrode. 54 is shielded by a part.
  • the capacity corresponding to each pixel is small. For this reason, the delay of the signal supplied to the data line 52 and the gate line 51 becomes small, and each pixel is displayed without delay. Therefore, the IPS method is suitable for a high-definition model having a large number of displayed pixels.
  • the delay of pixel display is insufficiently reduced even with the conventional IPS method.
  • the delay of pixel display is greatly affected by the parasitic capacitance of the data line 52.
  • the parasitic capacitance of the data line 52 corresponding to each pixel shields the capacitance between the data line 52 and the gate line 51 via the TFT 56, the capacitance of the portion where the data line 52 intersects the common wiring 53, and the data line 52.
  • the capacitance between the common electrode 54 and the data line 52 is included.
  • Patent Document 1 discloses that an insulating film is disposed between the common electrode 54 that shields the data line 52 and the data line 52. However, even if an insulating film is present, the capacitance between the data line 52 and the common electrode 54 is still large, and the delay is not sufficiently reduced.
  • the present invention has been made in view of such circumstances, and an object of the present invention is to provide a liquid crystal in which the delay of pixel display is sufficiently reduced by reducing the parasitic capacitance of the data line as much as possible. It is to provide a display device.
  • a liquid crystal display device includes a pair of substrates and a liquid crystal sandwiched between the pair of substrates, and one of the pair of substrates includes a plurality of gate lines arranged in parallel.
  • a plurality of data lines arranged in parallel across the gate line, and active elements arranged corresponding to the intersections of the gate line and the data line are formed, and the gate line and the data line
  • the liquid crystal display device further including a signal supply unit that sequentially supplies signals to the data lines, the one substrate has a common line to which a common signal is supplied, and each intersection of the gate line and the data line.
  • first electrode and the second electrode are arranged between the first electrode and the second electrode arranged corresponding to the intersection of the gate line and the data line to which a signal is supplied. Further, an electric field for driving the liquid crystal containing a component parallel to the one substrate is generated.
  • the liquid crystal display device includes a pair of substrates sandwiching liquid crystal, and a plurality of gate lines and data lines are arranged on one substrate so as to intersect each other.
  • One substrate is provided with a common wiring to which a common signal is supplied, and an active element is connected to the first electrode connected to the data line and the gate line and the common wiring corresponding to the intersection of the gate line and the data line.
  • the 2nd electrode connected via is arrange
  • the liquid crystal display device is characterized in that a part of the data line also serves as a part of the first electrode.
  • a part of the data line also serves as a part of the first electrode.
  • the electric field generated between the data line and the second electrode is an electric field used for pixel display and does not become an unnecessary electric field. For this reason, there is no shield for preventing an unnecessary electric field from being generated between the data line and the electrode, and no capacitance is generated between the data line and the shield.
  • a plurality of the common lines are formed on the one substrate, and the common lines are arranged alternately with the data lines in parallel with the data lines. It is characterized by that.
  • the common wiring is arranged alternately with the data lines in parallel with the data lines. There is almost no portion where the data line and the common wiring intersect, and the capacitance between the data line and the common wiring is small.
  • the first electrode and the second electrode each have one or a plurality of linear portions, and the linear portions of the first electrode and the second electrode are linear.
  • the portions are alternately arranged in a direction along the one substrate.
  • the first electrode and the second electrode include linear portions, and the linear portions of the first electrode and the linear portions of the second electrode are alternately arranged in the direction along the substrate. .
  • this configuration it is possible to display an image using the IPS method.
  • the parasitic capacitance of the data line is lower than before, the delay of the signal passing through the data line is reduced, and the delay of the pixel display is sufficiently reduced. Therefore, the present invention has excellent effects, such as realizing a high-definition and large-sized liquid crystal display device.
  • FIG. 3 is a schematic front view illustrating a part of the active matrix circuit according to the first embodiment.
  • 2 is a schematic circuit diagram showing a part of an active matrix circuit in Embodiment 1.
  • FIG. 5 is a schematic cross-sectional view of the circuit board along the line VV shown in FIG. 3.
  • 2 is a schematic circuit diagram showing a configuration of an active matrix circuit in Embodiment 1.
  • FIG. 5 is a schematic front view showing a part of an active matrix circuit in Embodiment 2.
  • FIG. FIG. 6 is a schematic front view showing a part of an active matrix circuit in a third embodiment. It is a schematic circuit diagram which shows a part of active matrix circuit in the conventional IPS system.
  • FIG. 1 is a schematic perspective view showing an appearance of a liquid crystal display device
  • FIG. 2 is an exploded perspective view showing a configuration of optical elements of the liquid crystal display device.
  • the liquid crystal display device is, for example, a television receiver.
  • the liquid crystal display device includes a liquid crystal panel 1 and a backlight 2 disposed behind the liquid crystal panel 1.
  • the liquid crystal panel 1 is illuminated by the backlight 2 from behind and displays an image.
  • the liquid crystal panel 1 includes a polarizing plate 11 and a polarizing plate 15 in which the polarization directions of linearly polarized light to be transmitted are orthogonal to each other.
  • the other elements of the liquid crystal panel 1 are disposed between the polarizing plate 11 and the polarizing plate 15.
  • a transparent circuit board 14 on which an active matrix circuit is formed is disposed on the front side of the polarizing plate 15.
  • a liquid crystal part 13 is disposed which is configured by sandwiching a liquid crystal layer from the front and back with an alignment film for aligning liquid crystal molecules.
  • a color filter substrate 12 on which a color filter is formed is disposed on the front side of the liquid crystal unit 13.
  • the liquid crystal unit 13 is sandwiched between the circuit board 14 and the color filter substrate 12.
  • the liquid crystal display device may further include other optical elements.
  • FIG. 3 is a schematic front view showing a part of the active matrix circuit in the first embodiment
  • FIG. 4 is a schematic circuit diagram showing a part of the active matrix circuit in the first embodiment.
  • FIG. 3 shows a portion corresponding to each of a plurality of pixels or sub-pixels constituting an image displayed by the liquid crystal display device
  • FIG. 4 shows a circuit diagram of this portion.
  • a plurality of gate lines 31 are arranged in parallel, and a plurality of data lines 32 are arranged so as to cross the gate lines 31.
  • a plurality of common wires 33 are arranged in parallel with the data lines 32.
  • the data lines 32 and the common wirings 33 are alternately arranged along the circuit board 14.
  • a common signal is supplied to the common wiring 33 in the entire active matrix circuit.
  • a signal having a constant potential is supplied to the common wiring 33.
  • 3 corresponding to each pixel or sub-pixel is located at a position corresponding to each intersection of the gate line 31 and the data line 32 and is adjacent to two adjacent gate lines 31 in the active matrix circuit. This is a portion surrounded by two common wires 33.
  • a first electrode 34, a second electrode 35, and a TFT 36 are provided in a portion corresponding to one pixel or sub-pixel in the active matrix circuit.
  • the first electrode 34 is connected to the data line 32, and the second electrode 35 is connected to the gate line 31 and the common wiring 33 via the TFT 36.
  • the TFT 36 has a gate connected to the gate line 31, a source connected to the common wiring 33, and a drain connected to the second electrode 35.
  • the first electrode 34 is formed on both sides of the data line 32 in a plane along the circuit board 14.
  • the first electrode 34 includes a plurality of parallel linear portions, and a part of the data line 32 also serves as one linear portion.
  • the second electrode 35 is formed in a comb shape including a plurality of parallel linear portions.
  • the linear portions of the first electrodes 34 and the linear portions of the second electrodes 35 are alternately arranged in the direction along the circuit board 14.
  • the TFT 36 When a signal is supplied to the gate line 31, the TFT 36 is turned on.
  • a signal is supplied to the data line 32 in this state, an electric field is generated between the first electrode 34 and the second electrode 35.
  • 3 and 4 show the minimum configuration of the active matrix circuit, and the active matrix circuit may include circuit elements not shown.
  • FIG. 5 is a schematic cross-sectional view of the circuit board 14 taken along the line VV shown in FIG.
  • the circuit board 14 includes a transparent substrate 141 such as a glass substrate, and a first insulating film 142 is formed on the transparent substrate 141.
  • the data line 32, the common wiring 33 and the first electrode 34 are formed on the first insulating film 142.
  • a second insulating film 143 is formed on the first insulating film 142 so as to cover the data line 32, the common wiring 33 and the first electrode 34.
  • the second electrode 35 is formed on the second insulating film 143.
  • An electric field in the direction indicated by the arrow in FIG. 5 is generated between the first electrode 34 including the data line 32 and the second electrode 35.
  • the generated electric field includes a component parallel to the circuit board 14.
  • the component of the electric field parallel to the circuit board 14 changes the orientation of the liquid crystal molecules in the liquid crystal unit 13 so that the light from the backlight 2 passes through the liquid crystal panel 1, and the pixel or color in
  • FIG. 6 is a schematic circuit diagram showing the configuration of the active matrix circuit in the first embodiment.
  • a plurality of gate lines 31 and data lines 32 are arranged in a lattice pattern.
  • a first electrode 34, a second electrode 35, and a TFT 36 are disposed at a position corresponding to the intersection of the gate line 31 and the data line 32.
  • a set of the first electrode 34, the second electrode 35, and the TFT 36 is arranged in a matrix.
  • the liquid crystal display device includes a gate driver 41 connected to the plurality of gate lines 31, a data driver 42 connected to the plurality of data lines 32, and a common signal unit 43 connected to the plurality of common lines 33. Yes.
  • the gate driver 41 and the data driver 42 correspond to the signal supply unit in the present invention.
  • the common signal unit 43 supplies a common signal to a plurality of common wires.
  • the common signal unit 43 is a constant potential source.
  • the gate driver 41 generates a signal to be supplied to the plurality of gate lines 31 and sequentially supplies the generated signal to each gate line 31.
  • the data driver 42 generates a signal to be supplied to the plurality of data lines 32 and sequentially supplies the generated signal to each data line 32.
  • An electric field is generated between the first electrode 34 and the second electrode 35 arranged corresponding to the intersection of the gate line 31 and the data line 32 to which a signal is supplied, and a pixel or a sub-pixel is displayed.
  • the TFT 56 is connected between the gate line 51 and the data line 52 as shown in FIG. 9, whereas in this embodiment, the gate line 31 and the data are shown in FIG. No TFT is connected between the line 32.
  • the capacitance between the gate line 31 and the data line 32 is lower than the conventional one because there is no increase in capacitance due to the TFT.
  • the capacitance between the second electrode 35 and the common wiring 33 is increased by the TFT 36, it is in series with the capacitance between the data line 32 and the second electrode 35. The contribution to capacity is small.
  • the common wiring 33 is arranged in parallel with the data line 32, and there is almost no portion where the data line 32 and the common wiring 33 intersect. For this reason, the capacitance between the data line 32 and the common line 33 is reduced as compared with the conventional liquid crystal display device in which the common line 53 is arranged so as to intersect the data line 52.
  • the data line 32 and the first electrode 34 have the same potential.
  • the electric field generated between the data line 32 and the second electrode 35 is an electric field similar to the electric field generated between the first electrode 34 and the second electrode 35 and is used for displaying a pixel or a sub-pixel. Electric field. That is, a part of the data line 32 also serves as a part of the first electrode 34.
  • the data line is used to prevent an unnecessary electric field from being generated between the data line 32 and the electrode. It is not necessary to shield 32. Therefore, in the present embodiment, the shield of the data line 32 does not exist, and no capacitance is generated between the data line 32 and the shield.
  • the parasitic capacitance of the data line 32 is lower than that of the conventional liquid crystal display device. For this reason, the delay of the signal passing through the data line 32 is reduced, and the delay of the pixel display is sufficiently reduced. Since the delay in pixel display is sufficiently reduced, a high-definition and large-sized liquid crystal display device can be realized. Further, even if the liquid crystal display device does not have a configuration in which data drivers are arranged at both ends of the data line 32, the delay in pixel display is sufficiently reduced, so that an increase in cost is suppressed.
  • FIG. 7 is a schematic front view illustrating a part of the active matrix circuit according to the second embodiment.
  • FIG. 7 shows a portion corresponding to each of the pixel and the sub-pixel.
  • the linear portion of the first electrode 34 is bent, and the linear portion of the second electrode 35 is also bent in parallel.
  • the data line 32 and the common wiring 33 are also bent. Since the first electrode 34 and the second electrode 35 are bent, the direction of the component parallel to the circuit board 14 of the electric field generated between the first electrode 34 and the second electrode 35 is partially different. For this reason, the orientation of the liquid crystal molecules driven by the electric field is partially different, and fluctuations in the brightness of the image according to the viewing angle are alleviated.
  • the TFT is not connected between the gate line 31 and the data line 32, and the shield of the data line 32 does not exist. Therefore, in the liquid crystal display device according to the present embodiment, the parasitic capacitance of the data line 32 is lower than in the conventional case, the delay of the signal passing through the data line 32 is reduced, and the delay of the pixel display is sufficiently reduced. ing.
  • the linear portions included in the first electrode 34 and the second electrode 35 are parallel to the data lines 32.
  • the liquid crystal display device includes the first electrode 34 and the second electrode 35.
  • the linear part of the second electrode 35 may be formed in a direction intersecting the data line 32.
  • Embodiment 3 shows an FFS (Fringe Field Switching) type liquid crystal display device.
  • FIG. 8 is a schematic front view illustrating a part of the active matrix circuit according to the third embodiment.
  • FIG. 8 shows a portion corresponding to each pixel or sub-pixel.
  • the first electrode 34 has a flat shape.
  • the second electrode 35 has a flat plate shape and is disposed so as to overlap the first electrode 34 with an insulating layer (not shown) interposed therebetween.
  • the second electrode 35 is formed with a plurality of slits. An electric field is generated between the first electrode 34 and the second electrode 35 through the slit.
  • a component parallel to the circuit board 14 is included in the electric field, and the orientation of the liquid crystal molecules is changed by the component parallel to the circuit board 14 of the electric field, so that pixels or sub-pixels are displayed.
  • the TFT is not connected between the gate line 31 and the data line 32, and the shield of the data line 32 does not exist. Therefore, in the liquid crystal display device according to the present embodiment, the parasitic capacitance of the data line 32 is lower than in the conventional case, the delay of the signal passing through the data line 32 is reduced, and the delay of the pixel display is sufficiently reduced. ing.
  • the common wiring 33 is parallel to the data line 32.
  • the liquid crystal display device has a common wiring 33 parallel to the gate line 31. May be.
  • the first electrode 34 is formed in the same layer as the data line 32 and the common wiring 33 in the circuit board 14.
  • the liquid crystal display device includes the first electrode 34. 34 may be formed in a layer different from the data line 32 or the common wiring 33.
  • the TFT is used as the active element.
  • the liquid crystal display device may be an active element other than the TFT.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
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Abstract

Provided is a liquid crystal display device capable of sufficiently reducing the delay when displaying pixels by minimizing the parasitic capacity of a data line as much as possible. In an IPS liquid crystal display device, a first electrode 34 connected to a data line 32, and a second electrode 35 connected to a gate line 31 and common wiring 33 through a TFT 36 are arranged in a portion corresponding to each pixel in an active matrix circuit. An electric field is generated between the first electrode 34 and the second electrode 35, to thereby drive the liquid crystal. Since the TFT is not connected between the data line 32 and the first electrode 34, the capacity between the data line 32 and the first electrode 34 is small; no shield is required to prevent the generation of unwanted electric fields between the data line 32 and the electrode; therefore, no capacity is generated between the data line 32 and the shield. Thereby, it is possible to minimize the parasitic capacity of the data line 32, decrease the delay of a signal passing through the data line 32, and sufficiently reduce the delay when displaying pixels.

Description

液晶表示装置Liquid crystal display
　本発明は、液晶パネルを用いて画像を表示する液晶表示装置に関し、より詳しくは、ＩＰＳ方式等の横電界方式の液晶表示装置に関する。 The present invention relates to a liquid crystal display device that displays an image using a liquid crystal panel, and more particularly to a horizontal electric field type liquid crystal display device such as an IPS method.
　液晶表示装置の表示方式の一つとして、ＩＰＳ（In-Plane Switching）方式がある。ＩＰＳ方式の液晶表示装置では、カラーフィルタが形成されたカラーフィルタ基板とアクティブマトリクス回路が形成された回路基板との間に液晶を挟持しており、回路基板は回路基板に平行な成分を含む電界を発生させ、液晶を駆動する。 One of the display methods of the liquid crystal display device is an IPS (In-Plane Switching) method. In an IPS liquid crystal display device, liquid crystal is sandwiched between a color filter substrate on which a color filter is formed and a circuit substrate on which an active matrix circuit is formed, and the circuit substrate includes an electric field including a component parallel to the circuit substrate. To drive the liquid crystal.
　図９は、従来のＩＰＳ方式でのアクティブマトリクス回路の一部を示す模式的回路図である。図９には、アクティブマトリクス回路の内、液晶表示装置で表示される画像を構成する複数の画素の夫々に対応する部分を示している。ゲート線（走査線）５１とデータ線５２とが交差して配置されており、更に櫛歯状の画素電極５５と共通電極５４とが形成されている。共通電極５４は共通の信号が供給される共通配線５３に接続されており、共通配線５３はデータ線５２に交差して配置されている。画素電極５５は、アクティブ素子であるＴＦＴ（thin film transistor）５６を介してデータ線５２及びゲート線５１に接続されている。複数のデータ線５２及びゲート線５１は格子状に配置されており、回路基板の画素に対応する部分は、マトリクス状に配置されている。データ線５２及びゲート線５１に信号が供給された場合に、ＴＦＴ５６がオン状態となり、画素電極５５と共通電極５４との間に電界が発生し、液晶の向きが変化し、画素が表示される。特許文献１に開示された液晶表示装置では、データ線５２と共通電極５４及び画素電極５５との間に画素の表示に不要な電界が発生することを防止するために、データ線５２は共通電極５４の一部によってシールドされている。 FIG. 9 is a schematic circuit diagram showing a part of an active matrix circuit in the conventional IPS system. FIG. 9 shows a portion of the active matrix circuit corresponding to each of a plurality of pixels constituting an image displayed on the liquid crystal display device. A gate line (scanning line) 51 and a data line 52 are arranged so as to intersect with each other, and a comb-like pixel electrode 55 and a common electrode 54 are formed. The common electrode 54 is connected to a common wiring 53 to which a common signal is supplied, and the common wiring 53 is disposed so as to intersect the data line 52. The pixel electrode 55 is connected to the data line 52 and the gate line 51 through a TFT (thin film) transistor 56 which is an active element. The plurality of data lines 52 and the gate lines 51 are arranged in a grid pattern, and portions corresponding to the pixels of the circuit board are arranged in a matrix pattern. When a signal is supplied to the data line 52 and the gate line 51, the TFT 56 is turned on, an electric field is generated between the pixel electrode 55 and the common electrode 54, the direction of the liquid crystal is changed, and the pixel is displayed. . In the liquid crystal display device disclosed in Patent Document 1, in order to prevent an unnecessary electric field from being generated for display of pixels between the data line 52 and the common electrode 54 and the pixel electrode 55, the data line 52 is provided with the common electrode. 54 is shielded by a part.
　ＩＰＳ方式の液晶表示装置では、各画素に対応する部分での容量が小さい。このため、データ線５２及びゲート線５１に供給される信号の遅延が小さくなり、夫々の画素が遅延無く表示される。従って、表示される画素の数が多い高精細の機種にＩＰＳ方式は適している。 In the IPS liquid crystal display device, the capacity corresponding to each pixel is small. For this reason, the delay of the signal supplied to the data line 52 and the gate line 51 becomes small, and each pixel is displayed without delay. Therefore, the IPS method is suitable for a high-definition model having a large number of displayed pixels.
特開２００２－２５８３２１号公報JP 2002-258321 A
　しかしながら、８Ｋ４Ｋの機種等のより高精細で大型の機種では、従来のＩＰＳ方式でも、画素表示の遅延の低減が不十分である。画素表示の遅延には、データ線５２の寄生容量の影響が大きい。各画素に対応するデータ線５２の寄生容量には、ＴＦＴ５６を介したデータ線５２及びゲート線５１間の容量、データ線５２が共通配線５３と交差する部分の容量、並びにデータ線５２をシールドする共通電極５４とデータ線５２との間の容量が含まれる。 However, with a higher definition and larger model such as an 8K4K model, the delay of pixel display is insufficiently reduced even with the conventional IPS method. The delay of pixel display is greatly affected by the parasitic capacitance of the data line 52. The parasitic capacitance of the data line 52 corresponding to each pixel shields the capacitance between the data line 52 and the gate line 51 via the TFT 56, the capacitance of the portion where the data line 52 intersects the common wiring 53, and the data line 52. The capacitance between the common electrode 54 and the data line 52 is included.
　データ線５２の容量による影響を小さくする方法として、データ線５２の両端から信号を供給することで信号の遅延を低減させる方法がある。しかし、この方法では、信号を供給するドライバをデータ線５２の両端に備える必要があり、液晶表示装置のコストが上昇する。また、特許文献１には、データ線５２をシールドする共通電極５４とデータ線５２との間に絶縁膜を配置することが開示されている。しかしながら、絶縁膜が存在していても、データ線５２と共通電極５４との間の容量は依然として大きく、遅延の低減は十分ではない。 As a method of reducing the influence of the capacity of the data line 52, there is a method of reducing a signal delay by supplying a signal from both ends of the data line 52. However, in this method, it is necessary to provide a driver for supplying a signal at both ends of the data line 52, which increases the cost of the liquid crystal display device. Patent Document 1 discloses that an insulating film is disposed between the common electrode 54 that shields the data line 52 and the data line 52. However, even if an insulating film is present, the capacitance between the data line 52 and the common electrode 54 is still large, and the delay is not sufficiently reduced.
　本発明は、斯かる事情に鑑みてなされたものであって、その目的とするところは、データ線の寄生容量を可及的に低下させることにより、画素表示の遅延が十分に低減された液晶表示装置を提供することにある。 The present invention has been made in view of such circumstances, and an object of the present invention is to provide a liquid crystal in which the delay of pixel display is sufficiently reduced by reducing the parasitic capacitance of the data line as much as possible. It is to provide a display device.
　本発明に係る液晶表示装置は、一対の基板と、該一対の基板の間に挟持された液晶とを備え、前記一対の基板の一方の基板には、並行に配置された複数のゲート線と、該ゲート線に交差して並行に配置された複数のデータ線と、前記ゲート線及び前記データ線の各交点に対応して配置されたアクティブ素子とが形成されており、前記ゲート線及び前記データ線に順次的に信号を供給する信号供給部を更に備える液晶表示装置において、前記一方の基板には、共通の信号が供給される共通配線と、前記ゲート線及び前記データ線の各交点に対応して配置され、前記データ線に接続された第１電極と、前記ゲート線及び前記データ線の各交点に対応して配置され、前記ゲート線及び前記共通線に前記アクティブ素子を介して接続された第２電極とが形成されており、前記第１電極及び前記第２電極は、信号を供給された前記ゲート線及び前記データ線の交点に対応して配置された前記第１電極及び前記第２電極の間に、前記一方の基板に平行な成分を含む前記液晶を駆動させるための電界が発生するように形成されていることを特徴とする。 A liquid crystal display device according to the present invention includes a pair of substrates and a liquid crystal sandwiched between the pair of substrates, and one of the pair of substrates includes a plurality of gate lines arranged in parallel. A plurality of data lines arranged in parallel across the gate line, and active elements arranged corresponding to the intersections of the gate line and the data line are formed, and the gate line and the data line In the liquid crystal display device further including a signal supply unit that sequentially supplies signals to the data lines, the one substrate has a common line to which a common signal is supplied, and each intersection of the gate line and the data line. Correspondingly arranged and connected to the first electrode connected to the data line and each intersection of the gate line and the data line, connected to the gate line and the common line via the active element Second electrode The first electrode and the second electrode are arranged between the first electrode and the second electrode arranged corresponding to the intersection of the gate line and the data line to which a signal is supplied. Further, an electric field for driving the liquid crystal containing a component parallel to the one substrate is generated.
　本発明においては、液晶表示装置は液晶を挟持した一対の基板を備え、一方の基板には複数のゲート線及びデータ線が交差して配置されている。一方の基板には、共通の信号が供給される共通配線が配置され、ゲート線及びデータ線の交点に対応して、データ線に接続された第１電極と、ゲート線及び共通配線にアクティブ素子を介して接続された第２電極とが配置されている。ゲート線及びデータ線に信号が供給された場合、第１電極と第２電極との間に、基板に平行な成分を含む電界が発生し、液晶が駆動される。データ線と第１電極との間にアクティブ素子が接続されていないので、データ線と第１電極との間の容量は小さい。 In the present invention, the liquid crystal display device includes a pair of substrates sandwiching liquid crystal, and a plurality of gate lines and data lines are arranged on one substrate so as to intersect each other. One substrate is provided with a common wiring to which a common signal is supplied, and an active element is connected to the first electrode connected to the data line and the gate line and the common wiring corresponding to the intersection of the gate line and the data line. The 2nd electrode connected via is arrange | positioned. When a signal is supplied to the gate line and the data line, an electric field including a component parallel to the substrate is generated between the first electrode and the second electrode, and the liquid crystal is driven. Since no active element is connected between the data line and the first electrode, the capacitance between the data line and the first electrode is small.
　本発明に係る液晶表示装置は、前記データ線の一部は、前記第１電極の一部を兼ねていることを特徴とする。 The liquid crystal display device according to the present invention is characterized in that a part of the data line also serves as a part of the first electrode.
　また本発明においては、データ線の一部は第１電極の一部を兼ねている。データ線と第２電極との間に発生する電界は、画素表示のために利用される電界であり、不要な電界とはならない。このため、データ線と電極との間に不要な電界が発生することを防止するためのシールドは存在せず、データ線とシールドとの間に容量が発生することは無い。 In the present invention, a part of the data line also serves as a part of the first electrode. The electric field generated between the data line and the second electrode is an electric field used for pixel display and does not become an unnecessary electric field. For this reason, there is no shield for preventing an unnecessary electric field from being generated between the data line and the electrode, and no capacitance is generated between the data line and the shield.
　本発明に係る液晶表示装置は、前記一方の基板には、複数の前記共通配線が形成されており、前記共通配線は、前記データ線に並行して、前記データ線と交互に配置されていることを特徴とする。 In the liquid crystal display device according to the present invention, a plurality of the common lines are formed on the one substrate, and the common lines are arranged alternately with the data lines in parallel with the data lines. It is characterized by that.
　また本発明においては、共通配線は、データ線に並行して、データ線と交互に配置されている。データ線と共通配線とが交差する部分がほぼ存在せず、データ線と共通配線との間の容量は小さい。 In the present invention, the common wiring is arranged alternately with the data lines in parallel with the data lines. There is almost no portion where the data line and the common wiring intersect, and the capacitance between the data line and the common wiring is small.
　本発明に係る液晶表示装置は、前記第１電極及び前記第２電極は、夫々に、一又は複数の線状部分を有し、前記第１電極の線状部分と前記第２電極の線状部分とが前記一方の基板に沿った方向に交互に配置されていることを特徴とする。 In the liquid crystal display device according to the present invention, the first electrode and the second electrode each have one or a plurality of linear portions, and the linear portions of the first electrode and the second electrode are linear. The portions are alternately arranged in a direction along the one substrate.
　また本発明においては、第１電極及び第２電極は線状部分を含んでおり、第１電極の線状部分と第２電極の線状部分とは基板に沿った方向に交互に並んでいる。この構成により、ＩＰＳ方式での画像表示が可能となる。 In the present invention, the first electrode and the second electrode include linear portions, and the linear portions of the first electrode and the linear portions of the second electrode are alternately arranged in the direction along the substrate. . With this configuration, it is possible to display an image using the IPS method.
　本発明にあっては、データ線の寄生容量が従来よりも低下しており、データ線を通る信号の遅延が低減され、画素表示の遅延が十分に低減されている。従って、高精細で大型の液晶表示装置を実現することが可能となる等、本発明は優れた効果を奏する。 In the present invention, the parasitic capacitance of the data line is lower than before, the delay of the signal passing through the data line is reduced, and the delay of the pixel display is sufficiently reduced. Therefore, the present invention has excellent effects, such as realizing a high-definition and large-sized liquid crystal display device.
液晶表示装置の外観を示す模式的斜視図である。It is a typical perspective view which shows the external appearance of a liquid crystal display device. 液晶表示装置の光学的要素の構成を示す分解斜視図である。It is a disassembled perspective view which shows the structure of the optical element of a liquid crystal display device. 実施形態１におけるアクティブマトリクス回路の一部を示す模式的正面図である。FIG. 3 is a schematic front view illustrating a part of the active matrix circuit according to the first embodiment. 実施形態１におけるアクティブマトリクス回路の一部を示す模式的回路図である。2 is a schematic circuit diagram showing a part of an active matrix circuit in Embodiment 1. FIG. 図３に示すＶ－Ｖ線に沿った回路基板の模式的断面図である。FIG. 5 is a schematic cross-sectional view of the circuit board along the line VV shown in FIG. 3. 実施形態１におけるアクティブマトリクス回路の構成を示す模式的回路図である。2 is a schematic circuit diagram showing a configuration of an active matrix circuit in Embodiment 1. FIG. 実施形態２におけるアクティブマトリクス回路の一部を示す模式的正面図である。5 is a schematic front view showing a part of an active matrix circuit in Embodiment 2. FIG. 実施形態３におけるアクティブマトリクス回路の一部を示す模式的正面図である。FIG. 6 is a schematic front view showing a part of an active matrix circuit in a third embodiment. 従来のＩＰＳ方式でのアクティブマトリクス回路の一部を示す模式的回路図である。It is a schematic circuit diagram which shows a part of active matrix circuit in the conventional IPS system.
　以下本発明をその実施の形態を示す図面に基づき具体的に説明する。
＜実施形態１＞
　図１は、液晶表示装置の外観を示す模式的斜視図であり、図２は、液晶表示装置の光学的要素の構成を示す分解斜視図である。液晶表示装置は、例えばテレビジョン受像機である。液晶表示装置は、液晶パネル１と、液晶パネル１の背後に配置されたバックライト２とを備えている。液晶パネル１は、背後からバックライト２に照明され、画像を表示する。液晶パネル１は、透過させる直線偏光の偏光方向が互いに直交する偏光板１１及び偏光板１５を備えている。液晶パネル１の他の要素は、偏光板１１及び偏光板１５の間に挟まれて配置されている。偏光板１５の前側には、透明でアクティブマトリクス回路が形成された回路基板１４が配置されている。回路基板１４の前側には、液晶分子を配向させる配向膜で液晶層を前後から挟んで構成された液晶部１３が配置されている。液晶部１３の前側には、カラーフィルタが形成されたカラーフィルタ基板１２が配置されている。液晶部１３は、回路基板１４とカラーフィルタ基板１２との間に挟持されている。なお、液晶表示装置は、更に他の光学要素を含んでいてもよい。 Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof.
<Embodiment 1>
FIG. 1 is a schematic perspective view showing an appearance of a liquid crystal display device, and FIG. 2 is an exploded perspective view showing a configuration of optical elements of the liquid crystal display device. The liquid crystal display device is, for example, a television receiver. The liquid crystal display device includes a liquid crystal panel 1 and a backlight 2 disposed behind the liquid crystal panel 1. The liquid crystal panel 1 is illuminated by the backlight 2 from behind and displays an image. The liquid crystal panel 1 includes a polarizing plate 11 and a polarizing plate 15 in which the polarization directions of linearly polarized light to be transmitted are orthogonal to each other. The other elements of the liquid crystal panel 1 are disposed between the polarizing plate 11 and the polarizing plate 15. A transparent circuit board 14 on which an active matrix circuit is formed is disposed on the front side of the polarizing plate 15. On the front side of the circuit board 14, a liquid crystal part 13 is disposed which is configured by sandwiching a liquid crystal layer from the front and back with an alignment film for aligning liquid crystal molecules. A color filter substrate 12 on which a color filter is formed is disposed on the front side of the liquid crystal unit 13. The liquid crystal unit 13 is sandwiched between the circuit board 14 and the color filter substrate 12. The liquid crystal display device may further include other optical elements.
　図３は、実施形態１におけるアクティブマトリクス回路の一部を示す模式的正面図であり、図４は、実施形態１におけるアクティブマトリクス回路の一部を示す模式的回路図である。図３には、液晶表示装置が表示する画像を構成する複数の画素又はサブ画素の夫々に対応する部分を示しており、図４には、この部分の回路図を示している。アクティブマトリクス回路には、複数のゲート線３１が並行して配置されており、ゲート線３１に交差して複数のデータ線３２が配置されている。また、データ線３２に並行して複数の共通配線３３が配置されている。データ線３２と共通配線３３とは回路基板１４に沿って交互に配置されている。共通配線３３には、アクティブマトリクス回路全体で共通の信号が供給される。例えば、共通配線３３には、一定電位の信号が供給される。夫々の画素又はサブ画素に対応する図３に示す部分は、ゲート線３１とデータ線３２との各交点に対応する位置にあり、アクティブマトリクス回路内で隣接する二本のゲート線３１と隣接する二本の共通配線３３とで囲まれた部分である。 FIG. 3 is a schematic front view showing a part of the active matrix circuit in the first embodiment, and FIG. 4 is a schematic circuit diagram showing a part of the active matrix circuit in the first embodiment. FIG. 3 shows a portion corresponding to each of a plurality of pixels or sub-pixels constituting an image displayed by the liquid crystal display device, and FIG. 4 shows a circuit diagram of this portion. In the active matrix circuit, a plurality of gate lines 31 are arranged in parallel, and a plurality of data lines 32 are arranged so as to cross the gate lines 31. A plurality of common wires 33 are arranged in parallel with the data lines 32. The data lines 32 and the common wirings 33 are alternately arranged along the circuit board 14. A common signal is supplied to the common wiring 33 in the entire active matrix circuit. For example, a signal having a constant potential is supplied to the common wiring 33. 3 corresponding to each pixel or sub-pixel is located at a position corresponding to each intersection of the gate line 31 and the data line 32 and is adjacent to two adjacent gate lines 31 in the active matrix circuit. This is a portion surrounded by two common wires 33.
　アクティブマトリクス回路内の一つの画素又はサブ画素に対応する部分には、第１電極３４、第２電極３５及びＴＦＴ３６が設けられている。第１電極３４はデータ線３２に接続されており、第２電極３５はＴＦＴ３６を介してゲート線３１及び共通配線３３に接続されている。ＴＦＴ３６は、ゲートがゲート線３１に接続され、ソースが共通配線３３に接続され、ドレインが第２電極３５に接続されている。第１電極３４は、回路基板１４に沿った平面内でデータ線３２の両側に亘って形成されている。第１電極３４は並行した複数の線状部分を含んでおり、データ線３２の一部が一つの線状部分を兼ねている。第２電極３５は、並行した複数の線状部分を含んだ櫛歯状に形成されている。第１電極３４の線状部分と第２電極３５の線状部分は、回路基板１４に沿った方向に交互に配置されている。ゲート線３１に信号が供給された場合、ＴＦＴ３６がオン状態となり、この状態でデータ線３２に信号が供給された場合、第１電極３４と第２電極３５との間に電界が発生する。なお、図３及び図４にはアクティブマトリクス回路の最小限の構成を示しており、アクティブマトリクス回路は図示されていない回路素子を含んでいてもよい。 A first electrode 34, a second electrode 35, and a TFT 36 are provided in a portion corresponding to one pixel or sub-pixel in the active matrix circuit. The first electrode 34 is connected to the data line 32, and the second electrode 35 is connected to the gate line 31 and the common wiring 33 via the TFT 36. The TFT 36 has a gate connected to the gate line 31, a source connected to the common wiring 33, and a drain connected to the second electrode 35. The first electrode 34 is formed on both sides of the data line 32 in a plane along the circuit board 14. The first electrode 34 includes a plurality of parallel linear portions, and a part of the data line 32 also serves as one linear portion. The second electrode 35 is formed in a comb shape including a plurality of parallel linear portions. The linear portions of the first electrodes 34 and the linear portions of the second electrodes 35 are alternately arranged in the direction along the circuit board 14. When a signal is supplied to the gate line 31, the TFT 36 is turned on. When a signal is supplied to the data line 32 in this state, an electric field is generated between the first electrode 34 and the second electrode 35. 3 and 4 show the minimum configuration of the active matrix circuit, and the active matrix circuit may include circuit elements not shown.
　図５は、図３に示すＶ－Ｖ線に沿った回路基板１４の模式的断面図である。回路基板１４は、ガラス基板等の透明基板１４１を有し、透明基板１４１上に第１絶縁膜１４２が形成されている。データ線３２、共通配線３３及び第１電極３４は、第１絶縁膜１４２上に形成されている。データ線３２、共通配線３３及び第１電極３４を覆って、第１絶縁膜１４２上に、第２絶縁膜１４３が形成されている。第２電極３５は、第２絶縁膜１４３上に形成されている。データ線３２を含む第１電極３４と第２電極３５との間には、図５中に矢印で示す方向の電界が発生する。発生した電界には、回路基板１４に平行な成分が含まれている。電界の回路基板１４に平行な成分によって、液晶部１３内の液晶分子の向きが変化し、バックライト２からの光が液晶パネル１を通過するようになり、カラーフィルタに応じた色で画素又はサブ画素が表示される。 FIG. 5 is a schematic cross-sectional view of the circuit board 14 taken along the line VV shown in FIG. The circuit board 14 includes a transparent substrate 141 such as a glass substrate, and a first insulating film 142 is formed on the transparent substrate 141. The data line 32, the common wiring 33 and the first electrode 34 are formed on the first insulating film 142. A second insulating film 143 is formed on the first insulating film 142 so as to cover the data line 32, the common wiring 33 and the first electrode 34. The second electrode 35 is formed on the second insulating film 143. An electric field in the direction indicated by the arrow in FIG. 5 is generated between the first electrode 34 including the data line 32 and the second electrode 35. The generated electric field includes a component parallel to the circuit board 14. The component of the electric field parallel to the circuit board 14 changes the orientation of the liquid crystal molecules in the liquid crystal unit 13 so that the light from the backlight 2 passes through the liquid crystal panel 1, and the pixel or color in the color according to the color filter Sub-pixels are displayed.
　図６は、実施形態１におけるアクティブマトリクス回路の構成を示す模式的回路図である。複数のゲート線３１及びデータ線３２が格子状に配置されている。ゲート線３１及びデータ線３２の交点に対応する位置に、第１電極３４、第２電極３５及びＴＦＴ３６が配置されている。第１電極３４、第２電極３５及びＴＦＴ３６の組は、マトリクス状に配置されている。液晶表示装置は、複数のゲート線３１に接続されたゲートドライバ４１と、複数のデータ線３２に接続されたデータドライバ４２と、複数の共通配線３３に接続された共通信号部４３とを備えている。ゲートドライバ４１及びデータドライバ４２は本発明における信号供給部に対応する。共通信号部４３は、複数の共通配線へ共通の信号を供給する。例えば、共通信号部４３は、定電位源である。ゲートドライバ４１は、複数のゲート線３１へ供給するための信号を生成し、生成した信号を順次各ゲート線３１へ供給する。データドライバ４２は、複数のデータ線３２へ供給するための信号を生成し、生成した信号を順次各データ線３２へ供給する。信号を供給されたゲート線３１及びデータ線３２の交点に対応して配置された第１電極３４及び第２電極３５の間に電界が発生し、画素又はサブ画素が表示される。夫々のゲート線３１及びデータ線３２へ順次信号が供給されることにより、画素又はサブ画素が順次表示され、画像が表示される。表示される画像は、複数の画素で構成され、一つの画素は複数のサブ画素で構成される。 FIG. 6 is a schematic circuit diagram showing the configuration of the active matrix circuit in the first embodiment. A plurality of gate lines 31 and data lines 32 are arranged in a lattice pattern. A first electrode 34, a second electrode 35, and a TFT 36 are disposed at a position corresponding to the intersection of the gate line 31 and the data line 32. A set of the first electrode 34, the second electrode 35, and the TFT 36 is arranged in a matrix. The liquid crystal display device includes a gate driver 41 connected to the plurality of gate lines 31, a data driver 42 connected to the plurality of data lines 32, and a common signal unit 43 connected to the plurality of common lines 33. Yes. The gate driver 41 and the data driver 42 correspond to the signal supply unit in the present invention. The common signal unit 43 supplies a common signal to a plurality of common wires. For example, the common signal unit 43 is a constant potential source. The gate driver 41 generates a signal to be supplied to the plurality of gate lines 31 and sequentially supplies the generated signal to each gate line 31. The data driver 42 generates a signal to be supplied to the plurality of data lines 32 and sequentially supplies the generated signal to each data line 32. An electric field is generated between the first electrode 34 and the second electrode 35 arranged corresponding to the intersection of the gate line 31 and the data line 32 to which a signal is supplied, and a pixel or a sub-pixel is displayed. By sequentially supplying signals to the respective gate lines 31 and data lines 32, pixels or sub-pixels are sequentially displayed, and an image is displayed. The displayed image is composed of a plurality of pixels, and one pixel is composed of a plurality of sub-pixels.
　従来の液晶表示装置では、図９に示すようにゲート線５１とデータ線５２との間にＴＦＴ５６が接続されているのに対し、本実施形態では、図４に示すようにゲート線３１とデータ線３２との間にＴＦＴは接続されていない。本実施形態では、ゲート線３１とデータ線３２との間の容量は、ＴＦＴによる容量の増加が無いので、従来に比べて低下する。一方で、第２電極３５及び共通配線３３の間の容量は、ＴＦＴ３６によって大きくなっているものの、データ線３２及び第２電極３５の間の容量と直列になっているので、データ線３２の寄生容量への寄与は小さい。 In the conventional liquid crystal display device, the TFT 56 is connected between the gate line 51 and the data line 52 as shown in FIG. 9, whereas in this embodiment, the gate line 31 and the data are shown in FIG. No TFT is connected between the line 32. In the present embodiment, the capacitance between the gate line 31 and the data line 32 is lower than the conventional one because there is no increase in capacitance due to the TFT. On the other hand, although the capacitance between the second electrode 35 and the common wiring 33 is increased by the TFT 36, it is in series with the capacitance between the data line 32 and the second electrode 35. The contribution to capacity is small.
　また、本実施形態では、共通配線３３はデータ線３２に並行して配置されており、データ線３２と共通配線３３とが交差する部分がほぼ存在しない。このため、データ線３２と共通配線３３との間の容量は、データ線５２に交差して共通配線５３が配置されている従来の液晶表示装置に比べて、低下する。 In the present embodiment, the common wiring 33 is arranged in parallel with the data line 32, and there is almost no portion where the data line 32 and the common wiring 33 intersect. For this reason, the capacitance between the data line 32 and the common line 33 is reduced as compared with the conventional liquid crystal display device in which the common line 53 is arranged so as to intersect the data line 52.
　また、本実施形態では、第１電極３４が直接にデータ線３２に接続しているので、データ線３２と第１電極３４とは同一電位になる。データ線３２と第２電極３５との間に発生する電界は、第１電極３４と第２電極３５との間に発生する電界と同様の電界であり、画素又はサブ画素の表示のために利用される電界となる。即ち、データ線３２の一部は、第１電極３４の一部を兼ねている。このように、データ線３２と第２電極３５との間に発生する電界は不要な電界では無いので、データ線３２と電極との間に不要な電界が発生することを防止するためにデータ線３２をシールドすることは不要となる。従って、本実施形態では、データ線３２のシールドは存在せず、データ線３２とシールドとの間に容量が発生することも無い。 In the present embodiment, since the first electrode 34 is directly connected to the data line 32, the data line 32 and the first electrode 34 have the same potential. The electric field generated between the data line 32 and the second electrode 35 is an electric field similar to the electric field generated between the first electrode 34 and the second electrode 35 and is used for displaying a pixel or a sub-pixel. Electric field. That is, a part of the data line 32 also serves as a part of the first electrode 34. As described above, since the electric field generated between the data line 32 and the second electrode 35 is not an unnecessary electric field, the data line is used to prevent an unnecessary electric field from being generated between the data line 32 and the electrode. It is not necessary to shield 32. Therefore, in the present embodiment, the shield of the data line 32 does not exist, and no capacitance is generated between the data line 32 and the shield.
　以上のように、本実施形態では、従来の液晶表示装置に比べて、データ線３２の寄生容量は低下している。このため、データ線３２を通る信号の遅延が低減され、画素表示の遅延が十分に低減されている。画素表示の遅延が十分に低減されているので、高精細で大型の液晶表示装置を実現することが可能となる。また、液晶表示装置は、データ線３２の両端にデータドライバを配置した構成とせずとも、画素表示の遅延が十分に低減されるので、コストの上昇が抑制される。 As described above, in this embodiment, the parasitic capacitance of the data line 32 is lower than that of the conventional liquid crystal display device. For this reason, the delay of the signal passing through the data line 32 is reduced, and the delay of the pixel display is sufficiently reduced. Since the delay in pixel display is sufficiently reduced, a high-definition and large-sized liquid crystal display device can be realized. Further, even if the liquid crystal display device does not have a configuration in which data drivers are arranged at both ends of the data line 32, the delay in pixel display is sufficiently reduced, so that an increase in cost is suppressed.
＜実施形態２＞
　図７は、実施形態２におけるアクティブマトリクス回路の一部を示す模式的正面図である。図７には、画素又はサブ画素の夫々に対応する部分を示している。第１電極３４の線状部分が屈曲しており、並行して第２電極３５の線状部分も屈曲している。第１電極３４及び第２電極３５の形状に合わせて、データ線３２及び共通配線３３も屈曲した形状になっている。第１電極３４及び第２電極３５が屈曲していることによって、第１電極３４及び第２電極３５の間に発生する電界の回路基板１４に平行な成分の方向が部分的に異なる。このため、電界により駆動される液晶分子の向きが部分的に異なり、視野角に応じた画像の明るさの変動が緩和される。 <Embodiment 2>
FIG. 7 is a schematic front view illustrating a part of the active matrix circuit according to the second embodiment. FIG. 7 shows a portion corresponding to each of the pixel and the sub-pixel. The linear portion of the first electrode 34 is bent, and the linear portion of the second electrode 35 is also bent in parallel. According to the shape of the first electrode 34 and the second electrode 35, the data line 32 and the common wiring 33 are also bent. Since the first electrode 34 and the second electrode 35 are bent, the direction of the component parallel to the circuit board 14 of the electric field generated between the first electrode 34 and the second electrode 35 is partially different. For this reason, the orientation of the liquid crystal molecules driven by the electric field is partially different, and fluctuations in the brightness of the image according to the viewing angle are alleviated.
　本実施形態においても、ゲート線３１とデータ線３２との間にＴＦＴは接続されておらず、データ線３２のシールドは存在していない。従って、本実施形態に係る液晶表示装置では、従来に比べて、データ線３２の寄生容量は低下しており、データ線３２を通る信号の遅延が低減され、画素表示の遅延は十分に低減されている。 Also in this embodiment, the TFT is not connected between the gate line 31 and the data line 32, and the shield of the data line 32 does not exist. Therefore, in the liquid crystal display device according to the present embodiment, the parasitic capacitance of the data line 32 is lower than in the conventional case, the delay of the signal passing through the data line 32 is reduced, and the delay of the pixel display is sufficiently reduced. ing.
　なお、以上の実施形態１及び２においては、第１電極３４及び第２電極３５に含まれる線状部分がデータ線３２に平行な形態を示したが、液晶表示装置は、第１電極３４及び第２電極３５の線状部分がデータ線３２に交差する方向に形成された形態であってもよい。 In the first and second embodiments described above, the linear portions included in the first electrode 34 and the second electrode 35 are parallel to the data lines 32. However, the liquid crystal display device includes the first electrode 34 and the second electrode 35. The linear part of the second electrode 35 may be formed in a direction intersecting the data line 32.
＜実施形態３＞
　実施形態３では、ＦＦＳ（Fringe Field Switching）方式の液晶表示装置を示す。図８は、実施形態３におけるアクティブマトリクス回路の一部を示す模式的正面図である。図８には、画素又はサブ画素の夫々に対応する部分を示している。第１電極３４は、平板状の形状になっている。第２電極３５は、平板状の形状になっており、図示しない絶縁層を介在させて第１電極３４に重ねて配置されている。また、第２電極３５には、複数のスリットが形成されている。第１電極３４と第２電極３５との間には、スリットを通って電界が発生する。電界には回路基板１４に平行な成分が含まれており、電界の回路基板１４に平行な成分によって液晶分子の向きが変化し、画素又はサブ画素が表示される。 <Embodiment 3>
Embodiment 3 shows an FFS (Fringe Field Switching) type liquid crystal display device. FIG. 8 is a schematic front view illustrating a part of the active matrix circuit according to the third embodiment. FIG. 8 shows a portion corresponding to each pixel or sub-pixel. The first electrode 34 has a flat shape. The second electrode 35 has a flat plate shape and is disposed so as to overlap the first electrode 34 with an insulating layer (not shown) interposed therebetween. The second electrode 35 is formed with a plurality of slits. An electric field is generated between the first electrode 34 and the second electrode 35 through the slit. A component parallel to the circuit board 14 is included in the electric field, and the orientation of the liquid crystal molecules is changed by the component parallel to the circuit board 14 of the electric field, so that pixels or sub-pixels are displayed.
　本実施形態においても、ゲート線３１とデータ線３２との間にＴＦＴは接続されておらず、データ線３２のシールドは存在していない。従って、本実施形態に係る液晶表示装置では、従来に比べて、データ線３２の寄生容量は低下しており、データ線３２を通る信号の遅延が低減され、画素表示の遅延は十分に低減されている。 Also in this embodiment, the TFT is not connected between the gate line 31 and the data line 32, and the shield of the data line 32 does not exist. Therefore, in the liquid crystal display device according to the present embodiment, the parasitic capacitance of the data line 32 is lower than in the conventional case, the delay of the signal passing through the data line 32 is reduced, and the delay of the pixel display is sufficiently reduced. ing.
　なお、以上の実施形態１～３においては、共通配線３３がデータ線３２に並行している形態を示したが、液晶表示装置は、共通配線３３がゲート線３１に並行している形態であってもよい。また、実施形態１～３においては、回路基板１４中で第１電極３４をデータ線３２及び共通配線３３と同一の層に形成してある形態を示したが、液晶表示装置は、第１電極３４をデータ線３２又は共通配線３３と異なる層に形成した形態であってもよい。また、実施形態１～３においては、アクティブ素子としてＴＦＴを用いた形態を示したが、液晶表示装置は、ＴＦＴ以外のアクティブ素子を用いた形態であってもよい。 In the first to third embodiments, the common wiring 33 is parallel to the data line 32. However, the liquid crystal display device has a common wiring 33 parallel to the gate line 31. May be. In the first to third embodiments, the first electrode 34 is formed in the same layer as the data line 32 and the common wiring 33 in the circuit board 14. However, the liquid crystal display device includes the first electrode 34. 34 may be formed in a layer different from the data line 32 or the common wiring 33. In the first to third embodiments, the TFT is used as the active element. However, the liquid crystal display device may be an active element other than the TFT.
　１　液晶パネル
　１２　カラーフィルタ基板
　１３　液晶部
　１４　回路基板
　２　バックライト
　３１　ゲート線
　３２　データ線
　３３　共通配線
　３４　第１電極
　３５　第２電極
　３６　ＴＦＴ DESCRIPTION OF SYMBOLS 1 Liquid crystal panel 12 Color filter board | substrate 13 Liquid crystal part 14 Circuit board 2 Backlight 31 Gate line 32 Data line 33 Common wiring 34 1st electrode 35 2nd electrode 36 TFT

Claims (4)

  1. 　一対の基板と、該一対の基板の間に挟持された液晶とを備え、前記一対の基板の一方の基板には、並行に配置された複数のゲート線と、該ゲート線に交差して並行に配置された複数のデータ線と、前記ゲート線及び前記データ線の各交点に対応して配置されたアクティブ素子とが形成されており、前記ゲート線及び前記データ線に順次的に信号を供給する信号供給部を更に備える液晶表示装置において、
    　前記一方の基板には、
    　共通の信号が供給される共通配線と、
    　前記ゲート線及び前記データ線の各交点に対応して配置され、前記データ線に接続された第１電極と、
    　前記ゲート線及び前記データ線の各交点に対応して配置され、前記ゲート線及び前記共通線に前記アクティブ素子を介して接続された第２電極とが形成されており、
    　前記第１電極及び前記第２電極は、信号を供給された前記ゲート線及び前記データ線の交点に対応して配置された前記第１電極及び前記第２電極の間に、前記一方の基板に平行な成分を含む前記液晶を駆動させるための電界が発生するように形成されていること
    　を特徴とする液晶表示装置。     A pair of substrates and a liquid crystal sandwiched between the pair of substrates, and one substrate of the pair of substrates includes a plurality of gate lines arranged in parallel and a plurality of gate lines arranged in parallel and intersecting the gate lines And a plurality of data lines arranged in a row and active elements arranged corresponding to the intersections of the gate lines and the data lines are formed, and signals are sequentially supplied to the gate lines and the data lines. In a liquid crystal display device further comprising a signal supply unit for
    On the one substrate,
    Common wiring to which a common signal is supplied; and
    A first electrode disposed corresponding to each intersection of the gate line and the data line and connected to the data line;
    A second electrode disposed corresponding to each intersection of the gate line and the data line and connected to the gate line and the common line via the active element;
    The first electrode and the second electrode are disposed on the one substrate between the first electrode and the second electrode disposed corresponding to an intersection of the gate line and the data line supplied with a signal. A liquid crystal display device, wherein an electric field for driving the liquid crystal containing parallel components is generated.
  2. 　前記データ線の一部は、前記第１電極の一部を兼ねていること
    　を特徴とする請求項１に記載の液晶表示装置。     The liquid crystal display device according to claim 1, wherein a part of the data line also serves as a part of the first electrode.
  3. 　前記一方の基板には、複数の前記共通配線が形成されており、
    　前記共通配線は、前記データ線に並行して、前記データ線と交互に配置されていること
    　を特徴とする請求項１又は２に記載の液晶表示装置。     A plurality of the common wirings are formed on the one substrate,
    The liquid crystal display device according to claim 1, wherein the common wiring is arranged alternately with the data lines in parallel with the data lines.
  4. 　前記第１電極及び前記第２電極は、夫々に、一又は複数の線状部分を有し、
    　前記第１電極の線状部分と前記第２電極の線状部分とが前記一方の基板に沿った方向に交互に配置されていること
    　を特徴とする請求項１から３までのいずれか一つに記載の液晶表示装置。     Each of the first electrode and the second electrode has one or more linear portions,
    The linear portion of the first electrode and the linear portion of the second electrode are alternately arranged in a direction along the one substrate. 4. A liquid crystal display device according to 1.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11288000A (en) * 1998-04-06 1999-10-19 Hitachi Ltd Liquid crystal display device
JP2000047250A (en) * 1998-07-24 2000-02-18 Nec Corp Liquid crystal display panel
JP2012234212A (en) * 2012-09-03 2012-11-29 Nlt Technologies Ltd Active matrix substrate and liquid crystal panel

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11288000A (en) * 1998-04-06 1999-10-19 Hitachi Ltd Liquid crystal display device
JP2000047250A (en) * 1998-07-24 2000-02-18 Nec Corp Liquid crystal display panel
JP2012234212A (en) * 2012-09-03 2012-11-29 Nlt Technologies Ltd Active matrix substrate and liquid crystal panel

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