WO2017046032A1

WO2017046032A1 - Latch circuit and method for blocking a data line

Info

Publication number: WO2017046032A1
Application number: PCT/EP2016/071447
Authority: WO
Inventors: Peter Buschmann
Original assignee: Hella Kgaa Hueck & Co.
Priority date: 2015-09-18
Filing date: 2016-09-12
Publication date: 2017-03-23
Also published as: CN108476154B; US20200235779A1; US10911098B2; CN108476154A; DE102015012002A1

Abstract

The invention relates to a latch circuit and to a method for suppressing an echo on a receive line, the latch circuit blocking the receive line in the presence of a signal on a transmit line, and the receive line having a transmit side to which the echo signal is applied and a receive side on which the echo signal can be blocked. Particularly the echo signal of a CAN driver is suppressed so that a control component for a light matrix of a headlight does not receive undesired commands.

Description

Locking circuit and method for locking a data line

The invention relates to a latch circuit and a method for blocking a data line.

Adaptive headlamps can implement different functions, such as bend lighting, high beam, dipped beam, apron lighting, running light with animation. Also the

Environmental adaptive functions, such. B. light cone with a black tunnel, so that oncoming road users are not dazzled, while all other areas are illuminated with high beam, can be realized.

The lighting is often realized with a matrix of light elements, especially LEDs. These individual light elements can be switched independently of each other, so as to generate different illumination patterns (functions). For simplified control of such a matrix special integrated components have been developed, for. For example, the Light Matrix Manager (LMM) for

Vehicle systems TPS92661. In this case, the brightness of each light element is controlled by means of a PWM control of the current. This happens for each

Light element (LED) individually. To control the PWM ratio, the LMM provides a set of registers that can be set via Universal Asynchronous Receiver Transmitters (UART).

Such a device has an internal state machine that correctly processes only defined commands. However, if this receives an unknown command or garbage, there is a risk that the state machine entangled and the function of the device is impaired.

The document DE 103 40 806 B3 teaches how by means of a simple

Interface circuit, the detection of a short circuit, or a

Access collision on a single-wire line in UART mode is simplified. in this connection an OR gate is used, which compares the address bits of a data signal in the transmit and receive paths. The result is provided via a separate diagnostic pin.

The present invention is based on the object to prevent an echo on a second data line, which is due to a signal on a first data line. There are components that produce such an echo. This in turn could disturb other components and affect their functionality. A

Echo cancellation allows the simultaneous use of both types of

Components.

According to the invention the above object with the features of

solved independent claims. Advantageous embodiments are in the

Subclaims described.

A latch circuit for suppressing an echo on a

Receive line, locks in the presence of a signal on a transmission line, the receiving line. The receiving line has a transmitting side to which the echo signal is applied and a receiving side on which the echo signal can be blocked.

A signal herein means a change in a voltage level from one ground level to another level. These can be used to define binary values (bits). A signal usually represents one bit here, in particular when considering the existing measurements. A sequence of signals (plural), which may represent several bits, the z. B. form a data word, may occasionally be referred to as a signal.

Such a locking circuit is particularly suitable for 2 single-wire data lines, ie a transmitting and a receiving line, which allows one for bidirectional communication in full duplex operation between two communication partners. Such communication may be serial data transfer on a serial bus. In this different bus protocols application can be found, such as RS232, SPI (Serial Peripheral Interface), I ² C (I-square-C) or UART.

It is to make that one of the two lines lockable, get on the data from the echo generating device to the communication partner. It would be unfavorable if both communication partners produce echoes.

Various solutions for blocking or blocking the output line are conceivable, such as discrete realized by means of transistors, analogous with a transmission gate. In the following, a solution by means of digital logic is proposed.

In a particular embodiment, in the latch circuit, a control signal derived from the transmission signal may be present on a control line. The control line is connected to the input of an inverter whose output is connected to an input of an OR gate in the case of signals with negative logic, or an AND gate in the case of signals with positive logic. A second input of the gate is connected to the transmitting side of the receiving line and the output of the gate to the receiving side of the receiving line.

Advantageously, the circuit can thus be realized with a small amount of hardware. Elaborate alternatives, such as complex deduction by means of a microcontroller or error handling when receiving an echo, can thus be avoided.

In the simplest case, the control signal can also be directly the transmission signal. The derivative does not refer to a derivation in the mathematical sense, but to a dependence, ie the control signal is determined by the state or course of the transmission signal. The description of the circuit also includes circuit variants in which further components are used as long as they do not change the logic of the circuit. This may include buffer elements or driver stages.

In a particular embodiment, a delay circuit affects the control signal so that the latch circuit latches for a longer period of time than the signal is present on the transmission line.

Advantageously, the echo signal can thus be completely suppressed. Otherwise, there is the danger that if there is no more send signal, but the delayed echo is still active, this remainder of the echo on the receiving line is still visible.

The complete latch circuit consists of two parts, namely the delay circuit and the actual latch circuit. In order to prevent too early release of the receive line, the control signal which moves the lock circuit to lock must be extended. The

Delay circuit also extends the control signal beyond the end of the signal on the transmission line.

In a particular embodiment of the latch circuit, the delay circuit connects the transmission line via a diode to the control line.

Furthermore, while the control line via a resistor (R1) with the

Supply voltage and via a capacitor (C1) connected to ground.

Advantageously, only a small amount of hardware is possible here. Other realization ideas like a timer in a microcontroller or a

Interrupt control seem to be more complex.

The diode is connected in the reverse direction, ie the transmission line is connected to the cathode, the control line to the anode. In a further embodiment, a Schottky diode can be used as the diode. This has lower ohmic losses and a lower one

Breakdown voltage.

In a particular embodiment of the latch circuit, a CAN driver which generates the echo is connected to the transmission line and the transmission side of the reception line.

Such a CAN driver translates signals from a CAN bus to a serial bus. Different bus protocols can be used on this, such as RS232, SPI, l ² C or UART. The following is an example of UART.

Usually, both buses are realized by two single-wire cables. Some well-known CAN driver blocks echo on the UART side bus. Specifically, when a serial signal arrives at the TxD input, an echo appears on the RxD output of the UART-side bus with a time delay. Of course, the actual useful function is fulfilled and this signal forwarded on the CAN side.

It can take place on the CAN side only a realization of the physical layer (low-voltage differential voltage signals), so that the UART protocol is transmitted on the physical CAN layer. Alternatively, in addition to the physical conversion, a complete translation of the data protocol (data backup layer) from UART to CAN can take place.

On the one hand, the echo can on the one hand offer a desired functionality, such as: B. the plausibility of a correct data transmission described in the prior art, on the other hand, this echo can also interfere with the communicating devices. This allows the state machine of a connected block (eg LMM)

confused when sent via the echo, a message (data word) to the block that does not represent a message that awaits the block.

In a further embodiment of the latch circuit is a

Control module for lighting control connected to the locking circuit. The locking circuit prevents the echo from reaching the drive module.

In a particular embodiment of the latch circuit, at least one light matrix manager module, as a special drive module for lighting control, is connected to the transmission line and the reception side of the reception line. In this case, the at least one light matrix manager module sends the signal on the

Transmission line.

Advantageously, thus the functionality of the LMMs can be improved because no unwanted messages arrive via the receiving line at the LMM.

In a special version of the Light Matrix Manager module, a block with the type designation TPS92661 can be used. Other components that fulfill this functionality are of course conceivable.

In another embodiment, the latch circuit is between a CAN driver and a LMM. The two communicate

Communication partner without an echo, which generates the CAN driver, arrives at the LMM and could disturb him so.

The UART communication used by the LMM is not necessarily one

common standard in automotive applications. This type of transmission can cause problems with longer cable lengths, such as those found in automobiles. It is therefore possible to use an already established bus or transmission protocol, such as CAN or LIN. In particular, CAN seems to meet the conditions for the required data transmission rates, available signals and EMC robustness for the desired line lengths.

Therefore, a CAN transmission is selected for a long line, which is converted into a UART transmission via a CAN driver located close to the LMM. Advantageously, such a transmission can be carried out over greater distances at an acceptable transmission rate.

Such a transmission rate can be 500 kbps. At these bit rates, a CAN driver is often used because the CAN signal is a low voltage differential signal and less prone to attenuation and reflections.

Typically, inputs are high impedance, but with a characteristic impedance of 120 ohms for single and two-wire cables, it would need low-impedance

Termination resistors to avoid reflections (180 degree reflections).

A pull-up resistor is at the same time a terminating resistor and must also be dimensioned correctly with regard to the described effect. Another aspect is performed EMC measurements. Such an arrangement with pull-up resistance becomes sensitive to the radiation resistance. In the presence of a low-impedance pull-up resistance increases the immunity to interference.

In another embodiment, there is a controller, master ECU (MCU), e.g. B. realized by a microcontroller, which drives the LMMs. If that

Control unit only a UART and CAN communication is not possible, it can also be used on the controller side another CAN driver. This converts the UART signals into CAN and is connected via an optionally long line to the other CAN driver, which again generates UART signals from the CAN signals which can be read by the LMM.

Since possibly also the MCU communicates by means of UART, on the

Transmission line if necessary 2 CAN drivers are used. The first is located near the MCU microcontroller and there is a UART transfer between the two. On the CAN side, a possibly long cable to the headlight is connected. Before the line reaches the LMM, the CAN connection is again converted into a UART connection by a second CAN driver located near the LMM. This signal path then exists twice to ensure full duplex transmission. In a particular embodiment of the latch circuit, the latch circuit is applied to a circuit board on which also the CAN driver, a communication interface and the at least one light matrix manager module are located.

Advantageously, a printed circuit board offers the possibility to interconnect several components together to form a module, to mass-produce and a simple

Handling and standardized installation in z. B. a headlight or its

To allow housing. Also, various components or functionalities are available only once. For example, this relates to components associated with the

Power supply or a clock.

A communication interface is in the simplest case in one

Connection possibility for one or more cables, via which the CAN communication is realized. The MCU can communicate with the LMM via this interface, whereby the signal is transmitted via the board and thus via CAN driver and

Interlocking circuit to the LMM is running. The same applies to the signal path back.

In another embodiment, multiple LMMs exist on a circuit board. This is suitable for. B. when different light functionalities are to be realized within a headlight with different LMMs that can be close to each other. As described, synergies arise because some components only have to be provided once per circuit board.

In a particular embodiment of the locking circuit, a printed circuit board is designed such that it can receive a component according to claim 7 or, alternatively, a component, which is a direct connection between the

Communication interface and the Light Matrix Manager module.

Advantageously, in this case the same circuit board can be used, if a communication according to the invention is to take place via CAN with conversion to UART, just as a classic UART communication between MCU and LMM should take place.

In the second case, essentially the signal from the

Communication interface to the LMM be looped through. A direct one

In the present case, communication means that there is no protocol conversion by means of CAN drivers or interlocking. Possibly. are passive components, like

Input or pull-up resistors can be provided.

The advantage of a printed circuit board for both is the flexibility of manufacture. So the headlight housing can be built identically, since the same

Board holder is provided for both variants. Even production costs can be saved, since only one version of the PCB has been developed, tested, or

must be produced.

A method for suppressing an echo on a receiving line detects a signal on a transmission line and then blocks the transmission on the

Receive line for the duration of the signal.

In a further embodiment of the method, a control signal is derived from the transmission signal. This is inverted and ORed with the signal on the transmitting side of the receiving line, if they are negative logic signals, as they are for. B. are common in the RS232 interface. The result is the receive signal which is blocked under the described circumstances and which can be forwarded to the communication partner.

In the case of signals with positive logic, an AND operation must be used instead of the OR-.

In a further embodiment of the method, the control signal is extended so that it is locked for a longer period of time than the signal is present on the transmission line. A headlight system includes a plurality of light sources, a matrix controller of these light sources, an interface for communication with the matrix controller, a CAN driver and a latch circuit according to this invention.

Advantageously, an integrated headlight system can be offered, which is merely installed in a vehicle and its interface to the CAN

must be connected. This reduces the variety of variants of the hardware and processing steps, which at least the OEM can be relieved. Thus, as much of the supply chain as possible remains with the supplier.

Embodiments of the invention are explained below with reference to the drawings.

Show it:

FIG. 1 shows a communication architecture between a control device and light-matrix management modules,

FIG. 2 shows two different architectures for connecting a plurality of light-matrix management modules,

FIG. 3 is a block diagram of a CAN driver;

FIG. 4 shows the measurement of an input and output of a CAN driver,

FIG. 5 shows a circuit implementation of the circuit,

FIG. 6 shows a circuit logic for a latch circuit,

FIG. 7 shows a measurement of the transmission delay of a starting edge,

FIG. 8 shows a measurement of the transmission delay of an end flank,

FIG. 9 shows a measurement with a locking time which is too short,

10 shows a delay circuit in combination with the latch circuit, FIG.

FIG. 11 shows a measurement of the signals from FIG. 10

FIG. 12 shows a measurement of the communication between the CAN driver and the light matrix management module using the delay circuit in FIG

Combination with the interlocking circuit and FIG. 13 shows an assembly variant for a printed circuit board.

In Figure 1 is a design for a communication architecture between a

Control unit (master ECU (MCU)) and various (light matrix management modules (LMM)) described.

Here is shown an architecture that enables full duplex communication. The transmit output (Tx) of the MCU is connected to the receive inputs (Rx) of all LMMs. The same applies to the transmission outputs (Tx) of all LMMs that are connected to the

Receive input (Rx) of the MCU are connected.

An advantage of this arrangement may be a cheap solution to be implemented, possibly even the cheapest of all presented here. Distances between the MCU and the LMMs of up to 50 cm or 70 cm can be bridged without the EMC robustness being impaired too much.

In Figure 2, two different architectures are shown.

Figure 2a shows a point to point (PtP) connection between an MCU and multiple LMMs mounted on a printed circuit board (PCB). Between the MCU and the circuit board, or board is a cable connection over which preferably a CAN or LIN connection can be realized.

An internal clock must be available on each PCB, with which, for example, the UART communication signal must be sampled, since no clock generated outside the PCB is available. With the PtP variant, only one clock generator is necessary for the entire PCB, which can be accessed by the several LMMs.

With the PtP variant, the EMC susceptibility can be improved by adding a push-pull stage (totem pole output) for the transmission signal (Tx) of the LMM. Figure 2b shows a point to multipoint (PtM) connection between an MCU and a plurality of LMMs, each arranged on a printed circuit board.

There is one between the MCU and the various printed circuit boards

Cable connection over which preferably a CAN or LIN connection can be realized. In this case, a star architecture, d. H. individual lines from the MCU to each circuit board and thus to the respective LMM or a bus architecture according to FIG. 1 are realized.

In the PtM variant several clock generators are necessary, i. d. R. for each

Circuit board one. This can make the PtM variant more expensive than the PtP variant. The same applies to the increased power consumption caused by several clock generators, amplified when they are operated at 5V instead of 3.3V, or the

Communication is operated with the higher of the two voltages.

With the PtM variant, attention must be paid to the value of the entire pull-up resistor. Possibly. The values of the pull-up resistors must be selected when fitting the printed circuit boards depending on the number of printed circuit boards to be connected. Depending on the type of circuit, the different pull-up resistors should work in parallel. Ie. the resistance values should be chosen so that they are not below a minimum value. Of the

Total resistance can z. B. have a value of 1k, 2k or 5k ohms.

Certain applications, such as automobiles, are specific

Minimum data transmission rates required and this under the existing EMC influence. For example, data transfer rates of 500 kbps may be required at a 16-times higher clock rate (equal to 8 MHz). Such a clock rate may be too high to safely transmit and distribute by cable.

The PtM variant can also be used in a single headlight, but each circuit board is usually responsible for a different function (such as cornering, high beam, dipped beam). FIG. 3 shows a block diagram of a CAN driver which converts, converts or translates between the CAN signals on the left side and UART signals on the right side.

It should be noted in this illustration that the pin referred to as TxD here represents an input, i. The Tx signal of the communication partner must be connected here. Likewise, the RxD pin designates an output on which the CAN driver sends.

A CAN driver or CAN-UART converter translates the 5 V (or 3.3 V) UART signals Tx and Rx into CAN signals CANH and CANL, which are known to consist of low-voltage and differential signals. Such signals can be transmitted more easily over greater distances. Often this is realized with twisted wires. Furthermore, the CAN driver meets other automotive requirements, eg. B. Short-circuit protection against ground and the on-board supply voltage (12V).

Unfortunately, such drivers generate a local echo. In this case, signals that are fed to the UART-side input (TxD) are routed to the CAN side and reach CANH and CANL. From there they reach the receiver block, via which they are also available at the UART-side output RxD.

A microcontroller can suppress the echo by blocking the receive interrupt or even making use of the echo signal, for example by using the echo signal. B. verifies that the received is equal to the transmitted signal.

However, an LMM with its internal state machine is likely to be disturbed if it gets sent by the echo bit sequences that are not provided in its architecture. In other words: So can the

State machine of a connected LMM confused when sent via the echo, a message (data word) to the LMM that no

Message that the LMM expects. FIG. 4 shows a measurement of a CAN driver in which a signal 41 of the LMM enters the TxD input of the CAN driver and an echo signal 42 is generated on the RxD output of the CAN driver. Between both signals there is a delay, here on about 100ns. A latch circuit must be suitably sized to lock before the echo begins, and release this latch only after the echo has ended. In this example, this means that the latch must be active faster than in 100ns after the beginning edge of the TxD signal, and after the end edge must block more than 100ns longer than the TxD signal is active.

Two commercially available modules for CAN drivers are proposed. According to the data sheet, the TLE6250 has a transmission delay between 150ns and 280ns for both flanks. The TJA1051 has a transmission delay of 40ns to 250ns according to the data sheet.

FIG. 5 shows a circuit implementation of the wiring of a CAN driver with a latch circuit.

In the middle is the IC1000, the CAN driver, which translates between the CAN signals on the left (CANH, CANL) and the serial UART signals on the right (RxD, TxD).

Between the CAN inputs / outputs and the CAN driver there are blocks that serve as the basic circuit for interference suppression, eg. B. a bifilar choke L1000 or resistors R1000, R1001 for the bus termination.

The components D1001, R1002, C1002 serve as a delay element for the release of the lock, according to FIG. 10.

The component IC1001 is used for the logical connection for blocking the

Receiving line, according to FIG. 6.

It should again be pointed out that the line designated TxD transmits the data from the connected LMM to the CAN driver, from the point of view of the CAN Driver so unlike the name suggests, represents an input. Conversely, the same applies to the RxD line.

In Figure 6, a circuit logic is proposed which provides a logical function for 0 active levels (negative logic) according to the formula Rx = (NOT A) OR B, where A is a control signal which, when active, blocks the signal B should effect. The control signal is derived from the transmission signal and is in the simplest case identical to this. The signal B is the transmitting side

Receive line Rx (from CAN Rx), d. H. the output signal RxD from the CAN driver.

In a hardware implementation, the control line on which the control signal is applied is connected to the input of an inverter (INV) whose output is connected to one of two inputs of an OR gate (OR). The second input is connected to the send side of the receiver line (from CAN Rx), ie the RxD pin of the CAN driver. The output of the OR gate is connected to the receive side of the receiver line (to LMM Rx), ie the Rx pin of the LMM (s).

It should be noted that in this locking circuit no direct

There is a connection between the RxD output of the CAN driver (from CAN Rx) and the Rx input of the LMM module (to LMM Rx), but a connection is made only via the gate so that it can be locked if necessary. Otherwise, the transmission line Tx can connect both blocks directly from LMM Tx to CAN Tx.

The above circuit is suitable for negative logic signals (0-active logic). In the case of a positive logic, i. H. that the bit value 1 is realized via a Hi level, the OR gate is to be replaced by an AND gate by the same

Effect locking functionality.

This logic functionality can be achieved by means of configurable multi-function gates such. B. the blocks 74LVC1G57, 74LVC1G97 and 74LVC1G98 be realized. In particular, the 74LVC1G57GW-Q100 is suitable because it is cost-effective and qualified for automotive applications.

Figures 7 and 8 show the transmission delays for these logic circuits, which have switching times of less than 8 ns, and thus are fast enough to block the receiving line in good time before the echo from the CAN driver arrives.

The curves 71 and 81 show an input signal A or Tx in the logic circuit, the curves 72 and 82 the resulting output signal.

FIG. 7 shows the curve for the beginning flank, and FIG. 8 for the end flank.

FIG. 9 shows the problem that although the latch circuit according to FIG. 6 switches in time before the beginning edge of the echo, it does not latch long enough to unlock again only after the end of the echo. For this purpose, according to the present measurement, the lock would have to remain active for at least 280ns after the end of the signal on the transmission line.

For signals with negative logic, the start edge is falling (from Hi to Lo level) and the end edge is rising (from Lo to Hi), and reversed for signals with positive logic.

Signal 91 is the signal applied to the transmission line Tx, i. H. the TxD input signal of the CAN driver. The echo signal 92 appearing on the transmitting side of the receiving line Rx is the output signal of the CAN driver. Signal 93 shows the unwanted part of the echo that would have been transmitted anyway because an exclusive existing circuit according to Figure 6 would not have locked long enough.

In Figure 10, a circuit is shown which causes a delay in the cancellation of the control signal for the lock, that causes a time delay with a time delay constant. A diode D1, D1001 is in the reverse direction between the transmission line and the

Control line switched, it shows with the cathode side to the transmission line and the anode side to the control line. Ie. if the Tx level is Hi, the diode blocks if it is Lo, lets it through. This ensures that a falling edge of the Tx signal, which corresponds to the beginning edge in the case of negative logic, is immediately applied to the

Control signal breaks through. A rising edge, however, leads to the blocking of the diode and thus the control signal is then dependent on the other components.

The control line A is connected via a resistor R1, R1002 with the

Supply voltage Vcc and connected to a capacitor C1, C1002 to ground. A Lo level of the Tx signal discharges the capacitor via the then in

Forward direction switched diode. Otherwise, the capacitor charges in a speed corresponding to the component values from the Lo direction Hi level. The switching point of the control signal is determined by the switching level, the z. B. at Vcc / 2 is determined. The time constant is determined by the resistance and the

Capacitor value.

From this point, the downstream logic circuit of Inverter (INV) and OR gates (OR) would switch. This was presented in FIG.

FIG. 11 shows a measurement of the signals. v (a) is the measurement of the analog Tx signal, v (b) of the analog control signal, v (c) of the digital control signal, and v (d) of the digital Tx signal.

For this measurement, an alternating 0-1 bit pattern was used, as can be seen on the equidistant edges of the digital Tx signal v (d). The digital

Control signal indicating the times / durations of the active lock now has a delay and is still active after the end edge of the Tx signal. Thus, the unwanted remainder of the echo signal shown in FIG. 9 can now also be suppressed.

Optionally, between the described components still others on the

Signal paths that cause more or improved functions. For example, you can Signal driver stages between the Tx line and the diode or the RC element and the logic circuit are installed.

The time constant of this measurement is chosen to be half a duration of one bit (about 500ns). This leaves enough tolerance for the needed

Delay and releases the latch circuit during the occurrence of the stop bit, thus allowing communication without any timing constraints. The receiving channel is immediately free again after a lock for receiving another communication from the MCU.

FIG. 12 shows a communication between an MCU and an LMM via a CAN driver, in which the interlocking circuit according to FIG. 10 is used. Here, a data word is transmitted from the MCU to the LMM, which then responds with a data word to the MCU.

The signal 121 is the bit pattern that is transmitted from the MCU via the CAN driver via the

Receive line (Rx) is sent to the LMM and can content a

Request to the LMM represent that this should send data. This signal is measured at the receiving end of the LMM, d. H. after the output of the gate of the latch circuit.

The signal 123, however, is the signal of the receiving line, but measured on the output side of the CAN driver. Here the echo is visible in the right half of the measurement resulting from the Tx signal.

The signal 122 shows said Tx signal on the transmission line, which is e.g. B. may be the requested data, which sends the LMM to the MCU, or CAN driver.

As a result of the circuit according to the invention, the echo of the response of the LMM could be completely suppressed. FIG. 13 shows an assembly variant for a printed circuit board which has a

Assembly according to the circuit of Figure 5 allows, as the crossed-out components of the figure show. Here, however, an alternative assembly is shown, in the event that no CAN communication between the MCU and LMM is used, but a direct UART communication.

In this case, essentially the output pins ST1-Tx or CANH are connected to the UART-side Tx only via the resistor R1010 with the pull-up R1008 applied. Similarly, the input pin ST1-Rx, or CANL is connected to the UART-side Rx only via the resistor R1013 with applied pull-up R1009. Even a short circuit instead of the contact resistance is conceivable.

LIST OF REFERENCE NUMBERS

MCU Master-ECU, control unit

Tx transmit pin, transmission line

Rx receive pin, receiving line

TPS92661 light matrix management module, type Tl TPS92661

LMM light matrix management module

CANH Can-Hi connection

CANL Can-Lo connection

Vcc supply voltage

TxD connection for transmission line, input in CAN driver

RxD connection for receive line, output from CAN driver

41 Signal on transmission line

42 signal on receiving line, here echo

D1000, components for CAN input circuit

C1000,

R1000,

R1001,

L1000

IC1000 CAN driver

D1001, (D1), Delay circuit components

R1002, (R1),

C1002, (C1) IC1001 logic device

A control signal

B, transmit side receive signal

fromCANRx toCANRx Receive-side receive signal

INV inverter

OR Or Gate

71 Input signal of a logic module of a starting edge

72 Output signal of a logic module of a start edge

81 Input signal of a logic module of an end edge

82 Output signal of a logic module of an end edge

91 Transmission signal to toCANTx

92 Receive signal to fromCANRx

93 Remaining echo signal to toLMMRx toCANTx Send line connection to CAN driver fromLMMTx Send line connection to LMM v (a) Measurement of analog transmission signal v (b) Measurement of analogue control signal v (c) Measurement of digital control signal v (d) Measurement of digital transmission signal

121 bit pattern signal from MCU to LMM (request) 122 bit pattern signal from LMM to MCU (response)

123 Signal at the RxD output of the CAN driver

R1010, volume resistances

R1013

R1008, pull-up resistors

R1009

Claims

Latch circuit and method for blocking a data line. Claims

A latch circuit for suppressing an echo (42) on a

Receiving line (Rx),

characterized in that

the latch circuit, in the presence of a signal (41) on a transmission line (Tx), blocks the reception line (Rx),

wherein the receiving line has a transmitting side (B, from CAN Rx) to which the echo signal is applied and a receiving side (to LMM Rx), on which the echo signal can be blocked.

2. Locking circuit according to claim 1, characterized in that a control signal (A) derived from the transmission signal (41) can be present on a control line,

the control line being connected to the input of an inverter (INV),

whose output is connected to an input of an OR gate (OR) in the case of signals with negative logic, or an AND gate in the case of signals with positive logic,

wherein a second input of the gate with the transmitting side of the

Receive line (from CAN Rx) is connected and

wherein the output of the gate is connected to the receiving side of the receiving line (to LMM Rx).

A latch circuit according to claim 2, characterized in that a delay circuit (D1 + R1 + C1) influences the control signal (A) so that the latch circuit latches for a longer period of time than the signal is applied to the transmission line.

4. Locking circuit according to claim 3, characterized in that the delay circuit, the transmission line via a diode (D1) with the control line (A)

and the control line via a resistor (R1) with the

Supply voltage,

and via a capacitor (C1) connects to ground.

5. Locking circuit according to one of the preceding claims, characterized

marked that

a CAN driver capable of generating the echo is connected to the transmission line and the transmission side of the reception line.

6. Locking circuit according to one of the preceding claims, characterized

marked that

at least one light matrix manager module (TPS92661) is connected to the transmission line and the reception side of the reception line,

wherein the at least one light matrix manager module transmits the signal on the transmission line.

7. Locking circuit according to claims 5 and 6, characterized

marked that

the locking circuit is applied to a printed circuit board,

including the CAN driver,

a communication interface

and that at least one light matrix manager module are located.

8. Locking circuit according to one of the preceding claims, characterized

marked that

a printed circuit board is designed such that it can accommodate a fitting according to claim 7

or alternatively an assembly that allows a direct connection between the communication interface and the light matrix manager module.

9. A method for suppressing an echo (42) on a receiving line (Rx),

wherein a signal (41) on a transmission line (Tx) is detected and then the transmission on the receiving line (Rx) is blocked for the duration of the signal.

10. Headlamp system, comprising

several light sources,

a matrix control of these light sources,

an interface for communication with the matrix controller,

a CAN driver and

a latch circuit according to claim 1.