WO2017038447A1 - Nitride surface-emitting laser - Google Patents

Nitride surface-emitting laser Download PDF

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Publication number
WO2017038447A1
WO2017038447A1 PCT/JP2016/073882 JP2016073882W WO2017038447A1 WO 2017038447 A1 WO2017038447 A1 WO 2017038447A1 JP 2016073882 W JP2016073882 W JP 2016073882W WO 2017038447 A1 WO2017038447 A1 WO 2017038447A1
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Prior art keywords
dielectric multilayer
multilayer film
semiconductor layer
layer
current injection
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PCT/JP2016/073882
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French (fr)
Japanese (ja)
Inventor
将一郎 泉
達史 濱口
統之 風田川
大 倉本
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ソニー株式会社
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Priority to JP2017537714A priority Critical patent/JP6973077B2/en
Publication of WO2017038447A1 publication Critical patent/WO2017038447A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/10Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/30Structure or shape of the active region; Materials used for the active region
    • H01S5/34Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
    • H01S5/343Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser

Definitions

  • the present technology relates to, for example, a nitride surface emitting laser that emits laser light in the stacking direction.
  • a surface emitting laser is generally provided with light reflecting layers (Distributed Bragg Reflector layers; DBR layers) above and below a semiconductor layer including an active layer.
  • DBR layers distributed Bragg Reflector layers
  • laser oscillation occurs by resonating light between the two DBR layers. For this reason, it is necessary to smooth the semiconductor surface on which the DBR layer is formed on the sub-nanometer order. If an appropriate smoothness cannot be obtained, the light reflectivity of each DBR layer is reduced, and variations in characteristics (e.g., oscillation threshold) are increased, and it is difficult to obtain laser oscillation.
  • Control of the resonator length is also important. The resonator length also needs to be controlled in the order of nanometers. If the resonator length deviates from the design value, sufficient gain cannot be obtained, and it becomes difficult to obtain laser oscillation.
  • Patent Document 1 proposes a method of embedding a multilayer dielectric layer that can function as a DBR layer in a semiconductor layer by using a selective growth method.
  • this method there is an alignment step for forming a light extraction portion on the multilayer dielectric layer that becomes the DBR layer. For this reason, in consideration of alignment variations, a multilayer dielectric layer larger than the light extraction portion is formed and embedded.
  • a first nitride surface-emitting laser according to an embodiment of the present technology is provided on a substrate and faces a first dielectric multilayer film and a second dielectric multilayer film that are adjacent to each other, and the first dielectric multilayer film.
  • a current injection region provided at a position, and an opening provided between the first dielectric multilayer film and the second dielectric multilayer film.
  • the first dielectric multilayer film, the opening And the current injection region has an angle ⁇ between the line segment connecting the edge of the upper surface of the first dielectric multilayer film and the edge of the current injection region with the shortest distance and the upper surface of the first dielectric multilayer film, It is formed to be arctan (H / W) or more and 90 ° or less.
  • the angle ⁇ formed with the upper surface of the multilayer film was set to arctan (H / W) or more and 90 ° or less.
  • a second nitride surface emitting laser is provided on a substrate and faces a first dielectric multilayer film and a second dielectric multilayer film that are adjacent to each other, and the first dielectric multilayer film.
  • a current injection region provided at a position, and an opening provided between the first dielectric multilayer film and the second dielectric multilayer film.
  • the distance between the first dielectric multilayer film and the second dielectric multilayer film is W
  • the opening is from the intersection of the perpendicular drawn from the outer edge of the upper surface of the first dielectric multilayer film and the bottom of the first dielectric multilayer film
  • the thickness of the first dielectric multilayer film in the normal direction relative to the substrate is H
  • the first dielectric multilayer film, the opening and the current injection region are the upper surface of the first dielectric multilayer film.
  • An angle ⁇ formed by a line segment connecting the edge of each of the current injection regions with the edge of the current injection region and the upper surface of the first dielectric multilayer film is arctan (H / (W + W ′)) or more and 90 ° or less. It is formed to become.
  • the angle ⁇ formed with the upper surface of the multilayer film was set to arctan (H / (W + W ′)) or more and 90 ° or less.
  • the first dielectric semiconductor film, the opening, and the current injection region are formed in the first nitride semiconductor laser.
  • the angle ⁇ is not less than arctan (H / (W + W ′)) and not more than 90 ° so that the angle ⁇ is not less than arctan (H / W) and not more than 90 °. Therefore, it is possible to irradiate the current injection region and the vicinity thereof with laser light and excitation light without being blocked by the first dielectric multilayer film from the substrate side. Therefore, the reliability and manufacturing yield of the nitride surface emitting laser can be improved. Note that the effects described here are not necessarily limited, and may be any effects described in the present disclosure.
  • FIG. 1 is a cross-sectional view of a surface emitting semiconductor laser according to a first embodiment of the present technology.
  • FIG. 2 is an enlarged schematic view for explaining a main part of the semiconductor laser shown in FIG. 1.
  • It is a schematic diagram showing the planar shape of the dielectric multilayer film of the semiconductor laser shown in FIG.
  • FIG. 8 is an enlarged schematic diagram for explaining a main part of the semiconductor laser shown in FIG. 7.
  • FIG. 8 is a schematic diagram showing another shape of the dielectric multilayer film of the semiconductor laser shown in FIG. 7. It is a schematic diagram for demonstrating the device characteristic test
  • FIG. 8 is a schematic diagram for explaining defect repair in the semiconductor laser shown in FIG. 7.
  • First embodiment semiconductor laser in which the dielectric multilayer film on the substrate side has a rectangular cross section
  • Overall configuration 1-2.
  • Manufacturing method 1-3.
  • Action / Effect Second Embodiment Silicon Laser with Dielectric Multilayered Film on the Substrate Side has a Forward Tapered Shape
  • Main part configuration 2-2.
  • FIG. 1 shows an example of a cross-sectional configuration of a nitride surface emitting laser (semiconductor laser 1) according to the first embodiment of the present technology.
  • the semiconductor laser 1 includes a substrate 11 and a plurality of dielectric multilayer films 41 in contact with the surface S1 of the substrate 11.
  • the plurality of dielectric multilayer films 41 are provided on the substrate 11 at intervals.
  • the semiconductor laser 1 further has a configuration in which the semiconductor layer 20, the insulating film 24, the transparent electrode 32, the second electrode 33, and the second DBR layer 42 are stacked in this order.
  • the pair of first DBR layer 41A and second DBR layer 42 function as a resonator.
  • the semiconductor layer 20 has a configuration in which a first semiconductor layer 21, an active layer 22, and a second semiconductor layer 23 are stacked in this order from the substrate 11 side.
  • Each dielectric multilayer film 41 is buried with the first semiconductor layer 21.
  • a groove-shaped opening 41H is formed between the first DBR layer 41A and the dielectric multilayer film 41 adjacent to the first DBR layer 41A. Is formed.
  • the semiconductor laser 1 has a first electrode 31 in contact with the surface S2 of the substrate 11 (the surface facing the surface S1). Note that the semiconductor laser 1 in FIG. 1 is schematically shown and is different from actual dimensions.
  • the substrate 11 is an element forming substrate used for manufacturing the semiconductor layer 20.
  • the substrate 11 is provided in contact with the semiconductor layer 20 (first semiconductor layer 21).
  • various substrates such as a GaN substrate, a sapphire substrate, a GaAs substrate, a SiC substrate, an alumina substrate, a ZnS substrate, a ZnO substrate, a LiMgO substrate, a LiGaO 2 substrate, a MgAl 2 O 4 substrate, and an InP substrate are used. it can.
  • an insulating substrate made of AlN or the like, a semiconductor substrate made of Si, SiC, Ge, or the like, a metal substrate, or an alloy substrate may be used.
  • the thickness of the substrate 11 in the stacking direction (hereinafter simply referred to as thickness) is preferably 0.05 mm to 0.5 mm, for example.
  • the semiconductor layer 20 has a configuration in which a first semiconductor layer 21, an active layer 22, and a second semiconductor layer 23 are sequentially stacked from the substrate 11 side.
  • the first semiconductor layer 21 and the second semiconductor layer 23 have different conductivity types.
  • the first semiconductor layer 21 is formed of an n-type compound semiconductor
  • the second semiconductor layer 23 is formed of a p-type compound semiconductor. Is formed.
  • the first semiconductor layer 21, the active layer 22, and the second semiconductor layer 23 are each composed of a nitride-based compound semiconductor.
  • Specific nitride compound semiconductors include GaN compound semiconductors such as GaN, AlGaN, InGaN, and AlInGaN. In addition, AlN, AlInN, and InN are mentioned.
  • the active layer 22 may contain boron (B) atoms, thallium (Tl) atoms, arsenic (As) atoms, phosphorus (P) atoms, and antimony (Sb) atoms as desired.
  • the active layer 22 preferably has a quantum well structure. Specifically, it may have a single quantum well structure (QW structure) or a multiple quantum well structure (MQW structure).
  • the active layer 22 having a quantum well structure has a structure in which at least one well layer and a barrier layer are stacked.
  • the first semiconductor layer 21 and the second semiconductor layer 23 may each be a single structure layer or a multilayer structure layer. Further, it may be a layer having a superlattice structure. Furthermore, it can also be set as the layer provided with the composition gradient layer and the density
  • a current confinement structure is formed between the semiconductor layer 20 (specifically, the second semiconductor layer 23) and the second electrode 33.
  • the current confinement structure is configured by an insulating film 24 provided on the second semiconductor layer 23, for example.
  • the insulating film 24 has an opening 24A from which the second semiconductor layer 23 is exposed, and this opening serves as a current injection region R in the semiconductor layer 20 (second semiconductor layer 23).
  • the current injection region R in the semiconductor layer 20 (second semiconductor layer 23) corresponds to the emission window 24W that emits light emitted from the active layer 22.
  • the insulating film 24 is made of, for example, SiO x , SiN x or AlO x .
  • the current confinement structure is not necessarily formed by the insulating film 24.
  • the mesa structure may be formed by etching the second semiconductor layer 23 by a reactive ion etching (RIE) method or the like, or a part of the stacked second semiconductor layers 23. May be partially oxidized from the lateral direction to form a current injection region.
  • impurities may be ion-implanted into the second semiconductor layer 23 to form a region with reduced conductivity, and these may be combined as appropriate.
  • the transparent electrode 32 is provided on the second semiconductor layer 23, and the transparent electrode 32 needs to be electrically connected to a part of the second semiconductor layer 23 through which a current flows.
  • the first electrode 31 is provided on the surface S2 opposite to the surface S1 of the substrate 11 on which the semiconductor layer 20 is formed.
  • the first electrode 31 includes, for example, gold (Au), silver (Ag), palladium (Pd), platinum (Pt), nickel (Ni), Ti (titanium), vanadium (V), tungsten (W), chromium ( It is a single layer film or a laminated film containing at least one kind of metal (including an alloy) of Cr), Al (aluminum), Cu (copper), Zn (zinc), tin (Sn), and indium (In). It is preferable.
  • a laminated film is mentioned. Note that the layer before the “/” in the multilayer structure is located closer to the active layer 22 side.
  • the transparent electrode 32 is provided on the semiconductor layer 20, specifically, on the second semiconductor layer 23.
  • the transparent electrode 32 is provided in contact with the emission window 24 ⁇ / b> W in the second semiconductor layer 23.
  • the transparent electrode 32 is formed of a so-called transparent conductive material having optical transparency.
  • transparent conductive materials include, for example, indium-tin oxide (including ITO, Indium Tin Oxide, Sn-doped In 2 O 3 , crystalline ITO, and amorphous ITO), indium-zinc oxide (IZO, Indium zinc oxide), IFO (F-doped in 2 O 3), tin oxide (SnO 2), ATO (Sb-doped SnO 2), FTO (F doped SnO 2), zinc oxide (ZnO, ZnO of Al-doped And B-doped ZnO).
  • a transparent conductive film whose base layer is gallium oxide, titanium oxide, niobium oxide, nickel oxide, or the like may be used.
  • the material which comprises the transparent electrode 32 is based on the arrangement state of the 2nd DBR layer 42 and the transparent electrode 32 mentioned later, it is not limited to a transparent conductive material, Palladium (Pd), platinum (Pt), nickel Metals such as (Ni), gold (Au), cobalt (Co), rhodium (Rh) can also be used.
  • the transparent electrode 32 may be composed of at least one of these materials.
  • the second electrode 33 is provided on the transparent electrode 32 and is used for electrical connection with an external electrode or circuit.
  • the second electrode 33 is, for example, a single layer film containing at least one metal selected from Ti (titanium), aluminum (Al), Pt (platinum), Au (gold), Ni (nickel), and Pd (palladium). Or it is preferable that it is a laminated film. Specifically, for example, a laminated film of Ti / Pt / Au, Ti / Au, Ti / Pd / Au, Ti / Pd / Au, Ti / Ni / Au, Ti / Ni / Au / Cr / Au, etc. It is done.
  • a plurality of dielectric multilayer films 41 are provided in the plane of the substrate 11 and are embedded with the first semiconductor layer 21.
  • a groove-shaped opening 41 ⁇ / b> H is provided between adjacent dielectric multilayer films 41, and the opening 41 ⁇ / b> H is embedded by the first semiconductor layer 21.
  • the dielectric multilayer film 41 includes, for example, Si, Mg, Al, Hf, Nb, Zr, Sc, Ta, Ga, Zn, Y, B, Ti, and other oxides and nitrides (for example, SiN x , AlN x , AlGaN, GaN x , BN x, etc.) or fluoride.
  • the first DBR layer 41A includes two or more kinds of dielectric films made of dielectric materials having different refractive indexes among the dielectric materials (for example, TaO x having a high refractive index and SiO x having a low refractive index). It is preferable that the layers are alternately stacked. Thereby, the light reflection effect is obtained.
  • Examples of combinations of the two types of dielectric films include SiO x / SiN x , SiO x / NbO x , SiO x / ZrO x , SiO x / AlN x in addition to SiO x / TaO x .
  • the material, the film thickness, the number of stacked layers, and the like constituting each dielectric film may be appropriately selected.
  • the dielectric multilayer film 41 is preferably arranged or arranged so as to grow laterally in the [1120] direction.
  • the side surface of the dielectric multilayer film 41 is perpendicular or substantially perpendicular to the substrate 11.
  • the opening 41H provided between the adjacent dielectric multilayer films 41 does not necessarily have a uniform width between all the adjacent dielectric multilayer films 41, but in the present embodiment, at least the first
  • the width of the groove-shaped opening 41H between the 1DBR layer 41A and the dielectric multilayer film 41 adjacent to the first DBR layer 41A is provided to satisfy the following range.
  • FIG. 2 is a diagram for explaining the main part of this embodiment (the positional relationship between the first DBR layer 41A, the opening 41H, and the current injection region R).
  • the distance (width of the opening 41H) between the first DBR layer 41A and the dielectric multilayer film 41 adjacent to the first DBR layer 41A is W, and the first DBR.
  • the first DBR layer 41A, the opening 41H, and the current injection region R include the edge of the upper surface of the first DBR layer 41A and the edge of the current injection region R. Is formed such that an angle ⁇ between a line segment LN connecting the two and the upper surface of the first DBR layer 41A is not less than arctan (H / W) and not more than 90 °.
  • the edge of the upper surface of the 1DBR layer 41A, and the point where the line segment LN contact with each other is represented by X 1
  • the edge of the current injection region R, the point where the line segment LN contact with each other It is represented by X 2.
  • the current injection region R can be confirmed from the opening 41H without being blocked by the first DBR layer 41A from the back surface (surface S2) side of the substrate 11.
  • arctan (H / W) when the width W of the opening 41H is 4.5 ⁇ m and the thickness H of the first DBR layer 41A is 2.5 ⁇ m is about 29. °. Therefore, the angle ⁇ formed by the line segment LN and the upper surface of the first DBR layer 41A may be in the range of 29 ° ⁇ ⁇ 90 °, for example, 45 °.
  • each dielectric film can be adjusted as appropriate depending on the material used, and is determined by the light emission wavelength ⁇ 0 and the refractive index n of the material used at the light emission wavelength ⁇ 0. Specifically, an odd multiple of ⁇ 0 / (4n) is preferable.
  • the thickness of each dielectric film is preferably about 40 nm to 70 nm.
  • the number of stacked layers is preferably 5 or more, and more preferably 15 or more.
  • the total thickness of the dielectric multilayer film 41 is preferably, for example, 0.6 ⁇ m to 3.0 ⁇ m.
  • the planar shape of the dielectric multilayer film 41 is, for example, a lattice (rectangular) shape (A), a polygonal shape including a regular hexagon (B), a circular shape including an ellipse (C), a stripe shape ( D) or an island shape.
  • the cross-sectional shape of the dielectric multilayer film 41 may be rectangular as shown in FIG. 3, or may be formed in a trapezoidal shape.
  • the second DBR layer 42 is provided at a position facing the first DBR layer 41 ⁇ / b> A with the semiconductor layer 20 in between, specifically, provided on the transparent electrode 32. Similar to the dielectric multilayer film 41, the second DBR layer 42 is made of an oxide or nitride such as Si, Mg, Al, Hf, Nb, Zr, Sc, Ta, Ga, Zn, Y, B, Ti (for example, SiN x , AlN x , AlGaN, GaN x , BN x, etc.) or fluoride.
  • oxide or nitride such as Si, Mg, Al, Hf, Nb, Zr, Sc, Ta, Ga, Zn, Y, B, Ti (for example, SiN x , AlN x , AlGaN, GaN x , BN x, etc.) or fluoride.
  • a high refractive index material such as SiN x or TaO x
  • a low refractive index material such as SiO x
  • high light Reflectance can be obtained.
  • the film thickness, the number of stacked layers, and the like may be appropriately selected. The thickness of each dielectric film can be adjusted as appropriate depending on the material used, and is determined by the light emission wavelength ⁇ 0 and the refractive index n of the material used at the light emission wavelength ⁇ 0. Specifically, an odd multiple of ⁇ 0 / (4n) is preferable.
  • the thickness of each dielectric film is preferably about 40 nm to 70 nm.
  • the number of stacked layers is 2 or more, preferably 2 to 15.
  • the total thickness of the dielectric multilayer film 41 is preferably, for example, 0.6 ⁇ m to 1.7 ⁇ m.
  • the semiconductor laser 1 of the present embodiment can be manufactured as follows, for example.
  • a plurality of dielectric multilayer films 41 are formed on the substrate 11. Specifically, for example, after forming a multilayer film in which, for example, five layers of SiO x films and SiN x films are alternately stacked using any film formation method such as sputtering, CVD, and vapor deposition, By selectively etching, a plurality of dielectric multilayer films 41 whose side surfaces are surrounded by groove-shaped openings 41H are formed. For the etching step, wet etching using hydrofluoric acid or the like, dry etching using an RIE apparatus, or the like can be used. Thereby, a plurality of dielectric multilayer films 41 are formed in the surface of the substrate 11.
  • the semiconductor layer 20 covering the dielectric multilayer film 41 and the insulating film 24 having the openings 24A are formed.
  • the dielectric multilayer film 41 is used as a selective growth mask, and the substrate 11 is placed in a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus and heated to a desired temperature.
  • MOCVD Metal Organic Chemical Vapor Deposition
  • TMGa trimethylgallium
  • TMAl trimethylaluminum
  • TMIn trimethylindium
  • SiH 4 silane
  • SiH 4 silane
  • NH 3 ammonia gas
  • the first semiconductor layer 21 is grown to 5 ⁇ m
  • the active layer 22 is grown to 80 nm
  • the second semiconductor layer 23 is grown to 100 nm.
  • an insulating film 24 for forming a current confinement structure is formed.
  • the SiO 2 film is formed to have a thickness of, for example, 200 nm by using any film formation method such as sputtering, CVD, and vapor deposition.
  • An insulating film 24 having an opening 24A from which 23 is exposed is formed.
  • wet etching using hydrofluoric acid or the like, dry etching using an RIE apparatus, or the like can be used.
  • the semiconductor layer 20 covering the dielectric multilayer film 41 and the insulating film 24 having the opening 24A having a current confinement structure are formed.
  • the area of the current injection region R is preferably less than or equal to half of the area of the dielectric multilayer film 41 (first DBR layer 41A) facing the current injection region R.
  • the area of the current injection region R is, for example, about 25 ⁇ m 2 .
  • the current injection region R can be formed while avoiding a defect region (singular point) of the semiconductor layer 20.
  • the transparent electrode 32, the second electrode 33, and the second DBR layer 42 are formed.
  • an ITO film is formed to a thickness of 50 nm by using any film formation method such as sputtering, CVD, and vapor deposition, and then selectively etched, thereby transparent electrode 32 having a desired shape.
  • etching process wet etching using hydrochloric acid or the like, dry etching using a reactive ion etching apparatus, or the like can be used.
  • Au, Pt, and Ti are formed in this order by using any film forming method such as sputtering, CVD, and vapor deposition, and then selectively etched to form Ti / Pt only at a desired portion.
  • the second electrode 33 is formed leaving the / Au film.
  • wet etching using acid or the like, dry etching using a reactive ion etching apparatus or the like, lift-off using the PR method, or the like can be used.
  • the second DBR layer 42 having a desired shape is formed by etching.
  • etching step wet etching using hydrofluoric acid or the like, dry etching using an RIE apparatus, or the like can be used.
  • the semiconductor laser 1 shown in FIG. 1 is completed.
  • the semiconductor laser 1 includes the plurality of dielectric multilayer films 41, the first semiconductor layer 21, the active layer 22, the second semiconductor layer 23, the transparent electrode 32, and the second DBR layer 42 on the surface S1 of the substrate 11.
  • the first electrode 31 is formed on the other surface S2 stacked in this order and facing the surface S1 of the substrate 11.
  • a current that narrows the current injection region in order to increase the current injection efficiency into the active layer 22 and reduce the threshold ground current.
  • a constriction structure opening 24A of insulating film 24
  • the current injected from the first electrode 31 and the transparent electrode 32 is narrowed by the current confinement structure and then injected into the active layer 22. Thereby, light emission by recombination of electrons and holes occurs. This light is reflected by the first DBR layer 41A and the second DBR layer 42, causes laser oscillation at a predetermined wavelength, and is emitted to the outside through the first DBR layer 41A or the second DBR layer 42.
  • Defects in this ITO film can be repaired by irradiating laser light, but in order to irradiate the defective part with laser light for repair from the back side of the substrate, a large-diameter dielectric layer is obstructed. It was easy to be. For this reason, it is difficult to improve the reliability, and the manufacturing yield is reduced.
  • is not less than arctan (H / W) and not more than 90 °.
  • FIG. 5 schematically shows a method for inspecting the device characteristics of the semiconductor laser 1.
  • FIG. 6 schematically shows a method for repairing a defect in the transparent electrode 32 provided in the semiconductor laser 1.
  • the inspection of device characteristics and the repair of defects in the electrode (transparent electrode 32) are performed by using excitation light L1 or laser light L2 from the back surface (surface S2) side of the substrate 11 and the active layer 22 or transparent electrode 32, respectively. It is done by irradiating.
  • the angle ⁇ is not less than arctan (H / W) and not more than 90 °, the laser beam L2 is supplied from the substrate 11 side without being blocked by the first DBR layer 41A.
  • the injection region R can be selectively irradiated with the excitation light L1 on the active layer 22 below the current injection region R. Therefore, device characteristics inspection (photoexcitation inspection) and defect repair of the transparent electrode 32 can be performed regardless of external factors. As a result, the reliability and manufacturing yield of the semiconductor laser 1 are improved.
  • FIG. 7 illustrates an example of a cross-sectional configuration of a nitride surface emitting laser (semiconductor laser 2) according to the second embodiment of the present technology.
  • the semiconductor laser 2 is different from the first embodiment in that the semiconductor laser 1 includes a dielectric multilayer film 51 instead of the dielectric multilayer film 41 in the semiconductor laser 1 of the first embodiment.
  • the dielectric multilayer film 51 has a laminated structure similar to that of the dielectric multilayer film 41, and the cross-sectional configuration of the dielectric multilayer film 41 is that the side surface of the dielectric multilayer film 51 is inclined in a forward tapered shape. It is different.
  • the pair of first DBR layer 51A and second DBR layer 42 function as a resonator.
  • the semiconductor layer 20 has a configuration in which a first semiconductor layer 21, an active layer 22, and a second semiconductor layer 23 are stacked in this order from the substrate 11 side.
  • Each dielectric multilayer film 51 is embedded with the first semiconductor layer 21, and a groove-shaped opening 51H is formed between the first DBR layer 51A and the dielectric multilayer film 51 adjacent to the first DBR layer 51A. Is formed.
  • the semiconductor laser 2 has a first electrode 31 in contact with the surface S2 of the substrate 11 (the surface facing the surface S1). Note that the semiconductor laser 1 in FIG. 7 is schematically shown and is different from actual dimensions.
  • a plurality of dielectric multilayer films 51 are provided in the plane of the substrate 11 and are embedded with the first semiconductor layer 21.
  • a groove-shaped opening 51H is provided between adjacent dielectric multilayer films 51, and the first semiconductor layer 21 is embedded in the opening 51H.
  • the dielectric multilayer film 51 includes, for example, Si, Mg, Al, Hf, Nb, Zr, Sc, Ta, Ga, Zn, Y, B, Ti, and other oxides and nitrides (for example, SiN x , AlN x , AlGaN, GaN x , BN x, etc.) or fluoride.
  • the first DBR layer 51A includes two or more kinds of dielectric films made of dielectric materials having different refractive indexes among the dielectric materials (for example, TaO x having a high refractive index and SiO x having a low refractive index). It is preferable that the layers are alternately stacked. Thereby, the light reflection effect is obtained.
  • the combination of two dielectric films for example, in addition to SiO x / TaO x, SiO x / SiN x, SiO x / NbO x, SiO x / ZrO x, SiO x / AlN x , and the like.
  • the material, the film thickness, the number of stacked layers, and the like constituting each dielectric film may be appropriately selected.
  • the dielectric multilayer film 51 is preferably arranged or arranged so as to grow laterally in the [1120] direction.
  • the opening 51H provided between the adjacent dielectric multilayer films 51 does not necessarily have a uniform width between all the adjacent dielectric multilayer films 51, but in the present embodiment, the first DBR is used.
  • the width of the groove-shaped opening 51H between the layer 51A and the dielectric multilayer film 51 adjacent to the first DBR layer 51A is provided so as to satisfy the following range.
  • FIG. 8 is for explaining the main part of this embodiment (the positional relationship between the first DBR layer 51A, the opening 51H and the current injection region R).
  • the distance (width of the opening 51H) between the first DBR layer 51A and the dielectric multilayer film 51 adjacent to the first DBR layer 51A is W, and the first DBR.
  • the first DBR layer 51A, the opening 51H, and the current injection region R include a line segment LN connecting the edge of the upper surface of the first DBR layer 51A and the edge of the current injection region R at the shortest distance, and the upper surface of the first DBR layer 51A. Is formed so as to be not less than arctan (H / (W + W ′)) and not more than 90 °.
  • the edge of the upper surface of the 1DBR layer 51A, and the point where the line segment LN contact with each other is represented by X 1
  • the edge of the current injection region R, the point where the line segment LN contact with each other It is represented by X 2.
  • the current injection region R can be confirmed from the opening 51H without being blocked by the first DBR layer 51A from the back surface (surface S2) side of the substrate 11.
  • Specific numerical values of the values satisfying this condition are, for example, an opening width W of 4.5 ⁇ m, a distance W ′ from the intersection of the perpendicular drawn from the upper outer peripheral portion X1 and the bottom side of the first DBR layer 51A to the opening 51H.
  • arctan (H / (W + W ′)) is about 21 ° when the thickness H of the first DBR layer 41A is 2.5 ⁇ m. Therefore, the angle ⁇ formed by the line segment LN and the upper surface of the first DBR layer 51A may be in a range of 21 ° ⁇ ⁇ ⁇ 90 °, and is about 30 °, for example.
  • the cross-sectional shape of the dielectric multilayer film 51 is a part of the upper corner of the dielectric multilayer film 51 (for example, the dielectric multilayer film 51, for example, as shown in FIG. 9A). It is good also as a shape where a part of side surfaces S1 and S2) was shaved from the upper surface. Further, the cross-sectional shape of the dielectric multilayer film 51 does not necessarily have to be symmetric, and even if the upper corner of only one side surface (here, the side surface S1) is cut as shown in FIG. 9B. Good. Furthermore, it is not necessary that all of the plurality of dielectric multilayer films 51 provided on the substrate 11 have the same shape, and only the dielectric multilayer film 51 that becomes the first DBR layer 51A is processed into the above shape. Good.
  • an angle ⁇ formed by a line segment LN connecting the edge of the upper surface of the first DBR layer 51A and the edge of the current injection region R with the shortest distance and the upper surface of the first DBR layer 51A is arctan ( H / (W + W ′)) to 90 °.
  • FIG. 10 schematically shows a method for inspecting the device characteristics of the semiconductor laser 2.
  • FIG. 11 schematically shows a method for repairing a defect in the transparent electrode 32 provided in the semiconductor laser 2.
  • the inspection of device characteristics and the repair of defects in the electrode (transparent electrode 32) are performed by using excitation light L1 or laser light L2 from the back surface (surface S2) side of the substrate 11 and the active layer 22 or transparent electrode 32, respectively. It is done by irradiating.
  • the laser beam L2 can be selectively irradiated to the current injection region R and the excitation light L1 can be selectively irradiated to the active layer 22 below the current injection region R without being blocked by the first DBR layer 51A from the substrate 11. Therefore, device characteristics inspection (photoexcitation inspection) and defect repair of the transparent electrode 32 can be performed regardless of external factors. As a result, the reliability and manufacturing yield of the semiconductor laser 2 are improved.
  • this technique can also take the following structures.
  • a current injection region provided at a position facing the first dielectric multilayer film;
  • An opening provided between the first dielectric multilayer film and the second dielectric multilayer film;
  • the first dielectric multilayer film, the opening, and the current injection region include a line segment that connects an edge of the upper surface of the first dielectric multilayer film and an edge of the current injection region with the shortest distance;
  • the nitride surface emitting laser according to (1) wherein a side surface of the first dielectric multilayer film is perpendicular to the substrate.
  • the first dielectric multilayer film, the opening, and the current injection region include a line segment that connects the edge of the upper surface of the first dielectric multilayer film and the edge of the current injection region with the shortest distance; 1.
  • Body multilayer film The nitride surface emitting laser according to any one of (6) to (8), wherein the first dielectric multilayer film is a first light reflecting layer.

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Abstract

A first nitride surface-emitting laser comprising: a first dielectric multilayer film and a second dielectric multilayer film that are provided upon a substrate and are adjacent to each other; a current injection region provided at a position facing the first dielectric multilayer film; and an opening provided between the first dielectric multilayer film and the second dielectric multilayer film. When the distance between the first dielectric multilayer film and the second dielectric multilayer film is W and the thickness of the first dielectric multilayer film in the normal direction relative to the substrate is H, the first dielectric multilayer film, the opening, and the current injection region are formed such that an angle θ is at least arctan (H/W) and no more than 90°, said angle θ being between the upper surface of the first dielectric multilayer film and a line connecting, by the shortest distance, an end edge of the upper surface of the first dielectric multilayer film and an end edge of the current injection region.

Description

窒化物面発光レーザNitride surface emitting laser
 本技術は、例えば、積層方向にレーザ光を射出する窒化物面発光レーザに関する。 The present technology relates to, for example, a nitride surface emitting laser that emits laser light in the stacking direction.
 面発光レーザには、一般に、活性層を含む半導体層の上下に光反射層(Distributed Bragg Reflector層;DBR層)が設けられている。面発光レーザは、この2つのDBR層の間で光を共振させることによりレーザ発振が生じる。このため、DBR層を形成する半導体表面をサブ・ナノメートルオーダーで平滑にする必要がある。適切な平滑度が得られないと各DBR層の光反射率が低下し、特性(発振閾値等)のバラツキが大きくなり、しいては、レーザ発振を得ることすら困難となる。また、共振器長の制御も重要である。共振器長もナノメートルオーダーで制御する必要があり、設計値から乖離すると十分な利得を得ることが儘ならず、レーザ発振を得ることが困難となる。 A surface emitting laser is generally provided with light reflecting layers (Distributed Bragg Reflector layers; DBR layers) above and below a semiconductor layer including an active layer. In the surface emitting laser, laser oscillation occurs by resonating light between the two DBR layers. For this reason, it is necessary to smooth the semiconductor surface on which the DBR layer is formed on the sub-nanometer order. If an appropriate smoothness cannot be obtained, the light reflectivity of each DBR layer is reduced, and variations in characteristics (e.g., oscillation threshold) are increased, and it is difficult to obtain laser oscillation. Control of the resonator length is also important. The resonator length also needs to be controlled in the order of nanometers. If the resonator length deviates from the design value, sufficient gain cannot be obtained, and it becomes difficult to obtain laser oscillation.
 この問題に対し、例えば、特許文献1では、選択成長法を用いてDBR層として機能しうる多層膜誘電体層を半導体層に埋め込む方法が提案されている。この方法ではDBR層となる多層膜誘電体層の上に、光取り出し部を形成するためのアライメント工程がある。このため、アライメントのバラつきを考慮して光取り出し部よりも大きな多層膜誘電体層が形成され、埋め込まれていた。 For this problem, for example, Patent Document 1 proposes a method of embedding a multilayer dielectric layer that can function as a DBR layer in a semiconductor layer by using a selective growth method. In this method, there is an alignment step for forming a light extraction portion on the multilayer dielectric layer that becomes the DBR layer. For this reason, in consideration of alignment variations, a multilayer dielectric layer larger than the light extraction portion is formed and embedded.
特開平10-308558号公報JP-A-10-308558
 しかしながら、大口径の多層膜誘電体層を埋め込んだ場合には、デバイス特性の検査および電極中の欠陥の修復等が困難になる。このため、信頼性を向上させることが難しく、また、製造歩留まりが低下するという問題があった。 However, when a large-diameter multilayer dielectric layer is embedded, it becomes difficult to inspect device characteristics and repair defects in the electrodes. For this reason, it is difficult to improve the reliability, and the manufacturing yield is reduced.
  従って、信頼性および製造歩留まりを向上させることが可能な窒化物面発光レーザを提供することが望ましい。 Therefore, it is desirable to provide a nitride surface emitting laser capable of improving reliability and manufacturing yield.
 本技術の一実施形態の第1の窒化物面発光レーザは、基板上に設けられ、互いに隣り合う第1誘電体多層膜および第2誘電体多層膜と、第1誘電体多層膜と対向する位置に設けられた電流注入領域と、第1誘電体多層膜と第2誘電体多層膜との間に設けられた開口部とを備えている。第1誘電体多層膜と第2誘電体多層膜との間の距離をW、第1誘電体多層膜の基板に対する法線方向の厚みをHとするとき、第1誘電体多層膜、開口部および電流注入領域は、第1誘電体多層膜の上面の端縁と、電流注入領域の端縁とを最短距離で結ぶ線分と、第1誘電体多層膜の上面とのなす角θが、arctan(H/W)以上90°以下となるように形成されている。 A first nitride surface-emitting laser according to an embodiment of the present technology is provided on a substrate and faces a first dielectric multilayer film and a second dielectric multilayer film that are adjacent to each other, and the first dielectric multilayer film. A current injection region provided at a position, and an opening provided between the first dielectric multilayer film and the second dielectric multilayer film. When the distance between the first dielectric multilayer film and the second dielectric multilayer film is W and the thickness of the first dielectric multilayer film in the normal direction to the substrate is H, the first dielectric multilayer film, the opening And the current injection region has an angle θ between the line segment connecting the edge of the upper surface of the first dielectric multilayer film and the edge of the current injection region with the shortest distance and the upper surface of the first dielectric multilayer film, It is formed to be arctan (H / W) or more and 90 ° or less.
 本技術の一実施形態の第1の窒化物面発光レーザでは、第1誘電体多層膜の上面の端縁と、電流注入領域の端縁とを最短距離で結ぶ線分と、第1誘電体多層膜の上面とのなす角θが、arctan(H/W)以上90°以下となるようにした。これにより、基板側から第1誘電体多層膜に遮られることなく、電流注入領域およびその近傍へのレーザ光や励起光の照射が可能となる。 In a first nitride surface emitting laser according to an embodiment of the present technology, a line segment connecting the edge of the upper surface of the first dielectric multilayer film and the edge of the current injection region with the shortest distance, and the first dielectric The angle θ formed with the upper surface of the multilayer film was set to arctan (H / W) or more and 90 ° or less. Thereby, it is possible to irradiate the current injection region and the vicinity thereof with laser light and excitation light without being blocked by the first dielectric multilayer film from the substrate side.
 本技術の一実施形態の第2の窒化物面発光レーザは、基板上に設けられ、互いに隣り合う第1誘電体多層膜および第2誘電体多層膜と、第1誘電体多層膜と対向する位置に設けられた電流注入領域と、第1誘電体多層膜と第2誘電体多層膜との間に設けられた開口部とを備えている。第1誘電体多層膜と第2誘電体多層膜との間の距離をW、第1誘電体多層膜の上面の外縁から引いた垂線と第1誘電体多層膜の底辺との交点から開口部までの距離をW’、第1誘電体多層膜の基板に対する法線方向の厚みをHとするとき、第1誘電体多層膜、開口部および電流注入領域は、第1誘電体多層膜の上面の端縁と、電流注入領域の端縁とを最短距離で結ぶ線分と、第1誘電体多層膜の上面とのなす角θが、arctan(H/(W+W’))以上90°以下となるように形成されている。 A second nitride surface emitting laser according to an embodiment of the present technology is provided on a substrate and faces a first dielectric multilayer film and a second dielectric multilayer film that are adjacent to each other, and the first dielectric multilayer film. A current injection region provided at a position, and an opening provided between the first dielectric multilayer film and the second dielectric multilayer film. The distance between the first dielectric multilayer film and the second dielectric multilayer film is W, the opening is from the intersection of the perpendicular drawn from the outer edge of the upper surface of the first dielectric multilayer film and the bottom of the first dielectric multilayer film And the thickness of the first dielectric multilayer film in the normal direction relative to the substrate is H, the first dielectric multilayer film, the opening and the current injection region are the upper surface of the first dielectric multilayer film. An angle θ formed by a line segment connecting the edge of each of the current injection regions with the edge of the current injection region and the upper surface of the first dielectric multilayer film is arctan (H / (W + W ′)) or more and 90 ° or less. It is formed to become.
 本技術の一実施形態の第2の窒化物面発光レーザでは、第1誘電体多層膜の上面の端縁と、電流注入領域の端縁とを最短距離で結ぶ線分と、第1誘電体多層膜の上面とのなす角θが、arctan(H/(W+W’))以上90°以下となるようにした。これにより、基板側から第1誘電体多層膜に遮られることなく、電流注入領域およびその近傍へのレーザ光や励起光の照射が可能となる。 In the second nitride surface emitting laser according to an embodiment of the present technology, a line segment connecting the edge of the upper surface of the first dielectric multilayer film and the edge of the current injection region with the shortest distance, and the first dielectric The angle θ formed with the upper surface of the multilayer film was set to arctan (H / (W + W ′)) or more and 90 ° or less. Thereby, it is possible to irradiate the current injection region and the vicinity thereof with laser light and excitation light without being blocked by the first dielectric multilayer film from the substrate side.
 本技術の一実施形態の第1および一実施形態の第2の窒化物面発光レーザによれば、第1誘電体多層膜、開口部および電流注入領域を、第1の窒化物半導体レーザでは、角θが、arctan(H/W)以上90°以下となるように、第2の窒化物面発光レーザでは、角θが、arctan(H/(W+W’))以上90°以下となるようにしたので、基板側から第1誘電体多層膜に遮られることなく、電流注入領域およびその近傍へのレーザ光や励起光の照射が可能となる。よって、窒化物面発光レーザの信頼性および製造歩留まりを向上させることが可能となる。なお、ここに記載された効果は必ずしも限定されるものではなく、本開示中に記載されたいずれの効果であってもよい。 According to the first nitride surface emitting laser of the first embodiment of the present technology and the second nitride surface emitting laser of the embodiment, the first dielectric semiconductor film, the opening, and the current injection region are formed in the first nitride semiconductor laser. In the second nitride surface emitting laser, the angle θ is not less than arctan (H / (W + W ′)) and not more than 90 ° so that the angle θ is not less than arctan (H / W) and not more than 90 °. Therefore, it is possible to irradiate the current injection region and the vicinity thereof with laser light and excitation light without being blocked by the first dielectric multilayer film from the substrate side. Therefore, the reliability and manufacturing yield of the nitride surface emitting laser can be improved. Note that the effects described here are not necessarily limited, and may be any effects described in the present disclosure.
本技術の第1の実施の形態に係る面発光型の半導体レーザの断面図である。1 is a cross-sectional view of a surface emitting semiconductor laser according to a first embodiment of the present technology. 図1に示した半導体レーザの要部を説明するための拡大模式図である。FIG. 2 is an enlarged schematic view for explaining a main part of the semiconductor laser shown in FIG. 1. 図1に示した半導体レーザの誘電体多層膜の平面形状を表す模式図である。It is a schematic diagram showing the planar shape of the dielectric multilayer film of the semiconductor laser shown in FIG. 図1に示した半導体レーザの製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor laser shown in FIG. 図4Aに続く工程について説明するための断面図である。It is sectional drawing for demonstrating the process following FIG. 4A. 図4Bに続く工程について説明するための断面図である。It is sectional drawing for demonstrating the process following FIG. 4B. 図1に示した半導体レーザにおけるデバイス特性検査を説明するための模式図である。It is a schematic diagram for demonstrating the device characteristic test | inspection in the semiconductor laser shown in FIG. 図1に示した半導体レーザにおける欠陥修復を説明するための模式図である。It is a schematic diagram for demonstrating the defect repair in the semiconductor laser shown in FIG. 本技術の第2の実施の形態に係る面発光型の半導体レーザの断面図である。It is sectional drawing of the surface emitting semiconductor laser which concerns on the 2nd Embodiment of this technique. 図7に示した半導体レーザの要部を説明するための拡大模式図である。FIG. 8 is an enlarged schematic diagram for explaining a main part of the semiconductor laser shown in FIG. 7. 図7に示した半導体レーザの誘電体多層膜の他の形状を表す模式図である。FIG. 8 is a schematic diagram showing another shape of the dielectric multilayer film of the semiconductor laser shown in FIG. 7. 図7に示した半導体レーザにおけるデバイス特性検査を説明するための模式図である。It is a schematic diagram for demonstrating the device characteristic test | inspection in the semiconductor laser shown in FIG. 図7に示した半導体レーザにおける欠陥修復を説明するための模式図である。FIG. 8 is a schematic diagram for explaining defect repair in the semiconductor laser shown in FIG. 7.
 以下、本技術における一実施形態について、図面を参照して詳細に説明する。なお、説明は以下の順序で行う。
1.第1の実施の形態(基板側の誘電体多層膜の断面が矩形状である半導体レーザ)
 1-1.全体構成
 1-2.製造方法
 1-3.作用・効果
2.第2の実施の形態(基板側の誘電体多層膜の断面が順テーパ形状を有する半導体レーザ)
 2-1.要部構成
 2-2.作用・効果
Hereinafter, an embodiment of the present technology will be described in detail with reference to the drawings. The description will be given in the following order.
1. First embodiment (semiconductor laser in which the dielectric multilayer film on the substrate side has a rectangular cross section)
1-1. Overall configuration 1-2. Manufacturing method 1-3. Action / Effect Second Embodiment (Semiconductor Laser with Dielectric Multilayered Film on the Substrate Side has a Forward Tapered Shape)
2-1. Main part configuration 2-2. Action / Effect
<1.第1の実施の形態>
 図1は、本技術の第1の実施の形態に係る窒化物面発光レーザ(半導体レーザ1)の断面構成の一例を表したものである。半導体レーザ1は、基板11と、基板11の面S1に接する複数の誘電体多層膜41とを有する。複数の誘電体多層膜41は間隔をあけて基板11上に設けられている。半導体レーザ1は、さらに、半導体層20、絶縁膜24、透明電極32、第2電極33および第2DBR層42がこの順に積層された構成を有する。複数の誘電体多層膜41のうち、第2DBR層42と対向する誘電体多層膜41を第1DBR層41Aとすると、一組の第1DBR層41Aおよび第2DBR層42が、共振器として機能する。半導体層20は、第1半導体層21、活性層22、第2半導体層23が基板11側からこの順に積層され積層された構成を有する。各誘電体多層膜41は、第1半導体層21によって埋め込まれており、第1DBR層41Aと、第1DBR層41Aと隣り合う誘電体多層膜41との間には、溝状の開口部41Hが形成されている。第1DBR層41Aの上面の端縁と、電流注入領域Rの端縁とを最短距離で結ぶ線分と、第1DBR層41Aの上面とのなす角が、所定の範囲内となっている。半導体レーザ1は、基板11の面S2(面S1と対向する面)に接する第1電極31を有する。なお、図1の半導体レーザ1は模式的に表したものであり、実際の寸法とは異なっている。
<1. First Embodiment>
FIG. 1 shows an example of a cross-sectional configuration of a nitride surface emitting laser (semiconductor laser 1) according to the first embodiment of the present technology. The semiconductor laser 1 includes a substrate 11 and a plurality of dielectric multilayer films 41 in contact with the surface S1 of the substrate 11. The plurality of dielectric multilayer films 41 are provided on the substrate 11 at intervals. The semiconductor laser 1 further has a configuration in which the semiconductor layer 20, the insulating film 24, the transparent electrode 32, the second electrode 33, and the second DBR layer 42 are stacked in this order. If the dielectric multilayer film 41 facing the second DBR layer 42 among the plurality of dielectric multilayer films 41 is the first DBR layer 41A, the pair of first DBR layer 41A and second DBR layer 42 function as a resonator. The semiconductor layer 20 has a configuration in which a first semiconductor layer 21, an active layer 22, and a second semiconductor layer 23 are stacked in this order from the substrate 11 side. Each dielectric multilayer film 41 is buried with the first semiconductor layer 21. Between the first DBR layer 41A and the dielectric multilayer film 41 adjacent to the first DBR layer 41A, a groove-shaped opening 41H is formed. Is formed. An angle between a line segment connecting the edge of the upper surface of the first DBR layer 41A and the edge of the current injection region R with the shortest distance and the upper surface of the first DBR layer 41A is within a predetermined range. The semiconductor laser 1 has a first electrode 31 in contact with the surface S2 of the substrate 11 (the surface facing the surface S1). Note that the semiconductor laser 1 in FIG. 1 is schematically shown and is different from actual dimensions.
(1-1.全体構成)
 基板11は、半導体層20の製造に用いられた素子形成基板である。基板11は、半導体層20(第1半導体層21)に接して設けられている。基板11は、例えば、GaN基板、サファイア基板、GaAs基板、SiC基板、アルミナ基板、ZnS基板、ZnO基板、LiMgO基板、LiGaO2基板、MgAl24基板、InP基板といった各種の基板を用いることができる。この他、AlN等からなる絶縁性基板、Si、SiC、Ge等からなる半導体基板、金属製基板や合金製基板を用いてもよい。基板11の積層方向の厚み(以下、単に厚みという)、例えば、0.05mm~0.5mmであることが好ましい。
(1-1. Overall configuration)
The substrate 11 is an element forming substrate used for manufacturing the semiconductor layer 20. The substrate 11 is provided in contact with the semiconductor layer 20 (first semiconductor layer 21). As the substrate 11, for example, various substrates such as a GaN substrate, a sapphire substrate, a GaAs substrate, a SiC substrate, an alumina substrate, a ZnS substrate, a ZnO substrate, a LiMgO substrate, a LiGaO 2 substrate, a MgAl 2 O 4 substrate, and an InP substrate are used. it can. In addition, an insulating substrate made of AlN or the like, a semiconductor substrate made of Si, SiC, Ge, or the like, a metal substrate, or an alloy substrate may be used. The thickness of the substrate 11 in the stacking direction (hereinafter simply referred to as thickness) is preferably 0.05 mm to 0.5 mm, for example.
 半導体層20は、第1半導体層21、活性層22および第2半導体層23が基板11側から順に積層された構成を有する。第1半導体層21および第2半導体層23は、互いに異なる導電型を有し、例えば、第1半導体層21はn型の化合物半導体から形成され、第2半導体層23はp型の化合物半導体から形成されている。第1半導体層21、活性層22および第2半導体層23は、それぞれ、窒化物系化合物半導体によって構成されている。具体的な窒化物系化合物半導体としては、GaN系化合物半導体、例えばGaN、AlGaN、InGaN、AlInGaNが挙げられる。この他、AlN、AlInNおよびInNが挙げられる。更に、これらの化合物半導体には、所望に応じて、ホウ素(B)原子やタリウム(Tl)原子、ヒ素(As)原子、リン(P)原子、アンチモン(Sb)原子が含まれていてもよい。活性層22は、量子井戸構造を有することが望ましい。具体的には、単一量子井戸構造(QW構造)を有していてもよいし、多重量子井戸構造(MQW構造)を有していてもよい。量子井戸構造を有する活性層22は、井戸層及び障壁層が、少なくとも1層、積層された構造を有するが、(井戸層を構成する化合物半導体,障壁層を構成する化合物半導体)の組合せとして、(InyGa(1-y)N,GaN)、(InyGa(1-y)N,InzGa(1-z)N)[但し、y>z]、(InyGa(1-y)N,AlGaN)、(AlGaN/GaN)、(AlzGa1-zN/AlyGa1-yN)[但し、y>z]が
挙げられる。
The semiconductor layer 20 has a configuration in which a first semiconductor layer 21, an active layer 22, and a second semiconductor layer 23 are sequentially stacked from the substrate 11 side. The first semiconductor layer 21 and the second semiconductor layer 23 have different conductivity types. For example, the first semiconductor layer 21 is formed of an n-type compound semiconductor, and the second semiconductor layer 23 is formed of a p-type compound semiconductor. Is formed. The first semiconductor layer 21, the active layer 22, and the second semiconductor layer 23 are each composed of a nitride-based compound semiconductor. Specific nitride compound semiconductors include GaN compound semiconductors such as GaN, AlGaN, InGaN, and AlInGaN. In addition, AlN, AlInN, and InN are mentioned. Furthermore, these compound semiconductors may contain boron (B) atoms, thallium (Tl) atoms, arsenic (As) atoms, phosphorus (P) atoms, and antimony (Sb) atoms as desired. . The active layer 22 preferably has a quantum well structure. Specifically, it may have a single quantum well structure (QW structure) or a multiple quantum well structure (MQW structure). The active layer 22 having a quantum well structure has a structure in which at least one well layer and a barrier layer are stacked. As a combination of (a compound semiconductor constituting a well layer and a compound semiconductor constituting a barrier layer), (In y Ga (1-y) N, GaN), (In y Ga (1-y) N, In z Ga (1-z) N) [where y> z], (In y Ga (1- y) N, AlGaN), (AlGaN / GaN), (AlzGa1 - zN / AlyGa1 -yN ) [where y> z].
 なお、第1半導体層21および第2半導体層23は、それぞれ単一構造の層であってもよいし、多層構造の層であってもよい。また、超格子構造の層であってもよい。更に、組成傾斜層、濃度傾斜層を備えた層とすることもできる。 The first semiconductor layer 21 and the second semiconductor layer 23 may each be a single structure layer or a multilayer structure layer. Further, it may be a layer having a superlattice structure. Furthermore, it can also be set as the layer provided with the composition gradient layer and the density | concentration gradient layer.
 半導体層20(具体的には、第2半導体層23)と第2電極33との間には、電流狭窄構造が形成されている。電流狭窄構造は、例えば、第2半導体層23上に設けられた絶縁膜24によって構成される。絶縁膜24は、第2半導体層23が露出する開口24Aを有し、この開口が半導体層20(第2半導体層23)における電流注入領域Rとなる。このとき、半導体層20(第2半導体層23)における電流注入領域Rが、活性層22から発せられた光を射出する射出窓24Wと対応している。絶縁膜24は、例えば、SiOx,SiNxあるいはAlOxによって形成されている。 A current confinement structure is formed between the semiconductor layer 20 (specifically, the second semiconductor layer 23) and the second electrode 33. The current confinement structure is configured by an insulating film 24 provided on the second semiconductor layer 23, for example. The insulating film 24 has an opening 24A from which the second semiconductor layer 23 is exposed, and this opening serves as a current injection region R in the semiconductor layer 20 (second semiconductor layer 23). At this time, the current injection region R in the semiconductor layer 20 (second semiconductor layer 23) corresponds to the emission window 24W that emits light emitted from the active layer 22. The insulating film 24 is made of, for example, SiO x , SiN x or AlO x .
 なお、電流狭窄構造は、必ずしも絶縁膜24によって形成されている必要はない。例えば、第2半導体層23を反応性イオンエッチング(Reactive Ion Etching;RIE)法等によりエッチングしてメサ構造を形成してもよいし、あるいは、積層された第2半導体層23の一部の層を横方向から部分的に酸化して電流注入領域を形成してもよい。更に、第2半導体層23に不純物をイオン注入して導電性が低下した領域を形成してもよいし、更にまた、これらを、適宜、組み合わせてもよい。但し、第2半導体層23上には、透明電極32が設けられており、この透明電極32は、電流が流れる第2半導体層23の一部と電気的に接続されている必要がある。 Note that the current confinement structure is not necessarily formed by the insulating film 24. For example, the mesa structure may be formed by etching the second semiconductor layer 23 by a reactive ion etching (RIE) method or the like, or a part of the stacked second semiconductor layers 23. May be partially oxidized from the lateral direction to form a current injection region. Furthermore, impurities may be ion-implanted into the second semiconductor layer 23 to form a region with reduced conductivity, and these may be combined as appropriate. However, the transparent electrode 32 is provided on the second semiconductor layer 23, and the transparent electrode 32 needs to be electrically connected to a part of the second semiconductor layer 23 through which a current flows.
 第1電極31は、半導体層20が形成された基板11の面S1とは反対側の面S2に設けられている。第1電極31は、例えば、金(Au)、銀(Ag)、パラジウム(Pd)、白金(Pt)、ニッケル(Ni)、Ti(チタン)、バナジウム(V)、タングステン(W)、クロム(Cr)、Al(アルミニウム)、Cu(銅)、Zn(亜鉛)、錫(Sn)およびインジウム(In)のうちの少なくとも1種類の金属(合金を含む)を含む単層膜または積層膜であることが好ましい。具体的には、例えば、Ti/Au、Ti/Al、Ti/Al/Au、Ti/Pt/Au、Ni/Au、Ni/Au/Pt、Ni/Pt、Pd/Pt、Ag/Pd等の積層膜が挙げられる。なお、多層膜構造における「/」の前の層ほど、より活性層22側に位置する。 The first electrode 31 is provided on the surface S2 opposite to the surface S1 of the substrate 11 on which the semiconductor layer 20 is formed. The first electrode 31 includes, for example, gold (Au), silver (Ag), palladium (Pd), platinum (Pt), nickel (Ni), Ti (titanium), vanadium (V), tungsten (W), chromium ( It is a single layer film or a laminated film containing at least one kind of metal (including an alloy) of Cr), Al (aluminum), Cu (copper), Zn (zinc), tin (Sn), and indium (In). It is preferable. Specifically, for example, Ti / Au, Ti / Al, Ti / Al / Au, Ti / Pt / Au, Ni / Au, Ni / Au / Pt, Ni / Pt, Pd / Pt, Ag / Pd, etc. A laminated film is mentioned. Note that the layer before the “/” in the multilayer structure is located closer to the active layer 22 side.
 透明電極32は、半導体層20上、具体的には、第2半導体層23上に設けられている。透明電極32は、第2半導体層23のうち、上記の射出窓24Wに接して設けられている。透明電極32は、光透過性を有するいわゆる透明導電性材料によって形成されている。具体的な透明導電性材料としては、例えば、インジウム-錫酸化物(ITO,Indium Tin Oxide,SnドープのIn23、結晶性ITOおよびアモルファスITOを含む)、インジウム-亜鉛酸化物(IZO,Indium Zinc Oxide)、IFO(FドープのIn23)、酸化錫(SnO2)、ATO(SbドープのSnO2)、FTO(FドープのSnO2)、酸化亜鉛(ZnO、AlドープのZnOやBドープのZnOを含む)が挙げられる。この他、ガリウム酸化物、チタン酸化物、ニオブ酸化物、ニッケル酸化物等を母層とする透明導電膜を用いてもよい。但し、透明電極32を構成する材料は、後述する第2DBR層42と透明電極32との配置状態によるが、透明導電性材料に限定するものではなく、パラジウム(Pd)、白金(Pt)、ニッケル(Ni)、金(Au)、コバルト(Co)、ロジウム(Rh)等の金属を用いることもできる。透明電極32は、これらの材料の少なくとも1種類から構成すればよい。 The transparent electrode 32 is provided on the semiconductor layer 20, specifically, on the second semiconductor layer 23. The transparent electrode 32 is provided in contact with the emission window 24 </ b> W in the second semiconductor layer 23. The transparent electrode 32 is formed of a so-called transparent conductive material having optical transparency. Specific transparent conductive materials include, for example, indium-tin oxide (including ITO, Indium Tin Oxide, Sn-doped In 2 O 3 , crystalline ITO, and amorphous ITO), indium-zinc oxide (IZO, Indium zinc oxide), IFO (F-doped in 2 O 3), tin oxide (SnO 2), ATO (Sb-doped SnO 2), FTO (F doped SnO 2), zinc oxide (ZnO, ZnO of Al-doped And B-doped ZnO). In addition, a transparent conductive film whose base layer is gallium oxide, titanium oxide, niobium oxide, nickel oxide, or the like may be used. However, although the material which comprises the transparent electrode 32 is based on the arrangement state of the 2nd DBR layer 42 and the transparent electrode 32 mentioned later, it is not limited to a transparent conductive material, Palladium (Pd), platinum (Pt), nickel Metals such as (Ni), gold (Au), cobalt (Co), rhodium (Rh) can also be used. The transparent electrode 32 may be composed of at least one of these materials.
 第2電極33は、透明電極32上に設けられたものであり、外部の電極あるいは回路と電気的に接続するためのものである。第2電極33は、例えば、Ti(チタン)、アルミニウム(Al)、Pt(白金)、Au(金)、Ni(ニッケル)、Pd(パラジウム)のうちの少なくとも1種類の金属を含む単層膜または積層膜であることが好ましい。具体的には、例えば、Ti/Pt/Au、Ti/Au、Ti/Pd/Au、Ti/Pd/Au、Ti/Ni/Au、Ti/Ni/Au/Cr/Au等の積層膜が挙げられる。 The second electrode 33 is provided on the transparent electrode 32 and is used for electrical connection with an external electrode or circuit. The second electrode 33 is, for example, a single layer film containing at least one metal selected from Ti (titanium), aluminum (Al), Pt (platinum), Au (gold), Ni (nickel), and Pd (palladium). Or it is preferable that it is a laminated film. Specifically, for example, a laminated film of Ti / Pt / Au, Ti / Au, Ti / Pd / Au, Ti / Pd / Au, Ti / Ni / Au, Ti / Ni / Au / Cr / Au, etc. It is done.
 誘電体多層膜41は、基板11の面内に複数設けられており、第1半導体層21によって埋め込まれている。隣り合う誘電体多層膜41の間には溝状の開口部41Hが設けられており、開口部41Hは、第1半導体層21によって埋設されている。誘電体多層膜41は、例えば、Si、Mg、Al、Hf、Nb、Zr、Sc、Ta、Ga、Zn、Y、B、Ti等の酸化物、窒化物(例えば、SiNx、AlNx、AlGaN、GaNx、BNx等)あるいはフッ化物等によって形成されている。具体的には、SiOx、TiOx、NbOx、ZrOx、TaOx、ZnOx、AlOx、HfOx、SiNx、AlNx等が挙げられる。第1DBR層41Aは、上記誘電体材料のうち、屈折率が異なる誘電体材料から成る2種類以上の誘電体膜(例えば、高い屈折率を有するTaOxと、低い屈折率を有するSiOxと)が交互に積層された構成となっていることが好ましい。これにより、光反射効果が得られる。2種類の誘電体膜の組み合わせとしては、例えば、SiOx/TaOxのほか、SiOx/SiNx、SiOx/NbOx、SiOx/ZrOx、SiOx/AlNx等が挙げられる。所望の光反射率を得るために、各誘電体膜を構成する材料、膜厚および積層数等を、適宜選択すればよい。誘電体多層膜41は、例えば、[1120]方向に横方向成長するように配置または配列させることが好ましい。 A plurality of dielectric multilayer films 41 are provided in the plane of the substrate 11 and are embedded with the first semiconductor layer 21. A groove-shaped opening 41 </ b> H is provided between adjacent dielectric multilayer films 41, and the opening 41 </ b> H is embedded by the first semiconductor layer 21. The dielectric multilayer film 41 includes, for example, Si, Mg, Al, Hf, Nb, Zr, Sc, Ta, Ga, Zn, Y, B, Ti, and other oxides and nitrides (for example, SiN x , AlN x , AlGaN, GaN x , BN x, etc.) or fluoride. Specifically, SiO x, TiO x, NbO x, ZrO x, TaO x, ZnO x, AlO x, HfO x, SiN x, AlN x , and the like. The first DBR layer 41A includes two or more kinds of dielectric films made of dielectric materials having different refractive indexes among the dielectric materials (for example, TaO x having a high refractive index and SiO x having a low refractive index). It is preferable that the layers are alternately stacked. Thereby, the light reflection effect is obtained. Examples of combinations of the two types of dielectric films include SiO x / SiN x , SiO x / NbO x , SiO x / ZrO x , SiO x / AlN x in addition to SiO x / TaO x . In order to obtain a desired light reflectance, the material, the film thickness, the number of stacked layers, and the like constituting each dielectric film may be appropriately selected. For example, the dielectric multilayer film 41 is preferably arranged or arranged so as to grow laterally in the [1120] direction.
 誘電体多層膜41の側面は、基板11に対して垂直、または概ね垂直となっている。隣り合う誘電体多層膜41の間に設けられている開口部41Hは、必ずしも隣り合う全ての誘電体多層膜41の間で均一な幅である必要はないが、本実施の形態では、少なくとも第1DBR層41Aと、第1DBR層41Aに隣り合う誘電体多層膜41との間の溝状の開口部41Hの幅は以下の範囲を満たすように設けられている。図2は、本実施の形態の要部(第1DBR層41A、開口部41Hおよび電流注入領域Rの位置関係)を説明するためのものである。第1DBR層41A、開口部41Hおよび電流注入領域Rは、第1DBR層41Aと、第1DBR層41Aに隣り合う誘電体多層膜41との間の距離(開口部41Hの幅)をW、第1DBR層41Aの基板11に対する法線方向の厚みをHとするとき、第1DBR層41A、開口部41Hおよび電流注入領域Rは、第1DBR層41Aの上面の端縁と、電流注入領域Rの端縁とを最短距離で結ぶ線分LNと、第1DBR層41Aの上面とのなす角θが、arctan(H/W)以上90°以下となるように形成されている。図2では、第1DBR層41Aの上面の端縁と、線分LNとが互いに接する点がX1で表されており、電流注入領域Rの端縁と、線分LNとが互いに接する点がX2で表されている。これにより、基板11の裏面(面S2)側から第1DBR層41Aに遮られることなく、電流注入領域Rを開口部41Hから確認することが可能となる。この条件を満たす各値の一具体例としては、例えば、開口部41Hの幅Wを4.5μm、第1DBR層41Aの厚みHを2.5μmとした場合のarctan(H/W)は約29°となる。よって、線分LNと、第1DBR層41Aの上面との成す角θは29°≦θ≦90°の範囲あればよく、例えば45°となる。 The side surface of the dielectric multilayer film 41 is perpendicular or substantially perpendicular to the substrate 11. The opening 41H provided between the adjacent dielectric multilayer films 41 does not necessarily have a uniform width between all the adjacent dielectric multilayer films 41, but in the present embodiment, at least the first The width of the groove-shaped opening 41H between the 1DBR layer 41A and the dielectric multilayer film 41 adjacent to the first DBR layer 41A is provided to satisfy the following range. FIG. 2 is a diagram for explaining the main part of this embodiment (the positional relationship between the first DBR layer 41A, the opening 41H, and the current injection region R). In the first DBR layer 41A, the opening 41H, and the current injection region R, the distance (width of the opening 41H) between the first DBR layer 41A and the dielectric multilayer film 41 adjacent to the first DBR layer 41A is W, and the first DBR. When the thickness of the layer 41A in the normal direction with respect to the substrate 11 is H, the first DBR layer 41A, the opening 41H, and the current injection region R include the edge of the upper surface of the first DBR layer 41A and the edge of the current injection region R. Is formed such that an angle θ between a line segment LN connecting the two and the upper surface of the first DBR layer 41A is not less than arctan (H / W) and not more than 90 °. In Figure 2, the edge of the upper surface of the 1DBR layer 41A, and the point where the line segment LN contact with each other is represented by X 1, and the edge of the current injection region R, the point where the line segment LN contact with each other It is represented by X 2. Accordingly, the current injection region R can be confirmed from the opening 41H without being blocked by the first DBR layer 41A from the back surface (surface S2) side of the substrate 11. As a specific example of each value satisfying this condition, for example, arctan (H / W) when the width W of the opening 41H is 4.5 μm and the thickness H of the first DBR layer 41A is 2.5 μm is about 29. °. Therefore, the angle θ formed by the line segment LN and the upper surface of the first DBR layer 41A may be in the range of 29 ° ≦ θ ≦ 90 °, for example, 45 °.
 各誘電体膜の厚みは、用いる材料等により適宜調整することができ、発光波長λ0、用いる材料の発光波長λ0での屈折率nによって決定される。具体的には、λ0/(4n)の奇数倍とすることが好ましい。例えば、発光波長λ0が410nmの発光素子において、誘電体多層膜41をSiOx/NbOyから構成する場合には、各誘電体膜の厚みは40nm~70nm程度であることが好ましい。積層数は、5以上であることが好ましく、より好ましくは、15以上である。誘電体多層膜41全体の厚みは、例えば、0.6μm~3.0μmであることが好ましい。 The thickness of each dielectric film can be adjusted as appropriate depending on the material used, and is determined by the light emission wavelength λ0 and the refractive index n of the material used at the light emission wavelength λ0. Specifically, an odd multiple of λ0 / (4n) is preferable. For example, in a light emitting device having an emission wavelength λ0 of 410 nm, when the dielectric multilayer film 41 is made of SiO x / NbO y , the thickness of each dielectric film is preferably about 40 nm to 70 nm. The number of stacked layers is preferably 5 or more, and more preferably 15 or more. The total thickness of the dielectric multilayer film 41 is preferably, for example, 0.6 μm to 3.0 μm.
 誘電体多層膜41の平面形状は、図3に示したように、例えば格子(矩形)状(A)、正六角形を含む多角形状(B)、楕円を含む円形状(C)、ストライプ状(D)あるいは島状形状に形成されている。誘電体多層膜41の断面形状は、図3に示したように矩形状でもよいし、あるいは台形状に形成してもよい。 As shown in FIG. 3, the planar shape of the dielectric multilayer film 41 is, for example, a lattice (rectangular) shape (A), a polygonal shape including a regular hexagon (B), a circular shape including an ellipse (C), a stripe shape ( D) or an island shape. The cross-sectional shape of the dielectric multilayer film 41 may be rectangular as shown in FIG. 3, or may be formed in a trapezoidal shape.
 第2DBR層42は、半導体層20を間にして第1DBR層41Aと対向する位置に設けられており、具体的には、透明電極32上に設けられている。第2DBR層42は、誘電体多層膜41と同様に、Si、Mg、Al、Hf、Nb、Zr、Sc、Ta、Ga、Zn、Y、B、Ti等の酸化物、窒化物(例えば、SiNx、AlNx、AlGaN、GaNx、BNx等)あるいはフッ化物等によって形成されている。第2DBR層42も誘電体多層膜41と同様に、SiNxやTaOx等の高屈折率材料と、SiOx等の低屈折率材料とを交互に積層することが好ましく、これにより、高い光反射率を得ることができる。所望の光反射率を得るためには、各誘電体膜を構成する材料のほか、膜厚および積層数等を適宜選択すればよい。各誘電体膜の厚みは、用いる材料等により適宜調整することができ、発光波長λ0、用いる材料の発光波長λ0での屈折率nによって決定される。具体的には、λ0/(4n)の奇数倍とすることが好ましい。例えば、発光波長λ0が410nmの発光素子において、誘電体多層膜41をSiOx/NbOyから構成する場合には、各誘電体膜の厚みは40nm~70nm程度であることが好ましい。積層数は2以上、好ましくは、2~15である。誘電体多層膜41全体の厚みは、例えば、0.6μm~1.7μmであることが好ましい。 The second DBR layer 42 is provided at a position facing the first DBR layer 41 </ b> A with the semiconductor layer 20 in between, specifically, provided on the transparent electrode 32. Similar to the dielectric multilayer film 41, the second DBR layer 42 is made of an oxide or nitride such as Si, Mg, Al, Hf, Nb, Zr, Sc, Ta, Ga, Zn, Y, B, Ti (for example, SiN x , AlN x , AlGaN, GaN x , BN x, etc.) or fluoride. As with the 2DBR layer 42 a dielectric multilayer film 41, a high refractive index material such as SiN x or TaO x, it is preferable to alternately laminating a low refractive index material such as SiO x, thereby, high light Reflectance can be obtained. In order to obtain a desired light reflectance, in addition to the material constituting each dielectric film, the film thickness, the number of stacked layers, and the like may be appropriately selected. The thickness of each dielectric film can be adjusted as appropriate depending on the material used, and is determined by the light emission wavelength λ0 and the refractive index n of the material used at the light emission wavelength λ0. Specifically, an odd multiple of λ0 / (4n) is preferable. For example, in a light emitting device having an emission wavelength λ0 of 410 nm, when the dielectric multilayer film 41 is made of SiO x / NbO y , the thickness of each dielectric film is preferably about 40 nm to 70 nm. The number of stacked layers is 2 or more, preferably 2 to 15. The total thickness of the dielectric multilayer film 41 is preferably, for example, 0.6 μm to 1.7 μm.
(1-2.製造方法)
 本実施の形態の半導体レーザ1は、例えば、次のようにして製造することができる。
(1-2. Manufacturing method)
The semiconductor laser 1 of the present embodiment can be manufactured as follows, for example.
 図4A~図4Cは、半導体レーザ1の製造方法を工程順に表わしたものである。まず、図4Aに示したように、基板11上に、複数の誘電体多層膜41を形成する。具体的には、例えば、スパッタ、CVDおよび蒸着等いずれの成膜方法を用いてSiOx膜およびSiNx膜を交互に、例えば5層積層された多層膜を形成したのち、例えば、多層膜を選択的にエッチングすることにより側面が溝状の開口部41Hに囲まれた複数の誘電体多層膜41を形成する。エッチング工程にはフッ化水素酸等によるウェットエッチング、RIE装置等を用いたドライエッチング等を用いることができる。これにより、基板11の面内に複数の誘電体多層膜41が形成される。 4A to 4C show a method of manufacturing the semiconductor laser 1 in the order of steps. First, as shown in FIG. 4A, a plurality of dielectric multilayer films 41 are formed on the substrate 11. Specifically, for example, after forming a multilayer film in which, for example, five layers of SiO x films and SiN x films are alternately stacked using any film formation method such as sputtering, CVD, and vapor deposition, By selectively etching, a plurality of dielectric multilayer films 41 whose side surfaces are surrounded by groove-shaped openings 41H are formed. For the etching step, wet etching using hydrofluoric acid or the like, dry etching using an RIE apparatus, or the like can be used. Thereby, a plurality of dielectric multilayer films 41 are formed in the surface of the substrate 11.
 次に、図4Bに示したように、誘電体多層膜41を覆う半導体層20および開口24Aを有する絶縁膜24を形成する。具体的には、誘電体多層膜41を選択成長用マスクとして用い、基板11をMOCVD(Metal Organic Chemical Vapor Deposition;有機金属化学気相成長)装置に設置し、所望の温度に加熱した状態で、例えば、n型GaNからなる第1半導体層21、活性層(発光層)22、例えば、p型GaNからなる第2半導体層23等を含む半導体層20を成長させる。成長には、Ga原料としてトリメチルガリウム(TMGa)、Al原料としてトリメチルアルミニウム(TMAl)、In原料としてトリメチルインジウム(TMIn)、n型不純物のSiの原料としてシラン(SiH4)、p型不純物のMgの原料としてシクロペンタジエニルマグネシウム(Cp2Mg)、N原料としてアンモニアガス(NH3)等を用いる。ここでは、例えば、第1半導体層21を5μm、活性層22を80nm、第2半導体層23を100nm成長させる。続いて、電流狭窄構造を形成する絶縁膜24を形成する。例えばSiO2膜を、例えばスパッタ、CVDおよび蒸着等いずれの成膜方法を用いて、例えば200nmの厚みで成膜したのち、選択的にエッチングすることにより、電流注入領域Rとなる第2半導体層23が露出した開口24Aを有する絶縁膜24を形成する。エッチング工程にはフッ化水素酸等によるウェットエッチング、RIE装置等を用いたドライエッチング等を用いることができる。これにより、誘電体多層膜41を覆う半導体層20および電流狭窄構造となる開口24Aを有する絶縁膜24が形成される。ここで、電流注入領域Rの面積は、電流注入領域Rに対向する誘電体多層膜41(第1DBR層41A)の面積の半分以下となっていることが好ましい。電流注入領域Rの面積は、例えば、25πμm2程度である。このようにした場合には、半導体層20の欠陥領域(特異点)を避けて電流注入領域Rを形成することができる。 Next, as shown in FIG. 4B, the semiconductor layer 20 covering the dielectric multilayer film 41 and the insulating film 24 having the openings 24A are formed. Specifically, the dielectric multilayer film 41 is used as a selective growth mask, and the substrate 11 is placed in a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus and heated to a desired temperature. For example, the semiconductor layer 20 including the first semiconductor layer 21 made of n-type GaN and the active layer (light emitting layer) 22, for example, the second semiconductor layer 23 made of p-type GaN, is grown. For growth, trimethylgallium (TMGa) as a Ga source, trimethylaluminum (TMAl) as an Al source, trimethylindium (TMIn) as an In source, silane (SiH 4 ) as an n-type impurity Si source, and p-type impurity Mg Cyclopentadienylmagnesium (Cp 2 Mg) is used as a raw material for the above, and ammonia gas (NH 3 ) is used as the N raw material. Here, for example, the first semiconductor layer 21 is grown to 5 μm, the active layer 22 is grown to 80 nm, and the second semiconductor layer 23 is grown to 100 nm. Subsequently, an insulating film 24 for forming a current confinement structure is formed. For example, the SiO 2 film is formed to have a thickness of, for example, 200 nm by using any film formation method such as sputtering, CVD, and vapor deposition. An insulating film 24 having an opening 24A from which 23 is exposed is formed. For the etching step, wet etching using hydrofluoric acid or the like, dry etching using an RIE apparatus, or the like can be used. As a result, the semiconductor layer 20 covering the dielectric multilayer film 41 and the insulating film 24 having the opening 24A having a current confinement structure are formed. Here, the area of the current injection region R is preferably less than or equal to half of the area of the dielectric multilayer film 41 (first DBR layer 41A) facing the current injection region R. The area of the current injection region R is, for example, about 25πμm 2 . In this case, the current injection region R can be formed while avoiding a defect region (singular point) of the semiconductor layer 20.
 続いて、図4Cに示したように、透明電極32、第2電極33および第2DBR層42を形成する。具体的には、例えばITO膜を、例えば、スパッタ、CVDおよび蒸着等いずれの成膜方法を用いて50nm厚みに成膜したのち、選択的にエッチングすることにより、所望の形状を有する透明電極32を形成する。エッチング工程には塩酸等によるウェットエッチング、リアクティブイオンエッチング装置等を用いたドライエッチング等を用いることができる。次に、例えばAu、PtおよびTiを、例えば、スパッタ、CVDおよび蒸着等いずれの成膜方法を用いてこの順に成膜したのち、選択的にエッチングすることにより、所望の部分にのみTi/Pt/Au膜を残して第2電極33を形成する。エッチング工程には酸等によるウェットエッチング、リアクティブイオンエッチング装置等を用いたドライエッチング、PR法によるリフトオフ等を用いることができる。続いて、例えば、スパッタ、CVDおよび蒸着等いずれの成膜方法を用いてSiOx膜およびSiNx膜を交互に、例えば、5層積層された誘電体多層膜を形成したのち、例えば、選択的にエッチングすることにより所望の形状を有する第2DBR層42を形成する。エッチング工程にはフッ化水素酸等によるウェットエッチング、RIE装置等を用いたドライエッチング等を用いることができる。 Subsequently, as shown in FIG. 4C, the transparent electrode 32, the second electrode 33, and the second DBR layer 42 are formed. Specifically, for example, an ITO film is formed to a thickness of 50 nm by using any film formation method such as sputtering, CVD, and vapor deposition, and then selectively etched, thereby transparent electrode 32 having a desired shape. Form. For the etching process, wet etching using hydrochloric acid or the like, dry etching using a reactive ion etching apparatus, or the like can be used. Next, for example, Au, Pt, and Ti are formed in this order by using any film forming method such as sputtering, CVD, and vapor deposition, and then selectively etched to form Ti / Pt only at a desired portion. The second electrode 33 is formed leaving the / Au film. For the etching process, wet etching using acid or the like, dry etching using a reactive ion etching apparatus or the like, lift-off using the PR method, or the like can be used. Subsequently, for example, after forming a dielectric multilayer film in which, for example, five layers of SiO x films and SiN x films are alternately formed by using any film forming method such as sputtering, CVD, and vapor deposition, for example, selective The second DBR layer 42 having a desired shape is formed by etching. For the etching step, wet etching using hydrofluoric acid or the like, dry etching using an RIE apparatus, or the like can be used.
 次に、基板11を裏面側から研削および研磨を行ったのち、第1電極31を成膜する。最後に、基板11から素子を劈開等によって切り出す。以上により、図1に示した半導体レーザ1が完成する。 Next, after the substrate 11 is ground and polished from the back side, the first electrode 31 is formed. Finally, the element is cut out from the substrate 11 by cleavage or the like. Thus, the semiconductor laser 1 shown in FIG. 1 is completed.
 半導体レーザ1は、上記のように、基板11の面S1に、複数の誘電体多層膜41、第1半導体層21、活性層22、第2半導体層23、透明電極32および第2DBR層42がこの順に積層され、基板11の面S1に対向する他の面S2には第1電極31が形成された構成を有する。第1DBR層41Aおよび第2DBR層42のいずれか一方(ここでは、第2DBR層42側)には、活性層22への電流注入効率を高め、閾地電流を下げるために電流注入領域を狭める電流狭窄構造(絶縁膜24の開口24A)が設けられている。半導体レーザ1では、第1電極31および透明電極32から注入された電流が電流狭窄構造により狭窄されたのち、活性層22に注入される。これにより、電子と正孔の再結合による発光が生じる。この光は、第1DBR層41Aおよび第2DBR層42によって反射され、所定の波長でレーザ発振が生じ、第1DBR層41Aまたは第2DBR層42を介して外部にレーザ光として射出される。 As described above, the semiconductor laser 1 includes the plurality of dielectric multilayer films 41, the first semiconductor layer 21, the active layer 22, the second semiconductor layer 23, the transparent electrode 32, and the second DBR layer 42 on the surface S1 of the substrate 11. The first electrode 31 is formed on the other surface S2 stacked in this order and facing the surface S1 of the substrate 11. In either one of the first DBR layer 41A and the second DBR layer 42 (here, on the second DBR layer 42 side), a current that narrows the current injection region in order to increase the current injection efficiency into the active layer 22 and reduce the threshold ground current. A constriction structure (opening 24A of insulating film 24) is provided. In the semiconductor laser 1, the current injected from the first electrode 31 and the transparent electrode 32 is narrowed by the current confinement structure and then injected into the active layer 22. Thereby, light emission by recombination of electrons and holes occurs. This light is reflected by the first DBR layer 41A and the second DBR layer 42, causes laser oscillation at a predetermined wavelength, and is emitted to the outside through the first DBR layer 41A or the second DBR layer 42.
(1-3.作用・効果)
 前述したように、活性層を含む半導体層の上下にDBR層を有する面発光レーザでは、DBR層の間で光を共振させてレーザ発振を生じさせるために、共振器長の制御およびDBR層の表面をサブ・ナノメートルオーダーで平滑にする必要がある。このため、DBR層を選択成長用マスクとして用いて半導体層を成長させ、このDBR層が半導体層に埋め込まれた面発光レーザが開発されているが、DBR層上に光取り出し図を形成する際のアライメントのばらつきを考慮してDBR層は光取り出し部よりも大きく設計されていた。
(1-3. Action and effect)
As described above, in a surface emitting laser having a DBR layer above and below a semiconductor layer including an active layer, in order to cause light to resonate between the DBR layers to generate laser oscillation, control of the resonator length and the DBR layer The surface needs to be smooth on the order of sub-nanometers. For this reason, a surface emitting laser in which a semiconductor layer is grown using the DBR layer as a selective growth mask and this DBR layer is embedded in the semiconductor layer has been developed. However, when a light extraction diagram is formed on the DBR layer. The DBR layer was designed to be larger than the light extraction portion in consideration of the alignment variation.
 しかしながら、大口径の誘電体多層膜を埋め込んだ場合には、デバイス特性の検査および電極中の欠陥の修復等が困難になる。デバイス特性の検査は、例えば、基板の裏面側から発光層となる活性層に励起光が照射される。このとき、半導体層20を構成するGaNの光吸収および誘電体多層膜のストップバンドを回避して直接活性層を励起することが望ましいが、大口径の誘電体多層膜を形成した場合、誘電体多層膜を避けて励起光を照射することが難しかった。また、一般的な窒化物面発光レーザに用いられる電極には、ITO等の透明電極材料が用いられるが、ITOは欠陥を含みやすい。このITO膜中の欠陥はレーザ光を照射することで修復することができるが、基板の裏面側から修復用のレーザ光を欠陥部に照射するためには、大口径の誘電体層は妨げになりやすかった。このため、信頼性を向上させることが難しく、また、製造歩留まりが低下するという問題があった。 However, when a large-diameter dielectric multilayer film is embedded, it becomes difficult to inspect device characteristics and repair defects in the electrode. In the device characteristic inspection, for example, excitation light is irradiated from the back surface side of the substrate to the active layer serving as the light emitting layer. At this time, it is desirable to directly excite the active layer while avoiding the light absorption of GaN constituting the semiconductor layer 20 and the stop band of the dielectric multilayer film, but when a large-diameter dielectric multilayer film is formed, It was difficult to irradiate the excitation light avoiding the multilayer film. In addition, a transparent electrode material such as ITO is used for an electrode used in a general nitride surface emitting laser, but ITO is likely to include defects. Defects in this ITO film can be repaired by irradiating laser light, but in order to irradiate the defective part with laser light for repair from the back side of the substrate, a large-diameter dielectric layer is obstructed. It was easy to be. For this reason, it is difficult to improve the reliability, and the manufacturing yield is reduced.
 これに対して、本実施の形態では、第1DBR層41Aの上面の端縁と、電流注入領域Rの端縁とを最短距離で結ぶ線分LNと、第1DBR層41Aの上面とのなす角θが、arctan(H/W)以上90°以下となっている。 On the other hand, in the present embodiment, the angle formed by the line segment LN connecting the edge of the upper surface of the first DBR layer 41A and the edge of the current injection region R with the shortest distance and the upper surface of the first DBR layer 41A. θ is not less than arctan (H / W) and not more than 90 °.
 図5は、半導体レーザ1のデバイス特性の検査方法を模式的に表したものである。図6は、半導体レーザ1に設けられた透明電極32中の欠陥修復の方法を模式的に表したものである。デバイス特性の検査および電極(透明電極32)中の欠陥修復は、上述したように、基板11の裏面(面S2)側から励起光L1あるいはレーザ光L2を、それぞれ、活性層22あるいは透明電極32に照射することによって行われる。本実施の形態では、上記のように、角θが、arctan(H/W)以上90°以下となっているので、基板11側から第1DBR層41Aに遮られることなく、レーザ光L2を電流注入領域Rに、励起光L1を電流注入領域R下の活性層22に選択的に照射することが可能となる。よって、外部要因に左右されることなくデバイス特性の検査(光励起検査)および透明電極32の欠陥修復が可能となる。その結果、半導体レーザ1の信頼性および製造歩留まりが向上する。 FIG. 5 schematically shows a method for inspecting the device characteristics of the semiconductor laser 1. FIG. 6 schematically shows a method for repairing a defect in the transparent electrode 32 provided in the semiconductor laser 1. As described above, the inspection of device characteristics and the repair of defects in the electrode (transparent electrode 32) are performed by using excitation light L1 or laser light L2 from the back surface (surface S2) side of the substrate 11 and the active layer 22 or transparent electrode 32, respectively. It is done by irradiating. In the present embodiment, as described above, since the angle θ is not less than arctan (H / W) and not more than 90 °, the laser beam L2 is supplied from the substrate 11 side without being blocked by the first DBR layer 41A. The injection region R can be selectively irradiated with the excitation light L1 on the active layer 22 below the current injection region R. Therefore, device characteristics inspection (photoexcitation inspection) and defect repair of the transparent electrode 32 can be performed regardless of external factors. As a result, the reliability and manufacturing yield of the semiconductor laser 1 are improved.
 以下に、本技術の第2の実施の形態について説明する。なお、第1の実施の形態と同様の構成については、同じ符号を付し、その説明を省略する。 Hereinafter, a second embodiment of the present technology will be described. In addition, about the structure similar to 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.
<2.第2の実施の形態>
 図7は、本技術の第2の実施の形態に係る窒化物面発光レーザ(半導体レーザ2)の断面構成の一例を表したものである。半導体レーザ2は、第1の実施の形態の半導体レーザ1において、誘電体多層膜41の代わりに、誘電体多層膜51を備えている点で、上記第1の実施の形態と相違する。誘電体多層膜51は、誘電体多層膜41と同様の積層構造となっており、誘電体多層膜51の側面が順テーパ状に傾斜されている点で、誘電体多層膜41の断面構成と相違している。複数の誘電体多層膜51のうち、第2DBR層42と対向する誘電体多層膜51を第1DBR層51Aとすると、一組の第1DBR層51Aおよび第2DBR層42が、共振器として機能する。半導体層20は、第1半導体層21、活性層22、第2半導体層23が基板11側からこの順に積層され積層された構成を有する。各誘電体多層膜51は、第1半導体層21によって埋め込まれており、第1DBR層51Aと、第1DBR層51Aと隣り合う誘電体多層膜51との間には、溝状の開口部51Hが形成されている。第1DBR層51Aの上面の端縁と、電流注入領域Rの端縁とを最短距離で結ぶ線分と、第1DBR層51Aの上面とのなす角が、所定の範囲内となっている。半導体レーザ2は、基板11の面S2(面S1と対向する面)に接する第1電極31を有する。なお、図7の半導体レーザ1は模式的に表したものであり、実際の寸法とは異なっている。
<2. Second Embodiment>
FIG. 7 illustrates an example of a cross-sectional configuration of a nitride surface emitting laser (semiconductor laser 2) according to the second embodiment of the present technology. The semiconductor laser 2 is different from the first embodiment in that the semiconductor laser 1 includes a dielectric multilayer film 51 instead of the dielectric multilayer film 41 in the semiconductor laser 1 of the first embodiment. The dielectric multilayer film 51 has a laminated structure similar to that of the dielectric multilayer film 41, and the cross-sectional configuration of the dielectric multilayer film 41 is that the side surface of the dielectric multilayer film 51 is inclined in a forward tapered shape. It is different. When the dielectric multilayer film 51 facing the second DBR layer 42 among the plurality of dielectric multilayer films 51 is the first DBR layer 51A, the pair of first DBR layer 51A and second DBR layer 42 function as a resonator. The semiconductor layer 20 has a configuration in which a first semiconductor layer 21, an active layer 22, and a second semiconductor layer 23 are stacked in this order from the substrate 11 side. Each dielectric multilayer film 51 is embedded with the first semiconductor layer 21, and a groove-shaped opening 51H is formed between the first DBR layer 51A and the dielectric multilayer film 51 adjacent to the first DBR layer 51A. Is formed. An angle between a line segment connecting the edge of the upper surface of the first DBR layer 51A and the edge of the current injection region R with the shortest distance and the upper surface of the first DBR layer 51A is within a predetermined range. The semiconductor laser 2 has a first electrode 31 in contact with the surface S2 of the substrate 11 (the surface facing the surface S1). Note that the semiconductor laser 1 in FIG. 7 is schematically shown and is different from actual dimensions.
(2-1.要部構成)
 誘電体多層膜51は、基板11の面内に複数設けられており、第1半導体層21によって埋め込まれている。隣り合う誘電体多層膜51の間には溝状の開口部51Hが設けられており、開口部51Hには、第1半導体層21が埋設されている。誘電体多層膜51は、例えば、Si、Mg、Al、Hf、Nb、Zr、Sc、Ta、Ga、Zn、Y、B、Ti等の酸化物、窒化物(例えば、SiNx、AlNx、AlGaN、GaNx、BNx等)あるいはフッ化物等によって形成されている。具体的には、SiOx、TiOx、NbOx、ZrOx、TaOx、ZnOx、AlOx、HfOx、SiNx、AlNx等が挙げられる。第1DBR層51Aは、上記誘電体材料のうち、屈折率が異なる誘電体材料から成る2種類以上の誘電体膜(例えば、高い屈折率を有するTaOxと、低い屈折率を有するSiOxと)が交互に積層された構成となっていることが好ましい。これにより、光反射効果が得られる。2種類の誘電体膜の組み合わせとしては、例えば、SiOx/TaOxのほか、SiOx/SiNx、SiOx/NbOx、SiOx/ZrOx、SiOx/AlNx等が挙げられる。所望の光反射率を得るために、各誘電体膜を構成する材料、膜厚および積層数等を、適宜選択すればよい。誘電体多層膜51は、例えば、[1120]方向に横方向成長するように配置または配列させることが好ましい。
(2-1. Main part configuration)
A plurality of dielectric multilayer films 51 are provided in the plane of the substrate 11 and are embedded with the first semiconductor layer 21. A groove-shaped opening 51H is provided between adjacent dielectric multilayer films 51, and the first semiconductor layer 21 is embedded in the opening 51H. The dielectric multilayer film 51 includes, for example, Si, Mg, Al, Hf, Nb, Zr, Sc, Ta, Ga, Zn, Y, B, Ti, and other oxides and nitrides (for example, SiN x , AlN x , AlGaN, GaN x , BN x, etc.) or fluoride. Specifically, SiO x, TiO x, NbO x, ZrO x, TaO x, ZnO x, AlO x, HfO x, SiN x, AlN x , and the like. The first DBR layer 51A includes two or more kinds of dielectric films made of dielectric materials having different refractive indexes among the dielectric materials (for example, TaO x having a high refractive index and SiO x having a low refractive index). It is preferable that the layers are alternately stacked. Thereby, the light reflection effect is obtained. The combination of two dielectric films, for example, in addition to SiO x / TaO x, SiO x / SiN x, SiO x / NbO x, SiO x / ZrO x, SiO x / AlN x , and the like. In order to obtain a desired light reflectance, the material, the film thickness, the number of stacked layers, and the like constituting each dielectric film may be appropriately selected. For example, the dielectric multilayer film 51 is preferably arranged or arranged so as to grow laterally in the [1120] direction.
 隣り合う誘電体多層膜51の間に設けられている開口部51Hは、必ずしも隣り合う全ての誘電体多層膜51の間で均一な幅である必要はないが、本実施の形態では、第1DBR層51Aと、第1DBR層51Aに隣り合う誘電体多層膜51との間の溝状の開口部51Hの幅は、以下の範囲を満たすように設けられている。 The opening 51H provided between the adjacent dielectric multilayer films 51 does not necessarily have a uniform width between all the adjacent dielectric multilayer films 51, but in the present embodiment, the first DBR is used. The width of the groove-shaped opening 51H between the layer 51A and the dielectric multilayer film 51 adjacent to the first DBR layer 51A is provided so as to satisfy the following range.
 図8は、本実施の形態の要部(第1DBR層51A、開口部51Hおよび電流注入領域Rの位置関係)を説明するためのものである。第1DBR層51A、開口部51Hおよび電流注入領域Rは、第1DBR層51Aと、第1DBR層51Aに隣り合う誘電体多層膜51との間の距離(開口部51Hの幅)をW、第1DBR層51Aの上面の外縁から引いた垂線と第1DBR層51Aの底辺との交点から開口部51Hまでの距離をW'、第1DBR層51Aの基板11に対する法線方向の厚みをHとするとき、第1DBR層51A、開口部51Hおよび電流注入領域Rは、第1DBR層51Aの上面の端縁と、電流注入領域Rの端縁とを最短距離で結ぶ線分LNと、第1DBR層51Aの上面とのなす角θが、arctan(H/(W+W'))以上90°以下となるように形成されている。図8では、第1DBR層51Aの上面の端縁と、線分LNとが互いに接する点がX1で表されており、電流注入領域Rの端縁と、線分LNとが互いに接する点がX2で表されている。これにより、基板11の裏面(面S2)側から第1DBR層51Aに遮られることなく、電流注入領域Rを開口部51Hから確認することが可能となる。この条件を満たす各値の具体的な数値は、例えば、開口幅Wは4.5μm、上部外周部X1から引いた垂線と第1DBR層51Aの底辺との交点から開口部51Hまでの距離W'を2μmおよび第1DBR層41Aの厚みHを2.5μmとした場合のarctan(H/(W+W'))は約21°となる。よって、線分LNと、第1DBR層51Aの上面との成す角θは21°≦θ≦90°の範囲であればよく、例えば30°程度となる。 FIG. 8 is for explaining the main part of this embodiment (the positional relationship between the first DBR layer 51A, the opening 51H and the current injection region R). In the first DBR layer 51A, the opening 51H, and the current injection region R, the distance (width of the opening 51H) between the first DBR layer 51A and the dielectric multilayer film 51 adjacent to the first DBR layer 51A is W, and the first DBR. When the distance from the intersection of the perpendicular drawn from the outer edge of the upper surface of the layer 51A and the bottom of the first DBR layer 51A to the opening 51H is W ′, and the thickness of the first DBR layer 51A in the normal direction to the substrate 11 is H, The first DBR layer 51A, the opening 51H, and the current injection region R include a line segment LN connecting the edge of the upper surface of the first DBR layer 51A and the edge of the current injection region R at the shortest distance, and the upper surface of the first DBR layer 51A. Is formed so as to be not less than arctan (H / (W + W ′)) and not more than 90 °. 8, the edge of the upper surface of the 1DBR layer 51A, and the point where the line segment LN contact with each other is represented by X 1, and the edge of the current injection region R, the point where the line segment LN contact with each other It is represented by X 2. Thus, the current injection region R can be confirmed from the opening 51H without being blocked by the first DBR layer 51A from the back surface (surface S2) side of the substrate 11. Specific numerical values of the values satisfying this condition are, for example, an opening width W of 4.5 μm, a distance W ′ from the intersection of the perpendicular drawn from the upper outer peripheral portion X1 and the bottom side of the first DBR layer 51A to the opening 51H. And arctan (H / (W + W ′)) is about 21 ° when the thickness H of the first DBR layer 41A is 2.5 μm. Therefore, the angle θ formed by the line segment LN and the upper surface of the first DBR layer 51A may be in a range of 21 ° ≦ θ ≦ 90 °, and is about 30 °, for example.
 なお、誘電体多層膜51の断面形状は、順テーパ形状以外に、例えば、図9(A)に示したように、誘電体多層膜51の上部角の一部(例えば、誘電体多層膜51の上面から側面S1,S2の一部)が削られた形状としてもよい。また、誘電体多層膜51の断面形状は必ずしも対称である必要はなく、図9(B)に示したように、一方の側面(ここでは、側面S1)のみの上部角が削られていてもよい。更にまた、基板11上に設けられた複数の誘電体多層膜51のすべてが同じ形状である必要はなく、第1DBR層51Aとなる誘電体多層膜51のみが、上記形状に加工されていてもよい。 In addition to the forward tapered shape, the cross-sectional shape of the dielectric multilayer film 51 is a part of the upper corner of the dielectric multilayer film 51 (for example, the dielectric multilayer film 51, for example, as shown in FIG. 9A). It is good also as a shape where a part of side surfaces S1 and S2) was shaved from the upper surface. Further, the cross-sectional shape of the dielectric multilayer film 51 does not necessarily have to be symmetric, and even if the upper corner of only one side surface (here, the side surface S1) is cut as shown in FIG. 9B. Good. Furthermore, it is not necessary that all of the plurality of dielectric multilayer films 51 provided on the substrate 11 have the same shape, and only the dielectric multilayer film 51 that becomes the first DBR layer 51A is processed into the above shape. Good.
 その他の構成については、第1の実施の形態と同様である。 Other configurations are the same as those in the first embodiment.
(2-2.作用・効果)
 本実施の形態では、第1DBR層51Aの上面の端縁と、電流注入領域Rの端縁とを最短距離で結ぶ線分LNと、第1DBR層51Aの上面とのなす角θが、arctan(H/(W+W'))以上90°以下となっている。
(2-2. Action and effect)
In the present embodiment, an angle θ formed by a line segment LN connecting the edge of the upper surface of the first DBR layer 51A and the edge of the current injection region R with the shortest distance and the upper surface of the first DBR layer 51A is arctan ( H / (W + W ′)) to 90 °.
 図10は、半導体レーザ2のデバイス特性の検査方法を模式的に表したものである。図11は、半導体レーザ2に設けられた透明電極32中の欠陥修復の方法を模式的に表したものである。デバイス特性の検査および電極(透明電極32)中の欠陥修復は、上述したように、基板11の裏面(面S2)側から励起光L1あるいはレーザ光L2を、それぞれ、活性層22あるいは透明電極32に照射することによって行われる。基板11から第1DBR層51Aに遮られることなく、レーザ光L2を電流注入領域Rに、励起光L1を電流注入領域R下の活性層22に選択的に照射することが可能となる。よって、外部要因に左右されることなくデバイス特性の検査(光励起検査)および透明電極32の欠陥修復が可能となる。その結果、半導体レーザ2の信頼性および製造歩留まりが向上する。 FIG. 10 schematically shows a method for inspecting the device characteristics of the semiconductor laser 2. FIG. 11 schematically shows a method for repairing a defect in the transparent electrode 32 provided in the semiconductor laser 2. As described above, the inspection of device characteristics and the repair of defects in the electrode (transparent electrode 32) are performed by using excitation light L1 or laser light L2 from the back surface (surface S2) side of the substrate 11 and the active layer 22 or transparent electrode 32, respectively. It is done by irradiating. The laser beam L2 can be selectively irradiated to the current injection region R and the excitation light L1 can be selectively irradiated to the active layer 22 below the current injection region R without being blocked by the first DBR layer 51A from the substrate 11. Therefore, device characteristics inspection (photoexcitation inspection) and defect repair of the transparent electrode 32 can be performed regardless of external factors. As a result, the reliability and manufacturing yield of the semiconductor laser 2 are improved.
 以上、第1実施の形態および第2の実施の形態を挙げて本技術を説明したが、本技術は上記実施の形態等に限定されるものではなく、種々変形可能である。 Although the present technology has been described with reference to the first embodiment and the second embodiment, the present technology is not limited to the above-described embodiments and the like, and various modifications can be made.
 なお、本明細書に記載された効果はあくまで例示であってこれに限定されるものではなく、また他の効果があってもよい。 It should be noted that the effects described in the present specification are merely examples and are not limited to these, and other effects may be obtained.
 なお、本技術は以下の様な構成をとることも可能である。
(1)
 基板の上に設けられ、互いに隣り合う第1誘電体多層膜および第2誘電体多層膜と、
 前記第1誘電体多層膜と対向する位置に設けられた電流注入領域と、
 前記第1誘電体多層膜と前記第2誘電体多層膜との間に設けられた開口部とを備え、
 前記第1誘電体多層膜と前記第2誘電体多層膜との間の距離をW、前記第1誘電体多層膜の前記基板に対する法線方向の厚みをHとするとき、
 前記第1誘電体多層膜、前記開口部および前記電流注入領域は、前記第1誘電体多層膜の上面の端縁と、前記電流注入領域の端縁とを最短距離で結ぶ線分と、前記第1誘電体多層膜の上面とのなす角θが、arctan(H/W)以上90°以下となるように形成されている
 窒化物面発光レーザ。
(2)
 前記第1誘電体多層膜の側面は、前記基板に対して垂直である、前記(1)に記載の窒化物面発光レーザ。
(3)
 前記電流注入領域の面積は、前記第1誘電体多層膜の面積の半分以下である、前記(1)または(2)に記載の窒化物面発光レーザ。
(4)
 第1半導体層と、
 前記第1半導体層の上に設けられた活性層と、
 前記活性層の上に設けられ、前記活性層から発せられた光を射出する射出窓を有する第2半導体層とを備え、
 前記第1半導体層、前記活性層および前記第2半導体層を間にして、前記第1半導体層に埋め込まれている1つの前記第1誘電体多層膜と対向する位置に設けられた第3誘電体多層膜をさらに有する、前記(1)乃至(3)のうちのいずれかに記載の窒化物面発光レーザ。
(5)
 前記第1半導体層、前記活性層および前記第2半導体層は、GaN系化合物半導体によって構成されている、前記(4)に記載の窒化物面発光レーザ。
(6)
 基板の上に設けられ、互いに隣り合う第1誘電体多層膜および第2誘電体多層膜と、
 前記第1誘電体多層膜と対向する位置に設けられた電流注入領域と、
 前記第1誘電体多層膜と前記第2誘電体多層膜との間に設けられた開口部とを備え、
 前記第1誘電体多層膜と前記第2誘電体多層膜との間の距離をW、前記第1誘電体多層膜の上面の外縁から引いた垂線と前記第1誘電体多層膜の底辺との交点から前記開口部までの距離をW'、前記第1誘電体多層膜の前記基板に対する法線方向の厚みをHとするとき、
 前記第1誘電体多層膜、前記開口部および前記電流注入領域は、前記第1誘電体多層膜の上面の端縁と、前記電流注入領域の端縁とを最短距離で結ぶ線分と、第1誘電体多層膜の上面とのなす角θが、arctan(H/(W+W'))以上90°以下となるように形成されている
 窒化物面発光レーザ。
(7)
 前記第1誘電体多層膜の側面の少なくとも一部は、順テーパ形状を有している、前記(6)に記載の窒化物面発光レーザ。
(8)
 前記電流注入領域の面積は、前記第1誘電体多層膜の面積の半分以下である、前記(6)または(7)に記載の窒化物面発光レーザ。
(9)
 第1半導体層と、
 前記第1半導体層の上に設けられた活性層と、
 前記活性層の上に設けられ、前記活性層から発せられた光を射出する射出窓を有する第2半導体層とを備え、
 前記第1半導体層、前記活性層および前記第2半導体層を間にして、前記第1半導体層に埋め込まれている1つの前記第1誘電体多層膜と対向する位置に設けられた第3誘電体多層膜をさらに備え、
 前記第1誘電体多層膜は、第1光反射層である、前記(6)乃至(8)のうちのいずれかに記載の窒化物面発光レーザ。
(10)
 前記第1半導体層、前記活性層および前記第2半導体層は、GaN系化合物半導体によって構成されている、前記(9)に記載の窒化物面発光レーザ。
In addition, this technique can also take the following structures.
(1)
A first dielectric multilayer film and a second dielectric multilayer film provided on the substrate and adjacent to each other;
A current injection region provided at a position facing the first dielectric multilayer film;
An opening provided between the first dielectric multilayer film and the second dielectric multilayer film;
When the distance between the first dielectric multilayer film and the second dielectric multilayer film is W, and the thickness of the first dielectric multilayer film in the normal direction to the substrate is H,
The first dielectric multilayer film, the opening, and the current injection region include a line segment that connects an edge of the upper surface of the first dielectric multilayer film and an edge of the current injection region with the shortest distance; A nitride surface emitting laser formed such that an angle θ formed with the upper surface of the first dielectric multilayer film is not less than arctan (H / W) and not more than 90 °.
(2)
The nitride surface emitting laser according to (1), wherein a side surface of the first dielectric multilayer film is perpendicular to the substrate.
(3)
The nitride surface emitting laser according to (1) or (2), wherein an area of the current injection region is not more than half of an area of the first dielectric multilayer film.
(4)
A first semiconductor layer;
An active layer provided on the first semiconductor layer;
A second semiconductor layer provided on the active layer and having an emission window for emitting light emitted from the active layer;
A third dielectric provided at a position facing one of the first dielectric multilayer films embedded in the first semiconductor layer with the first semiconductor layer, the active layer, and the second semiconductor layer in between. The nitride surface emitting laser according to any one of (1) to (3), further including a body multilayer film.
(5)
The nitride surface emitting laser according to (4), wherein the first semiconductor layer, the active layer, and the second semiconductor layer are formed of a GaN-based compound semiconductor.
(6)
A first dielectric multilayer film and a second dielectric multilayer film provided on the substrate and adjacent to each other;
A current injection region provided at a position facing the first dielectric multilayer film;
An opening provided between the first dielectric multilayer film and the second dielectric multilayer film;
The distance between the first dielectric multilayer film and the second dielectric multilayer film is W, the perpendicular drawn from the outer edge of the upper surface of the first dielectric multilayer film, and the bottom of the first dielectric multilayer film When the distance from the intersection to the opening is W ′, and the thickness of the first dielectric multilayer film in the normal direction to the substrate is H,
The first dielectric multilayer film, the opening, and the current injection region include a line segment that connects the edge of the upper surface of the first dielectric multilayer film and the edge of the current injection region with the shortest distance; 1. A nitride surface emitting laser formed so that an angle θ formed with an upper surface of a dielectric multilayer film is not less than arctan (H / (W + W ′)) and not more than 90 °.
(7)
The nitride surface emitting laser according to (6), wherein at least a part of the side surface of the first dielectric multilayer film has a forward tapered shape.
(8)
The nitride surface emitting laser according to (6) or (7), wherein an area of the current injection region is not more than half of an area of the first dielectric multilayer film.
(9)
A first semiconductor layer;
An active layer provided on the first semiconductor layer;
A second semiconductor layer provided on the active layer and having an emission window for emitting light emitted from the active layer;
A third dielectric provided at a position facing one of the first dielectric multilayer films embedded in the first semiconductor layer with the first semiconductor layer, the active layer, and the second semiconductor layer in between. Body multilayer film,
The nitride surface emitting laser according to any one of (6) to (8), wherein the first dielectric multilayer film is a first light reflecting layer.
(10)
The nitride surface emitting laser according to (9), wherein the first semiconductor layer, the active layer, and the second semiconductor layer are formed of a GaN-based compound semiconductor.
 本出願は、日本国特許庁において2015年9月2日に出願された日本特許出願番号2015-172748号を基礎として優先権を主張するものであり、この出願の全ての内容を参照によって本出願に援用する。 This application claims priority based on Japanese Patent Application No. 2015-172748 filed on September 2, 2015 at the Japan Patent Office. The entire contents of this application are hereby incorporated by reference. Incorporated into.
 当業者であれば、設計上の要件や他の要因に応じて、種々の修正、コンビネーション、サブコンビネーション、および変更を想到し得るが、それらは添付の請求の範囲やその均等物の範囲に含まれるものであることが理解される。 Those skilled in the art will envision various modifications, combinations, subcombinations, and changes, depending on design requirements and other factors, which are within the scope of the appended claims and their equivalents. It is understood that

Claims (10)

  1.  基板の上に設けられ、互いに隣り合う第1誘電体多層膜および第2誘電体多層膜と、
     前記第1誘電体多層膜と対向する位置に設けられた電流注入領域と、
     前記第1誘電体多層膜と前記第2誘電体多層膜との間に設けられた開口部とを備え、
     前記第1誘電体多層膜と前記第2誘電体多層膜との間の距離をW、前記第1誘電体多層膜の前記基板に対する法線方向の厚みをHとするとき、
     前記第1誘電体多層膜、前記開口部および前記電流注入領域は、前記第1誘電体多層膜の上面の端縁と、前記電流注入領域の端縁とを最短距離で結ぶ線分と、前記第1誘電体多層膜の上面とのなす角θが、arctan(H/W)以上90°以下となるように形成されている
     窒化物面発光レーザ。
    A first dielectric multilayer film and a second dielectric multilayer film provided on the substrate and adjacent to each other;
    A current injection region provided at a position facing the first dielectric multilayer film;
    An opening provided between the first dielectric multilayer film and the second dielectric multilayer film;
    When the distance between the first dielectric multilayer film and the second dielectric multilayer film is W, and the thickness of the first dielectric multilayer film in the normal direction to the substrate is H,
    The first dielectric multilayer film, the opening, and the current injection region include a line segment that connects an edge of the upper surface of the first dielectric multilayer film and an edge of the current injection region with the shortest distance; A nitride surface emitting laser formed such that an angle θ formed with the upper surface of the first dielectric multilayer film is not less than arctan (H / W) and not more than 90 °.
  2.  前記第1誘電体多層膜の側面は、前記基板に対して垂直である、請求項1に記載の窒化物面発光レーザ。 The nitride surface-emitting laser according to claim 1, wherein a side surface of the first dielectric multilayer film is perpendicular to the substrate.
  3.  前記電流注入領域の面積は、前記第1誘電体多層膜の面積の半分以下である、請求項1に記載の窒化物面発光レーザ。 2. The nitride surface emitting laser according to claim 1, wherein an area of the current injection region is not more than half of an area of the first dielectric multilayer film.
  4.  第1半導体層と、
     前記第1半導体層の上に設けられた活性層と、
     前記活性層の上に設けられ、前記活性層から発せられた光を射出する射出窓を有する第2半導体層とを備え、
     前記第1半導体層、前記活性層および前記第2半導体層を間にして、前記第1半導体層に埋め込まれている1つの前記第1誘電体多層膜と対向する位置に設けられた第3誘電体多層膜をさらに有する、請求項1に記載の窒化物面発光レーザ。
    A first semiconductor layer;
    An active layer provided on the first semiconductor layer;
    A second semiconductor layer provided on the active layer and having an emission window for emitting light emitted from the active layer;
    A third dielectric provided at a position facing one of the first dielectric multilayer films embedded in the first semiconductor layer with the first semiconductor layer, the active layer, and the second semiconductor layer in between. The nitride surface emitting laser according to claim 1, further comprising a multilayered body film.
  5.  前記第1半導体層、前記活性層および前記第2半導体層は、GaN系化合物半導体によって構成されている、請求項4に記載の窒化物面発光レーザ。 The nitride surface-emitting laser according to claim 4, wherein the first semiconductor layer, the active layer, and the second semiconductor layer are made of a GaN-based compound semiconductor.
  6.  基板の上に設けられ、互いに隣り合う第1誘電体多層膜および第2誘電体多層膜と、
     前記第1誘電体多層膜と対向する位置に設けられた電流注入領域と、
     前記第1誘電体多層膜と前記第2誘電体多層膜との間に設けられた開口部とを備え、
     前記第1誘電体多層膜と前記第2誘電体多層膜との間の距離をW、前記第1誘電体多層膜の上面の外縁から引いた垂線と前記第1誘電体多層膜の底辺との交点から前記開口部までの距離をW’、前記第1誘電体多層膜の前記基板に対する法線方向の厚みをHとするとき、
     前記第1誘電体多層膜、前記開口部および前記電流注入領域は、前記第1誘電体多層膜の上面の端縁と、前記電流注入領域の端縁とを最短距離で結ぶ線分と、第1誘電体多層膜の上面とのなす角θが、arctan(H/(W+W’))以上90°以下となるように形成されている
     窒化物面発光レーザ。
    A first dielectric multilayer film and a second dielectric multilayer film provided on the substrate and adjacent to each other;
    A current injection region provided at a position facing the first dielectric multilayer film;
    An opening provided between the first dielectric multilayer film and the second dielectric multilayer film;
    The distance between the first dielectric multilayer film and the second dielectric multilayer film is W, the perpendicular drawn from the outer edge of the upper surface of the first dielectric multilayer film, and the bottom of the first dielectric multilayer film When the distance from the intersection to the opening is W ′, and the thickness of the first dielectric multilayer film in the normal direction to the substrate is H,
    The first dielectric multilayer film, the opening, and the current injection region include a line segment that connects the edge of the upper surface of the first dielectric multilayer film and the edge of the current injection region with the shortest distance; 1. A nitride surface emitting laser formed so that an angle θ formed with an upper surface of a dielectric multilayer film is not less than arctan (H / (W + W ′)) and not more than 90 °.
  7.  前記第1誘電体多層膜の側面の少なくとも一部は、順テーパ形状を有している、請求項6に記載の窒化物面発光レーザ。 The nitride surface emitting laser according to claim 6, wherein at least a part of a side surface of the first dielectric multilayer film has a forward tapered shape.
  8.  前記電流注入領域の面積は、前記第1誘電体多層膜の面積の半分以下である、請求項6に記載の窒化物面発光レーザ。 The nitride surface emitting laser according to claim 6, wherein an area of the current injection region is not more than half of an area of the first dielectric multilayer film.
  9.  第1半導体層と、
     前記第1半導体層の上に設けられた活性層と、
     前記活性層の上に設けられ、前記活性層から発せられた光を射出する射出窓を有する第2半導体層とを備え、
     前記第1半導体層、前記活性層および前記第2半導体層を間にして、前記第1半導体層に埋め込まれている1つの前記第1誘電体多層膜と対向する位置に設けられた第3誘電体多層膜をさらに備え、
     前記第1誘電体多層膜は、第1光反射層である、請求項6に記載の窒化物面発光レーザ。
    A first semiconductor layer;
    An active layer provided on the first semiconductor layer;
    A second semiconductor layer provided on the active layer and having an emission window for emitting light emitted from the active layer;
    A third dielectric provided at a position facing one of the first dielectric multilayer films embedded in the first semiconductor layer with the first semiconductor layer, the active layer, and the second semiconductor layer in between. Body multilayer film,
    The nitride surface emitting laser according to claim 6, wherein the first dielectric multilayer film is a first light reflecting layer.
  10.  前記第1半導体層、前記活性層および前記第2半導体層は、GaN系化合物半導体によって構成されている、請求項9に記載の窒化物面発光レーザ。 The nitride surface-emitting laser according to claim 9, wherein the first semiconductor layer, the active layer, and the second semiconductor layer are made of a GaN-based compound semiconductor.
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Citations (3)

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JPH10308558A (en) * 1997-05-07 1998-11-17 Nichia Chem Ind Ltd Nitride semiconductor laser element and its manufacture
JP2000164989A (en) * 1998-11-26 2000-06-16 Sony Corp Method of growing nitride-based iii-v compound semiconductor and semiconductor device
JP2001313440A (en) * 2000-04-27 2001-11-09 Sony Corp Nitride semiconductor light-emitting element

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014053561A (en) * 2012-09-10 2014-03-20 Canon Inc Vertical resonator surface-emitting laser
JP2015035543A (en) * 2013-08-09 2015-02-19 ソニー株式会社 Light emitting element manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10308558A (en) * 1997-05-07 1998-11-17 Nichia Chem Ind Ltd Nitride semiconductor laser element and its manufacture
JP2000164989A (en) * 1998-11-26 2000-06-16 Sony Corp Method of growing nitride-based iii-v compound semiconductor and semiconductor device
JP2001313440A (en) * 2000-04-27 2001-11-09 Sony Corp Nitride semiconductor light-emitting element

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