WO2017035871A1 - 信号转接装置及测试系统 - Google Patents

信号转接装置及测试系统 Download PDF

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Publication number
WO2017035871A1
WO2017035871A1 PCT/CN2015/089832 CN2015089832W WO2017035871A1 WO 2017035871 A1 WO2017035871 A1 WO 2017035871A1 CN 2015089832 W CN2015089832 W CN 2015089832W WO 2017035871 A1 WO2017035871 A1 WO 2017035871A1
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Prior art keywords
test
port
assembly
ports
tested
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Ceased
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PCT/CN2015/089832
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English (en)
French (fr)
Inventor
左清成
梁超
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Wuhan China Star Optoelectronics Technology Co Ltd
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/897,799 priority Critical patent/US10436820B2/en
Publication of WO2017035871A1 publication Critical patent/WO2017035871A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/20—Modifications of basic electric elements for use in electric measuring instruments; Structural combinations of such elements with such instruments
    • G01R1/206—Switches for connection of measuring instruments or electric motors to measuring loads
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/44—Testing lamps
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09236—Parallel layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09245—Crossing layout

Definitions

  • the present invention relates to the field of signal testing technologies, and in particular, to a signal switching device, and to a test system having the signal switching device.
  • the signal connection between the connection test device and the liquid crystal display module (device under test) is usually used because the interface between the module and the test device is different.
  • Device the signal connection between the connection test device and the liquid crystal display module (device under test) is usually used because the interface between the module and the test device is different.
  • FIG. 1 is a schematic structural view of a signal switching device in the prior art.
  • the test device 30 is provided with a high speed signal test port, a low speed signal test port, and a power test port.
  • Each test port is electrically connected to a corresponding measured port of the device under test 10 through the signal switching device 20, respectively.
  • each test port is electrically connected to a corresponding measured port through an electrical connection portion provided on the signal switching device 20.
  • the prior art test device 30 is electrically connected to the device under test 10 through the signal switching device 20 in conjunction with Table 1, Table 2, Figure 2 and Figure 3.
  • Test Equipment Device under test 1 D0P 2 D0N 3 CLKP 4 CLKN 5 D1P 6 D1N 7 LEDK 8 VCC 9 IOVCC 10 RESET 11 LEDA
  • a total of 11 ports to be tested are provided on the device under test 10.
  • the high-speed signal is tested on a total of six ports, namely: D0P, D0N, D1P, D1N, CLKP and CLKN ports.
  • the D0P and D0N ports form a pair of differential signal test ports
  • the D1P and D1N ports form a pair of differential signal test ports
  • the CLKP and CLKN ports form a pair of differential signal test ports.
  • There are 3 ports tested at low speed respectively LEDA, LEDK and RESET port.
  • There are two ports tested on the power supply namely VCC and IOVCC ports.
  • the DOP port is electrically connected to the test port No. 1 of the test device 30 via the signal switching device 20.
  • the D1P port is electrically coupled to the test port No. 2 of the test device 30 via the signal switching device 20.
  • the LEDA port is electrically coupled to the test port No. 11 of the test device 30 via the signal switching device 20.
  • the VCC port is electrically connected to the test port No. 1 of the test equipment 30 via the signal switching device 20.
  • the LEDK port is electrically coupled to the test port No. 2 of the test device 30 via the signal switching device 20.
  • the IOVCC port is electrically coupled to the test port No. 11 of the test device 30 via the signal switching device 20.
  • the signal switching device 20 is a matrix type switching device.
  • the printed lines (measured tracks) connected to the ports to be tested are used as rows of the matrix, and the printed lines (test tracks) connected to the respective test ports are used as columns of the matrix.
  • the intersections of the rows and columns represent electrical connections for connecting the tested printed lines and test tracks corresponding to each other.
  • the layout position of the electrical connection portion is determined by an interface definition table preset by the manufacturer.
  • a disadvantage of the signal switching device 20 in the prior art is that when the interface is defined such that there is no ground separation between the tested printed lines/test tracks for transmitting differential signals adjacent to each other, since the distance is relatively close, the printing is performed. Signal interference occurs between the lines. As the transmission speed of the liquid crystal display module increases and the signal amplitude decreases, the prior art signal switching device 20 has become a bottleneck for high speed testing.
  • the technical problem to be solved by the present invention is that when the interface is defined such that there is no ground separation between the tested printed lines/test tracks for transmitting differential signals adjacent to each other, the distance between the printed lines is easy due to the close distance. Signal interference is generated.
  • the present invention provides a signal conversion device with strong anti-interference capability and a test system having the same.
  • a signal switching device comprising:
  • each of the first assembly units including two first test assembly ports connected to the first test port and two second test assembly ports connected to the second test port, the first test port and the first
  • the second test port constitutes a pair of differential signal test ports of the test device
  • each of the second assembly units including two first measured assembly ports connecting the first port to be tested and two second measured assembly ports connected to the second port to be tested, the first The tested port and the second measured port constitute a pair of differential signal measured ports of the device under test;
  • each test assembly port passes through a corresponding gate switch and a corresponding test trace Electrical connection, each tested assembly port is electrically connected to a corresponding tested printed line through a corresponding strobe switch;
  • All test traces arranged in parallel form a grid structure with all tested traces arranged in parallel; the distance between test traces corresponding to the same test assembly port, and the measured trace corresponding to the same tested assembly port The distance between them meets the preset requirements.
  • the signal switching device further includes:
  • the third assembly unit including two third test assembly ports each connected to a power test port of the test device;
  • fourth assembly unit wherein the fourth assembly unit includes two third measured assembly ports each connected to the power-tested port of the device under test.
  • the signal switching device further includes:
  • the fifth assembly unit including two fourth test assembly ports each connected to a low speed signal test port of the test device;
  • the sixth assembly unit comprising two fourth tested assembly ports each connected to the low speed signal measured port of the device under test.
  • the test track extends in a horizontal/vertical direction, and the line to be tested extends in a vertical/horizontal direction.
  • the device under test is a liquid crystal display module.
  • a test system comprising a test device and a signal switching device, the signal switching device comprising:
  • each of the first assembly units including two first test assembly ports connected to the first test port and two second test assembly ports connected to the second test port, the first test port and the first
  • the second test port constitutes a pair of differential signal test ports of the test device
  • each of the second assembly units including two first measured assembly ports connecting the first port to be tested and two second measured assembly ports connected to the second port to be tested, the first The tested port and the second measured port constitute a pair of differential signal measured ports of the device under test;
  • each test assembly port is electrically connected to a corresponding test print line through a corresponding gate switch, and each tested assembly port is respectively Electrically connected to the corresponding printed circuit line through the corresponding strobe switch;
  • All test traces arranged in parallel form a grid structure with all tested traces arranged in parallel; the distance between test traces corresponding to the same test assembly port, and the measured trace corresponding to the same tested assembly port The distance between them meets the preset requirements.
  • the signal switching device further includes:
  • the third assembly unit including two third test assembly ports each connected to a power test port of the test device;
  • fourth assembly unit wherein the fourth assembly unit includes two third measured assembly ports each connected to the power-tested port of the device under test.
  • the signal switching device further includes:
  • the fifth assembly unit including two fourth test assembly ports each connected to a low speed signal test port of the test device;
  • the sixth assembly unit comprising two fourth tested assembly ports each connected to the low speed signal measured port of the device under test.
  • the test track extends in a horizontal/vertical direction, and the line to be tested extends in a vertical/horizontal direction.
  • the device under test is a liquid crystal display module.
  • the printing line connected to the test circuit can be flexibly selected according to the actual situation, and the test line/test line for transmitting differential signals adjacent to each other can be ensured.
  • the distance between the tested printed lines/test tracks is less likely to cause signal interference.
  • the invention can realize the effective avoidance of signals, and solves the technical problem that signal interference is easily generated between the tested printed lines/test printed lines for transmitting differential signals in the prior art.
  • FIG. 1 is a schematic structural view of a signal switching device in the prior art
  • FIG. 2 is a schematic diagram showing the layout of the electrical connection portion of the signal switching device in the prior art when the interface definition is as shown in Table 1;
  • FIG. 3 is a schematic diagram showing the layout of the electrical connection portion of the signal switching device in the prior art when the interface definition is as shown in Table 2;
  • FIG. 4 is a schematic structural diagram of a signal switching device according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram showing the layout of the electrical connection portion of the signal switching device according to the embodiment of the present invention when the interface definition is as shown in Table 3;
  • FIG. 6 is a schematic diagram showing the layout of the electrical connection portion of the signal switching device according to the embodiment of the present invention when the interface definition is as shown in Table 4.
  • the technical problem to be solved by the present invention is that when the interface is defined such that there is no ground separation between the tested printed lines/test tracks for transmitting differential signals adjacent to each other, the distance between the printed lines will be due to the close distance. Signal interference is generated.
  • the embodiment of the present invention provides a signal switching device with strong anti-interference capability.
  • FIG. 4 is a schematic structural diagram of a signal switching device according to an embodiment of the present invention.
  • the signal switching device of this embodiment mainly includes a plurality of first assembly units, a plurality of second assembly units, a plurality of gate switches 50, 70, and a circuit board 80 having the printed lines 81, 82 and the electrical connection portion 83. .
  • each first assembly unit is used to assemble a differential signal test port of test device 30.
  • the structure of each first assembly unit will be described by taking a certain first assembly unit as an example.
  • An exemplary first assembly unit is used to assemble a pair of differential signal test ports of test device 30.
  • the pair of differential signal test ports are respectively recorded as a first test port and a second test port.
  • the first assembly unit includes two first test assembly ports and two second test assembly ports. The two first test assembly ports are connected to the first test port, and the two second test assembly ports are connected to the second test port.
  • each second assembly unit is used to assemble the differential signal to be tested port of the device under test 10.
  • the structure of each second assembly unit will be described by taking a second assembly unit as an example.
  • An exemplary second assembly unit is used to assemble a pair of differential signal sensed ports of the device under test 10.
  • the pair of differential signal measured ports are respectively recorded as the first measured port and the second measured port.
  • the second assembly unit includes two first measured assembly ports and two second measured assembly ports. The two first tested assembly ports are connected to the first measured port, and the two second tested assembly ports are connected to the second measured port.
  • Each of the assembly ports of the signal switching device is provided with a gate switch 50, 70, respectively. That is, each test assembly port 60 of the signal switching device is separately provided with a gate switch 70. Each of the tested assembly ports 40 of the signal switching device is respectively provided with a gate switch 50.
  • Circuit board 80 is preferably a flexible printed circuit board.
  • the circuit board 80 includes test print lines 82 corresponding to the respective test assembly ports 60, test traces 81 corresponding to the respective test assembly ports 40, and electrical connection test traces 82 and measured traces. Electrical connection portion 81 of 81. That is, for each test assembly port 60, the circuit board 80 has a test trace 82 corresponding to the test assembly port 60. Corresponding to each of the tested assembly ports 40, the circuit board 80 has a measured printed line 81 corresponding to the tested assembly port 40. Referring to Fig. 4, all of the test tracks 82 of the signal switching device are arranged in parallel with each other, and the length direction of the test track 82 extends in the vertical direction.
  • All of the detected tracks 81 of the signal switching device are arranged in parallel with each other, and the length direction of the detected tracks 81 extends in the horizontal direction.
  • the test traces 82 are interleaved with the traces to be tested 81 to form a grid structure.
  • the test traces 82 form a column of grid structures, and the traces 81 to be tested form rows of grid structures.
  • Test assembly port 60 is electrically coupled to corresponding test traces 82 via respective gate switches 70.
  • the track to be tested 81 is electrically connected to the corresponding printed track 81 via a corresponding gate switch 50.
  • the state of loading signals of the two test tracks 82 corresponding to the same test port can be determined by controlling the open/close state of the strobe switch 70.
  • the two test traces 82 can alternatively load the signals or simultaneously load the signals, depending on the relationship between the actual signals.
  • the state of loading signals of the two tested printed lines 81 corresponding to the same port under test can be determined by controlling the open/close state of the strobe switch 50.
  • the two tested tracks 81 can be loaded with signals alternatively or simultaneously. That is, in the specific implementation process, the opening and closing state of the gating switch is determined according to the relationship between the actual signals, so as to effectively avoid the signal.
  • the electrical connection 83 is used to connect the corresponding test trace 82 and the trace to be tested 81 to close the test loop.
  • the electrical connection portion 83 is preferably a via or a tin.
  • the distance between the test tracks 82 corresponding to the same test assembly port 60, and the corresponding The distance between the tested printed lines 81 of the test assembly port 40 satisfies the preset requirements.
  • the distance between the test traces 82 is such that the distance D2 between the test traces 82 for transmitting the differential signals is at least greater than 2 line widths.
  • the distance between the above-mentioned tested printed lines 81 needs to be satisfied: the distance D1 between the tested printed lines 81 for transmitting differential signals is at least greater than 2 times the line width.
  • the signal switching device further includes one or more third assembly units and one or more fourth assembly units.
  • Each of the third assembly units includes two power test ports that are each connected to the test device 30.
  • Each of the fourth assembly units includes two third measured assembly ports each connected to the power-tested port of the device under test 10.
  • the signal switching device further includes a gate switch and a printed line corresponding to the newly added assembly ports (two third test assembly ports and two third measured assembly ports) of the present embodiment.
  • the connection manner of the assembly port, the strobe switch and the printed circuit in this embodiment is the same as that in the above embodiment, and details are not described herein again.
  • the signal switching device further includes one or more fifth assembly units and one or more sixth assembly units.
  • Each of the fifth assembly units includes two fourth test assembly ports that are each connected to the low speed signal test port of the test equipment 30.
  • Each of the sixth assembly units includes two fourth measured assembly ports each connected to the low speed signal measured port of the device under test 10.
  • the signal switching device further includes a gate switch and a printed line corresponding to the newly added assembly ports (two fourth test assembly ports and two fourth measured assembly ports) of the present embodiment.
  • the connection manner of the assembly port, the strobe switch and the printed circuit in this embodiment is the same as that in the above embodiment, and details are not described herein again.
  • test device 30 is electrically connected to the device under test 10 by the signal switching device of the embodiment of the present invention in conjunction with Tables 3, 4, 5 and 6.
  • Test Equipment Device under test 1 RESET 2 D0N 3 D0P 4 D1N 5 D1P 6 CLKN 7 CLKP 8 VCC 9 LEDK 10 LEDA 11 IOVCC
  • a total of 11 ports to be tested are provided on the device under test 10.
  • the high-speed signal is tested on a total of six ports, namely: D0P, D0N, D1P, D1N, CLKP and CLKN ports.
  • the DOP port of the D0P forms a pair of differential signal test ports
  • the D1P and D1N ports form a pair of differential signal test ports
  • the CLKP and CLKN ports form a pair of differential signal test ports.
  • There are 3 ports tested at low speed which are LEDA, LEDK and RESET port.
  • There are two ports tested on the power supply namely VCC and IOVCC ports.
  • the RESET port is electrically coupled to the test port No. 1 of the test device 30 via a signal switching device.
  • the DON port is electrically connected to the test port No. 2 of the test device 30 through a signal switching device.
  • the IOVCC port is electrically connected to the test port No. 11 of the test device 30 via a signal switching device.
  • the LEDK port is electrically coupled to the test port No. 1 of the test device 30 via a signal switching device.
  • the CLKN port is electrically coupled to the test port No. 2 of the test device 30 via a signal switching device.
  • the IOVCC port is electrically connected to the test port No. 11 of the test device 30 via a signal switching device.
  • 5 and 6 respectively show the layout of the electrical connection portion 83 of the signal switching device when the interface definition is as shown in Tables 3 and 4.
  • the strobe switch determines whether the two test/test assembly traces load the signal in an alternative manner or all load signals.
  • the printed lines corresponding to all the test ports and the corresponding printed lines of all the tested ports are loaded with signals in an alternative manner.
  • the electrical connection portion 83 is provided in the manner shown in Fig. 5, and the signal interference between the test printed circuit 82 for transmitting the differential signal/the detected printed wiring 81 can be minimized.
  • the electrical connection portion 83 is provided in the manner shown in Fig. 6, which can minimize the signal interference between the test printed line 82/the detected printed line 81 for transmitting differential signals.
  • the device under test 10 is preferably a liquid crystal display module.
  • the test device 30 tests the liquid crystal display module by the signal switching device of the embodiment of the present invention.
  • an embodiment of the present invention further provides a test system.
  • the test system includes a test device 30 and a signal switching device in the above embodiment. Since the structure of the signal switching device has been described in detail above, it will not be described again here.
  • the signal switching device can be flexibly selected to access the test line of the test circuit according to the actual situation, and the tested printed line 81 for transmitting differential signals adjacent to each other can be ensured. / Test the sufficient distance between the printed lines 82 so that signal interference between the tested printed lines 81/test tracks 82 is less likely to occur.
  • the embodiment of the invention can realize the effective avoidance of the signal, and solves the technical problem that the signal line interference between the tested printed line 81 and the test printed line 82 for transmitting the differential signal adjacent to each other in the prior art is easy to generate.
  • the embodiment on the basis of the preset interface definition, not only the differential pair routing but also the serpentine routing can be realized, and the flexibility is strong.

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  • General Physics & Mathematics (AREA)
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Abstract

一种信号转接装置及测试系统。信号转接装置包括多个第一装配单元、多个第二装配单元、多个选通开关（50、70）以及具有印制线（81、82）和电连接部（83）的电路板（80），每个第一装配单元包括连接第一测试端口的两个第一测试装配端口（60）和连接第二测试端口的两个第二测试装配端口（60），第一测试端口和第二测试端口构成测试设备的一对差分信号测试端口；每个第二装配单元包括连接第一被测端口的两个第一被测装配端口（40）和连接第二被测端口的两个第二被测装配端口（40），所述第一被测端口和第二被测端口构成被测设备的一对差分信号被测端口；对应同一测试装配端口（60）的测试印制线（82）间的距离，和对应同一被测装配端口（40）的被测印制线间（81）的距离均满足预设要求。可灵活地根据实际情况选择接入测试回路的印制线，保证相互邻近的用于传输差分信号的被测印制线（81）/测试印制线（82）间充足的距离，使印制线间不易产生信号干扰。

Description

信号转接装置及测试系统
本申请要求享有2015年8月28日提交的名称为“信号转接装置及测试系统”的中国专利申请CN201510540407.8的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及信号测试技术领域，尤其涉及一种信号转接装置，还涉及一种具有该信号转接装置的测试系统。
背景技术
目前，在生产测试液晶显示模组(LCM,Liquid Crystal Module)的过程中，由于模组和测试设备的接口不同，通常会利用连接测试设备与液晶显示模组(被测设备)的信号转接装置。
图1示出了现有技术中信号转接装置的结构示意图。如图1所示，测试设备30设有高速信号测试端口、低速信号测试端口和电源测试端口。各测试端口分别通过信号转接装置20与被测设备10的相应被测端口电连接。一般来讲，各测试端口与对应的被测端口通过设置在信号转接装置20上的电连接部电连接。
下面结合表1、表2、图2和图3详细描述现有技术中测试设备30是如何通过信号转接装置20与被测设备10电连接的。
表1
测试设备 被测设备
1 D0P
2 D0N
3 CLKP
4 CLKN
5 D1P
6 D1N
7 LEDK
8 VCC
9 IOVCC
10 RESET
11 LEDA
表2
测试设备 被测设备
1 VCC
2 LEDK
3 D1P
4 D1N
5 CLKP
6 CLKN
7 D0N
8 D0P
9 RESET
10 LEDA
11 IOVCC
参照表1和表2所示的接口定义，被测设备10上共设有11个被测端口。其中，高速信号被测端口共6个，分别为：D0P、D0N、D1P、D1N、CLKP和CLKN端口。这里，D0P和D0N端口形成一对差分信号被测端口，D1P和D1N端口形成一对差分信号被测端口，CLKP和CLKN端口形成一对差分信号被测端口。低速信号被测端口共3个，分别为 LEDA、LEDK和RESET端口。电源被测端口共2个，分别为VCC和IOVCC端口。根据表1，D0P端口通过信号转接装置20与测试设备30的1号测试端口电连接。D1P端口通过信号转接装置20与测试设备30的2号测试端口电连接。以此类推，LEDA端口通过信号转接装置20与测试设备30的11号测试端口电连接。根据表2，VCC端口通过信号转接装置20与测试设备30的1号测试端口电连接。LEDK端口通过信号转接装置20与测试设备30的2号测试端口电连接。以此类推，IOVCC端口通过信号转接装置20与测试设备30的11号测试端口电连接。
图2和图3分别示出了接口定义如表1和表2所示时信号转接装置20上电连接部的布设示意图。参照图2和图3，信号转接装置20为矩阵型转接装置。与各被测端口连接的印制线(被测印制线)作为矩阵的行，与各测试端口连接的印制线(测试印制线)作为矩阵的列。行列的交叉点(如图2和图3中所示的实心圆点)代表用于连接彼此对应的被测印制线和测试印制线的电连接部。电连接部的布设位置由厂家预设的接口定义表确定。
现有技术中信号转接装置20的缺陷在于：当接口定义使得相互邻近的用于传输差分信号的被测印制线/测试印制线间无地线隔离时，由于距离较近，在印制线间会产生信号干扰。随着液晶显示模组传输速度的提升及信号幅度的降低，现有技术中的信号转接装置20已成为高速测试的瓶颈。
发明内容
本发明所要解决的技术问题是：当接口定义使得相互邻近的用于传输差分信号的被测印制线/测试印制线间无地线隔离时，由于距离较近，在印制线间易产生信号干扰。为了解决上述技术问题，本发明提供了一种抗干扰能力强的信号转接装置及具有该信号转接装置的测试系统。
根据本发明的一个方面，提供了一种信号转接装置，其包括：
多个第一装配单元，每个第一装配单元包括连接第一测试端口的两个第一测试装配端口和连接第二测试端口的两个第二测试装配端口，所述第一测试端口和第二测试端口构成测试设备的一对差分信号测试端口；
多个第二装配单元，每个第二装配单元包括连接第一被测端口的两个第一被测装配端口和连接第二被测端口的两个第二被测装配端口，所述第一被测端口和第二被测端口构成被测设备的一对差分信号被测端口；
分别对应各个装配端口的选通开关；以及
电路板，其包括分别对应各个测试装配端口的测试印制线、分别对应各个被测装配端 口的被测印制线、以及用于电连接所述测试印制线和所述被测印制线的电连接部；各个测试装配端口分别通过相应的选通开关与相应的测试印制线电连接，各个被测装配端口分别通过相应的选通开关与相应的被测印制线电连接；
平行排列的所有测试印制线与平行排列的所有被测印制线形成网格结构；对应同一测试装配端口的测试印制线间的距离，和对应同一被测装配端口的被测印制线间的距离均满足预设要求。
优选的是，上述信号转接装置还包括：
第三装配单元，所述第三装配单元包括均连接所述测试设备的电源测试端口的两个第三测试装配端口；以及
第四装配单元，所述第四装配单元包括均连接所述被测设备的电源被测端口的两个第三被测装配端口。
优选的是，上述信号转接装置还包括：
第五装配单元，所述第五装配单元包括均连接所述测试设备的低速信号测试端口的两个第四测试装配端口；以及
第六装配单元，所述第六装配单元包括均连接所述被测设备的低速信号被测端口的两个第四被测装配端口。
优选的是，所述测试印制线沿水平/垂直方向延伸，所述被测印制线沿垂直/水平方向延伸。
优选的是，所述被测设备为液晶显示模组。
根据本发明的另一个方面，提供了一种测试系统，其包括测试设备和信号转接装置，所述信号转接装置包括：
多个第一装配单元，每个第一装配单元包括连接第一测试端口的两个第一测试装配端口和连接第二测试端口的两个第二测试装配端口，所述第一测试端口和第二测试端口构成所述测试设备的一对差分信号测试端口；
多个第二装配单元，每个第二装配单元包括连接第一被测端口的两个第一被测装配端口和连接第二被测端口的两个第二被测装配端口，所述第一被测端口和第二被测端口构成被测设备的一对差分信号被测端口；
分别对应各个装配端口的选通开关；以及
电路板，其包括分别对应各个测试装配端口的测试印制线、分别对应各个被测装配端口的被测印制线、以及用于电连接所述测试印制线和所述被测印制线的电连接部；各个测试装配端口分别通过相应的选通开关与相应的测试印制线电连接，各个被测装配端口分别 通过相应的选通开关与相应的被测印制线电连接；
平行排列的所有测试印制线与平行排列的所有被测印制线形成网格结构；对应同一测试装配端口的测试印制线间的距离，和对应同一被测装配端口的被测印制线间的距离均满足预设要求。
优选的是，所述信号转接装置还包括：
第三装配单元，所述第三装配单元包括均连接所述测试设备的电源测试端口的两个第三测试装配端口；以及
第四装配单元，所述第四装配单元包括均连接所述被测设备的电源被测端口的两个第三被测装配端口。
优选的是，所述信号转接装置还包括：
第五装配单元，所述第五装配单元包括均连接所述测试设备的低速信号测试端口的两个第四测试装配端口；以及
第六装配单元，所述第六装配单元包括均连接所述被测设备的低速信号被测端口的两个第四被测装配端口。
优选的是，所述测试印制线沿水平/垂直方向延伸，所述被测印制线沿垂直/水平方向延伸。
优选的是，所述被测设备为液晶显示模组。
与现有技术相比，上述方案中的一个或多个实施例可以具有如下优点或有益效果：
应用本发明所述的信号转接装置，可灵活地根据实际情况选择接入测试回路的印制线，可保证相互邻近的用于传输差分信号的被测印制线/测试印制线间充足的距离，从而使该被测印制线/测试印制线间不易产生信号干扰。本发明能够实现信号的有效避让，解决了现有技术中相互邻近的用于传输差分信号的被测印制线/测试印制线间易产生信号干扰的技术问题。
本发明的其它特征和优点将在随后的说明书中阐述，并且部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：
图1示出了现有技术中信号转接装置的结构示意图；
图2示出了接口定义如表1所示时，现有技术中信号转接装置上电连接部的布设示意图；
图3示出了接口定义如表2所示时，现有技术中信号转接装置上电连接部的布设示意图；
图4示出了本发明实施例信号转接装置的结构示意图；
图5示出了接口定义如表3所示时，本发明实施例信号转接装置上电连接部的布设示意图；以及
图6示出了接口定义如表4所示时，本发明实施例信号转接装置上电连接部的布设示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
本发明要解决的技术问题是：当接口定义使得相互邻近的用于传输差分信号的被测印制线/测试印制线间无地线隔离时，由于距离较近，在印制线间会产生信号干扰。为了解决上述技术问题，本发明实施例提供了一种抗干扰能力强的信号转接装置。
如图4所示，是本发明实施例信号转接装置的结构示意图。本实施例的信号转接装置，主要包括多个第一装配单元、多个第二装配单元、多个选通开关50,70以及具有印制线81,82和电连接部83的电路板80。
具体地，每个第一装配单元用于装配测试设备30的差分信号测试端口。以某一个第一装配单元为例说明各个第一装配单元的结构。示例的第一装配单元用于装配测试设备30的一对差分信号测试端口。这一对差分信号测试端口分别记为第一测试端口和第二测试端口。第一装配单元包括两个第一测试装配端口和两个第二测试装配端口。其中，两个第一测试装配端口均连接第一测试端口，两个第二测试装配端口均连接第二测试端口。
相对应地，每个第二装配单元用于装配被测设备10的差分信号被测端口。以某一个第二装配单元为例说明各个第二装配单元的结构。示例的第二装配单元用于装配被测设备10的一对差分信号被测端口。这一对差分信号被测端口分别记为第一被测端口和第二被测端口。第二装配单元包括两个第一被测装配端口和两个第二被测装配端口。其中，两个第一被测装配端口均连接第一被测端口，两个第二被测装配端口均连接第二被测端口。
信号转接装置的每个装配端口分别配置有一个选通开关50,70。即，信号转接装置的每个测试装配端口60分别配置有一个选通开关70。信号转接装置的每个被测装配端口40分别配置有一个选通开关50。
电路板80优选为柔性印刷电路板。电路板80包括分别对应各个测试装配端口60的测试印制线82、分别对应各个被测装配端口40的被测印制线81、以及用于电连接测试印制线82和被测印制线81的电连接部83。即，对应每个测试装配端口60，电路板80具有与该测试装配端口60相对应的测试印制线82。对应每个被测装配端口40，电路板80具有与该被测装配端口40相对应的被测印制线81。参照图4，信号转接装置的所有测试印制线82彼此平行排列，测试印制线82的长度方向沿垂直方向延伸。信号转接装置的所有被测印制线81彼此平行排列，被测印制线81的长度方向沿水平方向延伸。测试印制线82与被测印制线81交错形成网格结构。测试印制线82形成网格结构的列，被测印制线81形成网格结构的行。
测试装配端口60通过相应的选通开关70与相应的测试印制线82电连接。同样地，被测印制线81通过相应的选通开关50与相应的被测印制线81电连接。在具体实施过程中，可通过控制选通开关70的开闭状态来决定对应同一测试端口的两条测试印制线82加载信号的状态。两条测试印制线82可以择一地加载信号，也可以同时加载信号，具体根据实际信号间的关系决定。同样地，可通过控制选通开关50的开闭状态来决定对应同一被测端口的两条被测印制线81加载信号的状态。两条被测印制线81可以择一地加载信号，也可以同时加载信号。即在具体实施过程中，根据实际信号间的关系来确定选通开关的开闭状态，以进行信号的有效避让。
选通开关的状态确定后，也即确定了电连接部83的设置位置。电连接部83用于连接相应的测试印制线82和被测印制线81，以闭合测试回路。特别地，电连接部83优选为过孔或者点锡。
另外，为了有效减少邻近的用于传输差分信号的被测印制线81/测试印制线82间的信号干扰，对应同一测试装配端口60的测试印制线82间的距离，和对应同一被测装配端口40的被测印制线81间的距离均满足预设要求。在本发明一优选的实施例中，上述测试印制线82间的距离需满足：用于传输差分信号的测试印制线82间的距离D2至少大于2倍线宽。上述被测印制线81间的距离需满足：用于传输差分信号的被测印制线81间的距离D1至少大于2倍线宽。
在本发明一优选的实施例中，上述信号转接装置还包括一个或多个第三装配单元和一个或多个第四装配单元。每个第三装配单元包括均连接测试设备30的电源测试端口的两 个第三测试装配端口。每个第四装配单元包括均连接被测设备10的电源被测端口的两个第三被测装配端口。相应地，信号转接装置还包括与本实施例新增的装配端口(两个第三测试装配端口和两个第三被测装配端口)相对应的选通开关以及印制线。本实施例中装配端口、选通开关与印制线的连接方式与上述实施例相同，在此不再赘述。
在本发明一优选的实施例中，上述信号转接装置还包括一个或多个第五装配单元和一个或多个第六装配单元。每个第五装配单元包括均连接测试设备30的低速信号测试端口的两个第四测试装配端口。每个第六装配单元包括均连接被测设备10的低速信号被测端口的两个第四被测装配端口。相应地，信号转接装置还包括与本实施例新增的装配端口(两个第四测试装配端口和两个第四被测装配端口)相对应的选通开关以及印制线。本实施例中装配端口、选通开关与印制线的连接方式与上述实施例相同，在此不再赘述。
下面结合表3、表4、图5和图6详细描述测试设备30是如何通过本发明实施例的信号转接装置与被测设备10电连接的。
表3
测试设备 被测设备
1 RESET
2 D0N
3 D0P
4 D1N
5 D1P
6 CLKN
7 CLKP
8 VCC
9 LEDK
10 LEDA
11 IOVCC
表4
测试设备 被测设备
1 LEDK
2 CLKN
3 CLKP
4 D1N
5 D1P
6 D0N
7 D0P
8 VCC
9 RESET
10 LEDA
11 IOVCC
参照表3和表4所示的接口定义，被测设备10上共设有11个被测端口。其中，高速信号被测端口共6个，分别为：D0P、D0N、D1P、D1N、CLKP和CLKN端口。这里，D0P的D0N端口形成一对差分信号被测端口，D1P和D1N端口形成一对差分信号被测端口，CLKP和CLKN端口形成一对差分信号被测端口。低速信号被测端口共3个，分别为LEDA、LEDK和RESET端口。电源被测端口共2个，分别为VCC和IOVCC端口。针对表1，RESET端口通过信号转接装置与测试设备30的1号测试端口电连接。D0N端口通过信号转接装置与测试设备30的2号测试端口电连接。以此类推，IOVCC端口通过信号转接装置与测试设备30的11号测试端口电连接。针对表2，LEDK端口通过信号转接装置与测试设备30的1号测试端口电连接。CLKN端口通过信号转接装置与测试设备30的2号测试端口电连接。以此类推，IOVCC端口通过信号转接装置与测试设备30的11号测试端口电连接。
图5和图6分别示出了接口定义如表3和表4所示时信号转接装置上电连接部83的布设示意图。对于每个测试/被测端口，分别有两个测试/被测装配端口与该测试/被测端口电连接。通过选通开关来决定两条测试/被测装配印制线以择一的方式加载信号还是全部都加载信号。
参照图5，所有测试端口对应的印制线和所有被测端口对应的印制线都以择一地方式加载信号。根据表3的接口定义，按照图5所示的方式设置电连接部83，能最大程度地减少用于传输差分信号的测试印制线82/被测印制线81间的信号干扰。
参照图6，仅IOVCC端口、所有差分信号被测端口对应的印制线和所有差分信号测试端口对应的印制线以择一地方式加载信号。根据表4的接口定义，按照图6所示的方式设置电连接部83，能最大程度地减少用于传输差分信号的测试印制线82/被测印制线81间的信号干扰。
在本发明一优选的实施例中，上述被测设备10优选为液晶显示模块。测试设备30通过本发明实施例的信号转接装置对液晶显示模块进行测试。
相应地，本发明实施例还提供了一种测试系统。该测试系统包括测试设备30和上述实施例中的信号转接装置。由于上文已对信号转接装置的结构进行了详细阐述，故在此不再进行赘述。
综上所述，应用本实施例所述的信号转接装置，可灵活地根据实际情况选择接入测试回路的印制线，可保证相互邻近的用于传输差分信号的被测印制线81/测试印制线82间充足的距离，从而使该被测印制线81/测试印制线82间不易产生信号干扰。本发明实施例能够实现信号的有效避让，解决了现有技术中相互邻近的用于传输差分信号的被测印制线81/测试印制线82间易产生信号干扰的技术问题。另外，应用本实施例，在预设的接口定义的基础上，不仅可以实现差分对走线，还可以实现蛇形走线，灵活性强。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (18)

  1. 一种信号转接装置，包括：
    多个第一装配单元，每个所述第一装配单元包括连接第一测试端口的两个第一测试装配端口和连接第二测试端口的两个第二测试装配端口，所述第一测试端口和第二测试端口构成测试设备的一对差分信号测试端口；
    多个第二装配单元，每个所述第二装配单元包括连接第一被测端口的两个第一被测装配端口和连接第二被测端口的两个第二被测装配端口，所述第一被测端口和第二被测端口构成被测设备的一对差分信号被测端口；
    分别对应各个装配端口的选通开关；以及
    电路板，其包括分别对应各个测试装配端口的测试印制线、分别对应各个被测装配端口的被测印制线、以及用于电连接所述测试印制线和所述被测印制线的电连接部；各个测试装配端口分别通过相应的选通开关与相应的测试印制线电连接，各个被测装配端口分别通过相应的选通开关与相应的被测印制线电连接；
    平行排列的所有测试印制线与平行排列的所有被测印制线形成网格结构；对应同一测试装配端口的测试印制线间的距离，和对应同一被测装配端口的被测印制线间的距离均满足预设要求。
  2. 根据权利要求1所述的信号转接装置，其中，所述测试印制线沿水平/垂直方向延伸，所述被测印制线沿垂直/水平方向延伸。
  3. 根据权利要求1所述的信号转接装置，其中，所述被测设备为液晶显示模组。
  4. 根据权利要求1所述的信号转接装置，其中，还包括：
    第三装配单元，其包括均连接所述测试设备的电源测试端口的两个第三测试装配端口；以及
    第四装配单元，其包括均连接所述被测设备的电源被测端口的两个第三被测装配端口。
  5. 根据权利要求4所述的信号转接装置，其中，所述测试印制线沿水平/垂直方向延伸，所述被测印制线沿垂直/水平方向延伸。
  6. 根据权利要求4所述的信号转接装置，其中，所述被测设备为液晶显示模组。
  7. 根据权利要求1所述的信号转接装置，其中，还包括：
    第五装配单元，其包括均连接所述测试设备的低速信号测试端口的两个第四测试装配端口；以及
    第六装配单元，其包括均连接所述被测设备的低速信号被测端口的两个第四被测装配 端口。
  8. 根据权利要求7所述的信号转接装置，其中，所述测试印制线沿水平/垂直方向延伸，所述被测印制线沿垂直/水平方向延伸。
  9. 根据权利要求7所述的信号转接装置，其中，所述被测设备为液晶显示模组。
  10. 一种测试系统，包括测试设备和信号转接装置，所述信号转接装置包括：
    多个第一装配单元，每个所述第一装配单元包括连接第一测试端口的两个第一测试装配端口和连接第二测试端口的两个第二测试装配端口，所述第一测试端口和第二测试端口构成所述测试设备的一对差分信号测试端口；
    多个第二装配单元，每个所述第二装配单元包括连接第一被测端口的两个第一被测装配端口和连接第二被测端口的两个第二被测装配端口，所述第一被测端口和第二被测端口构成被测设备的一对差分信号被测端口；
    分别对应各个装配端口的选通开关；以及
    电路板，其包括分别对应各个测试装配端口的测试印制线、分别对应各个被测装配端口的被测印制线、以及用于电连接所述测试印制线和所述被测印制线的电连接部；各个测试装配端口分别通过相应的选通开关与相应的测试印制线电连接，各个被测装配端口分别通过相应的选通开关与相应的被测印制线电连接；
    平行排列的所有测试印制线与平行排列的所有被测印制线形成网格结构；对应同一测试装配端口的测试印制线间的距离，和对应同一被测装配端口的被测印制线间的距离均满足预设要求。
  11. 根据权利要求10所述的测试系统，其中，所述测试印制线沿水平/垂直方向延伸，所述被测印制线沿垂直/水平方向延伸。
  12. 根据权利要求10所述的测试系统，其中，所述被测设备为液晶显示模组。
  13. 根据权利要求10所述的测试系统，其中，所述信号转接装置还包括：
    第三装配单元，其包括均连接所述测试设备的电源测试端口的两个第三测试装配端口；以及
    第四装配单元，其包括均连接所述被测设备的电源被测端口的两个第三被测装配端口。
  14. 根据权利要求13所述的测试系统，其中，所述测试印制线沿水平/垂直方向延伸，所述被测印制线沿垂直/水平方向延伸。
  15. 根据权利要求13所述的测试系统，其中，所述被测设备为液晶显示模组。
  16. 根据权利要求10所述的测试系统，其中，所述信号转接装置还包括：
    第五装配单元，其包括均连接所述测试设备的低速信号测试端口的两个第四测试装配端口；以及
    第六装配单元，其包括均连接所述被测设备的低速信号被测端口的两个第四被测装配端口。
  17. 根据权利要求16所述的测试系统，其中，所述测试印制线沿水平/垂直方向延伸，所述被测印制线沿垂直/水平方向延伸。
  18. 根据权利要求16所述的测试系统，其中，所述被测设备为液晶显示模组。
PCT/CN2015/089832 2015-08-28 2015-09-17 信号转接装置及测试系统 Ceased WO2017035871A1 (zh)

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