WO2017033243A1 - Liquid crystal display device and method for driving liquid crystal display device - Google Patents

Abstract

Provided are a liquid crystal display device and a method for driving a liquid crystal display device with which it is possible to prevent an optimal counter voltage of a counter electrode that opposes a subpixel electrode included in a pixel from deviating from a preset counter voltage. Each of pixels P arranged in a matrix includes at least first and second subpixels each defined by including an electrode pair consisting of a subpixel electrode and a counter electrode opposing one another via a liquid crystal layer. A scan signal is applied from a scan signal line Gm for each row in the matrix to a gate electrode of a TFT for applying a data signal from a source signal line SL to the subpixel electrode included in each of the first and second subpixels. A discharge capacity electrode is connected to the subpixel electrode of the second subpixel via another TFT. The leading edge of a discharge signal applied from a discharge signal line Gs for each row in the matrix to a gate electrode of said other TFT is delayed by a predetermined time or longer from the trailing edge of a scan signal for a subsequent row.

Description

Liquid crystal display device and driving method of liquid crystal display device

The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device that improves the viewing angle dependency of gamma characteristics and a driving method of the liquid crystal display device.

The liquid crystal display device is a flat display device having excellent features such as high definition, thinness, light weight, and low power consumption, and is widely used for thin televisions, personal computer monitors, digital signage, and the like.

Conventionally, a commonly used TN (Twisted Nematic) mode liquid crystal display device has excellent productivity, but has a problem in viewing angle characteristics related to screen display. For example, when the display screen is viewed obliquely with respect to the normal line, the contrast ratio is remarkably lowered in the TN mode liquid crystal display device, and the luminance difference between gradations becomes remarkably unclear. In addition, a so-called gradation inversion phenomenon may be observed in which a portion that appears bright (or dark) when viewed from the front is viewed dark (or bright) when viewed from an oblique direction with respect to the normal.

Some liquid crystal display devices that improve the above-described viewing angle characteristics display in display modes such as an IPS (In-Plan Switching) mode and an MVA (Multi-domain Vertical Alignment) mode. A technique for realizing a display mode in these liquid crystal display devices is widely used as a technique for improving viewing angle characteristics.

As one of the problems of viewing angle characteristics, there is a problem that the gamma characteristics representing the gradation dependence of display luminance depend on the angle of the line of sight with respect to the normal of the display screen (hereinafter referred to as viewing angle dependence of the gamma characteristics). . This problem is that the gradation display state differs depending on the viewing direction with respect to the display screen, and the gamma characteristics differ between the case where the viewing direction is along the normal line of the display screen and the case where the viewing direction is oblique to the normal line. Is to be observed.

On the other hand, Non-Patent Document 1 discloses a liquid crystal display device that improves the viewing angle dependence of gamma characteristics (referred to as viewing angle dependence in some literatures). In the liquid crystal display device described in Non-Patent Document 1, each pixel includes a first subpixel and a second subpixel, and a discharge capacitance (Cdown) is provided in the second subpixel. The subpixel electrodes of the first and second subpixels are alternately different for each pixel in the vertical direction of the display screen via TFT1 and TFT2 to which a scanning signal (gate signal) is applied from the scanning signal line to the control electrode. Connected to the data signal line (source signal line), two lines are scanned simultaneously. As for the discharge capacity, the discharge capacity electrode facing the counter electrode is connected to the sub-pixel electrode of the second sub-pixel via the TFT 3. A discharge signal line for applying a discharge signal to the control electrode of the TFT 3 is connected to the scanning signal line behind two lines.

In the liquid crystal display device described in Non-Patent Document 1, a discharge signal delayed by one horizontal scanning period (1H) from the scanning signal for each pixel is applied to the control electrode of the TFT 3 for each pixel. In this way, by connecting the sub-pixel electrode and the discharge capacitance electrode of the second sub-pixel according to the signal delayed by 1H from the scanning signal, the effective voltage applied to the liquid crystal layer by each of the first and second sub-pixels can be obtained. Can be changed. In this case, each pixel is observed in a state in which different gamma characteristics are harmonized for each sub-pixel, so that the viewing angle dependency of the gamma characteristics is improved.

In addition, the liquid crystal display device described in Patent Document 1 includes first and second sub-pixels each having a sub-pixel electrode connected to the first and second storage capacitors. A third capacitor (corresponding to the discharge capacitor) is connected to the subpixel electrodes of the two subpixels via a third switching element (corresponding to the TFT 3). The subpixel electrodes of the first and second subpixels are connected to a data signal line via first and second switching elements (corresponding to the TFTs 1 and 2). A first gate signal (corresponding to the scanning signal) is applied to the control electrodes of the first and second switching elements from a first gate line (corresponding to the scanning signal line). A second gate signal (corresponding to the discharge signal) is applied from the second gate line (corresponding to the discharge signal line) to the control electrode of the third switching element. By turning on the third switching element to which the second gate signal is applied after the first gate signal, the sub-pixel electrode of the second sub-pixel is connected to the third capacitor, and the second sub-pixel is connected to the liquid crystal layer. The effective voltage applied to is changed.

The liquid crystal display device described in Patent Document 1 is characterized in that a part of the first gate signal overlaps the first line and the second line (similarly the third line and the fourth line), It is preferable to make the second gate signal of the first line substantially the same as the first gate signal of the third line. This means that part of the signal overlaps with the first gate signal on the second line and the second gate signal on the first line. For this reason, in the drawing described in Patent Document 1, in all the drawings scanned one line at every 1H, a part of the signal is generated by the first gate signal of the second line and the second gate signal of the first line. Or all overlap. In the case where two lines are scanned simultaneously, a part or all of the signals are overlapped by the first gate signal of the third and fourth lines and the second gate signal of the first and second lines.

By the way, in the TFT, due to the influence of the parasitic capacitance between the gate and the drain, a feedthrough voltage (so-called pull-in voltage) is generated when the drive voltage to the gate falls, and the drain voltage (that is, the sub-pixel electrode) is lowered. Are known. In addition to this phenomenon, the voltage of the subpixel electrode of the first subpixel is particularly limited to one due to the influence of other parasitic capacitance existing between each subpixel electrode and the discharge signal line (or the second gate line). A phenomenon may be observed in which the discharge signal (or the second gate signal) of the previous line slightly increases and decreases when the discharge signal (or the second gate signal) rises and falls. For example, when there is no signal overlap between the scanning signal (or the first gate signal) and the discharge signal (or the second gate signal) of the previous line, the influence at the time of rising and falling is affected by each subpixel electrode. The above phenomenon is difficult to observe because it is offset appropriately.

US Pat. No. 8,854,561

However, in the liquid crystal display device described in Non-Patent Document 1, in the two lines that are scanned simultaneously, the first line in which the first subpixel of the first line is turned on at the same timing as the scanning signal of the first line The first subpixel of the second line is affected by the discharge signal of the first line that rises at substantially the same timing as the fall of the scanning signal of the second line. For this reason, in any of the first sub-pixels, there is a possibility that the influence of the rise and fall of the voltage of the sub-pixel electrode generated at the rise and fall of the discharge signal may not be sufficiently offset, There has been a problem that the counter voltage optimum for the counter electrodes facing each other deviates from a preset counter voltage (hereinafter referred to as counter voltage shift).

In addition, in the liquid crystal display device described in Patent Document 1, the delay time of the rise of the second gate signal with respect to the fall of the first gate signal is within 1H for any line scanned by the first gate signal. Therefore, there is a case where a signal overlap occurs between the discharge signal of one line and the scanning signal of the second line following the one line, thereby causing a counter voltage shift. Specifically, when one line is scanned every 1H, a counter voltage shift occurs in the first subpixel of any line, and when two lines are scanned simultaneously, the first subpixel of the first line is scanned. A counter voltage shift occurs in the pixel.

The present invention has been made in view of such circumstances, and the object of the present invention is to make the counter voltage optimum for the counter electrode opposed to the sub-pixel electrode included in the pixel deviate from the preset counter voltage. It is an object of the present invention to provide a liquid crystal display device and a driving method of the liquid crystal display device that can prevent the above-described problem.

In the liquid crystal display device according to the present invention, pixels having at least first and second sub-pixels defined including a sub-pixel electrode and a counter-electrode pair facing each other through a liquid crystal layer are arranged in a matrix. , First and second switching elements for applying a data signal to subpixel electrodes included in the first and second subpixels, and a scanning signal on a control electrode of the first and second switching elements. A scanning signal line to be applied to each row; a discharge capacity electrode included in the second subpixel; a pair of discharge capacity counter electrodes connected to a predetermined potential; a subpixel electrode of the second subpixel; A third switching element connected between the discharge capacitance electrodes, and a discharge signal for turning on the third switching element to the control electrode of the third switching element for applying to each row of the matrix In the liquid crystal display device and a telegraph Route, the leading edge of the discharge signal is characterized by delayed more than a predetermined time than the trailing edge of the scanning signal line after one.

In the liquid crystal display device according to the present invention, the first and second sub-pixels are disposed in a direction that is in tolerance with the discharge signal line, and the discharge signal line is adjacent to the first adjacent pixel in the direction. And the second sub-pixel.

The liquid crystal display device according to the present invention is characterized in that the polarity of the data signal applied to the first and second sub-pixels is inverted every frame period.

In the liquid crystal display device according to the present invention, each of the first and second subpixels includes an electrode pair of an auxiliary capacitance electrode connected to the subpixel electrode and an auxiliary capacitance counter electrode connected to the predetermined potential. It is demarcated.

The liquid crystal display device according to the present invention further includes a discharge signal line driving circuit for applying the discharge signal to the discharge signal line.

The liquid crystal display device according to the present invention is characterized in that the pixel is defined including an electrode pair having electrodes connected to the sub-pixel electrode of the first sub-pixel and the discharge capacitance electrode, respectively.

The liquid crystal display device according to the present invention further includes two data signal lines for each column of the matrix for applying data signals alternately different for each row of the matrix to one end of the first and second switching elements. Two matching rows are scanned at the same time.

According to the driving method of the liquid crystal display device according to the present invention, pixels having at least first and second subpixels which are defined by including a subpixel electrode and a counter electrode pair facing each other through a liquid crystal layer are arranged in a matrix. A first switching element for applying a data signal to a subpixel electrode included in each of the first and second subpixels, and a scanning signal for a control electrode of the first and second switching elements. For each row of the matrix, a discharge capacitor electrode included in the second subpixel, a pair of discharge capacitor counter electrodes connected to a predetermined potential, and a subpixel of the second subpixel A third switching element connected between the electrode and the discharge capacitance electrode, and a discharge signal for turning on the third switching element applied to the control electrode of the third switching element for each row of the matrix A method of driving a liquid crystal display device and a order of discharge signal line, and wherein the delaying the leading edge of the discharge signal, a predetermined time or more than the trailing edge of the scanning signal line after one.

In the present invention, the pixels arranged in a matrix have at least first and second subpixels defined including a subpixel electrode and an electrode pair of the counter electrode facing each other through the liquid crystal layer. In addition, the control electrodes of the first and second switching elements for applying data signals to the subpixel electrodes included in the first and second subpixels are scanned from the scanning signal lines for each row of the matrix (that is, for each line). Apply a signal. A discharge capacitor electrode is connected to the subpixel electrode of the second subpixel through a third switching element, and a discharge capacitor counter electrode connected to a predetermined potential is opposed to the discharge capacitor electrode. The discharge signal applied to the control electrode of the third switching element from the discharge signal line for each line is delayed by a predetermined time or more from the trailing edge of the scanning signal of the next line.
As a result, a discharge signal is applied to the control electrode of the third switching element of the previous line after a predetermined time or more from the time when the data signal is no longer applied to the subpixel electrodes of the first and second subpixels of each line. Therefore, the influence of the voltage applied to the liquid crystal layer by at least the first and second sub-pixels included in the pixels of each line cancels the rise and fall of the discharge signal of the previous line.

In the present invention, the arrangement direction of the first and second sub-pixels is a direction that is in tolerance with the discharge signal line, and the discharge signal line is arranged between the adjacent first and second sub-pixels in the adjacent pixel. Has been.
Thereby, when the scanning signal line is arranged at a position overlapping each pixel, signal leakage between the discharge signal line and the scanning signal line is suppressed.

In the present invention, since the polarity of the data signal applied to each pixel is inverted every frame, the voltage of the subpixel electrode of the second subpixel effectively changes when the third switching element is turned on. As a result, the difference in brightness between the two sub-pixels increases.

In the present invention, the electrode pair defining each of the first and second subpixels of the pixel includes the electrode pair of the auxiliary capacitance electrode and the auxiliary capacitance counter electrode, and the auxiliary capacitance electrode serves as the subpixel electrode. The auxiliary capacitor counter electrode is electrically connected, and is connected to a predetermined potential as a connection destination of the discharge capacitor counter electrode.
As a result, the auxiliary capacitance formed by the auxiliary capacitance electrode and the auxiliary capacitance counter electrode is connected in parallel to the liquid crystal capacitance formed by the subpixel electrode and the counter electrode of each of the first and second subpixels. The voltage applied to the liquid crystal layer by the second subpixel is stably held for at least one frame period.

In the present invention, the discharge signal drive circuit applies a discharge signal to the discharge signal line.
As a result, the delay time of the leading edge of the discharge signal and the signal width of the discharge signal with respect to the trailing edge of the scanning signal of the next line are appropriately adjusted by the discharge signal driving circuit.

In the present invention, when the third switching element is turned on, a part of the electric charge accumulated in the second subpixel is connected to the subpixel electrode and the discharge capacitor electrode of the first subpixel. It moves to the first sub-pixel through the electrode pair it has.
As a result, the voltages of the subpixel electrodes of the first and second subpixels change with opposite polarities.

In the present invention, data signals that are alternately different from line to line from two data signal lines arranged for each column of the matrix are transmitted to the first and second subpixels via the first and second switching elements, respectively. Two lines are scanned within one horizontal scanning period in order to simultaneously turn on the scanning signals of two adjacent lines that are applied to the subpixel electrodes.

According to the present invention, a discharge signal is applied to the third switching element of the previous line after a predetermined time or more from the time when the data signal is no longer applied to the subpixel electrodes of the first and second subpixels of each line. Therefore, the influence of the voltage applied to the liquid crystal layer by at least the first and second sub-pixels included in the pixels of each line cancels the rise and fall of the discharge signal of the previous line.
Accordingly, it is possible to prevent the counter voltage optimum for the counter electrode opposed to the sub-pixel electrode included in the pixel from deviating from the preset counter voltage.

It is a block diagram which shows the structural example of the liquid crystal display device which concerns on Embodiment 1 of this invention. 4 is an explanatory diagram schematically showing a configuration for defining pixels in the liquid crystal display device according to Embodiment 1. FIG. It is sectional drawing which shows the structure of a liquid crystal panel typically. It is explanatory drawing which shows the parasitic capacitance accompanying a pixel. FIG. 5 is a timing chart showing a time change of a signal applied to each signal line and a voltage of a subpixel electrode. FIG. 6 is a timing chart showing temporal changes in signals applied to signal lines and subpixel electrode voltages in the liquid crystal display device according to the first embodiment. FIG. 6 is a timing chart showing temporal changes in signals applied to signal lines and subpixel electrode voltages in the liquid crystal display device according to the first embodiment. 6 is a block diagram illustrating a configuration example of a liquid crystal display device according to a first modification of the first embodiment. FIG. 6 is an explanatory diagram schematically showing a configuration in which pixels are defined in a liquid crystal panel according to a first modification of the first embodiment. FIG. 6 is an explanatory diagram schematically showing a configuration for defining pixels in a liquid crystal panel according to a second modification of the first embodiment. FIG. It is a block diagram which shows the structural example of the liquid crystal display device which concerns on Embodiment 2 of this invention. It is explanatory drawing which shows the connection relation of a pixel and a source signal line. FIG. 10 is a timing chart showing temporal changes in signals applied to signal lines and sub-pixel electrode voltages in the liquid crystal display device according to the second embodiment. FIG. 10 is a timing chart showing temporal changes in signals applied to signal lines and sub-pixel electrode voltages in the liquid crystal display device according to the second embodiment. It is a graph which shows the relationship between the delay time of a discharge signal, and the optimal counter voltage. It is explanatory drawing for demonstrating the presence or absence of the horizontal stripe which generate | occur | produces by a counter voltage shift | offset | difference.

Hereinafter, the present invention will be described in detail with reference to the drawings illustrating embodiments thereof.
(Embodiment 1)
FIG. 1 is a block diagram illustrating a configuration example of a liquid crystal display device according to Embodiment 1 of the present invention, and FIG. 2 schematically illustrates a configuration in which pixels P are defined in the liquid crystal display device according to Embodiment 1. It is explanatory drawing shown. In the liquid crystal display device shown in FIG. 1, a pixel P having at least two subpixels defined including an electrode pair to be described later includes a vertical direction (hereinafter also referred to as a row direction) and a horizontal direction (hereinafter referred to as a column direction) of the display screen. A liquid crystal panel 100a arranged in a matrix. In FIG. 1, two pixels P that are continuous in the row direction and the signal lines related to the pixels P are illustrated. Hereinafter, it is assumed that an electrode pair other than the electrode pair opposed via the liquid crystal layer 3 is opposed via an insulating layer (not shown) to form a capacitance (capacitor).

In FIG. 2, the pixel P has at least a sub-pixel SP1 (corresponding to the first sub-pixel) and a sub-pixel SP2 (corresponding to the second sub-pixel) that are bisected in the vertical direction of the display screen of the liquid crystal panel 100a. The sub-pixel SP1 is defined including an electrode pair of the sub-pixel electrode 11a and the counter electrode 21 facing each other through the liquid crystal layer 3, and an electrode pair of the auxiliary capacitance electrode 12a and the auxiliary capacitance counter electrode 22a. The sub-pixel electrode 11a is connected to a drain electrode of a TFT (Thin Transistor: corresponding to the first switching element) 15a. The subpixel electrode 11a and the auxiliary capacitance electrode 12a are electrically connected. The storage capacitor counter electrode 22a is connected to the potential of the counter electrode 21 (corresponding to a predetermined potential). A liquid crystal capacitor Clc1 is formed by the sub-pixel electrode 11a and the counter electrode 21. The auxiliary capacitance Ccs1 is formed by the auxiliary capacitance electrode 12a and the auxiliary capacitance counter electrode 22a.

The subpixel SP2 includes an electrode pair of the subpixel electrode 11b and the counter electrode 21, which are opposed to each other with the liquid crystal layer 3 interposed therebetween, an electrode pair of the auxiliary capacitor electrode 12b and the auxiliary capacitor counter electrode 22b, and a discharge capacitor electrode 13 and a discharge capacitor counter electrode. And 23 electrode pairs. A drain electrode of a TFT (corresponding to the second switching element) 15b is connected to the subpixel electrode 11b. The subpixel electrode 11b and the auxiliary capacitance electrode 12b are electrically connected. The discharge capacity electrode 13 is connected to the sub-pixel electrode 11b through a TFT (corresponding to the third switching element) 14. The auxiliary capacity counter electrode 22 b and the discharge capacity counter electrode 23 are connected to the potential of the counter electrode 21. The counter electrode 21 is common to the subpixels SP1 and SP2, but is not limited thereto. A liquid crystal capacitor Clc2 is formed by the sub-pixel electrode 11b and the counter electrode 21. The auxiliary capacitance Ccs2 is formed by the auxiliary capacitance electrode 12b and the auxiliary capacitance counter electrode 22b. Further, the discharge capacity Cdc is formed by the discharge capacity electrode 13 and the discharge capacity counter electrode 23.
Note that the size ratio of the subpixel electrode 11a and the subpixel electrode 11b is not limited to 1: 1, and the number of subpixels is not limited to two.

On one side in the horizontal direction of the pixel P, a source signal line (corresponding to a data signal line) SL for applying a source signal (corresponding to a data signal) to the sub-pixel electrodes 11a and 11b via the TFTs 15a and 15b, respectively. Are arranged linearly in the vertical direction. The source electrodes of the TFTs 15a and 15b are connected to the source signal line SL. Gate electrodes (corresponding to control electrodes) of the TFTs 15a and 15b are connected to a scanning signal line Gm that is linearly arranged so as to cross the central portion of the pixel P in the horizontal direction. A gate electrode of the TFT 14 is connected to a discharge signal line Gs linearly arranged so as to cross a horizontal direction between pixels P in the next row (hereinafter also referred to as a line) adjacent in the vertical direction (row direction). It is connected. The scanning signal line Gm and the discharge signal line Gs are arranged side by side in the row direction of the matrix. Since the scanning signal line Gm and the discharge signal line Gs in each row are appropriately separated, signal leakage between the scanning signal line Gm and the discharge signal line Gs is suppressed.

1, the liquid crystal display device according to the first embodiment also applies scanning signals to the scanning signal lines Gm, Gm,... Gm, and discharge signals to the discharging signal lines Gs, Gs,. A gate driver GDa for applying a source signal, a source driver SDa for applying a source signal to the source signal lines SL, SL,... SL, and a display control circuit for controlling display by the liquid crystal panel 100a using the gate driver GDa and the source driver SDa 4a.

The display control circuit 4 a receives an image signal input circuit 40 that receives an image signal including image data representing an image, and the gate driver GDa and the source driver SDa based on the clock signal and the synchronization signal separated by the image signal input circuit 40. It has a scanning signal control circuit 42a, a discharge signal control circuit 43a, and a source signal control circuit 41a to be controlled. The discharge signal control circuit 43a and the gate driver GDa correspond to a discharge signal drive circuit.

Each of the scanning signal control circuit 42a, the discharge signal control circuit 43a, and the source signal control circuit 41a generates control signals such as a start signal, a clock signal, and an enable signal necessary for the periodic operation of the gate driver GDa and the source driver SDa. To do. The source signal control circuit 41a also outputs the digital image data separated by the image signal input circuit 40 to the source driver SDa.

The gate driver GDa sequentially applies a scanning signal for each horizontal scanning period to the scanning signal lines Gm, Gm,... Gm within one frame period of the image data, and discharge signal lines Gs, Gs,. A discharge signal is sequentially applied to Gs every horizontal scanning period. The source driver SDa accumulates digital image data (serial data) supplied from the source signal control circuit 41a for one horizontal scanning period (1H) and generates an analog source signal (parallel signal) representing an image for one line. The generated source signal is applied in parallel to the source signal lines SL, SL,. The source signal for one line here is updated every horizontal scanning period.

The scanning signal applied to one of the scanning signal lines Gm, Gm,... Gm is applied to the gate electrodes of the TFTs 15a and 15b included in the pixels P, P,. Applied. Discharge signals are applied from the discharge signal lines Gs, Gs,... Gs to the gate electrodes of the TFTs 14 included in the pixels P, P,. The leading edge (rising edge) of the discharge signal of the previous line is delayed by a predetermined time or more with respect to the trailing edge (falling edge) of the scanning signal of each line. The delay time and the signal width of the discharge signal are adjusted in advance by the discharge signal control circuit 43a.

The source signal applied to the source signal lines SL, SL,... SL has a gate electrode connected to the one scanning signal line Gm in one horizontal scanning period in which the scanning signal is applied to one scanning signal line Gm. It is applied to the subpixel electrodes 11a and 11b via the TFTs 15a and 15b, respectively, and also to the auxiliary capacitance electrodes 12a and 12b. As a result, source signals are written into the liquid crystal capacitors Clc1 and Clc2 and the auxiliary capacitors Ccs1 and Ccs2 formed in the sub-pixels SP1 and SP2, respectively. In this way, one line of source signal is simultaneously written to one line of pixels P, P,... P in one horizontal scanning period. The source signals written in the subpixels SP1 and SP2 are held for one frame period as long as there is no change in their combined capacitance.

Next, the optical configuration of the liquid crystal panel 100a and other liquid crystal panels that can be replaced with the liquid crystal panel 100a will be described.
FIG. 3 is a cross-sectional view schematically showing the configuration of the liquid crystal panel 100a. The liquid crystal panel 100 a is configured by interposing a liquid crystal layer 3 between a first glass substrate (array substrate) 1 and a second glass substrate 2. A sealing material 33 for sealing the liquid crystal sealed in the liquid crystal layer 3 is disposed between the opposing surfaces of the first glass substrate 1 and the second glass substrate 2. It is provided along.

On one surface of the first glass substrate 1, subpixel electrodes 11a and 11b, auxiliary capacitance electrodes 12a and 12b, auxiliary capacitance counter electrodes 22a and 22b, discharge capacitance electrode 13 and discharge, each made of a transparent electrode, are formed. An alignment film 31 is formed on the layer including the capacitor counter electrode 23, the TFT 14, and the TFTs 15a and 15b. A polarizing plate 19 is attached to the other surface of the first glass substrate 1. A flexible substrate 18 on which a gate driver GDa is surface-mounted is attached to one edge of one surface of the first glass substrate 1.

A counter electrode 21 made of a transparent electrode and an alignment film 32 are laminated on one surface of the second glass substrate 2. In particular, in the liquid crystal panel 100a, a color filter CF is formed between the second glass substrate 2 and the counter electrode 21. A polarizing plate 29 is attached to the other surface of the second glass substrate 2. The polarization direction (polarization plane) of light passing through the polarizing plate 19 and the polarizing plate 29 is different by 90 degrees. The backlight (not shown) is provided on the other surface side of the first glass substrate 1 (the side on which the polarizing plate 19 is attached).

In the above-described configuration, for example, in the case of the normally black method, when no voltage is applied between the sub-pixel electrodes 11a and 11b of the pixel P and the counter electrode 21, the polarization direction of the light transmitted through the pixel P does not change. The light irradiated from the backlight and transmitted through the polarizing plate 19 is absorbed by the polarizing plate 29. In contrast, when a voltage is applied between each of the sub-pixel electrodes 11a and 11b of the pixel P and the counter electrode 21, the polarization direction of the light transmitted through the pixel P changes according to the magnitude of the voltage. The polarization direction of the light irradiated from the backlight and transmitted through the polarizing plate 19 is changed according to the magnitude of the voltage and is transmitted through the polarizing plate 29. Thereby, the brightness of the image displayed by the pixel P changes.

Next, parasitic capacitances not explicitly shown in FIG. 2 will be described.
FIG. 4 is an explanatory diagram illustrating the parasitic capacitance associated with the pixel P. In FIG. 4, for the following description, the pixel P of the k-th line (k is an integer of 0 or more: the same applies hereinafter), the scanning signal line Gm of the k-th line, and the discharge signal line Gs of the k-th line are respectively represented by Pk, It represents with Gmk and Gsk. Since every pixel Pk has a parasitic capacitance, it will be described without distinguishing each pixel Pk.

The TFTs 15a and 15b whose drain electrodes are connected to the subpixel electrodes 11a and 11b of the subpixels SP1 and SP2, respectively, have a parasitic capacitance between the drain and the gate. Further, stray capacitances exist between the scanning signal line Gmk connected to the gate electrodes of the TFTs 15a and 15b and the sub-pixel electrodes 11a and 11b, respectively. Since the parasitic capacitance between the drain and the gate and the stray capacitance act as a parallel capacitance, these capacitances are collectively referred to as a parasitic capacitance Cgd.

The TFT 14 in which the drain electrode (or source electrode) is connected to the subpixel electrode 11b of the subpixel SP2 has a parasitic capacitance between the drain and the gate (or between the source and the gate). Further, a stray capacitance exists between the discharge signal line Gsk connected to the gate electrode of the TFT 14 and the sub-pixel electrode 11b. Since the parasitic capacitance between the drain and gate (or between the source and gate) and the stray capacitance act as a parallel capacitance, these capacitances are collectively referred to as a parasitic capacitance Cgp. On the other hand, there is a stray capacitance between the sub-pixel electrode 11a of the sub-pixel SP1 and the discharge signal line Gsk-1 (for example, between the sub-pixel electrode 11a of the sub-pixel SP1 of the pixel P1 and the discharge signal line Gs0). Yes. This is a parasitic capacitance Csp.

Next, the case where there is a problem with respect to the influence of each parasitic capacitance described above will be described as an example.
FIG. 5 is a timing diagram showing temporal changes in the signal applied to each signal line and the voltage of the sub-pixel electrode 11a. In each of the seven timing charts shown in FIG. 5, the horizontal axis is the same time axis, and the vertical axis indicates the discharge signal line Gs0 for the 0th line, the scanning signal line Gm1 for the first line, The signal levels of the first discharge signal line Gs1, the second scan signal line Gm2, and the second discharge signal line Gs2, and the subpixel electrodes of the subpixel SP1 of the pixel P1 and the subpixel SP1 of the pixel P2, respectively. 11a voltage level. The signal level is represented by a positive pulse indicating the ON state, and the voltage level is represented as a potential difference with respect to the potential of the counter electrode 21, that is, the counter voltage Vcom. The period between the broken lines is 1H. The polarity of the data signal written to the pixel Pk is inverted every frame and every line.

The scanning signal from the scanning signal line Gmk is generated so as to have a signal width of about 1H with a delay of 1H for each line. When the scanning signal from the scanning signal line Gm1 (or Gm2) is turned on at time t1 (or t2), the TFTs 15a and 15b of the pixel P1 (or P2) are turned on (conducting state), and the signal from the source signal line SL is turned on. A data signal is applied to the sub-pixel electrodes 11a and 11b and the auxiliary capacitance electrodes 12a and 12b (see FIG. 2) of the pixel P1 (or P2). As a result, the voltages of the sub-pixel electrodes 11a and 11b become the same level as the voltage of the source signal line SL from time t1 to time t2 (or from time t2 to time t3). This voltage is a voltage applied to the liquid crystal capacitors Clc1 and Clc2. The voltage level of the subpixel electrode 11b is not shown. The voltage waveform of the subpixel electrode 11a of the pixel P1 is similar to that obtained by inverting the polarity with respect to Vcom after one frame and shifting the voltage waveform of the subpixel electrode 11a of the pixel P2 shown in FIG.

Thereafter, when the scanning signal from the scanning signal line Gm1 (or Gm2) is turned off at time t2 (or t3), the TFTs 15a and 15b of the pixel P1 (or P2) are turned off (non-conducting state). At time t2 (or t3), the voltage level of the subpixel electrodes 11a and 11b slightly decreases due to the so-called pull-in phenomenon (feedthrough) due to the parasitic capacitance Cgd. In this case, since the absolute value of the voltage level of the subpixel electrodes 11a and 11b changes to small / large depending on whether the polarity with respect to Vcom is positive or negative, the liquid crystal capacitance Clc1 is affected after being influenced by the pull-in phenomenon. And the average voltage applied to Clc2 is adjusted to Vcom. The counter voltage adjusted in this way is referred to as an optimal counter voltage.

Now, it is necessary that the discharge signal from the discharge signal line Gs1 (or Gs2) for turning on the TFT 14 of the pixel P1 (or P2) does not overlap the scan signal from the scan signal line Gm1 (or Gm2). Therefore, in FIG. 5, it rises at time t21 (or t31) and falls at time t4 (or t5). When the TFT 14 is turned on by this discharge signal, the discharge capacitor Cdc shown in FIG. 2 is connected in parallel to the liquid crystal capacitor Clc2 and the auxiliary capacitor Ccs2.

In this case, the charge accumulated in the discharge capacitor Cdc is accumulated one frame before, and the polarity is opposite to that of the charges accumulated in the liquid crystal capacitor Clc2 and the auxiliary capacitor Ccs2. For this reason, positive charge (or negative charge) moves from the time t21 to time t4 (or from time t31 to time t5) and from the auxiliary capacity Ccs2 to the discharge capacity Cdc, and is applied to the liquid crystal capacity Clc2. The absolute value of the applied voltage decreases. On the other hand, since the voltage applied to the liquid crystal capacitor Clc1 is not affected by the TFT 14 being turned on, the absolute value of the voltage applied to the liquid crystal capacitor Clc2 is smaller than the absolute value of the voltage applied to the liquid crystal capacitor Clc1, There is an effect that the viewing angle dependency of the gamma characteristic is improved.

Here, attention is paid to the influence that the subpixel electrode 11a of the subpixel SP1 of the pixel P1 (or P2) receives from the parasitic capacitance Csp existing between the subpixel electrode 11a and the discharge signal line Gs0 (or Gs1). The discharge signal from the discharge signal line Gs0 rises at time t11, which is 1H earlier than the time t21 when the discharge signal from the discharge signal line Gs1 rises, and falls at time t3. During the time t1 to t2 (or from t2 to t3) when the scanning signal from the scanning signal line Gm1 (or Gm2) is on, the subpixel electrode 11a is connected to the source signal line SL by the TFT 15a and is low. It is in an impedance state. For this reason, it is negligible that the voltage of the sub-pixel electrode 11a of the pixel P1 (or P2) is affected by being pushed up or pushed down from the discharge signal line Gs0 (or Gs1) via the parasitic capacitance Csp.

On the other hand, after time t2 (or after t3) when the scanning signal from the scanning signal line Gm1 (or Gm2) is off, the voltage of the subpixel electrode 11a of the pixel P1 (or P2) is the liquid crystal capacitance Clc1 and the auxiliary capacitance. The voltage is held by Ccs1, and the voltage is likely to fluctuate due to the movement of charges between the outside. Specifically, at time t11 (or t21), the voltage level of the sub-pixel electrode 11a of the pixel P1 (or P2) is hardly affected by rising at the leading edge of the discharge signal, whereas at time t3 (or t4). The voltage level of the sub-pixel electrode 11a of the pixel P1 (or P2) is pushed down due to the falling edge at the trailing edge of the discharge signal.

The above-described push-down occurs in the same direction regardless of whether the voltage of the subpixel electrode 11a is positive or negative. Therefore, the optimum counter voltage for the subpixel electrode 11a of the subpixel SP1 is the actual counter voltage Vcom. A phenomenon in which the voltage is shifted in a lower direction (counter voltage shift) occurs. When a counter voltage shift occurs, a DC voltage is applied to the liquid crystal capacitance Clc1, so that so-called image sticking or flicker occurs.
In the example of the timing chart shown in FIG. 5, the subpixel electrode 11b of the subpixel SP2 of the pixel P1 (or P2) is discharged via the parasitic capacitance Cgp existing between the discharge signal line Gs1 (or Gs2). Since the influences of the push-up and push-down are almost equal from the signal line Gs1 (or Gs2), these influences are offset and no problem occurs.

Below, the specific example with which the subject of this application is solved is demonstrated.
6A and 6B are timing charts showing temporal changes in the signal applied to each signal line and the voltage of the sub-pixel electrode 11a in the liquid crystal display device according to the first embodiment. In the seven timing charts shown in FIGS. 6A and 6B, the horizontal axis is the same time axis, and the vertical axis is the discharge signal line Gs0 of the 0th line and the scanning signal of the 1st line from the top of the figure. The line Gm1, the first discharge signal line Gs1, the second scanning signal line Gm2, and the second discharge signal line Gs2, and the subpixel electrode 11a of the subpixel SP1 of the pixel P1 and the pixel P2 respectively. Represents the voltage level. The signal level is represented by a positive pulse indicating the ON state, and the voltage level is represented as a potential difference with respect to the potential of the counter electrode 21, that is, the counter voltage Vcom. The period between the broken lines is 1H.

In FIG. 6A, the signal width of the scanning signal and the discharge signal is less than 1H, whereas in FIG. 6B, the signal width of the scanning signal and the discharge signal is longer than 1H and less than 2H. There is. The scanning signal from the scanning signal line Gmk is generated with a delay of 1H for each line, and the leading edge (rising edge in FIGS. 6A and 6B) of the discharging signal from the discharging signal line Gsk-1 is the scanning signal. 6A and 6B are common to the point delayed by a time (corresponding to a predetermined time) Td beyond the trailing edge of the scanning signal from the line Gmk (falling in FIGS. 6A and 6B). The same applies to the case where the signal width of the scanning signal and the discharge signal is longer than 2H.

In FIG. 6A, after the scanning signal from the scanning signal line Gm1 (or Gm2) rises from time t1 to t2 (or from time t2 to t3) and the TFTs 15a and 15b are turned on, the time t2 (or When falling at t3), the voltage level of the sub-pixel electrode 11a slightly decreases due to the influence of the pull-in phenomenon (feedthrough). Thereafter, the discharge signal from the discharge signal line Gs0 (or Gs1) rises after a delay of Td or more, and the discharge signal falls at time t3 (or t4). During this time, the voltage level of the sub-pixel electrode 11a of the pixel P1 (or P2) is substantially equally affected by the push-up and push-down caused by the rising and falling of the discharge signal from the discharge signal line Gs0 (or Gs1). The voltage is maintained at substantially the same voltage as when it was not affected at all by the discharge signal.

The same applies to FIG. 6B. After the scanning signal from the scanning signal line Gm1 (or Gm2) rises from time t0 to t1 (or from time t1 to t2) and the TFTs 15a and 15b are turned on, When falling at time t2 (or t3), the voltage level of the sub-pixel electrode 11a slightly decreases due to the influence of the pull-in phenomenon (feedthrough). Thereafter, the discharge signal from the discharge signal line Gs0 (or Gs1) rises after a delay of Td or more, and the discharge signal falls at time t4 (or t5). During this time, the voltage level of the sub-pixel electrode 11a of the pixel P1 (or P2) is substantially equally affected by the push-up and push-down caused by the rising and falling of the discharge signal from the discharge signal line Gs0 (or Gs1). The voltage is maintained at substantially the same voltage as when it was not affected at all by the discharge signal.

As described above, according to the first embodiment, the pixels P arranged in a matrix are defined including the electrode pairs of the counter electrodes 21 and the sub-pixel electrodes 11 a and 11 b that are opposed to each other with the liquid crystal layer 3 interposed therebetween. A TFT 15a for applying a data signal to the subpixel electrodes 11a and 11b included in the first subpixel SP1 and the second subpixel SP2, respectively. And a scanning signal is applied to the gate electrode of 15b from the scanning signal line Gm for each row (that is, for each line) of the matrix. A discharge capacitor electrode 13 is connected to the subpixel electrode 11b of the second subpixel SP2 via a TFT 14, and a discharge capacitor counter electrode 23 connected to the potential of the counter electrode 21 is opposed to the discharge capacitor electrode 13. Yes. The discharge signal applied to the gate electrode of the TFT 14 from the discharge signal line Gs for each line of the matrix has a leading edge (rising edge) delayed by Td or more than the trailing edge (falling edge) of the scanning signal of the next line. .
As a result, the gate electrode of the TFT 14 of the previous line is delayed by Td or more from the time when the data signal is not applied to the subpixel electrodes 11a and 11b of the first subpixel SP1 and the second subpixel SP2 of each line. Since the discharge signal is applied to the liquid crystal layer 3 by at least the first subpixel SP1 and the second subpixel SP2 included in the pixels P of each line, the rise of the discharge signal of the previous line and The effect of falling is offset.
Accordingly, it is possible to prevent the counter voltage optimum for the counter electrode 21 facing the sub-pixel electrodes 11a and 11b defining the pixel P from deviating from the preset counter voltage.

Further, according to the first embodiment, the arrangement direction of the first subpixel SP1 and the second subpixel SP2 is the direction in which the first subpixel SP1 and the second subpixel SP2 are tolerated, that is, the row direction, and the adjacent pixels P, The discharge signal line Gs is disposed between the adjacent subpixels SP1 and SP2 in P, and the scanning signal line is disposed between the first subpixel SP1 and the second subpixel SP2 in the pixel P. .
Therefore, it is possible to suppress signal leakage between the discharge signal line Gs and the scanning signal line Gm, and the manufacturing yield of the liquid crystal panel 100a is improved. On the other hand, the configuration described above increases the parasitic capacitance Csp between the discharge signal line Gs and the first subpixel SP1, but in such a case, the effect of preventing the counter voltage deviation is exhibited.

Further, according to the first embodiment, the polarity of the data signal applied to each pixel P is inverted every frame, so that the voltage of the subpixel electrode 11b of the second subpixel SP2 is effective when the TFT 14 is turned on. It is possible to change so that the contrast between the two sub-pixels increases.

Furthermore, according to the first embodiment, the electrode pair defining each of the first subpixel SP1 and the second subpixel SP2 included in the pixel P includes the electrode pair of the auxiliary capacitance electrode 12a and the auxiliary capacitance counter electrode 22a, and An electrode pair of the auxiliary capacitance electrode 12b and the auxiliary capacitance counter electrode 22b is included, and the auxiliary capacitance electrodes 12a and 12b are electrically connected to the subpixel electrodes 11a and 11b, respectively, and the auxiliary capacitance counter electrodes 22a and 22b. Each is connected to the potential of the counter electrode 21 to which the discharge capacity counter electrode 23 is connected.
Accordingly, the liquid crystal capacitors Clc1 and Clc2 formed by the subpixel electrodes 11a and 11b and the counter electrode 21 of the first subpixel SP1 and the second subpixel SP2 are formed by the auxiliary capacitor electrode 12a and the auxiliary capacitor counter electrode 22a. Since the auxiliary capacitance Ccs1 and the auxiliary capacitance Ccs2 formed by the auxiliary capacitance electrode 12b and the auxiliary capacitance counter electrode 22b are connected in parallel, they are applied to the liquid crystal layer 3 by the first subpixel SP1 and the second subpixel SP2. It is possible to stably hold the voltage to be applied for at least one frame period. As described above, with the configuration in which the optimum counter voltage can be set stably, it is possible to highlight the effect of preventing the counter voltage deviation.

Furthermore, according to the first embodiment, the discharge signal control circuit 43a applies a discharge signal to the discharge signal line Gs using the gate driver GDa.
Therefore, the delay time of the leading edge (rising) of the discharge signal and the signal width of the discharging signal with respect to the trailing edge (falling) of the scanning signal of the next line can be appropriately adjusted by the discharge signal driving circuit. It becomes.

(Modification 1)
The first embodiment is a mode in which the auxiliary capacity counter electrodes 22a and 22b and the discharge capacity counter electrode 23 are connected to the potential of the counter electrode 21, whereas the first modification of the first embodiment is the auxiliary capacity counter electrode 22a. , 22b and the discharge capacitor counter electrode 23 are connected to a predetermined potential different from the potential of the counter electrode 21.

FIG. 7 is a block diagram illustrating a configuration example of a liquid crystal display device according to the first modification of the first embodiment, and FIG. 8 illustrates a configuration in which the pixels P are defined by the liquid crystal panel according to the first modification of the first embodiment. It is explanatory drawing which shows this typically. The liquid crystal display device according to the first modification includes a liquid crystal panel 100b, a gate driver GDa, a source driver SDa, a display control circuit 4b that controls display by the liquid crystal panel 100b using the gate driver GDa and the source driver SDa, A storage capacitor voltage main line CSL for relaying a voltage applied from the display control circuit 4b to the liquid crystal panel 100b is provided. Hereinafter, the same reference numerals are given to the same components as those in the first embodiment, and the description thereof will be omitted, and the components different from those in the first embodiment will be described.

The liquid crystal panel 100b further includes auxiliary capacitance voltage lines CS1 and CS2 arranged so as to linearly cross both vertical ends of the pixel P in the horizontal direction as compared with the liquid crystal panel 100a of the first embodiment. Each of the auxiliary capacitance voltage lines CS1 and CS2 is connected to the auxiliary capacitance voltage trunk line CSL outside the liquid crystal panel 100b, and is connected to the auxiliary capacitance counter electrodes 22a and 22b inside the liquid crystal panel 100b (FIG. 8). reference). The auxiliary capacitance voltage line CS <b> 2 is further connected to the discharge capacitance counter electrode 23. In the present modification 1, the auxiliary capacitance voltage line CS2 is connected to the auxiliary capacitance voltage main line CSL outside the liquid crystal panel 100b. However, the auxiliary capacitance voltage main line CSL may be arranged in the liquid crystal panel 100b.

Compared to the display control circuit 4a in the first embodiment, the display control circuit 4b generates an auxiliary capacitance voltage generation circuit 44 that generates a predetermined voltage to be applied to the auxiliary capacitance voltage lines CS1 and CS2 via the auxiliary capacitance voltage main line CSL. It has further. The voltages applied to the auxiliary capacitance voltage lines CS1 and CS2 may be the same or different.

In the liquid crystal panel 100a and the liquid crystal panel 100b, whether the connection destinations of the auxiliary capacitor counter electrodes 22a and 22b and the discharge capacitor counter electrode 23 are the potential of the counter electrode 21 or the potentials of the auxiliary capacitor voltage lines CS1 and CS2. There is a difference. However, the auxiliary capacitors Ccs1 and Ccs2 are connected in parallel to the liquid crystal capacitors Clc1 and Clc2, respectively, to store charges, and the positive charge (moved from the liquid crystal capacitors Clc2 and auxiliary capacitors Ccs2 to the discharge capacitor Cdc when the TFT 14 is turned on) It is clear that there is no difference in the amount of (or negative charge). From this, it can be said that according to the first modification, the same effect as in the first embodiment can be obtained.
Note that the difference in the configuration of the first modification with respect to the configuration of the first embodiment can be applied to a second modification described later and other embodiments.

(Modification 2)
In the first embodiment, the absolute value of the effective voltage applied to the liquid crystal capacitor Clc1 does not change when the TFT 14 is turned on, whereas in the second modification of the first embodiment, the TFT 14 is turned on. In this mode, the absolute value of the effective voltage applied to the liquid crystal capacitor Clc1 changes.
FIG. 9 is an explanatory diagram schematically illustrating a configuration in which the pixels P are defined in the liquid crystal panel according to the second modification of the first embodiment.

In the second modification, the second discharge capacity (capacitor) formed by an electrode pair having electrodes connected to the discharge capacity electrode 13 and the auxiliary capacity electrode 12a, respectively, with respect to the configuration of the pixel P in the first embodiment. Cdc2 is connected. The difference between the liquid crystal panel in the second modification and the liquid crystal panel 100a in the first embodiment is only the presence or absence of the discharge capacity Cdc2. In addition, the same code | symbol is attached | subjected to the location corresponding to Embodiment 1, and the description is abbreviate | omitted.
Hereinafter, a change in voltage applied to the subpixel electrodes 11a and 11b when the TFT 14 is turned on will be described.

In the first embodiment, when the TFT 14 is turned on, a positive charge (or negative charge) moves from the liquid crystal capacitor Clc2 and the auxiliary capacitor Ccs2 to the discharge capacitor Cdc, and the absolute value of the voltage applied to the liquid crystal capacitor Clc2 is It has been explained that the absolute value of the voltage applied to the liquid crystal capacitor Clc1 does not change while it decreases. Further, the voltage of the discharge capacitor electrode 13 immediately before the TFT 14 was turned on was the voltage of the sub-pixel electrode 11b one frame before. On the other hand, in the second modification, due to the presence of the second discharge capacitor Cdc2, the voltage of the discharge capacitor electrode 13 immediately before the TFT 14 is turned on is different from the voltage of the sub-pixel electrode 11b one frame before, and the TFT 14 There is a difference that the absolute value of the voltage applied to the liquid crystal capacitance Clc1 also changes when turned on.

In order to specifically explain this, the capacitances of the liquid crystal capacitors Clc1, Clc2, auxiliary capacitors Ccs1, Ccs2, discharge capacity Cdc, and second discharge capacity Cdc2 are CLC, CCS, CDC, and CDC2. With reference to the timing chart shown in FIG. 6A, the voltages of the sub-pixel electrodes 11a and 11b of the pixel P1 at the time t1 before the TFTs 15a and 15b are turned on by the scanning signal from the scanning signal line Gm1 and the data signal is applied. Are V1 and V2. Further, the voltage of the sub-pixel electrodes 11a and 11b of the pixel P1 at time t2 when the data signal is applied is set to V3. The polarity of the voltage V3 is opposite to the polarity of the voltages V1 and V2. The voltage of the discharge capacitor electrode 13 at time t1 is maintained at V2 which is the same as the voltage of the subpixel electrode 11b since the TFT 14 was turned on / off one frame before.

When a data signal is applied to the subpixel electrode 11a of the pixel P1, the voltage of the subpixel electrode 11a increases (or decreases) from V1 to V3. Since this voltage change V3-V1 is divided by the series circuit of the second discharge capacity Cdc2 and the discharge capacity Cdc and added to the voltage of the discharge capacity electrode 13, the voltage Vdc of the discharge capacity electrode 13 at time t2. Is represented by the following formula (1).

Vdc = V2 + (V3-V1) × CDC2 / (CDC + CDC2) (1)

On the right side of Equation (1), the polarity of the first term V2 is opposite to that of the second term (V3-V1). When the TFT 14 is turned on later, in order for positive charges (or negative charges) to move from the liquid crystal capacitor Clc2 and the auxiliary capacitor Ccs2 to the discharge capacitor Cdc side, the polarity of Vdc is opposite to the polarity of V3. (That is, the same polarity as V2) is preferable. The size of CDC2 / (CDC + CDC2) is appropriately reduced so as to have such a polarity relationship. The voltage Vdc is a voltage of a series circuit in which the second discharge capacitor Cdc2 is connected in series to a circuit in which the liquid crystal capacitor Clc1 and the auxiliary capacitor Ccs1 are connected in parallel, and a parallel circuit in which the discharge capacitor Cdc is connected in parallel.

Next, when the TFT 14 is turned on by a discharge signal from the discharge signal line Gs1 between time t3 and t4, positive charges (or negative charges) move from the liquid crystal capacitor Clc2 and the auxiliary capacitor Ccs2 to the parallel circuit. Assume that Vdc has increased (or decreased) by ΔV. In this case, ΔV is divided by the series circuit and added to the voltage V3 of the liquid crystal capacitor Clc1 and the auxiliary capacitor Ccs1 (that is, the voltage of the subpixel electrode 11b of the pixel P1), so the voltage of the subpixel electrode 11a at time t4. V4 increases (or decreases) from the voltage V3 as represented by the following formula (2).

V4 = V3 + ΔV × CDC2 / (CLC + CCS + CDC2) (2)

On the other hand, the voltage of the sub-pixel electrode 11b after the positive charge (or negative charge) has moved from the liquid crystal capacitor Clc2 and the auxiliary capacitor Ccs2 to the parallel circuit surely decreases (or increases), so that the TFT 14 is turned on. As a result, the voltage change generated in the sub-pixel electrodes 11a and 11b has the opposite polarity. Thereby, the absolute value of the voltage applied to the liquid crystal capacitor Clc2 becomes smaller than the absolute value of the voltage applied to the liquid crystal capacitor Clc1, and the effect of improving the viewing angle dependency of the gamma characteristic is obtained.

In addition, the timing indicating the time change of the signal applied to each signal line and the voltage of the subpixel electrode 11a in Modification 2 is the same as that shown in FIGS. 6A and 6B of the first embodiment.
The difference in the configuration of the present modification 2 from the configuration of the first embodiment can be applied to the above-described modification 1 and other embodiments described later.

As described above, according to the second modification, when the TFT 14 is turned on, a part of the electric charge accumulated in the second subpixel SP2 is changed to the subpixel electrode 11a and the discharge capacitor electrode 13 of the first subpixel SP1, respectively. It moves to the first sub-pixel SP1 through the second discharge capacitor Cdc2 formed by the electrode pair having the electrodes connected to.
Accordingly, it is possible to change the voltages of the subpixel electrode 11a of the first subpixel SP1 and the subpixel electrode 11b of the second subpixel SP2 with opposite polarities. Thus, even when the voltage of the subpixel electrodes 11a and 11b changes with the reverse polarity when the discharge signal is turned on, the effect of preventing the counter voltage deviation is not impaired.

(Embodiment 2)
In the first embodiment, the same data signal is applied to the sub-pixel electrodes 11a and 11b via the TFTs 15a and 15b from the source signal line SL arranged for each column of the matrix. In the second embodiment, different data signals are alternately applied to the subpixel electrodes 11a and 11b via the TFTs 15a and 15b from the two source signal lines SL1 and SL2 arranged for each column of the matrix. It is a form.

FIG. 10 is a block diagram showing a configuration example of the liquid crystal display device according to Embodiment 2 of the present invention. The liquid crystal display device according to the second embodiment includes a liquid crystal panel 100c, a gate driver GDb, a source driver SDb, and a display control circuit 4c that controls display by the liquid crystal panel 100c using the gate driver GDb and the source driver SDb. Is provided. In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and most of the description thereof is omitted, and the components different from those in the first embodiment are mainly described.

In the liquid crystal panel 100c, as compared with the liquid crystal panel 100a of the first embodiment, the source signal line arranged in the vertical direction on one side of the pixel P is SL1, and is arranged in the vertical direction on the other side of the pixel P. The source signal line SL2 is further provided.

In the display control circuit 4c, compared to the display control circuit 4a in the first embodiment, the source signal control circuit 41b controls the two source signal lines SL1 and SL2 for each column of the matrix using the source driver SDb. The scanning signal control circuit 42b and the discharge signal control circuit 43b simultaneously control the two adjacent scanning signal lines Gm and Gm and the discharge signal lines Gs and Gs using the gate driver GDb. The point is different.

FIG. 11 is an explanatory diagram showing a connection relationship between the pixel P and the source signal line SL1 or SL2. Since the parasitic capacitance associated with the pixel P is the same as that shown in FIG. 4 of the first embodiment, the description thereof is omitted. The source electrodes of the TFTs 15a and 15b of the pixels P1, 3, 5,... Are connected to the source signal line SL1. The source electrodes of the TFTs 15a and 15b of the pixels P2, 4, 6,... Are connected to the source signal line SL2. That is, different data signals are alternately applied from the source signal lines SL1 and SL2 to the subpixel electrodes 11a and 11b via the TFTs 15a and 15b. With this configuration, by simultaneously turning on the scanning signals from the scanning signal lines Gm1 and Gm2, it is possible to simultaneously scan two lines including the pixels P1 and P2 within 1H (horizontal scanning period).

In the second embodiment, the discharge signals from the discharge signal lines Gs1 and Gs2 are simultaneously turned on, but these discharge signals are prevented from overlapping with the scan signals from the scan signal lines Gm1 and Gm2. What is necessary is the same as in the first embodiment. As long as this condition is cleared with a margin, the subpixel electrodes 11b of the subpixels SP2 of the pixels P1 and P2 are connected to the discharge signal lines Gs1 and Gs2 via the parasitic capacitance Cgp existing between the subpixel electrodes 11b and Gs2. Since the influence of the push-up and push-down is substantially equal from Gs2, there is basically no counter voltage shift for the second subpixel SP2 of the pixels P1 and P2.

On the other hand, for the first subpixel SP1 of the pixel P1, a counter voltage shift may occur in the configurations of the inventions described in Non-Patent Document 1 and Patent Document 1. In particular, when two lines are scanned simultaneously as in the second embodiment, the discharge signal affected by the first subpixel SP1 is affected by the first and second lines while the scanning signal is the same. Because of the difference, the counter voltage shift is likely to occur significantly in the first subpixel SP1 in the first line. As a result, white horizontal stripes are visually recognized every two lines on the display screen.

Below, the specific example with which the subject of this application is solved is demonstrated.
12A and 12B are timing charts showing time changes of signals applied to the signal lines and voltages of the subpixel electrodes 11a in the liquid crystal display device according to Embodiment 2. FIG. In the seven timing charts shown in FIGS. 12A and 12B, the horizontal axis is the same time axis, and the vertical axis is the discharge signal line Gs0 of the 0th line and the scanning signal of the 1st line from the top of the figure. The line Gm1, the first discharge signal line Gs1, the second scanning signal line Gm2, and the second discharge signal line Gs2, and the subpixel electrode 11a of the subpixel SP1 of the pixel P1 and the pixel P2 respectively. Represents the voltage level. The signal level is represented by a positive pulse indicating the ON state, and the voltage level is represented as a potential difference with respect to the potential of the counter electrode 21, that is, the counter voltage Vcom. The period between the broken lines is 1H.

In FIG. 12A, the signal width of the scanning signal and the discharge signal is less than 1H, whereas in FIG. 12B, the signal width of the scanning signal and the discharge signal is longer than 1H and less than 2H. There is. The scanning signal line Gmk (k is an integer of 0 or more) is turned on simultaneously for two lines, the scanning signal and the discharge signal are turned on with a delay of 1H every two lines, and the discharge signal line Gsk− The leading edge of the discharge signal from 1 (rising edge in FIGS. 12A and 12B) is delayed by Td or more than the trailing edge of the scanning signal from the scanning signal line Gmk (falling edge in FIGS. 12A and 12B). 12A and 12B are common. The same applies to the case where the signal width of the scanning signal and the discharge signal is longer than 2H.

In FIG. 12A, when the scanning signals from the scanning signal lines Gm1 and Gm2 rise from the time t1 to the time t2 and turn on the TFTs 15a and 15b and then fall at the time t2, the influence of the pull-in phenomenon (feedthrough) As a result, the voltage level of the sub-pixel electrode 11a slightly decreases. Thereafter, the discharge signal from the discharge signal line Gs0 (or Gs1) rises after a delay of Td or more, and the discharge signal falls at time t3 (or t4). During this time, the voltage level of the sub-pixel electrode 11a of the pixel P1 (or P2) is substantially equally affected by the push-up and push-down caused by the rising and falling of the discharge signal from the discharge signal line Gs0 (or Gs1). The voltage is maintained at substantially the same voltage as when it was not affected at all by the discharge signal.

The same applies to FIG. 12B. When the scanning signals from the scanning signal lines Gm1 and Gm2 rise from time t0 to t1 and turn on the TFTs 15a and 15b and then fall at time t2, the pull-in phenomenon (feed) The voltage level of the sub-pixel electrode 11a slightly decreases due to the influence of “through”. Thereafter, the discharge signal from the discharge signal line Gs0 (or Gs1) rises after a delay of Td or more, and the discharge signal falls at time t4 (or t5). During this time, the voltage level of the sub-pixel electrode 11a of the pixel P1 (or P2) is substantially equally affected by the push-up and push-down caused by the rising and falling of the discharge signal from the discharge signal line Gs0 (or Gs1). The voltage is maintained at substantially the same voltage as when it was not affected at all by the discharge signal.

In the following, the results of actually measuring the counter voltage deviation when Td is changed and the visual effect of the present invention will be described.
FIG. 13 is a graph showing the relationship between the delay time of the discharge signal and the optimum counter voltage, and FIG. 14 is an explanatory diagram for explaining the presence or absence of a horizontal stripe caused by the counter voltage deviation. The horizontal axis in FIG. 13 represents the delay time (μs) of the leading edge of the discharge signal one line before the trailing edge of the scanning signal, and the vertical axis represents the optimum counter voltage (V). Here, the liquid crystal display device used for the actual measurement was measured for the case of full HD, frame rate of 120 Hz, and displayed gradation of 64/255. A solid line represents the optimum counter voltage for the subpixel SP1 of the pixel P1, and a broken line represents the optimum counter voltage for the subpixel SP1 of the pixel P2 shown for comparison. Note that when the value of Td is negative, it indicates that the rise of the discharge signal of the pixel P0 precedes the fall of the scan signal of the pixel P1.

In the second embodiment, the discharge signal for the pixel P0 rises with a delay of Td or more from the fall of the scanning signal for the pixel P1, and the discharge signal for the pixel P1 with a delay of 1H + Td or more after the fall of the scanning signal for the pixel P2. stand up. For this reason, the sub-pixel electrode 11a of the sub-pixel SP1 of the pixel P2 basically does not cause a counter voltage shift, and the optimum counter voltage is constant at about 6.4 V (see the broken line in FIG. 13).

On the other hand, for the subpixel electrode 11a of the subpixel SP1 of the pixel P1, when the Td is changed to -7.4 μs, −3.0 μs, −0.74 μs, ± 0 μs, and +1.5 μs, the optimum counter voltage is Varies with 5.05V, 5.12V, 5.60V, 6.17V, and 6.42V. That is, it can be said that the counter voltage deviation still occurs when Td is 0 μs, and that the counter voltage deviation is eliminated if Td is secured to 1.5 μs or more.
Note that if the value of Td that can prevent the counter voltage deviation differs depending on the position on the display screen, the maximum Td may be adopted.

14, the upper part of the figure represents the display screen of the liquid crystal panel 100c when the counter voltage deviation occurs, and the lower part represents the display screen of the liquid crystal panel 100c when the counter voltage deviation does not occur. Since the luminance change of the pixel P with respect to the gradation change is non-linear, it is known that the luminance of the pixel P tends to shift to a brighter side than the ideal luminance when a counter voltage shift occurs. ing. For this reason, when a uniform halftone screen is displayed, a white horizontal stripe is visually recognized every two lines on the display screen (see the upper diagram). On the other hand, when the counter voltage deviation does not occur, white horizontal stripes are not visually recognized on the display screen (see the lower diagram).

As described above, according to the second embodiment, data signals that are alternately different for each line from the two source signal lines SL1 and SL2 arranged for each column of the matrix are supplied to the first sub-line via the TFTs 15a and 15b, respectively. Applied to the subpixel electrode 11a of the pixel SP1 and the subpixel electrode 11b of the second subpixel SP2, the scanning signals of two adjacent lines are simultaneously turned on.
Therefore, while it becomes possible to scan two lines within one horizontal scanning period, a counter voltage shift is likely to occur in the sub-pixel SP1 of the pixel P of the first line among the two lines scanned simultaneously. However, it is possible to prevent the counter voltage deviation.

The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the meanings described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims. In addition, the technical features described in each embodiment can be combined with each other.

P, P0, P1, P2 Pixel SP1, SP2 Subpixel Clc1, Clc2 Liquid crystal capacitance Ccs1, Ccs2 Auxiliary capacitance Cdc Discharge capacitance Cdc2 Second discharge capacitance CS1, CS2 Auxiliary capacitance voltage line CSL Auxiliary capacitance voltage trunk wiring Gm, Gm1, Gm2 Scan signal line GDa, GDb Gate driver Gs, Gs0, Gs1, Gs2 Discharge signal line SDa, SDb Source driver SL, SL1, SL2 Source signal line 11a, 11b Subpixel electrode 12a, 12b Auxiliary capacitance electrode 13 Discharge capacitance electrode 14, 15a 15b TFT
21 Counter electrode 22a, 22b Auxiliary capacity counter electrode 23 Discharge capacity counter electrode 3 Liquid crystal layer 4a, 4b, 4c Display control circuit 40 Image signal input circuit 41a, 41b Source signal control circuit 42a, 42b Scan signal control circuit 43a, 43b Discharge signal Control circuit 44 Auxiliary capacitance voltage generation circuit 100a, 100b, 100c Liquid crystal panel

Claims (8)

1. Pixels having at least first and second subpixels defined including a subpixel electrode and an electrode pair of the counter electrodes facing each other through a liquid crystal layer are arranged in a matrix, and the first and second subpixels are arranged. First and second switching elements for applying data signals to the subpixel electrodes included therein, and scanning signals for applying scanning signals to the control electrodes of the first and second switching elements for each row of the matrix A line, a discharge capacity electrode included in the second sub-pixel and an electrode pair of a discharge capacity counter electrode connected to a predetermined potential, and a first electrode connected between the sub-pixel electrode and the discharge capacity electrode of the second sub-pixel. A liquid crystal display device comprising: 3 switching elements; and a discharge signal line for applying a discharge signal for turning on the third switching element to the control electrode of the third switching element for each row of the matrix. In,
   2. A liquid crystal display device according to claim 1, wherein the leading edge of the discharge signal is delayed by a predetermined time or more than the trailing edge of the scanning signal of the next row.
2. The first and second subpixels are disposed in a direction that is in tolerance with the discharge signal line,
   The liquid crystal display device according to claim 1, wherein the discharge signal line is disposed between adjacent first and second subpixels in pixels adjacent in the direction.
3. 3. The liquid crystal display device according to claim 1, wherein the polarity of the data signal applied to the first and second sub-pixels is inverted every frame period.
4. Each of the first and second subpixels is defined to include an electrode pair of an auxiliary capacitance electrode connected to the subpixel electrode and an auxiliary capacitance counter electrode connected to the predetermined potential. The liquid crystal display device according to claim 1.
5. 5. The liquid crystal display device according to claim 1, further comprising a discharge signal line driving circuit that applies the discharge signal to the discharge signal line. 6.
6. The said pixel is demarcated including the electrode pair which has an electrode connected to the sub-pixel electrode of said 1st sub-pixel, and said discharge capacity electrode, respectively. A liquid crystal display device according to 1.
7. Two data signal lines for applying different data signals alternately to each row of the matrix to one end of the first and second switching elements for each column of the matrix;
   The liquid crystal display device according to any one of claims 1 to 6, wherein two adjacent rows are simultaneously scanned.
8. Pixels having at least first and second subpixels defined including a subpixel electrode and an electrode pair of the counter electrodes facing each other through a liquid crystal layer are arranged in a matrix, and the first and second subpixels are arranged. First and second switching elements for applying data signals to the subpixel electrodes included therein, and scanning signals for applying scanning signals to the control electrodes of the first and second switching elements for each row of the matrix A line, a discharge capacity electrode included in the second sub-pixel and an electrode pair of a discharge capacity counter electrode connected to a predetermined potential, and a first electrode connected between the sub-pixel electrode and the discharge capacity electrode of the second sub-pixel. A liquid crystal display device comprising: 3 switching elements; and a discharge signal line for applying a discharge signal for turning on the third switching element to the control electrode of the third switching element for each row of the matrix. A method of driving a
   A driving method of a liquid crystal display device, wherein the leading edge of the discharge signal is delayed by a predetermined time or more from the trailing edge of the scanning signal of the next row.

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