KR20070002221A - Multi-domain liquid crystal display device - Google Patents

Abstract

A multi-domain LCD(Liquid Crystal Display) is provided to form compensation TFTs(Thin Film Transistors) for compensating size difference of TFTs in each driving area for preventing generation of afterimages or flickers generated by a difference of parasitic capacitances per area, thereby improving visual characteristics. A multi-domain LCD includes first and second substrates facing each other and defined with a plurality of pixel areas. Gate lines(111) are formed on the first substrate to divide each of the pixel areas into first and second areas. Data lines(112) are formed at a side of the pixel areas and intersect the gate lines. First and second pixel electrodes(113a,113b) are respectively formed in the divided first and second areas. First TFTs(TFT1) are formed with a first width and a length between the gate and data lines in the first area for driving the first pixel electrodes. Second TFTs(TFT2) are formed with a second width and the length between the gate and data lines in the second area for driving the second pixel electrodes. Third TFTs(TFT3) are formed with the first width and the length in serial with the second TFTs. A liquid crystal layer is implanted between the substrates.

Description

Multi-domain Liquid Crystal Display Device

1 is a plan view showing one pixel of a liquid crystal display of a conventional VA mode.

2 is a plan view illustrating the driving area of FIG. 1 separately;

3A and 3B are perspective views three-dimensionally showing thin film transistors formed in respective driving regions of FIG. 2.

4 is a circuit diagram showing an equivalent circuit of one pixel of a liquid crystal display of the conventional VA mode.

5 is a cross-sectional view taken along line II ′ of FIG. 1;

6 is a timing diagram showing the level shift voltage and the voltage of the liquid crystal layer.

7 is a circuit diagram showing an equivalent circuit of the multi-domain liquid crystal display of the present invention.

8 is a plan view of one pixel equivalent to FIG. 7;

9A to 9C are three-dimensional perspective views of thin film transistors formed in the multi-domain liquid crystal display of the present invention.

* Description of Symbols Representing Major Parts of Drawings *

100 substrate 107 gate insulating film

108: interlayer insulating film 111: gate line

112: data line 113: pixel electrode

114: slit 211: dielectric film

The present invention relates to a liquid crystal display device, and more particularly, further includes a thin film transistor to compensate for the thin film transistor of each driving region when driving one pixel by dividing two driving regions so as to have excellent visibility characteristics. The present invention relates to a multi-domain liquid crystal display device that prevents flicker failure.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), electro luminescent displays (ELD), and vacuum fluorescent (VFD) Various flat panel display devices such as displays have been studied, and some of them are already used as display devices in various devices.

Among them, LCD is the most widely used as the substitute for CRT (Cathode Ray Tube) for mobile image display device because of its excellent image quality, light weight, thinness, and low power consumption. In addition to the use of the present invention has been developed in various ways such as a television and a computer monitor for receiving and displaying broadcast signals.

In order to use such a liquid crystal display as a general screen display device in various parts, it is a matter of how high quality images such as high definition, high brightness and large area can be realized while maintaining the characteristics of light weight, thinness and low power consumption. can do.

A general liquid crystal display device may be largely divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel includes first and second glass substrates bonded to each other with a predetermined space; It consists of a liquid crystal layer injected between the said 1st, 2nd glass substrate.

Here, the first glass substrate (TFT array substrate) has a plurality of gate lines arranged in one direction at regular intervals, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate lines, A plurality of pixel electrodes formed in a matrix form in each pixel region defined by crossing a gate line and a data line, and a plurality of thin film transistors switched by signals of the gate line to transfer the signal of the data line to each pixel electrode. Is formed.

The second glass substrate (color filter substrate) includes a light shielding layer for blocking light in portions other than the pixel region, an R, G, and B color filter layers for expressing color colors, and a common electrode for implementing an image. Is formed.

The driving principle of the general liquid crystal display device uses the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the arrangement of molecules can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal by optical anisotropy to express image information.

Hereinafter, a conventional multi-domain liquid crystal display will be described with reference to the accompanying drawings.

The driving mode of the multi-domain liquid crystal display described below will be described taking a vertical alignment mode as an example.

1 is a plan view illustrating one pixel of a liquid crystal display of the conventional VA mode, and FIG. 2 is a plan view illustrating the driving area of FIG. 1 separately. 3A and 3B are perspective views three-dimensionally illustrating thin film transistors formed in respective driving regions of FIG. 2. 4 is a circuit diagram illustrating an equivalent circuit of one pixel of the liquid crystal display of the conventional VA mode, and FIG. 5 is a structural cross-sectional view taken along line II ′ of FIG. 1.

As shown in FIGS. 1 to 5, the liquid crystal display of the conventional VA mode includes a first pixel substrate 10 and a second substrate 20 that face each other, and a pixel region intersecting each other on the first substrate 10. A gate line 11 and a data line 12 defining a 13, and a plurality of slits 16 formed at predetermined portions in the pixel region 13 of the first substrate 10. The pixel electrode 15, a dielectric film 21 formed corresponding to a region between the slits and the slits in the pixel region on the second substrate 20, and the first and second substrates 10 and 20 are filled with each other. And a liquid crystal layer (not shown).

Here, the first thin film transistor TFT1 and the second thin film transistor TFT2 driving the driving regions are divided into first and second driving regions in the pixel region 13. Same as 4. That is, as shown in FIG. 4, the first thin film transistor TFT1 and the second thin film transistor TFT2 are provided between the data line 12 on the upper side and the lower side of the gate line 11, respectively. The pixel electrodes positioned in the first and second driving regions are actually charged by varying the sizes of the TFT1 and the second thin film transistor TFT2 (the sizes of the widths W1 and W2 are different). Different voltage values.

1 through 5 are thin film transistors which control on / off in each region by dividing the opening region by a predetermined ratio, as shown in FIG. The TFT1 and TFT2 have different sizes, and the four domains are increased to eight domains by applying different voltages to the two regions.

ΔVg 가 되고, 제 2 영역의 레벨 쉬프트 전압 은 ΔVp2

ΔVg가 된다.As described above, in the illustrated example, since the sizes of the thin film transistors TFT1 and TFT2 are different, parasitic capacitance values between the gate sources of the two thin film transistors TFT1 and TFT2 are different, and thus, the first driving region in one pixel. And the second driving region have different level shift voltages ΔVp. That is, the level shift voltage of each first region is ΔVp1 =

ΔVg, and the level shift voltage of the second region is ΔVp2.

ΔVg.

The shape of the thin film transistor in each driving region of the liquid crystal display of the conventional VA mode described above is as follows. That is, as shown in FIG. 3A, the first thin film transistor TFT1 configured in the first driving region protrudes from the gate line 11 and includes a first gate electrode 11a formed at a predetermined portion on the substrate 10. A gate insulating film 17 formed on the entire surface of the substrate 10 including the first gate electrode 11a and a semiconductor layer 17 formed in an island shape on the gate insulating film 17 so as to cover the first gate electrode 11a. And a width W1 on both sides of the semiconductor layer 17, and a first source electrode 18a having a length L between the two electrodes and a first drain electrode 19a. 3B, the second thin film transistor TFT2 configured in the second driving region protrudes from the gate line 11 and includes a second gate electrode 11b formed at a predetermined portion on the substrate 10. A gate insulating film 17 formed on the entire surface of the substrate 10 including the second gate electrode 11b and a semiconductor layer 17 formed in an island shape on the gate insulating film 17 so as to cover the second gate electrode 11b. And a width W2 on both sides of the semiconductor layer 17, and a second source electrode 18b having a length L between the two electrodes and a second drain electrode 19b.

Hereinafter, the relationship between the level shift voltage and the filling voltage value of the liquid crystal layer will be described.

6 is a timing diagram showing the level shift voltage and the voltage of the liquid crystal layer.

As shown in FIG. 6, when the charge rate at which the voltage supplied to the data line is charged to the pixel electrode is 100%, the voltage VLC (t) of the liquid crystal layer immediately before the thin film transistor is turned off is the voltage VD applied to the ls line. As the gate voltage changes from Vgh to Vgl, the thin film transistor turns off, and at that moment, the voltage VLC (t) applied to the liquid crystal layer changes due to the parasitic capacitance Cgs.

The polarity of the voltage is alternately applied to the liquid crystal layer every frame. The level shift voltage ΔVp lowers the voltage applied to the liquid crystal layer in the + frame and increases the voltage applied to the liquid crystal layer in the frame by ΔVp. 6 illustrates a change in voltage of the liquid crystal layer due to various signal waveforms and level shift (or feed-through) voltages of the pixel. This voltage difference causes a brightness difference, resulting in flicker.

In the above-described liquid crystal display of the VA mode, each pixel region is divided into first and second driving regions, and the level shift voltage (ΔVp1 ≠ ΔVp2) of the first driving region and the second driving region is different. Two level shift voltages exist in one pixel, and even if the level shift voltage is compensated through the common voltage applied to the common electrode, the level shift voltage cannot be completely compensated for, resulting in afterimage and flicker. ) May be further aggravated.

The conventional multi-domain liquid crystal display as described above has the following problems.

In VA mode in which one pixel is divided into two regions for better visibility, and thin film transistors having different sizes are configured to fill different regions in each region, the level shift voltage of each region is also different. Two level shift voltages ΔVp1 and ΔVp2 are present in the pixel, and even if the level shift voltage is compensated through the common voltage applied to the common electrode by the difference between the two level shift voltages, the level shift voltage is completely compensated. The problem of afterimage, flicker and the like can be exacerbated.

The present invention has been made to solve the above problems, and further includes a thin film transistor that compensates when the size of the thin film transistor of each driving region is different when driving one pixel by dividing the two driving regions so as to improve the sense characteristics. Accordingly, an object of the present invention is to provide a multi-domain liquid crystal display which prevents afterimages and flicker defects.

In the multi-domain liquid crystal display of the present invention for achieving the above object, a plurality of pixel regions are defined, the first substrate and the second substrate formed to face each other, and the first region across each pixel region and A gate line formed on the first substrate, a data line formed on one side of the pixel regions, a first pixel electrode formed on the first region so as to be divided into a second region, A second width W1 and a length L between the gate line and the data line of the first region for driving the second pixel electrode formed in the second region and the first pixel electrode; A second thin film transistor having a second width W2 and a length L between the gate line and the data line of the second region for driving the first thin film transistor and the second pixel electrode; And a third thin film transistor having a first width W1 and a length L in series with the second thin film transistor, and a liquid crystal layer filled between the first substrate and the second substrate. There is this.

The first pixel electrode and the second pixel electrode each include one or more slits at predetermined portions.

Further comprising a dielectric on the second substrate corresponding to the region between the slit and the slit.

The first substrate and the second substrate further include a vertically aligned alignment layer.

The first thin film transistor includes a first gate electrode, a first source electrode, and a first drain electrode, wherein the first gate electrode is connected to the gate line, and the first drain electrode is connected to the data line. The first source electrode is connected to the first pixel electrode.

The second thin film transistor includes a second gate electrode, a second source electrode, and a second drain electrode, wherein the second gate electrode is connected to the gate line, and the second drain electrode is connected to the data line. The second source electrode is connected to the third thin film transistor.

The third thin film transistor includes a third gate electrode, a third source electrode, and a third drain electrode, the third gate electrode is connected to the gate line, and the third drain electrode is connected to the second source. An electrode is connected, and the third source electrode is connected to the second pixel electrode.

Hereinafter, a multi-domain liquid crystal display of the present invention will be described in detail with reference to the accompanying drawings.

7 is a circuit diagram illustrating an equivalent circuit of the multi-domain liquid crystal display of the present invention, FIG. 8 is a plan view of one pixel equivalent to that of FIG. 7, and FIGS. 9A to 9C are views of the multi-domain liquid crystal display of the present invention. It is a perspective view showing the thin film transistors formed three-dimensionally.

As shown in FIGS. 7 and 8, the multi-domain liquid crystal display of the present invention includes a first substrate 100 and a second substrate (not shown) in which a plurality of pixel regions are defined and formed to face each other, and the respective pixels. The first substrate 100 is divided into a first region (upper side based on the gate line 111 of FIG. 8) and a second region (lower side based on the gate line 111 of FIG. 8) across the region. A gate line 111 formed thereon, a data line 112 formed at one side of the pixel regions in a direction crossing the gate line 111, a first pixel electrode 113a formed at the first region, and In order to drive the second pixel electrode 113b and the first pixel electrode 113a formed in the second region, between the gate line 111 and the data line 112 of the first region, Of the first thin film transistor TFT1 having the width W1 and the length L, and the second pixel electrode 113b. For driving, a second thin film transistor TFT2 having a second width W2 and a length L between the gate line 111 and the data line 112 in the second region, and the second thin film transistor. A third thin film transistor TFT3 formed in the first width W1 and the length L in series with the TFT2, a common electrode (not shown) formed on the entire surface of the second substrate 200, and the first substrate It includes a liquid crystal layer (not shown) filled between the 100 and the second substrate (not shown). Here, the first pixel electrode 113a and the second pixel electrode 113b formed in the first region and the second region respectively include one or more slits 114 at predetermined portions. The dielectric film 211 is further included on the common electrode on the second substrate corresponding to the area between the slit 114 and the slit 114.

The illustrated multi-domain liquid crystal display is an example of a liquid crystal display of a VA (Verticla Alignment) mode in which one pixel area is divided into these regions to improve visibility. The first substrate 100 and the second substrate are shown. The top surfaces facing each other may further include a vertically oriented alignment film (not shown). The liquid crystal used in the liquid crystal layer is a liquid crystal having a negative refractive index. In the initial state, the liquid crystal is aligned in a vertical direction, and when driven by the thin film transistors in each region, pixel electrodes 113a and 113b for each region. The liquid crystal will be driven in a direction perpendicular to the vertical electric field formed between the common electrode and the common electrode.

On the other hand, the configuration of the thin film transistor formed in the first region and the second region of the pixel region is as follows.

8 and 9A, the first thin film transistor TFT1 includes a first gate electrode 111a, a first source electrode 122a, and a first drain electrode 121a. The gate electrode 111a extends from the gate line 111, the first drain electrode 121a extends from the data line 112, and the first source electrode 122a is formed of the first source electrode 122a. It is connected to one pixel electrode 113a.

As shown in FIG. 9B, the second thin film transistor TFT2 includes a second gate electrode 111b, a second source electrode 122b, and a second drain electrode 121b. 111b is formed to protrude from the gate line 111 toward the second region, the second drain electrode 121b is formed to extend from the data line, and the second source electrode 122b is formed in the third region. It is connected to the thin film transistor TFT3.

As illustrated in FIG. 9C, the third thin film transistor TFT3 includes a third gate electrode 111c, a third source electrode 122c, and a third drain electrode 122b, and the third gate electrode ( 111c extends from the gate line 111 toward the second region, and the third drain electrode 122b extends from the second source electrode 122b to be integrally formed or electrically connected. The third source electrode 122c is connected to the second pixel electrode 113b.

The second source electrode 122b and the third drain electrode are integrally formed or electrically connected to each other. When the second source electrode 122b is integrally formed, the second source electrode 122b of FIG. 9B is the third thin film transistor TFT3 of FIG. 9C. ), The width will be formed to extend from W2 to W1.

9A to 9C, reference numeral 107 denotes a gate insulating film formed on the front surface of the substrate 100 including gate electrodes 111a, 111b, and 111c, and 108 denotes a thin film transistor forming portion. It is a semiconductor layer formed.

ΔVg)에서 알 수 있는 바와 같이, 각 영역별 화소 전극측에 인접한 박막 트랜지스터의 게이트 전극과 소오스 전극 사이의 기생 캐패시턴스(Cgs)가 레벨 쉬프트 전압에 가장 크게 영향을 미치므로, 각 영역별 기생 캐패시턴스를 일치시키 위해 각 화소 전극에 인접한 박막 트랜지스터의 크기를 일치시킨다. 즉, 제 1 박막 트랜지스터(TFT1)와 제 2 박막 트랜지스터(TFT2)는 각각 미리 제 1, 제 2 화소 전극(113a, 113b)에 서로 다른 구동 전압을 인가하기 위해 서로 다른 크기로 미리 설계되어 있으므로, 제 2 박막 트랜지스터(TFT2)와 직렬로 연결되며 상기 제 1 박막 트랜지스터(TFT1)의 크기(W1, L)와 동일한 크기의 제 3 박막 트랜지스터를 더 형성하여 두어, 상기 제 2 화소 전극에 충전되는 전압에 가장 크게 영향을 미치는 요소인 기생 캐패시턴스(Cgs2)를 제 1 박막 트랜지스터와 동일하게 한다(Cgs1=Cgs2). 즉, 제 1 영역의 레벨 쉬프트 전압이 ΔVp1=

ΔVg 이며, 제 2 영역의 레벨 쉬프트 전압이 ΔVp2=

ΔVg라고 할 때, 분자항을 같게 유도하는 것이다.The configuration of the multi-domain liquid crystal display according to the present invention is such that the level shift voltage (?? Vp) difference for each region is generated when the dual thin film transistor is configured in the conventional VA mode. The structure is designed to minimize the shift voltage difference. That is, the equation for actually obtaining the level shift voltage (ΔVp =

As can be seen from ΔVg), the parasitic capacitance Cgs between the gate electrode and the source electrode of the thin film transistor adjacent to the pixel electrode side of each region has the greatest influence on the level shift voltage. To match, the size of the thin film transistor adjacent to each pixel electrode is matched. That is, since the first thin film transistor TFT1 and the second thin film transistor TFT2 are previously designed with different sizes in order to apply different driving voltages to the first and second pixel electrodes 113a and 113b in advance, A third thin film transistor connected in series with a second thin film transistor TFT2 and having a size equal to the size W1 and L of the first thin film transistor TFT1 is further formed to charge the second pixel electrode. The parasitic capacitance Cgs2, which is the most influential factor, is the same as that of the first thin film transistor (Cgs1 = Cgs2). That is, the level shift voltage of the first region is ΔVp1 =

ΔVg, and the level shift voltage of the second region is ΔVp2 =

When ΔVg, the molecular term is derived equally.

In the above configuration, only the parasitic capacitance Cgs2 between the gate and the source between the third thin film transistor TFT3 and the second pixel electrode 113b is higher than the second thin film transistor TFT2, and the level shift voltage ΔV2 of the second region. The parasitic capacitance due to the directly adjacent third thin film transistor TFT3 is most detected in the second pixel electrode 113b.

The multi-domain liquid crystal display of the present invention as described above has the following effects.

Considering that a difference in level shift voltage ΔVp is generated for each region, afterimage and flicker are generated, the level shift voltage difference is minimized for each region. That is, since the parasitic capacitance Cgs between the gate electrode and the source electrode of the thin film transistor adjacent to the pixel electrode side of each region when driving the pixel region into this region has the greatest influence on the level shift voltage. In order to match the parasitic capacitance, the size of the thin film transistor adjacent to each pixel electrode is matched. Since the first thin film transistor TFT1 and the second thin film transistor TFT2 are predesigned with different sizes to apply different driving voltages to the first and second pixel electrodes, respectively, the second thin film transistor TFT2 may be used. A third thin film transistor connected in series with the first thin film transistor TFT1 having the same size as the sizes W1 and L of the first thin film transistor TFT1 to further influence the voltage charged in the second pixel electrode. The parasitic capacitance Cgs2 is made the same as that of the first thin film transistor (Cgs1 = Cgs2).

This will prevent afterimage or flicker caused by the parasitic capacitance difference by region. Therefore, the visibility characteristic can be improved.

Claims (7)

A first substrate and a second substrate, each pixel area being defined and formed to face each other; A gate line formed on the first substrate to divide the pixel area into a first area and a second area across the pixel area; A data line formed on one side of the pixel regions in a direction crossing the gate line; A first pixel electrode formed in the first region; A second pixel electrode formed in the second region; A first thin film transistor having a first width W1 and a length L between the gate line and the data line of the first region for driving the first pixel electrode; In order to drive the second pixel electrode, a second thin film transistor having a second width W2 and a length L between the gate line and the data line of the second region, and in series with the second thin film transistor. A third thin film transistor having a first width W1 and a length L; And  And a liquid crystal layer filled between the first substrate and the second substrate. The method of claim 1, And the first pixel electrode and the second pixel electrode each include one or more slits in a predetermined portion. The method of claim 2, And a dielectric on the second substrate corresponding to the region between the slit and the slit. The method of claim 1, And the first substrate and the second substrate further comprise a vertically aligned alignment layer. The method of claim 1, The first thin film transistor includes a first gate electrode, a first source electrode, and a first drain electrode, And the first gate electrode is connected to the gate line, the first drain electrode is connected to the data line, and the first source electrode is connected to the first pixel electrode. The method of claim 1, The second thin film transistor includes a second gate electrode, a second source electrode, and a second drain electrode. The second gate electrode is connected to the gate line, the second drain electrode is connected to the data line, and the second source electrode is connected to the third thin film transistor. The method of claim 6, The third thin film transistor includes a third gate electrode, a third source electrode, and a third drain electrode, The third gate electrode is connected to the gate line, the third drain electrode is connected to the second source electrode, and the third source electrode is connected to the second pixel electrode. .

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