WO2017028510A1 - 一种射频开关电路和射频链路 - Google Patents

一种射频开关电路和射频链路 Download PDF

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WO2017028510A1
WO2017028510A1 PCT/CN2016/073785 CN2016073785W WO2017028510A1 WO 2017028510 A1 WO2017028510 A1 WO 2017028510A1 CN 2016073785 W CN2016073785 W CN 2016073785W WO 2017028510 A1 WO2017028510 A1 WO 2017028510A1
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resistor
circuit
pin
diodes
parallel
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PCT/CN2016/073785
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English (en)
French (fr)
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孙涵
宋林东
熊向飞
张利
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中兴通讯股份有限公司
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Publication of WO2017028510A1 publication Critical patent/WO2017028510A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

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  • the present invention relates to the field of electronic devices, and in particular to a radio frequency switching circuit and a radio frequency link.
  • LTE Long Term Evolution
  • SNR signal-to-noise ratio
  • the Relay Base Station improves the SNR by reducing the distance between the terminal and the Relay, which improves both capacity and coverage. Based on the spectrum used, Relay can be divided into two cases: in-band and out-of-band.
  • the RF switch circuit uses the TDD power amplifier transceiver switch, which has low transmission and reception isolation and poor reliability.
  • the embodiment of the invention provides a radio frequency switch circuit and a radio frequency link, which are used to solve the problem of the prior art in the in-band relay base station single board design, and the radio frequency switch circuit adopts the TDD power amplifier transceiver switch, and the transceiver has low isolation and reliability. Poor question.
  • an embodiment of the present invention provides a radio frequency switching circuit, including: two PIN diode series-parallel circuits and two isolation circuits, each of the PIN diode series-parallel circuits and one of the isolation circuits.
  • the PIN diode series-parallel circuit comprises: two sets of PIN diodes, each set of PIN diodes is composed of two parallel PIN diodes, the two sets of PIN diodes Connected in series to act as a switch for the circuit; the isolation circuit, comprising a branch consisting of two routing PIN diodes, provides a reverse bias voltage for a PIN diode series-parallel circuit in operation, and another PIN diode in an inactive state Series-parallel circuit provides positive bias voltage for isolation.
  • each of the PIN diode series-parallel circuits includes: two sets of PIN diodes, each set of PIN diodes comprising: two parallel PIN diodes of the same number;
  • anodes of the two diodes of the first group of PIN diodes are all connected to the RF input end, and the cathodes of the two diodes of the first group of PIN diodes are connected to the cathodes of the two diodes of the second group of PIN diodes
  • the anodes of the two diodes of the second group of PIN diodes are connected to the Uu port or the Un port;
  • a cathode of the two diodes of the first group of PIN diodes is further connected to one end of the first inductor, and the other end of the first inductor is connected to one end of the grounded first capacitor, and is also connected to the two resistors in parallel a resistor group, the other end of the resistor group is connected to an output of the control circuit to receive a control signal;
  • the cathode of the two diodes of the second group of PIN diodes is also connected to one end of the second inductor, and the other end of the second inductor is connected to one end of the grounded second capacitor, and is also connected to the resistor group.
  • each set of PIN diodes includes two parallel PIN diodes.
  • the isolation circuit includes: two isolation branches composed of two PIN diodes, four capacitors, and four resistors, and two isolated branches are connected in parallel, each branch Routing a PIN diode, two capacitors and a resistor; wherein an anode of a PIN diode of each branch is connected to an anode of two diodes of the second group of PIN diodes in the PIN diode series-parallel circuit,
  • the cathode of the PIN diode of each branch is connected to one end of the grounded third capacitor, and is also connected to one end of the first resistor, and the other end of the first resistor is connected to one end of the grounded fourth capacitor, and is also connected To one end of the second resistor, the other end of the second resistor is connected to the other output of the control circuit to receive another path control signal.
  • the method further includes: a three-way power supply circuit composed of three magnetic beads, three filtering devices, and three resistors; wherein each power supply circuit includes magnetic beads, filtering devices, and a resistor, the magnetic beads of each of the power supply circuits are connected to the power supply; the resistance of one of the three power supply circuits is connected to the symmetric position of the two symmetric RF switch circuits, and the other two power supply circuits are respectively connected to the The anodes of the two diodes of the second set of PIN diodes in the PIN diode series-parallel circuit are connected to the anode of the PIN diode in the isolation circuit.
  • the method further includes: the control circuit, wherein the control circuit outputs an output terminal and a third resistor of a control signal connected to the resistor group in the first group of PIN diodes
  • One end of the third resistor is connected to the base of the first PNP transistor, the emitter of the first PNP transistor is connected to one end of the fourth resistor, and the other end of the fourth resistor is a pair of parallel resistor groups are connected, the other end of the resistor group is connected to the RF input end, and the other end of the fourth resistor is further connected to a grounded fifth capacitor;
  • the first PNP type transistor a collector is coupled to the other output of the control circuit;
  • the other output end of the control circuit is further connected to one end of the fifth resistor, the other end of the fifth resistor is connected to the base of the second PNP type transistor, and the emitter and the second of the second PNP type transistor One end of the six resistors is connected, the other end of the sixth resistor is connected to the other end of the fourth resistor; the collector of the second PNP type transistor is connected to one end of the third resistor;
  • the collector of the first PNP transistor is further connected to the other output of the control circuit; the base of the first PNP transistor is connected to the drain of the first MOS transistor, and the first MOS transistor The drain is connected to the source through the first Schottky diode, the source is also grounded, the gate of the first MOS transistor is connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to the power supply Connected to the AN end of the converter;
  • a base of the second PNP transistor is connected to a drain of the second MOS transistor, the second The drain of the MOS transistor is connected to the source through a second Schottky diode, the source is also grounded, the gate of the second MOS transistor is connected to one end of the eighth resistor, and the other end of the eighth resistor
  • the power supply and the YOUT terminal of the converter are connected; the VCC terminal of the converter is connected to the sixth capacitor of the ground, and is also connected to the power supply through a magnetic bead, and the GND end of the converter is grounded.
  • the present invention provides a radio frequency link, comprising: the radio frequency switch circuit of any one of the above; the input end of the radio frequency switch circuit is connected to one port of the circulator, and the other end of the radio frequency switch circuit Connect to the Un or Uu port.
  • each PIN diode series-parallel circuit includes two sets of PIN diodes, each set of PIN diodes is composed of two parallel PIN diodes, and two sets of PIN diodes are connected in series.
  • two PIN diode series-parallel circuits form a symmetrical RF switch circuit, with low insertion loss, high reliability and isolation, and solve the prior art in the design of the in-band Relay base station single board, the RF switch circuit is more Adopting TDD power amplifier transceiver switch, its transmission and reception isolation is low, and the reliability is poor.
  • FIG. 1 is a schematic structural diagram of a radio frequency switch circuit according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of an isolation circuit in a radio frequency switch circuit according to an embodiment of the present invention
  • FIG. 3 is a diagram showing the position of a Relay switch in a radio frequency link in a preferred embodiment of the present invention
  • FIG. 4 is a schematic diagram showing the circuit structure of a Relay switch in a preferred embodiment of the present invention.
  • FIG. 5 is a schematic diagram showing the circuit structure of a driving circuit of a Relay switch in a preferred embodiment of the present invention.
  • the radio frequency switching circuit mostly adopts the TDD power amplifier transceiver switch, and the transmission and reception isolation is low, and the reliability is poor.
  • the invention provides a radio frequency switch circuit and a radio frequency chain.
  • the embodiment of the invention provides a radio frequency switch circuit.
  • the structure of the circuit is shown in FIG. 1 and includes:
  • each PIN diode series-parallel circuit and an isolation circuit form an RF switching circuit to obtain bilateral symmetry
  • the RF switching circuit wherein the PIN diode series-parallel circuit comprises: two sets of PIN diodes, each set of PIN diodes is composed of two parallel PIN diodes, two sets of PIN diodes are connected in series to serve as a circuit switch; the isolation circuit includes two A branch consisting of a routing PIN diode provides a reverse bias voltage for a PIN diode series-parallel circuit in operation and a positive bias voltage for another PIN diode series-parallel circuit in an inactive state for isolation.
  • each PIN diode series-parallel circuit includes two sets of PIN diodes, each set of PIN diodes is composed of two parallel PIN diodes, and two sets of PIN diodes are connected in series.
  • two PIN diode series-parallel circuits form a symmetrical RF switch circuit, with low insertion loss, high reliability and isolation, and solve the prior art in the design of the in-band Relay base station single board, the RF switch circuit is more Adopting TDD power amplifier transceiver switch, its transmission and reception isolation is low, and the reliability is poor.
  • each PIN diode series-parallel circuit comprises: two sets of PIN diodes, each set of PIN diodes comprising: two parallel PIN diodes of the same number (depending on requirements, for example two or four PIN diodes per channel) Wherein the anodes of the two diodes of the first group of PIN diodes are connected to the RF input end, and the cathodes of the two diodes of the first group of PIN diodes are connected to the cathodes of the two diodes of the second group of PIN diodes, The anodes of the two diodes of the second group of PIN diodes are connected to the Uu port or the Un port; the cathodes of the two diodes of the first group of PIN diodes are also connected to one end of the first inductor, and the other end of the first inductor is connected to the ground.
  • One end of the first capacitor is also connected to a resistor group formed by connecting two resistors in parallel, and the other end of the resistor group is connected Connected to one output of the control circuit to receive a control signal; the cathodes of the two diodes of the second group of PIN diodes are also connected to one end of the second inductor, and the other end of the second inductor is connected to the grounded second capacitor One end is also connected to the resistor bank.
  • the isolation circuit consists of two PIN diodes, four capacitors and four resistors.
  • the two isolated branches are connected in parallel.
  • Each branch is composed of a PIN diode, two capacitors and a resistor.
  • the structure diagram can be as shown in FIG. 2; wherein the anode of the PIN diode of each branch is connected to the anode of two diodes of the second group of PIN diodes in the PIN diode series-parallel circuit, and the PIN diode of each branch
  • One end of the third capacitor connected to the ground is also connected to one end of the first resistor, the other end of the first resistor is connected to one end of the fourth capacitor of the ground, and is also connected to one end of the second resistor, and the other of the second resistor
  • One end is connected to the other output of the control circuit to receive another control signal.
  • the device further comprises: a three-way power supply circuit composed of three magnetic beads, three filtering devices and three resistors; wherein each power supply circuit comprises magnetic beads, filtering devices and resistors connected in sequence, and magnetic circuit of each power supply circuit The bead is connected to the power supply; the resistance of one of the three power supply circuits is connected to the symmetric position of the symmetric RF switching circuit, and the other two power supply circuits are respectively connected to the second group of PIN diodes of the PIN diode series-parallel circuit The anode of the two-way diode is connected to the anode of the PIN diode in the isolation circuit.
  • the device further includes a control circuit, wherein an output end of the control signal connected to the resistor group of the first group of PIN diodes is connected to one end of the third resistor, and the other end of the third resistor is coupled to the first PNP
  • the base of the transistor is connected, the emitter of the first PNP transistor is connected to one end of the fourth resistor, the other end of the fourth resistor is connected to a pair of parallel resistor groups, and the other end of the resistor group is connected to the RF input terminal, The other end of the four resistor is also connected to the grounded fifth capacitor;
  • the collector of the first PNP transistor is connected to the other output of the control circuit;
  • the other output of the control circuit is also connected to one end of the fifth resistor,
  • the other end of the fifth resistor is connected to the base of the second PNP type transistor, and the emitter of the second PNP type transistor and the sixth resistor One end is connected, and the other end of the sixth resistor is connected to the other end of the fourth resistor; the
  • the collector of the first PNP transistor is further connected to the other output of the control circuit; the base of the first PNP transistor is connected to the drain of the first MOS transistor, and the drain of the first MOS transistor passes through the first Schott
  • the base diode is connected to the source, the source is also grounded, the gate of the first MOS transistor is connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to the power supply and the AN end of the converter;
  • the second PNP type transistor The base is connected to the drain of the second MOS transistor, the drain of the second MOS transistor is connected to the source through the second Schottky diode, the source is also grounded, and the gate of the second MOS transistor is connected to the eighth resistor One end is connected, and the other end of the eighth resistor is connected to the power supply and the YOUT terminal of the converter.
  • the VCC end of the above converter is connected to the sixth capacitor of the ground, and is also connected to the power supply through the magnetic beads, and the GND end of the converter is grounded.
  • the embodiment of the present invention further provides a radio frequency link, comprising: the radio frequency switch circuit of any one of the above; wherein the input end of the radio frequency switch circuit is connected to one port of the circulator, and the other end of the radio frequency switch circuit is connected to the Un port or Uu mouth.
  • the embodiment of the invention is directed to a symmetric, high-isolation, high-reliability RF switch that is added to the output of the power amplifier (PA) during the design phase of the in-band relay base station.
  • PA power amplifier
  • the RF switch provided in this embodiment is different from the TDD power amplifier transceiver switch.
  • the Relay switch RF circuit switch
  • the Relay switch is a symmetric switch applied to the symmetric RF switch between the power amplifier circulator 2 port and the connector, with low insertion loss and high isolation. Degree and RF signal passing through the switch for a long time, the reliability requirements are higher, the Un/Uu port isolation requirement is more than 50db, and the position in the RF link is shown in Figure 3.
  • the structure of the above RF switch circuit comprises a switch drive circuit (control circuit), a PIN diode series-parallel circuit and an isolation circuit, and the circuit structure thereof is shown in FIG. 4; the working principle is that when the power amplifier is switched to the Uu port, Un is isolated. Status, when switching to the Un port, the Uu port is isolated, the power, insertion loss, and isolation of the two ports are consistent, and the two ports are in normal use. In real-time, real-time switching is implemented according to high-level software control.
  • the left and right sides are completely symmetrical circuit diagrams. Below, the circuit on the left side is taken as an example.
  • the left dotted line frame 1 is surrounded by an isolation circuit, and the dotted line frame 2 is surrounded by a PIN diode string.
  • Parallel circuit; the drive circuit is not part of the switch itself, and therefore, is not shown in Figure 4, the drive circuit will be described in Figure 5.
  • the PIN diode series-parallel circuit includes: two sets of PIN diodes, each set of PIN diodes is a diode group in which a PIN diode is connected in parallel; wherein the anodes of the two diodes in the first group of PIN diodes are connected to the RF input
  • the cathodes of the two diodes of the first group of PIN diodes are connected to the cathodes of the two diodes of the second group of PIN diodes, and the anodes of the two diodes of the second group of PIN diodes are connected to the Un port (right part)
  • the circuit is connected to the Uu port; the cathode of the two diodes of the first group of PIN diodes is also connected to one end of the first inductor, the other end of the first inductor is connected to one end of the grounded first capacitor, and is also connected to two a resistor group in which the resistors are connected in parallel, the other end of the resist
  • the isolation circuit consists of two PIN diodes, four capacitors and four resistors.
  • the two isolated branches are connected in parallel.
  • Each branch is composed of a PIN diode, two capacitors and a resistor.
  • the anode of the PIN diode of one branch is connected to the anode of two diodes of the second group of PIN diodes in the PIN diode series-parallel circuit, and the cathode of the PIN diode of each branch is connected to one end of the grounded third capacitor, Connected to one end of the first resistor, the other end of the first resistor is connected to one end of the grounded fourth capacitor, and is also connected to one end of the second resistor, and the other end of the second resistor is connected to the other output of the control circuit to Receive another control signal.
  • a driving circuit is connected to the resistor group in the first group of PIN diodes.
  • the output end of the path control signal is connected to one end of the third resistor, and the other end of the third resistor is connected to the base of the first PNP type transistor, and the emitter of the first PNP type transistor is connected to one end of the fourth resistor, and the fourth resistor
  • the other end is connected to a pair of parallel resistor groups, the other end of the resistor group is connected to the RF input terminal, and the other end of the fourth resistor is also connected to the fifth capacitor of the ground;
  • the collector and control circuit of the first PNP transistor The other output is connected; the other output of the control circuit is further connected to one end of the fifth resistor, the other end of the fifth resistor is connected to the base of the second PNP type transistor, and the emitter and the second PNP type transistor are One end of the six resistors is connected, the other end of the sixth resistor is connected to the other end of the fourth resistor; the collector of the second P
  • the switch in order to adapt to the trend of miniaturization of the power amplifier board, the switch is implemented by using a PIN diode.
  • the heat dissipation of the PIN diode is relatively poor, and the diode is reduced in order to ensure heat dissipation of the diode and improve power amplifier efficiency.
  • the insertion loss is a critical issue, so two diodes are used in parallel to form a series switch, and the selected plastic PIN diode has a lower insertion loss for lower impedance.
  • the radio frequency switch provided by the embodiment has the following advantages: (1) different circuit forms can be selected according to different power, isolation, etc., to meet the customization requirements, and the inductance and capacitance models connected in parallel are adapted to different frequency bands. (2) Compared with other integrated switching devices, the switch of the embodiment can achieve smaller insertion loss and higher isolation, and the low insertion loss of the switch can effectively improve the efficiency of the power amplifier, and the high isolation can ensure Uu. Better isolation between the port and the Un port; (3) Compared with the integrated device, it has the advantage of low cost. The total cost is 2.5 yuan, which can reduce the cost by 85% compared with the switch chip provided by the manufacturer.
  • This embodiment uses a plastic-sealed diode, which has the advantages of low cost and simple welding process compared with the existing integrated switch module. And use ordinary PCB sheet and SMT processing technology, suitable for mass production; (5) Design corresponding drive circuit with small power consumption advantages, and ensure the switching speed of the switch.
  • each PIN diode series-parallel circuit includes two sets of PIN diodes, each set of PIN diodes is composed of two parallel PIN diodes, and two sets of PIN diodes are connected in series. Connection, two PIN diode series-parallel circuits form a symmetrical RF switch circuit, with low insertion loss, high reliability and isolation, and solve the prior art in the design of the in-band Relay base station single board, the RF switch circuit is more Adopt TDD
  • the power amplifier transceiver switch has low transmission and isolation isolation and poor reliability.

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Abstract

一种射频开关电路和射频链路，其中，该射频开关电路包括：两个PIN二极管串并联电路（11，12）和两个隔离电路（21，22），每个PIN二极管串并联电路（11，12）和一个隔离电路（21，22）组成一边射频开关电路，以得到两边对称的射频开关电路；其中，PIN二极管串并联电路（21，22）包括：两组PIN二极管，每组PIN二极管以并联的两路PIN二极管组成，两组PIN二极管串联连接，以作为电路的开关；隔离电路（21，22），包括两路由PIN二极管组成的支路，为一个处于工作状态的PIN二极管串并联电路提供反偏电压，为另一个处于非工作状态的PIN二极管串并联电路提供正偏电压，以进行隔离。

Description

一种射频开关电路和射频链路 技术领域
本发明涉及电子设备领域，特别是涉及一种射频开关电路和射频链路。
背景技术
长期演进(LTE，Long Term Evolution)是一个数据网络，为了给用户提供更高的速率，需要更高的信噪比(SNR，signal-to-noise ratio)。Relay基站(中继站，Relay Node)通过减少终端与Relay之间的距离以提高SNR，这样既可以提高容量，又可以改善覆盖。基于所使用的频谱来划分，Relay可以分为带内(in-band)和带外(out-of-band)这两种情况。
现有技术在带内Relay基站单板设计中，射频开关电路多采用TDD功放收发开关，其收发隔离度低，可靠性较差。
发明内容
本发明实施例提供一种射频开关电路和射频链路，用以解决现有技术在带内Relay基站单板设计中，射频开关电路多采用TDD功放收发开关，其收发隔离度低，可靠性较差的问题。
为解决上述技术问题，一方面，本发明实施例提供一种射频开关电路，包括：两个PIN二极管串并联电路和两个隔离电路，每个所述PIN二极管串并联电路和一个所述隔离电路组成一边射频开关电路，以得到两边对称的射频开关电路；其中，所述PIN二极管串并联电路包括：两组PIN二极管，每组PIN二极管以并联的两路PIN二极管组成，所述两组PIN二极管串联连接，以作为电路的开关；所述隔离电路，包括两路由PIN二极管组成的支路，为一个处于工作状态的PIN二极管串并联电路提供反偏电压，为另一个处于非工作状态的PIN二极管串并联电路提供正偏电压，以进行 隔离。
在本发明实施例一实施方式中，每个所述PIN二极管串并联电路包括：两组PIN二极管，每组PIN二极管包括：两路并联着相同个数的PIN二极管；
其中，第一组PIN二极管中的两路二极管的阳极均连接至射频输入端，所述第一组PIN二极管中的两路二极管的阴极均连接至第二组PIN二极管中的两路二极管的阴极，所述第二组PIN二极管中的两路二极管的阳极连接至Uu口或Un口；
所述第一组PIN二极管中的两路二极管的阴极还连接至第一电感的一端，所述第一电感的另一端连接至接地的第一电容的一端，还连接至由两个电阻并联而成的电阻组，所述电阻组的另一端连接至控制电路的一个输出端，以接收一路控制信号；
所述第二组PIN二极管中的两路二极管的阴极还连接至第二电感的一端，所述第二电感的另一端连接至接地的第二电容的一端，还连接至所述电阻组。
在本发明实施例一实施方式中，所述每组PIN二极管包括两个并联的PIN二极管。
在本发明实施例一实施方式中，所述隔离电路包括：由两个PIN二极管、四个电容和四个电阻组成的两路隔离支路，两个隔离支路组成的电路并联，每个支路由一个PIN二极管、两个电容和一个电阻组成；其中，每个支路的PIN二极管的阳极连接至所述PIN二极管串并联电路中的所述第二组PIN二极管中的两路二极管的阳极，所述每个支路的PIN二极管的阴极连接至接地的第三电容的一端，还连接至第一电阻的一端，所述第一电阻的另一端连接至接地的第四电容的一端，还连接至第二电阻的一端，所述第二电阻的另一端连接至所述控制电路的另一个输出端，以接收另一路 控制信号。
在本发明实施例一实施方式中，还包括：由三个磁珠、三个滤波装置和三个电阻组成的三路供电电路；其中，每一路供电电路包括依次连接的磁珠、滤波装置和电阻，所述每一路供电电路的磁珠连接至供电电源；三路供电电路中的一路供电电路的电阻连接至所述两边对称的射频开关电路的对称位置，其余两路供电电路分别连接至所述PIN二极管串并联电路中的所述第二组PIN二极管中的两路二极管的阳极和所述隔离电路中的PIN二极管的阳极连接。
在本发明实施例一实施方式中，还包括：所述控制电路，其中，所述控制电路与所述第一组PIN二极管中的所述电阻组连接的一路控制信号的输出端与第三电阻的一端连接，所述第三电阻的另一端与第一PNP型三极管的基极连接，所述第一PNP型三极管的发射极和第四电阻的一端连接，所述第四电阻的另一端和一对并联的电阻组连接，所述电阻组的另一端连接至所述射频输入端，所述所述第四电阻的另一端还和接地的第五电容连接；所述第一PNP型三极管的集电极和所述控制电路的另一个输出端连接；
所述控制电路的另一个输出端还和与第五电阻的一端连接，所述第五电阻的另一端与第二PNP型三极管的基极连接，所述第二PNP型三极管的发射极和第六电阻的一端连接，所述第六电阻的另一端和所述第四电阻的另一端连接；所述第二PNP型三极管的集电极和所述第三电阻的一端连接；
所述第一PNP型三极管的集电极还和所述控制电路的另一个输出端连接；所述第一PNP型三极管的基极连接至第一MOS管的漏极，所述第一MOS管的漏极通过第一肖特基二极管与源极连接，所述源极还接地连接，所述第一MOS管的栅极与第七电阻的一端连接，所述第七电阻的另一端与供电电源和转换器的AN端连接；
所述第二PNP型三极管的基极连接至第二MOS管的漏极，所述第二 MOS管的漏极通过第二肖特基二极管与源极连接，所述源极还接地连接，所述第二MOS管的栅极与第八电阻的一端连接，所述第八电阻的另一端与供电电源和所述转换器的YOUT端连接；所述转换器的VCC端与接地的第六电容连接，还通过磁珠连接至供电电源，所述转换器的GND端接地连接。
另一方面，本发明还提供一种射频链路，包括：上述任一项所述的射频开关电路；所述射频开关电路的输入端连接至环形器的一个端口，所述射频开关电路另一端连接至Un口或Uu口。
本发明实施例使用两个PIN二极管串并联电路作为开关，其中，每个PIN二极管串并联电路中包括两组PIN二极管，每组PIN二极管以并联的两路PIN二极管组成，且两组PIN二极管串联连接，两个PIN二极管串并联电路形成了对称的射频开关电路，插损较小，可靠性和隔离度都较高，解决了现有技术在带内Relay基站单板设计中，射频开关电路多采用TDD功放收发开关，其收发隔离度低，可靠性较差的问题。
附图说明
图1是本发明实施例中射频开关电路的结构示意图；
图2是本发明实施例中射频开关电路中隔离电路的结构示意图；
图3是本发明优选实施例中Relay开关在射频链路中的位置；
图4是本发明优选实施例中Relay开关的电路结构示意图；
图5是本发明优选实施例中Relay开关的驱动电路的电路结构示意图。
具体实施方式
为了解决现有技术在带内Relay基站单板设计中，射频开关电路多采用TDD功放收发开关，其收发隔离度低，可靠性较差的问题，本发明提供了一种射频开关电路和射频链路，以下结合附图以及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发 明，并不限定本发明。
本发明实施例提供一种射频开关电路，该电路的结构示意如图1所示，包括：
两个PIN二极管串并联电路(图中为11和12)和两个隔离电路(图中为21和22)，每个PIN二极管串并联电路和一个隔离电路组成一边射频开关电路，以得到两边对称的射频开关电路；其中，PIN二极管串并联电路包括：两组PIN二极管，每组PIN二极管以并联的两路PIN二极管组成，两组PIN二极管串联连接，以作为电路的开关；隔离电路，包括两路由PIN二极管组成的支路，为一个处于工作状态的PIN二极管串并联电路提供反偏电压，为另一个处于非工作状态的PIN二极管串并联电路提供正偏电压，以进行隔离。
本发明实施例使用两个PIN二极管串并联电路作为开关，其中，每个PIN二极管串并联电路中包括两组PIN二极管，每组PIN二极管以并联的两路PIN二极管组成，且两组PIN二极管串联连接，两个PIN二极管串并联电路形成了对称的射频开关电路，插损较小，可靠性和隔离度都较高，解决了现有技术在带内Relay基站单板设计中，射频开关电路多采用TDD功放收发开关，其收发隔离度低，可靠性较差的问题。
在实现时，每个PIN二极管串并联电路包括：两组PIN二极管，每组PIN二极管包括：两路并联着相同个数的PIN二极管(根据需求设置，例如每路两个或四个PIN二极管)；其中，第一组PIN二极管中的两路二极管的阳极均连接至射频输入端，第一组PIN二极管中的两路二极管的阴极均连接至第二组PIN二极管中的两路二极管的阴极，第二组PIN二极管中的两路二极管的阳极连接至Uu口或Un口；第一组PIN二极管中的两路二极管的阴极还连接至第一电感的一端，第一电感的另一端连接至接地的第一电容的一端，还连接至由两个电阻并联而成的电阻组，电阻组的另一端连 接至控制电路的一个输出端，以接收一路控制信号；第二组PIN二极管中的两路二极管的阴极还连接至第二电感的一端，第二电感的另一端连接至接地的第二电容的一端，还连接至电阻组。
隔离电路由两个PIN二极管、四个电容和四个电阻组成的两路隔离支路，两个隔离支路组成的电路并联，每个支路由一个PIN二极管、两个电容和一个电阻组成，其结构示意可以如图2所示；其中，每个支路的PIN二极管的阳极连接至PIN二极管串并联电路中的第二组PIN二极管中的两路二极管的阳极，每个支路的PIN二极管的阴极连接至接地的第三电容的一端，还连接至第一电阻的一端，第一电阻的另一端连接至接地的第四电容的一端，还连接至第二电阻的一端，第二电阻的另一端连接至控制电路的另一个输出端，以接收另一路控制信号。
上述装置还包括：由三个磁珠、三个滤波装置和三个电阻组成的三路供电电路；其中，每一路供电电路包括依次连接的磁珠、滤波装置和电阻，每一路供电电路的磁珠连接至供电电源；三路供电电路中的一路供电电路的电阻连接至两边对称的射频开关电路的对称位置，其余两路供电电路分别连接至PIN二极管串并联电路中的第二组PIN二极管中的两路二极管的阳极和隔离电路中的PIN二极管的阳极连接。
优选的，上述装置还包括控制电路，其中，控制电路与第一组PIN二极管中的电阻组连接的一路控制信号的输出端与第三电阻的一端连接，第三电阻的另一端与第一PNP型三极管的基极连接，第一PNP型三极管的发射极和第四电阻的一端连接，第四电阻的另一端和一对并联的电阻组连接，电阻组的另一端连接至射频输入端，第四电阻的另一端还和接地的第五电容连接；第一PNP型三极管的集电极和控制电路的另一个输出端连接；控制电路的另一个输出端还和与第五电阻的一端连接，第五电阻的另一端与第二PNP型三极管的基极连接，第二PNP型三极管的发射极和第六电阻的 一端连接，第六电阻的另一端和第四电阻的另一端连接；第二PNP型三极管的集电极和第三电阻的一端连接。
上述第一PNP型三极管的集电极还和控制电路的另一个输出端连接；第一PNP型三极管的基极连接至第一MOS管的漏极，第一MOS管的漏极通过第一肖特基二极管与源极连接，源极还接地连接，第一MOS管的栅极与第七电阻的一端连接，第七电阻的另一端与供电电源和转换器的AN端连接；第二PNP型三极管的基极连接至第二MOS管的漏极，第二MOS管的漏极通过第二肖特基二极管与源极连接，源极还接地连接，第二MOS管的栅极与第八电阻的一端连接，第八电阻的另一端与供电电源和转换器的YOUT端连接。
上述转换器的VCC端与接地的第六电容连接，还通过磁珠连接至供电电源，转换器的GND端接地连接。
本发明实施例还提供一种射频链路，其包括：上述任一项的射频开关电路；其中，射频开关电路的输入端连接至环形器的一个端口，射频开关电路另一端连接至Un口或Uu口。
本发明实施例针对带内Relay基站单板设计实现阶段在功放(PA)输出部分增加的一种对称型、高隔离度、高可靠性的射频开关。
本实施例提供的射频开关与TDD功放收发开关不同，Relay开关(射频电路开关)是一种对称开关，应用在功放环形器2口与连接器之间的对称射频开关，低插损、高隔离度、且射频信号长时间通过开关，可靠性要求更高，Un/Uu口隔离度要求50db以上，在射频链路中的位置如图3所示。上述射频开关电路的结构组成包括开关驱动电路(控制电路)、PIN二极管串并联电路和隔离电路，其电路结构如图4所示；其工作原理是，当功放切换到Uu口时，Un处于隔离状态，当切换到Un口时，Uu口处于隔离，两个端口承受的功率、插损以及隔离度保持一致，两个端口在正常使用状 态下，根据高层软件控制实现实时切换。
下面，基于图4说明对上述射频开关电路进行详细说明。
从图4中可以看出，左右两侧完全是对称的电路图，下面，以左侧部分的电路为例进行说明，左侧虚线框1包围的为隔离电路，虚线框2包围的为PIN二极管串并联电路；驱动电路不属于开关本身的一部分，因此，并未在图4中示出，将在图5中对驱动电路进行说明。
在图4中，PIN二极管串并联电路包括：两组PIN二极管，每组PIN二极管为并联着一个PIN二极管的二极管组；其中，第一组PIN二极管中的两路二极管的阳极均连接至射频输入端，第一组PIN二极管中的两路二极管的阴极均连接至第二组PIN二极管中的两路二极管的阴极，第二组PIN二极管中的两路二极管的阳极连接至Un口(右侧部分电路连接至Uu口)；第一组PIN二极管中的两路二极管的阴极还连接至第一电感的一端，第一电感的另一端连接至接地的第一电容的一端，还连接至由两个电阻并联而成的电阻组，电阻组的另一端连接至控制电路的一个输出端，以接收一路控制信号；第二组PIN二极管中的两路二极管的阴极还连接至第二电感的一端，第二电感的另一端连接至接地的第二电容的一端，还连接至电阻组。
隔离电路由两个PIN二极管、四个电容和四个电阻组成的两路隔离支路，两个隔离支路组成的电路并联，每个支路由一个PIN二极管、两个电容和一个电阻组成，每个支路的PIN二极管的阳极连接至PIN二极管串并联电路中的第二组PIN二极管中的两路二极管的阳极，每个支路的PIN二极管的阴极连接至接地的第三电容的一端，还连接至第一电阻的一端，第一电阻的另一端连接至接地的第四电容的一端，还连接至第二电阻的一端，第二电阻的另一端连接至控制电路的另一个输出端，以接收另一路控制信号。
如图5所示，驱动电路与上述第一组PIN二极管中的电阻组连接的一 路控制信号的输出端与第三电阻的一端连接，第三电阻的另一端与第一PNP型三极管的基极连接，第一PNP型三极管的发射极和第四电阻的一端连接，第四电阻的另一端和一对并联的电阻组连接，电阻组的另一端连接至射频输入端，第四电阻的另一端还和接地的第五电容连接；第一PNP型三极管的集电极和控制电路的另一个输出端连接；控制电路的另一个输出端还和与第五电阻的一端连接，第五电阻的另一端与第二PNP型三极管的基极连接，第二PNP型三极管的发射极和第六电阻的一端连接，第六电阻的另一端和第四电阻的另一端连接；第二PNP型三极管的集电极和第三电阻的一端连接；上述第一PNP型三极管的集电极还和控制电路的另一个输出端连接；第一PNP型三极管的基极连接至第一MOS管的漏极，第一MOS管的漏极通过第一肖特基二极管与源极连接，源极还接地连接，第一MOS管的栅极与第七电阻的一端连接，第七电阻的另一端与供电电源和转换器的AN端连接；第二PNP型三极管的基极连接至第二MOS管的漏极，第二MOS管的漏极通过第二肖特基二极管与源极连接，源极还接地连接，第二MOS管的栅极与第八电阻的一端连接，第八电阻的另一端与供电电源和转换器的YOUT端连接；上述转换器的VCC端与接地的第六电容连接，还通过磁珠连接至供电电源，转换器的GND端接地连接。
在本发明上述实施例中，为适应功放板小型化的趋势，开关使用PIN二极管来实现，与集成开关模块相比，PIN二极管散热相对较差，为了保证二极管的散热以及提高功放效率，降低二极管的插损是一个很关键的问题，所以使用两个二极管并联来组成串联开关，并且所选用的塑封PIN二极管插损较低，从而实现更低的阻抗。
为了保证开关的隔离度，在Uu和Un支路，均采用了两组并联的PIN二极管串联组成的形式，同时链路上的插损也得到改善。且在链路上增加两个对地正偏二极管，当Uu口导通时，Un端的并联二极管对地导通，提 高隔离度。同样，Un口导通时，Uu口并联二极管对地导通。为了保证开关的速度，并减小驱动电路的功耗，设计了驱动电路。驱动电路用双极晶体管替代了上拉电阻，基极由另一侧的电位控制。
采用本实施例提供的射频开关，具有以下优势：(1)可以根据不同功率，隔离度等需求，选择不同的电路形式，满足定制化需求，通过改变并联的电感、电容型号，适应不同频段的要求；(2)本实施例的开关与其他集成开关器件相比，能够做到更小的插损和更高的隔离度，开关低插损可以有效地提高功放效率，高隔离度可以保证Uu口与Un口更好的隔离；(3)与集成器件相比，具有成本低的优点。总成本在2.5元，相比厂家提供的开关芯片，可降低85％的成本；(4)本实施例使用塑封的二极管，与现成的集成开关模块相比，具有低成本，焊接工艺简单的优点，并且使用普通的PCB板材和SMT加工工艺，适用于批量生产；(5)设计了相应的具有功耗小优点的驱动电路，并保证了开关的切换速度。
尽管为示例目的，已经公开了本发明的优选实施例，本领域的技术人员将意识到各种改进、增加和取代也是可能的，因此，本发明的范围应当不限于上述实施例。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
本发明实施例使用两个PIN二极管串并联电路作为开关，其中，每个PIN二极管串并联电路中包括两组PIN二极管，每组PIN二极管以并联的两路PIN二极管组成，且两组PIN二极管串联连接，两个PIN二极管串并联电路形成了对称的射频开关电路，插损较小，可靠性和隔离度都较高，解决了现有技术在带内Relay基站单板设计中，射频开关电路多采用TDD
功放收发开关，其收发隔离度低，可靠性较差的问题。

Claims (7)

  1. 一种射频开关电路，包括：
    两个PIN二极管串并联电路和两个隔离电路，每个所述PIN二极管串并联电路和一个所述隔离电路组成一边射频开关电路，以得到两边对称的射频开关电路；其中，
    所述PIN二极管串并联电路包括：两组PIN二极管，每组PIN二极管以并联的两路PIN二极管组成，所述两组PIN二极管串联连接，以作为电路的开关；
    所述隔离电路，包括两路由PIN二极管组成的支路，为一个处于工作状态的PIN二极管串并联电路提供反偏电压，为另一个处于非工作状态的PIN二极管串并联电路提供正偏电压，以进行隔离。
  2. 如权利要求1所述的射频开关电路，其中，每个所述PIN二极管串并联电路包括：
    两组PIN二极管，每组PIN二极管包括：两路并联着相同个数的PIN二极管；
    其中，第一组PIN二极管中的两路二极管的阳极均连接至射频输入端，所述第一组PIN二极管中的两路二极管的阴极均连接至第二组PIN二极管中的两路二极管的阴极，所述第二组PIN二极管中的两路二极管的阳极连接至Uu口或Un口；
    所述第一组PIN二极管中的两路二极管的阴极还连接至第一电感的一端，所述第一电感的另一端连接至接地的第一电容的一端，还连接至由两个电阻并联而成的电阻组，所述电阻组的另一端连接至控制电路的一个输出端，以接收一路控制信号；
    所述第二组PIN二极管中的两路二极管的阴极还连接至第二电感的一端，所述第二电感的另一端连接至接地的第二电容的一端，还连接至所述 电阻组。
  3. 如权利要求2所述的射频开关电路，其中，所述每组PIN二极管包括两个并联的PIN二极管。
  4. 如权利要求2所述的射频开关电路，其中，所述隔离电路包括：
    由两个PIN二极管、四个电容和四个电阻组成的两路隔离支路，两个隔离支路组成的电路并联，每个支路由一个PIN二极管、两个电容和一个电阻组成；
    其中，每个支路的PIN二极管的阳极连接至所述PIN二极管串并联电路中的所述第二组PIN二极管中的两路二极管的阳极，所述每个支路的PIN二极管的阴极连接至接地的第三电容的一端，还连接至第一电阻的一端，所述第一电阻的另一端连接至接地的第四电容的一端，还连接至第二电阻的一端，所述第二电阻的另一端连接至所述控制电路的另一个输出端，以接收另一路控制信号。
  5. 如权利要求4所述的射频开关电路，其中，还包括：
    由三个磁珠、三个滤波装置和三个电阻组成的三路供电电路；其中，
    每一路供电电路包括依次连接的磁珠、滤波装置和电阻，所述每一路供电电路的磁珠连接至供电电源；
    三路供电电路中的一路供电电路的电阻连接至所述两边对称的射频开关电路的对称位置，其余两路供电电路分别连接至所述PIN二极管串并联电路中的所述第二组PIN二极管中的两路二极管的阳极和所述隔离电路中的PIN二极管的阳极连接。
  6. 如权利要求5所述的射频开关电路，其中，还包括：
    所述控制电路，其中，所述控制电路与所述第一组PIN二极管中的所述电阻组连接的一路控制信号的输出端与第三电阻的一端连接，所述第三电阻的另一端与第一PNP型三极管的基极连接，所述第一PNP型三极管的 发射极和第四电阻的一端连接，所述第四电阻的另一端和一对并联的电阻组连接，所述电阻组的另一端连接至所述射频输入端，所述所述第四电阻的另一端还和接地的第五电容连接；所述第一PNP型三极管的集电极和所述控制电路的另一个输出端连接；
    所述控制电路的另一个输出端还和与第五电阻的一端连接，所述第五电阻的另一端与第二PNP型三极管的基极连接，所述第二PNP型三极管的发射极和第六电阻的一端连接，所述第六电阻的另一端和所述第四电阻的另一端连接；所述第二PNP型三极管的集电极和所述第三电阻的一端连接；
    所述第一PNP型三极管的集电极还和所述控制电路的另一个输出端连接；
    所述第一PNP型三极管的基极连接至第一MOS管的漏极，所述第一MOS管的漏极通过第一肖特基二极管与源极连接，所述源极还接地连接，所述第一MOS管的栅极与第七电阻的一端连接，所述第七电阻的另一端与供电电源和转换器的AN端连接；
    所述第二PNP型三极管的基极连接至第二MOS管的漏极，所述第二MOS管的漏极通过第二肖特基二极管与源极连接，所述源极还接地连接，所述第二MOS管的栅极与第八电阻的一端连接，所述第八电阻的另一端与供电电源和所述转换器的YOUT端连接；
    所述转换器的VCC端与接地的第六电容连接，还通过磁珠连接至供电电源，所述转换器的GND端接地连接。
  7. 一种射频链路，包括：如权利要求1至6中任一项所述的射频开关电路；
    所述射频开关电路的输入端连接至环形器的一个端口，所述射频开关电路另一端连接至Un口或Uu口。
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