WO2017028327A1 - 一种液晶面板的esd保护电路 - Google Patents

一种液晶面板的esd保护电路 Download PDF

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Publication number
WO2017028327A1
WO2017028327A1 PCT/CN2015/088013 CN2015088013W WO2017028327A1 WO 2017028327 A1 WO2017028327 A1 WO 2017028327A1 CN 2015088013 W CN2015088013 W CN 2015088013W WO 2017028327 A1 WO2017028327 A1 WO 2017028327A1
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Prior art keywords
tube
ntft
ptft
signal line
input signal
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PCT/CN2015/088013
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English (en)
French (fr)
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彭香艺
陈归
张启沛
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深圳市华星光电技术有限公司
武汉华星光电技术有限公司
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Publication of WO2017028327A1 publication Critical patent/WO2017028327A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to an ESD protection circuit for a liquid crystal panel.
  • FIG. 2 it is an ESD protection circuit in the prior art. As can be seen from FIG. 2, when the gate of NTFT1 is at a high level, NTFT1 is turned on, and vice versa. When the gate of PTFT1 is at a low level, PTFT1 is turned on, and vice versa.
  • An object of the present invention is to provide an ESD protection circuit for a liquid crystal panel, which can reduce undesirable phenomena such as bright lines or dark lines caused by leakage of the ESD device of the liquid crystal panel.
  • An ESD protection circuit for a liquid crystal panel comprising:
  • a high level wire and a low level wire which are electrostatic output lines
  • a base unit includes an electrostatic input signal line, a first PTFT tube and a first NTFT tube, a gate and a source of the first PTFT tube being connected to the high level lead, and a gate of the first NTFT tube a pole and a source are connected to the low-level wire, a drain of the first PTFT tube is connected to a drain of the first NTFT tube, the static input signal line and the first PTFT tube and the first NTFT tube a common terminal connection between the drains;
  • An RC integrating circuit includes a resistor and a second NTFT tube, wherein one end of the resistor is connected to the high level wire, and the other end is connected to a gate of the second NTFT tube, and a source of the second NTFT tube And a drain connected to the low level wire;
  • a CTFT inverter comprising a second PTFT tube and a third NTFT tube, a source of the second PTFT tube being connected to the high level lead, a source of the third NTFT tube and the low level a wire connection, a drain of the second PTFT tube is connected to a drain of the third NTFT tube, a gate of the second PTFT tube is connected to a gate of the third NTFT tube, and the resistor and the second a common end of the gate of the PTFT tube and a common end between the second PTFT tube and the gate of the third NTFT tube;
  • a fourth NTFT tube having a gate and a second PTFT tube connected to a drain connection line of the third NTFT tube, wherein the source and the drain are respectively connected to the high level lead and the low level lead;
  • the base unit, the RC integration circuit, the CTFT inverter, and the fourth NTFT tube are sequentially arranged on the ESD protection circuit, and when the ESD phenomenon does not occur, the potential of the electrostatic input signal line is between the high power between the potential of the flat wire and the low level wire, the first NTFT tube, the third NTFT tube, the fourth NTFT tube, the first PTFT tube and the second PTFT tube are all closed.
  • the first NTFT tube is turned on, and the first PTFT tube, the second PTFT tube, the third NTFT tube, and the fourth NTFT tube are both turned off.
  • the first PTFT tube, the second PTFT tube and the fourth NTFT tube are turned on, and the first NTFT tube and the third NTFT tube are closed.
  • the first NTFT tube is turned on, the second PTFT tube is turned on, and the third NTFT tube is turned off.
  • the first NTFT tube and the third NTFT tube are closed, and the first PTFT tube, the second PTFT tube and the fourth NTFT tube are turned on.
  • the static electricity generated by the liquid crystal panel is discharged through the electrostatic input signal line and the low-level wire, and the potential of the electrostatic input signal line is higher than a potential of the high-level wire
  • the static electricity generated by the liquid crystal panel is input through the electrostatic input signal line, flows to the high-level wire through the first PTFT tube, and flows to the low level through the second PTFT tube and the fourth NTFT tube.
  • the wire is vented.
  • the static electricity generated by the liquid crystal panel is discharged through the electrostatic input signal line and the high-level wire, and the potential of the electrostatic input signal line is lower than a potential of the high-level wire
  • the static electricity generated by the liquid crystal panel is input through the electrostatic input signal line, flows to the low-level wire through the first NTFT tube, and flows to the high level through the fourth NTFT tube and the second PTFT tube.
  • the wire is vented.
  • the second NTFT tube is replaced by a capacitor.
  • An ESD protection circuit for a liquid crystal panel comprising:
  • a high level wire and a low level wire which are electrostatic output lines
  • a base unit includes an electrostatic input signal line, a first PTFT tube and a first NTFT tube, a gate and a source of the first PTFT tube being connected to the high level lead, and a gate of the first NTFT tube a pole and a source are connected to the low-level wire, a drain of the first PTFT tube is connected to a drain of the first NTFT tube, the static input signal line and the first PTFT tube and the first NTFT tube a common terminal connection between the drains;
  • An RC integrating circuit includes a resistor and a second NTFT tube, wherein one end of the resistor is connected to the high level wire, and the other end is connected to a gate of the second NTFT tube, and a source of the second NTFT tube And a drain connected to the low level wire;
  • a CTFT inverter comprising a second PTFT tube and a third NTFT tube, a source of the second PTFT tube being connected to the high level lead, a source of the third NTFT tube and the low level a wire connection, a drain of the second PTFT tube is connected to a drain of the third NTFT tube, a gate of the second PTFT tube is connected to a gate of the third NTFT tube, and the resistor and the second a common end of the gate of the PTFT tube and a common end between the second PTFT tube and the gate of the third NTFT tube;
  • a fourth NTFT tube having a gate and a second PTFT tube connected to a drain connection line of the third NTFT tube, wherein the source and the drain are respectively connected to the high level lead and the low level lead;
  • the base unit, the RC integration circuit, the CTFT inverter, and the fourth NTFT tube are sequentially arranged on the ESD protection circuit.
  • the potential of the electrostatic input signal line is between the potential of the high-level wire and the low-level wire, and the first NTFT tube, the third NTFT tube, and the fourth The NTFT tube, the first PTFT tube and the second PTFT tube are both closed.
  • the first An NTFT tube is turned on, and the first PTFT tube, the second PTFT tube, the third NTFT tube, and the fourth NTFT tube are both turned off.
  • the first A PTFT tube, a second PTFT tube and a fourth NTFT tube are turned on, and the first NTFT tube and the third NTFT tube are closed.
  • the first An NTFT tube is turned on, the second PTFT tube is electrically connected to the fourth NTFT tube, and the third NTFT tube is closed with the first PTFT tube.
  • the first An NTFT tube and a third NTFT tube are turned off, and the first PTFT tube, the second PTFT tube, and the fourth NTFT tube are turned on.
  • the liquid crystal panel when static electricity generated by the liquid crystal panel is discharged through the electrostatic input signal line and the low-level wire, and the potential of the electrostatic input signal line is lower than the potential of the low-level wire, the liquid crystal The static electricity generated by the panel is input through the electrostatic input signal line, and is discharged to the low-level wire through the first NTFT tube.
  • the liquid crystal panel when static electricity generated by the liquid crystal panel is discharged through the electrostatic input signal line and the low-level wire, and the potential of the electrostatic input signal line is higher than the potential of the high-level wire, the liquid crystal
  • the static electricity generated by the panel is input through the electrostatic input signal line, flows to the high-level wire through the first PTFT tube, and flows to the low-level wire through the second PTFT tube and the fourth NTFT tube. Release.
  • the liquid crystal panel when static electricity generated by the liquid crystal panel is discharged through the electrostatic input signal line and the high-level wire, and the potential of the electrostatic input signal line is lower than the potential of the high-level wire, the liquid crystal
  • the static electricity generated by the panel is input through the electrostatic input signal line, flows through the first NTFT tube to the low-level wire, and then flows to the high-level wire through the fourth NTFT tube and the second PTFT tube. Release.
  • the liquid crystal panel when static electricity generated by the liquid crystal panel is discharged through the electrostatic input signal line and the high-level wire, and the potential of the electrostatic input signal line is higher than the potential of the high-level wire, the liquid crystal The static electricity generated by the panel is input through the electrostatic input signal line, and is discharged to the high-level wire through the first PTFT tube.
  • the ESD protection circuit of a liquid crystal panel of the present invention effectively reduces the undesirable phenomena such as bright lines or dark lines caused by leakage of the ESD device of the liquid crystal panel by providing a circuit structure such as an RC integration circuit and a CTFT inverter. Expanded the range of process for LCD panels.
  • FIG. 1 is a structural diagram of an ESD protection circuit of the present invention
  • FIG. 2 is a structural diagram of a prior art ESD protection circuit.
  • FIG. 1 which is a structural diagram of an ESD protection circuit of the present invention
  • the ESD protection circuit of a liquid crystal panel of the present invention has a general structure including a high-level wire VH and a low-level wire VL.
  • a basic unit an RC integration circuit, a CTFT inverter and a fourth NTFT tube. These five parts are discussed below.
  • the high level wire VH and the low level wire VL wherein the potential of the high level wire VH and the potential of the low level wire VL remain unchanged.
  • a base unit includes an electrostatic input signal line Signal, a first PTFT tube and a first NTFT tube, and a gate and a source of the first PTFT tube are connected to the high level lead VH, the first NTFT tube a gate and a source are connected to the low-level wire VL, a drain of the first PTFT tube is connected to a drain of the first NTFT tube, the static input signal line Signal and the first PTFT tube are A common terminal connection between the drains of the first NTFT transistors.
  • An RC integrating circuit includes a resistor R and a second NTFT tube, one end of the resistor R is connected to the high level wire VH, and the other end is connected to the gate of the second NTFT tube, the second NTFT tube The source and drain are connected to the low level wire VL. Since the second NTFT tube functions as a capacitor in the circuit of the present invention, the second NTFT tube of the present embodiment can be replaced with a normal capacitor.
  • a CTFT inverter comprising a second PTFT tube and a third NTFT tube, a source of the second PTFT tube being connected to the high level wire VH, a source of the third NTFT tube and the low battery a flat wire VL is connected, a drain of the second PTFT tube is connected to a drain of the third NTFT tube, a gate of the second PTFT tube is connected to a gate of the third NTFT tube, and the resistor R and the A common end of the gate of the second PTFT tube and a common end between the second PTFT tube and the gate of the third NTFT tube are connected.
  • a fourth NTFT transistor having a gate and a second PTFT transistor connected to a drain connection line of the third NTFT transistor, wherein the source and the drain are respectively connected to the high-level wire VH and the low-level wire VL .
  • the electrostatic input signal line Signal is an electrostatic input end, and one end of the high-level wire VH and the low-level wire VL connected to the fourth NTFT tube is an electrostatic output end.
  • the potentials of the high-level wire and the low-level wire remain unchanged.
  • the potential of the electrostatic input signal line Signal is between the potential of the high-level wire VH and the low-level wire VL, and the first NTFT tube, the third NTFT tube, and the fourth The NTFT tube, the first PTFT tube and the second PTFT tube are both closed.
  • the electrostatic input signal line is only when an ESD phenomenon occurs in the circuit.
  • the potential of the Signal is lower than the potential of the low level wire VL or higher than the potential of the high level wire VH.
  • the NTFT is turned on when the gate of the N-type TFT is at a high level, and the PTFT is turned off when the gate of the P-type TFT is at a high level, when the potential of the electrostatic input signal line Signal is lower than the low-level wire VL At the potential, the first NTFT tube is turned on, and the first PTFT tube is turned off.
  • the potential of the electrostatic input signal line Signal is higher than the potential of the high-level wire VH, the first NTFT tube is turned off, and the first PTFT tube is turned on. According to the position where the ESD phenomenon occurs, the case where the charge generated by the ESD is discharged in this embodiment can be classified into the following types:
  • the first PTFT tube, the second PTFT tube and the fourth NTFT tube are turned on, and the first NTFT tube and the third NTFT tube are closed.
  • the electric charge generated by the ESD first flows to the high-level wire VH.
  • the second NTFT tube is equivalent to a capacitor, and the potential of the RC integrating circuit is to reach the high-level wire VH.
  • the potential needs a certain time, the voltage of the second NTFT tube does not rise to the potential on the high-level wire VH instantaneously, and the resistor R also occupies a certain potential, but at this time the source of the second PTFT tube
  • the extreme potential has risen to a potential on the high-level wire VH such that the potential of the gate terminal of the second PTFT tube, that is, the potential at the Q point is lower than the potential on the high-level wire VH, thereby making
  • the two PTFT tubes are turned on, at which time the potential on the high-level wire VH begins to enter the gate terminal of the fourth NTFT tube, so that the fourth NTFT tube is turned on, at which time the high-level wire VH is low.
  • the level wire VL forms a bleed passage through the fourth NTFT tube that is turned on, and the static electricity generated by the liquid crystal panel is input through the electrostatic input signal line, and flows to the high-level wire through the first PTFT tube. And flowing through the second PTFT tube and the fourth NTFT tube The low level wire is vented.
  • the first NTFT tube is turned on, the second PTFT tube and the fourth NTFT tube are turned on, and the third NTFT tube and the first PTFT tube are turned off.
  • the charge generated by the ESD first flows to the low-level wire VL.
  • the second NTFT tube is equivalent to a capacitor, and the potential of the RC integration circuit needs to reach the potential on the high-level wire VH.
  • the potential of the second NTFT tube does not rise to the potential on the high-level wire VH instantaneously, and the resistor R also occupies a certain potential, but at this time the potential of the source terminal of the second PTFT tube Has risen to a potential on the high-level wire VH such that the potential of the gate terminal of the second PTFT tube, that is, the potential at the Q point is lower than the potential on the high-level wire VH, thereby causing the second PTFT tube Is turned on, that is, the potential on the high-level wire VH starts to enter the gate end of the fourth NTFT tube, so that the fourth NTFT tube is turned on, at which time the high-level wire VH and the low-level wire VL forms a bleed passage through the fourth NTFT tube that is turned on, and static electricity generated by the liquid crystal panel is input through the electrostatic input signal line, flows through the first NTFT tube to the low-level wire, and then passes through The fourth NTFT tube and

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Abstract

一种液晶面板的ESD保护电路，总的结构包括高电平导线VH与低电平导线V L、一基础单元、一RC积分电路、一CTFT反相器和一第四NTFT管五个部分，其中所述基础单元、RC积分电路、CTFT反相器与第四NTFT管在所述ESD保护电路上顺序排列。

Description

一种液晶面板的ESD保护电路 技术领域
本发明涉及液晶显示器技术领域，特别涉及一种液晶面板的ESD保护电路。
 背景技术
目前，液晶面板电路的静电放电（Electro-Static Discharge，ESD）现象比较严重，电路受到ESD损伤的情形已经非常普遍。为了有效防止ESD对电路的损伤，特别是对于薄膜晶体管（Thin film transitor，TFT）现有技术采取了很多技术方案来解决。如图2所示，为现有技术中的一种ESD保护电路。从图2可以看出，当NTFT1的栅极为高电平时，NTFT1开启，反之则关闭。PTFT1的栅极为低电平时，PTFT1开启，反之则关闭。图2右侧的PTFT2和NTFT2长期处于反偏状态，而且承受的反偏电压一般高达17V（正常工作时，VH=10V，VL=-7V），这样就存在很大的漏电风险，再加上制程工艺的不稳定，TFT甚至有可能被击穿，如果TFT被击穿，TFT器件的漏电就会流到静电输入信号线Signal上面，容易使静电输入信号线Signal产生两线和暗线等不良现象，影响液晶面板的生产质量。
如何防止ESD对液晶面板电路的损伤，已经成为亟待解决的技术问题。
 技术问题
本发明的目的在于提供一种液晶面板的ESD保护电路，该电路可以减少液晶面板的ESD器件的漏电所述引起的亮线或暗线等不良现象。
 技术解决方案
一种液晶面板的ESD保护电路，其包括：
高电平导线与低电平导线，其为静电输出线；
一基础单元，其包括静电输入信号线、第一PTFT管与第一NTFT管，所述第一PTFT管的栅极及源极与所述高电平导线连接，所述第一NTFT管的栅极及源极与所述低电平导线连接，所述第一PTFT管的漏极与第一NTFT管的漏极连接，所述静电输入信号线和所述第一PTFT管与第一NTFT管的漏极之间的公共端连接；
一RC积分电路，包括一电阻与第二NTFT管，所述电阻一端与所述高电平导线连接，另一端与所述第二NTFT管的栅极连接，所述第二NTFT管的源极及漏极与所述低电平导线连接；
一CTFT反相器，包括第二PTFT管与第三NTFT管，所述第二PTFT管的源极与所述高电平导线连接，所述第三NTFT管的源极与所述低电平导线连接，所述第二PTFT管的漏极与第三NTFT管的漏极连接，所述第二PTFT管的栅极与第三NTFT管的栅极连接，且所述电阻与所述第二PTFT管的栅极的公共端和所述第二PTFT管与第三NTFT管的栅极之间的公共端连接；以及
一第四NTFT管，其栅极和所述第二PTFT管与第三NTFT管的漏极连接线连接，其源极和漏极分别与所述高电平导线及低电平导线连接；
其中所述基础单元、RC积分电路、CTFT反相器与第四NTFT管在所述ESD保护电路上顺序排列，在没有发生ESD现象时，所述静电输入信号线的电位介于所述高电平导线与低电平导线的电位之间，此时第一NTFT管、第三NTFT管、第四NTFT管、第一PTFT管与第二PTFT管均关闭。
优选地，其中当液晶面板产生的静电通过所述静电输入信号线与所述低电平导线泄放，且所述静电输入信号线的电位低于所述低电平导线的电位时，所述第一NTFT管导通，所述第一PTFT管、第二PTFT管、第三NTFT管与第四NTFT管均关闭。
优选地，其中当液晶面板产生的静电通过所述静电输入信号线与所述低电平导线泄放，且所述静电输入信号线的电位高于所述高电平导线的电位时，所述第一PTFT管、第二PTFT管与第四NTFT管导通，所述第一NTFT管与所述第三NTFT管关闭。
优选地，其中当液晶面板产生的静电通过所述静电输入信号线与所述高电平导线泄放，且所述静电输入信号线的电位低于所述高电平导线的电位时，所述第一NTFT管导通、第二PTFT管与第四NTFT管导通，所述第三NTFT管与第一PTFT管关闭。
优选地，其中当液晶面板产生的静电通过所述静电输入信号线与所述高电平导线泄放，且所述静电输入信号线的电位高于所述高电平导线的电位时，所述第一NTFT管与第三NTFT管关闭，所述第一PTFT管、第二PTFT管与第四NTFT管导通。
优选地，其中当液晶面板产生的静电通过所述静电输入信号线与所述低电平导线泄放，且所述静电输入信号线的电位低于所述低电平导线的电位时，所述液晶面板产生的静电通过所述静电输入信号线输入，经过所述第一NTFT管流向所述低电平导线泄放。
优选地，其中当液晶面板产生的静电通过所述静电输入信号线与所述低电平导线泄放，且所述静电输入信号线的电位高于所述高电平导线的电位时，所述液晶面板产生的静电通过所述静电输入信号线输入，经过第一PTFT管先流到所述高电平导线，再经过所述第二PTFT管与所述第四NTFT管流向所述低电平导线泄放。
优选地，其中当液晶面板产生的静电通过所述静电输入信号线与所述高电平导线泄放，且所述静电输入信号线的电位低于所述高电平导线的电位时，所述液晶面板产生的静电通过所述静电输入信号线输入，经过第一NTFT管先流到所述低电平导线，再经过所述第四NTFT管与所述第二PTFT管流向所述高电平导线泄放。
优选地，其中当液晶面板产生的静电通过所述静电输入信号线与所述高电平导线泄放，且所述静电输入信号线的电位高于所述高电平导线的电位时，所述液晶面板产生的静电通过所述静电输入信号线输入，经过所述第一PTFT管流向所述高电平导线泄放。
优选地，其中所述第二NTFT管置换为电容。
一种液晶面板的ESD保护电路，其包括：
高电平导线与低电平导线，其为静电输出线；
一基础单元，其包括静电输入信号线、第一PTFT管与第一NTFT管，所述第一PTFT管的栅极及源极与所述高电平导线连接，所述第一NTFT管的栅极及源极与所述低电平导线连接，所述第一PTFT管的漏极与第一NTFT管的漏极连接，所述静电输入信号线和所述第一PTFT管与第一NTFT管的漏极之间的公共端连接；
一RC积分电路，包括一电阻与第二NTFT管，所述电阻一端与所述高电平导线连接，另一端与所述第二NTFT管的栅极连接，所述第二NTFT管的源极及漏极与所述低电平导线连接；
一CTFT反相器，包括第二PTFT管与第三NTFT管，所述第二PTFT管的源极与所述高电平导线连接，所述第三NTFT管的源极与所述低电平导线连接，所述第二PTFT管的漏极与第三NTFT管的漏极连接，所述第二PTFT管的栅极与第三NTFT管的栅极连接，且所述电阻与所述第二PTFT管的栅极的公共端和所述第二PTFT管与第三NTFT管的栅极之间的公共端连接；以及
一第四NTFT管，其栅极和所述第二PTFT管与第三NTFT管的漏极连接线连接，其源极和漏极分别与所述高电平导线及低电平导线连接；
其中所述基础单元、RC积分电路、CTFT反相器与第四NTFT管在所述ESD保护电路上顺序排列。
优选地，在没有发生ESD现象时，所述静电输入信号线的电位介于所述高电平导线与低电平导线的电位之间，此时第一NTFT管、第三NTFT管、第四NTFT管、第一PTFT管与第二PTFT管均关闭。
优选地，当液晶面板产生的静电通过所述静电输入信号线与所述低电平导线泄放，且所述静电输入信号线的电位低于所述低电平导线的电位时，所述第一NTFT管导通，所述第一PTFT管、第二PTFT管、第三NTFT管与第四NTFT管均关闭。
优选地，当液晶面板产生的静电通过所述静电输入信号线与所述低电平导线泄放，且所述静电输入信号线的电位高于所述高电平导线的电位时，所述第一PTFT管、第二PTFT管与第四NTFT管导通，所述第一NTFT管与所述第三NTFT管关闭。
优选地，当液晶面板产生的静电通过所述静电输入信号线与所述高电平导线泄放，且所述静电输入信号线的电位低于所述高电平导线的电位时，所述第一NTFT管导通、第二PTFT管与第四NTFT管导通，所述第三NTFT管与第一PTFT管关闭。
优选地，当液晶面板产生的静电通过所述静电输入信号线与所述高电平导线泄放，且所述静电输入信号线的电位高于所述高电平导线的电位时，所述第一NTFT管与第三NTFT管关闭，所述第一PTFT管、第二PTFT管与第四NTFT管导通。
优选地，当液晶面板产生的静电通过所述静电输入信号线与所述低电平导线泄放，且所述静电输入信号线的电位低于所述低电平导线的电位时，所述液晶面板产生的静电通过所述静电输入信号线输入，经过所述第一NTFT管流向所述低电平导线泄放。
优选地，当液晶面板产生的静电通过所述静电输入信号线与所述低电平导线泄放，且所述静电输入信号线的电位高于所述高电平导线的电位时，所述液晶面板产生的静电通过所述静电输入信号线输入，经过第一PTFT管先流到所述高电平导线，再经过所述第二PTFT管与所述第四NTFT管流向所述低电平导线泄放。
优选地，当液晶面板产生的静电通过所述静电输入信号线与所述高电平导线泄放，且所述静电输入信号线的电位低于所述高电平导线的电位时，所述液晶面板产生的静电通过所述静电输入信号线输入，经过第一NTFT管先流到所述低电平导线，再经过所述第四NTFT管与所述第二PTFT管流向所述高电平导线泄放。
优选地，当液晶面板产生的静电通过所述静电输入信号线与所述高电平导线泄放，且所述静电输入信号线的电位高于所述高电平导线的电位时，所述液晶面板产生的静电通过所述静电输入信号线输入，经过所述第一PTFT管流向所述高电平导线泄放。
 有益效果
本发明的一种液晶面板的ESD保护电路，通过设置RC积分电路与CTFT反相器等电路结构，有效地减少液晶面板的ESD器件的漏电所述引起的亮线或暗线等不良现象，同时也扩大了液晶面板的制程的范围。
 附图说明
图1为本发明的ESD保护电路结构图；
图2为一种现有技术的ESD保护电路结构图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
实施例1
如图1所示，为本发明的ESD保护电路结构图，从如1可以看出，本发明的一种液晶面板的ESD保护电路，总的结构包括高电平导线VH与低电平导线VL、一基础单元、一RC积分电路、一CTFT反相器和一第四NTFT管五个部分，下面对这五个部分进行论述。
高电平导线VH与低电平导线VL，其中高电平导线VH的电位和低电平导线VL的电位保持不变的。
一基础单元，其包括静电输入信号线Signal、第一PTFT管与第一NTFT管，所述第一PTFT管的栅极及源极与所述高电平导线VH连接，所述第一NTFT管的栅极及源极与所述低电平导线VL连接，所述第一PTFT管的漏极与第一NTFT管的漏极连接，所述静电输入信号线Signal和所述第一PTFT管与第一NTFT管的漏极之间的公共端连接。
一RC积分电路，包括一电阻R与第二NTFT管，所述电阻R一端与所述高电平导线VH连接，另一端与所述第二NTFT管的栅极连接，所述第二NTFT管的源极及漏极与所述低电平导线VL连接。因为所述第二NTFT管在本发明的电路中起到电容的作用，所以本实施例的第二NTFT管可以置换为普通电容。
一CTFT反相器，包括第二PTFT管与第三NTFT管，所述第二PTFT管的源极与所述高电平导线VH连接，所述第三NTFT管的源极与所述低电平导线VL连接，所述第二PTFT管的漏极与第三NTFT管的漏极连接，所述第二PTFT管的栅极与第三NTFT管的栅极连接，且所述电阻R与所述第二PTFT管的栅极的公共端和所述第二PTFT管与第三NTFT管的栅极之间的公共端连接。
一第四NTFT管，其栅极和所述第二PTFT管与第三NTFT管的漏极连接线连接，其源极和漏极分别与所述高电平导线VH及低电平导线VL连接。
其中所述基础单元、RC积分电路、CTFT反相器与第四NTFT管在所述ESD保护电路上 从左到右按顺序排列。所述静电输入信号线Signal为静电输入端，所述高电平导线VH和低电平导线VL与所述第四NTFT管连接一端为静电输出端。
本实施例中，所述高电平导线与所述低电平导线的电位是保持不变的。在没有发生ESD现象时，所述静电输入信号线Signal的电位介于所述高电平导线VH与低电平导线VL的电位之间，此时第一NTFT管、第三NTFT管、第四NTFT管、第一PTFT管与第二PTFT管均关闭。只有当电路中出现了ESD现象的时候，所述静电输入信号线 Signal的电位才会低于所述低电平导线VL的电位，或者高于所述高电平导线VH的电位。因为N型TFT的栅极处于高电平时，NTFT导通，而P型TFT的栅极处于高电平时，PTFT关闭，当所述静电输入信号线Signal的电位低于所述低电平导线VL的电位时，所述第一NTFT管导通，所述第一PTFT管关闭。当所述静电输入信号线Signal的电位高于所述高电平导线VH的电位时，所述第一NTFT管关闭，所述第一PTFT管导通。根据ESD现象发生的位置不同，可以将本实施例对ESD产生的电荷进行泄放的情况分为以下几种：
第一，当液晶面板产生的静电是通过所述静电输入信号线Signal与所述低电平导线VL进行泄放，并且所述静电输入信号线Signal的电位低于所述低电平导线VL的电位的时候，所述第一NTFT管导通，所述第一PTFT管、第二PTFT管、第三NTFT管与第四NTFT管均关闭。这时所述液晶面板产生的静电通过所述静电输入信号线输入，经过所述第一NTFT管流向所述低电平导线泄放。
第二，当液晶面板产生的静电是通过所述静电输入信号线Signal与所述低电平导线VL进行泄放，且所述静电输入信号线Signal的电位高于所述高电平导线VH的电位的时候，所述第一PTFT管、第二PTFT管与第四NTFT管导通，所述第一NTFT管与所述第三NTFT管关闭。这时所述ESD产生的电荷先流到所述高电平导线VH上，此时所述第二NTFT管相当于一个电容，所述RC积分电路的电位要达到所述高电平导线VH上的电位需要一定时间，第二NTFT管的电压不会瞬间就上升到所述高电平导线VH上的电位，而且所述电阻R也要占据一定的电位，但是这时候第二PTFT管的源极端的电位已经上升到所述高电平导线VH上的电位，使得所述第二PTFT管的栅极端的电位即Q点的电位低于所述高电平导线VH上的电位，从而使得第二PTFT管得以导通，这时所述高电平导线VH上的电位开始进入所述第四NTFT管的栅极端，使得第四NTFT管导通，这时所述高电平导线VH与低电平导线VL通过导通的第四NTFT管，形成了一个泄放通道，所述液晶面板产生的静电通过所述静电输入信号线输入，经过第一PTFT管先流到所述高电平导线，再经过所述第二PTFT管与所述第四NTFT管流向所述低电平导线泄放。
第三，当液晶面板产生的静电是通过所述静电输入信号线Signal与所述低电平导线VH进行泄放，且所述静电输入信号线Signal的电位低于所述低电平导线的电位时，所述第一NTFT管导通、第二PTFT管与第四NTFT管导通，所述第三NTFT管与第一PTFT管关闭。所述ESD产生的电荷先流到所述低电平导线VL，此时所述第二NTFT管相当于一个电容，所述RC积分电路的电位要达到所述高电平导线VH上的电位需要一定时间，第二NTFT管的电位不会瞬间就上升到所述高电平导线VH上的电位，而且所述电阻R也要占据一定的电位，但是这时候第二PTFT管的源极端的电位已经上升到所述高电平导线VH上的电位，使得所述第二PTFT管的栅极端的电位即Q点的电位低于所述高电平导线VH上的电位，从而使得第二PTFT管得以导通，这是所述高电平导线VH上的电位开始进入所述第四NTFT管的栅极端，使得第四NTFT管导通，这时所述高电平导线VH与低电平导线VL通过导通的第四NTFT管，形成了一个泄放通道，所述液晶面板产生的静电通过所述静电输入信号线输入，经过第一NTFT管先流到所述低电平导线，再经过所述第四NTFT管与所述第二PTFT管流向所述高电平导线泄放。
第四，当液晶面板产生的静电是通过所述静电输入信号线Signal与所述低电平导线VH进行泄放，且所述静电输入信号线Signal的电位高于所述高电平导线VH的电位的时候，所述第一NTFT管与第三NTFT管关闭，所述第一PTFT管、第二PTFT管与第四NTFT管导通。这时所述液晶面板产生的静电通过所述静电输入信号线输入，经过所述第一PTFT管流向所述高电平导线泄放。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种液晶面板的ESD保护电路，其包括：
    高电平导线与低电平导线，其为静电输出线；
    一基础单元，其包括静电输入信号线、第一PTFT管与第一NTFT管，所述第一PTFT管的栅极及源极与所述高电平导线连接，所述第一NTFT管的栅极及源极与所述低电平导线连接，所述第一PTFT管的漏极与第一NTFT管的漏极连接，所述静电输入信号线和所述第一PTFT管与第一NTFT管的漏极之间的公共端连接；
    一RC积分电路，包括一电阻与第二NTFT管，所述电阻一端与所述高电平导线连接，另一端与所述第二NTFT管的栅极连接，所述第二NTFT管的源极及漏极与所述低电平导线连接；
    一CTFT反相器，包括第二PTFT管与第三NTFT管，所述第二PTFT管的源极与所述高电平导线连接，所述第三NTFT管的源极与所述低电平导线连接，所述第二PTFT管的漏极与第三NTFT管的漏极连接，所述第二PTFT管的栅极与第三NTFT管的栅极连接，且所述电阻与所述第二PTFT管的栅极的公共端和所述第二PTFT管与第三NTFT管的栅极之间的公共端连接；以及
    一第四NTFT管，其栅极和所述第二PTFT管与第三NTFT管的漏极连接线连接，其源极和漏极分别与所述高电平导线及低电平导线连接；
    其中所述基础单元、RC积分电路、CTFT反相器与第四NTFT管在所述ESD保护电路上顺序排列，在没有发生ESD现象时，所述静电输入信号线的电位介于所述高电平导线与低电平导线的电位之间，此时第一NTFT管、第三NTFT管、第四NTFT管、第一PTFT管与第二PTFT管均关闭。
  2. 根据权利要求1所述的ESD保护电路，其中当液晶面板产生的静电通过所述静电输入信号线与所述低电平导线泄放，且所述静电输入信号线的电位低于所述低电平导线的电位时，所述第一NTFT管导通，所述第一PTFT管、第二PTFT管、第三NTFT管与第四NTFT管均关闭。
  3. 根据权利要求1所述的ESD保护电路，其中当液晶面板产生的静电通过所述静电输入信号线与所述低电平导线泄放，且所述静电输入信号线的电位高于所述高电平导线的电位时，所述第一PTFT管、第二PTFT管与第四NTFT管导通，所述第一NTFT管与所述第三NTFT管关闭。
  4. 根据权利要求1所述的ESD保护电路，其中当液晶面板产生的静电通过所述静电输入信号线与所述高电平导线泄放，且所述静电输入信号线的电位低于所述高电平导线的电位时，所述第一NTFT管导通、第二PTFT管与第四NTFT管导通，所述第三NTFT管与第一PTFT管关闭。
  5. 根据权利要求1所述的ESD保护电路，其中当液晶面板产生的静电通过所述静电输入信号线与所述高电平导线泄放，且所述静电输入信号线的电位高于所述高电平导线的电位时，所述第一NTFT管与第三NTFT管关闭，所述第一PTFT管、第二PTFT管与第四NTFT管导通。
  6. 根据权利要求1所述的ESD保护电路，其中当液晶面板产生的静电通过所述静电输入信号线与所述低电平导线泄放，且所述静电输入信号线的电位低于所述低电平导线的电位时，所述液晶面板产生的静电通过所述静电输入信号线输入，经过所述第一NTFT管流向所述低电平导线泄放。
  7. 根据权利要求1所述的ESD保护电路，其中当液晶面板产生的静电通过所述静电输入信号线与所述低电平导线泄放，且所述静电输入信号线的电位高于所述高电平导线的电位时，所述液晶面板产生的静电通过所述静电输入信号线输入，经过第一PTFT管先流到所述高电平导线，再经过所述第二PTFT管与所述第四NTFT管流向所述低电平导线泄放。
  8. 根据权利要求1所述的ESD保护电路，其中当液晶面板产生的静电通过所述静电输入信号线与所述高电平导线泄放，且所述静电输入信号线的电位低于所述高电平导线的电位时，所述液晶面板产生的静电通过所述静电输入信号线输入，经过第一NTFT管先流到所述低电平导线，再经过所述第四NTFT管与所述第二PTFT管流向所述高电平导线泄放。
  9. 根据权利要求1所述的ESD保护电路，其中当液晶面板产生的静电通过所述静电输入信号线与所述高电平导线泄放，且所述静电输入信号线的电位高于所述高电平导线的电位时，所述液晶面板产生的静电通过所述静电输入信号线输入，经过所述第一PTFT管流向所述高电平导线泄放。
  10. 根据权利要求1所述的ESD保护电路，其中所述第二NTFT管置换为电容。
  11. 一种液晶面板的ESD保护电路，其包括：
    高电平导线与低电平导线，其为静电输出线；
    一基础单元，其包括静电输入信号线、第一PTFT管与第一NTFT管，所述第一PTFT管的栅极及源极与所述高电平导线连接，所述第一NTFT管的栅极及源极与所述低电平导线连接，所述第一PTFT管的漏极与第一NTFT管的漏极连接，所述静电输入信号线和所述第一PTFT管与第一NTFT管的漏极之间的公共端连接；
    一RC积分电路，包括一电阻与第二NTFT管，所述电阻一端与所述高电平导线连接，另一端与所述第二NTFT管的栅极连接，所述第二NTFT管的源极及漏极与所述低电平导线连接；
    一CTFT反相器，包括第二PTFT管与第三NTFT管，所述第二PTFT管的源极与所述高电平导线连接，所述第三NTFT管的源极与所述低电平导线连接，所述第二PTFT管的漏极与第三NTFT管的漏极连接，所述第二PTFT管的栅极与第三NTFT管的栅极连接，且所述电阻与所述第二PTFT管的栅极的公共端和所述第二PTFT管与第三NTFT管的栅极之间的公共端连接；以及
    一第四NTFT管，其栅极和所述第二PTFT管与第三NTFT管的漏极连接线连接，其源极和漏极分别与所述高电平导线及低电平导线连接；
    其中所述基础单元、RC积分电路、CTFT反相器与第四NTFT管在所述ESD保护电路上顺序排列。
  12. 根据权利要求11所述的ESD保护电路，其中在没有发生ESD现象时，所述静电输入信号线的电位介于所述高电平导线与低电平导线的电位之间，此时第一NTFT管、第三NTFT管、第四NTFT管、第一PTFT管与第二PTFT管均关闭。
  13. 根据权利要求11所述的ESD保护电路，其中当液晶面板产生的静电通过所述静电输入信号线与所述低电平导线泄放，且所述静电输入信号线的电位低于所述低电平导线的电位时，所述第一NTFT管导通，所述第一PTFT管、第二PTFT管、第三NTFT管与第四NTFT管均关闭。
  14. 根据权利要求11所述的ESD保护电路，其中当液晶面板产生的静电通过所述静电输入信号线与所述低电平导线泄放，且所述静电输入信号线的电位高于所述高电平导线的电位时，所述第一PTFT管、第二PTFT管与第四NTFT管导通，所述第一NTFT管与所述第三NTFT管关闭。
  15. 根据权利要求11所述的ESD保护电路，其中当液晶面板产生的静电通过所述静电输入信号线与所述高电平导线泄放，且所述静电输入信号线的电位低于所述高电平导线的电位时，所述第一NTFT管导通、第二PTFT管与第四NTFT管导通，所述第三NTFT管与第一PTFT管关闭。
  16. 根据权利要求11所述的ESD保护电路，其中当液晶面板产生的静电通过所述静电输入信号线与所述高电平导线泄放，且所述静电输入信号线的电位高于所述高电平导线的电位时，所述第一NTFT管与第三NTFT管关闭，所述第一PTFT管、第二PTFT管与第四NTFT管导通。
  17. 根据权利要求11所述的ESD保护电路，其中当液晶面板产生的静电通过所述静电输入信号线与所述低电平导线泄放，且所述静电输入信号线的电位低于所述低电平导线的电位时，所述液晶面板产生的静电通过所述静电输入信号线输入，经过所述第一NTFT管流向所述低电平导线泄放。
  18. 根据权利要求11所述的ESD保护电路，其中当液晶面板产生的静电通过所述静电输入信号线与所述低电平导线泄放，且所述静电输入信号线的电位高于所述高电平导线的电位时，所述液晶面板产生的静电通过所述静电输入信号线输入，经过第一PTFT管先流到所述高电平导线，再经过所述第二PTFT管与所述第四NTFT管流向所述低电平导线泄放。
  19. 根据权利要求11所述的ESD保护电路，其中当液晶面板产生的静电通过所述静电输入信号线与所述高电平导线泄放，且所述静电输入信号线的电位低于所述高电平导线的电位时，所述液晶面板产生的静电通过所述静电输入信号线输入，经过第一NTFT管先流到所述低电平导线，再经过所述第四NTFT管与所述第二PTFT管流向所述高电平导线泄放。
  20. 根据权利要求11所述的ESD保护电路，其中当液晶面板产生的静电通过所述静电输入信号线与所述高电平导线泄放，且所述静电输入信号线的电位高于所述高电平导线的电位时，所述液晶面板产生的静电通过所述静电输入信号线输入，经过所述第一PTFT管流向所述高电平导线泄放。
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