WO2017012460A1

WO2017012460A1 - Method and apparatus for detecting failure of random memory, and processor

Info

Publication number: WO2017012460A1
Application number: PCT/CN2016/088142
Authority: WO
Inventors: 潘静; 安康; 石金锋; 许建文
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2015-07-23
Filing date: 2016-07-01
Publication date: 2017-01-26
Also published as: CN106373616A; CN106373616B

Abstract

A method and apparatus for detecting a failure of a random memory, and a processor, comprising: acquiring a data message (100); performing an error check and correction (ECC) check on the data message, and writing the data message into a random memory (101); reading the data message from the random memory, and performing the ECC check on the read data message (102); and by comparing the ECC check result before the data message is written into the random memory and the ECC check result of the read data message, determining a failure detection result of the random memory (103).

Description

Method and device for detecting random memory failure, processor

Technical field

The present invention relates to a storage device failure detection technology, and in particular, to a method, device, and processor for detecting a random memory failure.

Background technique

Random access memory such as DDR3 Synchronous Dynamic Random Access Memory (DDR3SDRAM) has been widely used in network processors to store a large number of entries and data of network forwarding devices. Here, DDR3 SDRAM is abbreviated as DDR3.

With the increasing demand for network processing equipment performance and capacity in modern networks, large-capacity, high-speed forwarding devices have emerged, and the internal storage space of network processors is limited, requiring a large amount of random access memory such as DDR3 to be attached. Forward data and information in the storage network. However, due to problems in the production process of the random access memory, internal particle necrosis may occur. In addition, in the case of using the random access memory for a long time, since the data is written and read a plurality of times, internal user data may be erroneous, affecting the processing and transmission of some user services, and therefore, the random access memory is monitored and Testing is especially important.

The traditional detection scheme for random access memory is: using a central processing unit (CPU) to construct certain test data, and the CPU controls the test data to be written into the random access memory, and then controlled by the CPU, which will be randomly The data stored in the memory is read out and compared with the previously written data to obtain a failed random access memory address such as DDR3 unit information. However, due to the limited CPU bandwidth, this detection scheme is very time consuming when scanning large-capacity random access memory, the scanning period is long, the detection failure speed is slow, and it is necessary to have CPU participation to complete the self-test. CPU when the network processor forwarding plane has a large amount of data traffic It is necessary to manage and deliver the forwarding table entries, and perform protocol interaction and management operations. The CPU resource consumption in the above detection scheme is even more undesirable.

Summary of the invention

In order to solve the above technical problem, an embodiment of the present invention is directed to a method, apparatus, and processor for detecting a random memory failure, which can improve the efficiency of detecting a random memory failure.

The technical solution of the embodiment of the present invention is implemented as follows:

Embodiments of the present invention provide a method for detecting a random memory failure, including:

Obtain data packets;

Performing an Error Correcting Code (ECC) check on the data packet, and writing the data packet to a random access memory;

Reading the data packet from the random access memory, and performing ECC check on the read data packet;

The failure detection result of the random access memory is determined by comparing an ECC check result of the data message before writing to the random access memory and an ECC check result of the read data message.

In the above solution, the acquiring the data packet includes: acquiring data packets of multiple entries in sequence;

Performing an ECC check on the data packet, and writing the data packet to the random memory, including: performing ECC check on the data packet of each entry, and writing the data packet of each entry into the random Memory

The reading the data packet from the random access memory and performing the ECC check on the read data packet includes: reading a data packet of the at least one entry from the random access memory, and reading the data packet The data message of each entry is ECC checked;

Determining the fault detection result of the random access memory by comparing the ECC check result of the data message before the writing to the random access memory and the ECC check result of the read data message, including: By comparing the ECC check result of the data message of each entry read and The data packet of the corresponding entry is determined by the ECC check result before being written into the random access memory, and the fault detection result of the random access memory corresponding to the data packet corresponding to the entry is determined.

In the foregoing solution, in the data packet that sequentially acquires multiple entries, the data packet of each entry includes a write table index and data to be written; wherein the write table index carries the data to be written Address information stored in the random access memory;

The writing the data message of each entry to the random access memory comprises: writing, to the random access memory, the data to be written of the data message of the corresponding entry based on the write table index of the data message of the corresponding entry.

In the above solution, the reading the data message of the at least one entry from the random access memory comprises: receiving, by the network processor, at least one scan message from the packet sending device, and each scan message sent by the packet sending device. Include a lookup table index for searching data of a corresponding entry in the random access memory;

The reading the data message of the at least one entry from the random access memory further comprises: the network processor reading the data of the corresponding entry from the random access memory based on each received scan message.

In the above solution, the bandwidth of the scan packet sent by the packet sending device is determined according to the traffic of the network processor forwarding data at the current time obtained by the packetizer.

In the above solution, the ECC check result of the data message of each entry read and the data message of the corresponding entry are compared with the ECC check result before being written into the random access memory, and the data of the corresponding entry is determined. The fault detection result of the random access memory corresponding to the message includes: if the ECC check result of the data message of any one of the read items and the data message of the corresponding item are the ECC check result before being written into the random access memory If not, the fault information of the random access memory corresponding to the data packet of the corresponding entry is determined.

In the above solution, the ECC check algorithm of the data message before being written into the random access memory is the same as the ECC check algorithm of the read data message.

In the above solution, while the data message is written into the random access memory, the method further The method includes: storing the data message in an ECC check result before being written into the random access memory.

An embodiment of the present invention further provides an apparatus for detecting a random memory fault, comprising: an obtaining module, a first verifying module, a second verifying module, and a fault determining module; wherein

Obtaining a module, configured to obtain a data packet;

a first verification module, configured to perform error checking on the data packet and correct an ECC check, and write the data packet into a random access memory;

a second check module, configured to read the data packet from the random access memory, and perform ECC check on the read data packet;

The fault determining module is configured to determine a fault detection result of the random access memory by comparing an ECC check result of the read data message with an ECC check result of the data message before writing to the random access memory.

In the foregoing solution, the acquiring module is further configured to sequentially acquire data packets of multiple entries;

The first check module is further configured to perform ECC check on the data packet of each entry, and write the data packet of each entry into the random access memory;

The second verification module is further configured to: read a data packet of the at least one entry from the random access memory, and perform an ECC check on the read data packet of each entry;

The fault determining module is further configured to determine, by comparing the ECC check result of the data message of each entry read and the ECC check result of the data message of the corresponding entry before writing to the random access memory, to determine corresponding The failure detection result of the random access memory corresponding to the data message of the entry.

The first verification module is further configured to write, to the random access memory, the data to be written of the data message of the corresponding entry based on the write table index of the data message of the corresponding entry.

In the above solution, the second verification module is further configured to receive the packets from the packetizer in sequence. Having one scan message, each scan message sent by the packet sender includes a lookup table index for searching data of the corresponding entry in the random access memory;

The second verification module is further configured to read data of the corresponding entry from the random access memory based on each received scan message.

In the above solution, the fault determining module is further configured to: the ECC check result of the data message of any one of the read items and the ECC check result of the data message of the corresponding item before being written into the random access memory. When not the same, the fault information of the random access memory corresponding to the data message corresponding to the entry is determined.

The embodiment of the present invention further provides a network processor, including any one of the foregoing devices for detecting a random memory failure.

A method, device, and processor for detecting a random memory fault are provided by the embodiment of the present invention, and the error check and the corrected ECC check result and the data message before the data message is written into the random memory are read out The ECC check results are compared to obtain the fault detection result of the random memory. Since the random memory fault can be detected without the participation of the CPU, the CPU resource consumption can be reduced. In addition, compared with the existing ones. Compared with the scheme of writing and reading test data, the embodiment of the present invention only needs to compare the ECC check result of the corresponding data, and obviously can reduce the data calculation amount, improve the efficiency of detecting the random memory failure, and shorten the location of the random memory fault. time.

DRAWINGS

1 is a flow chart of a first embodiment of a method for detecting a random memory failure according to the present invention;

2 is a flow chart of a second embodiment of a method for detecting a random memory failure according to the present invention;

FIG. 3 is a schematic structural diagram of a device for detecting a random memory failure according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings.

First embodiment

1 is a flow chart of a first embodiment of a method for detecting a random memory failure according to the present invention. As shown in FIG. 1, the method includes:

Step 100: Obtain a data packet.

Here, the data message includes a write table index and data to be written, and the write table index carries address information that the data to be written needs to be stored in the random access memory, and the write table index may be located in the data report. In a certain field of the text, the length of the data to be written may be 64 bits, 128 bits or 256 bits, and the data to be written may be all 1 data, data composed of random numbers, data arranged in increments or in descending order. Data, etc.; the random access memory can be DDR3.

In this step, the network processor may be used to receive data packets from multiple items of the packetizer in sequence; further, the parameters of the data packet sent by the packetizer may be pre-configured, and the parameters of the data packet sent by the packetizer include: the packetizer Number of data packets sent, packet type, packet length, packet format, bandwidth, and transmission rate. The generation rule of the data packet sent by the packet sending device twice or twice may be the same or different; the bandwidth of the data packet sent by the packet sending device twice or twice may be the same or different.

In this step, the network processor can also be used to sequentially receive data of multiple entries from the CPU; here, the CPU controls the write table index and data of the data message sent by the network processor.

In the first embodiment of the present invention, when the packet sending device sends the data packet transmission mode to the network processor, since the parameters of the data packet sent by the packet sending device can be pre-configured, it is more suitable for performing random access to the granularity unit such as DDR3. Fault checking; and the manner in which the CPU writes data entries to the network processor is typically present in the actual forwarding scenario.

Step 101: Perform an ECC check on the data packet, and write the data packet into a random Memory.

Specifically, performing ECC check on the data packet, and writing the data packet to the random memory includes: performing ECC check on the data packet of each entry, and writing the data packet of each entry Random access memory.

Further, whether the data packet of the corresponding item needs to be ECC-checked may be pre-configured. In this case, performing ECC check on the data packet includes: a datagram of each entry of the network processor that needs to perform ECC check. The text is ECC checked. Here, the data message that needs to perform ECC check may be a data message of all entries received by the network processor, or may be part of a data message of all entries received by the network processor.

Here, writing the data message of each entry to the random access memory includes: writing the data to be written of the data message of the corresponding entry into the random access memory based on the write table index of the data message of the corresponding entry.

Here, while the data message is written into the random access memory, the ECC check result of the data message before being written into the random access memory may be stored, for example, the data message is written in the random The ECC check result before the memory is written to the random access memory.

Step 102: Read the data packet from the random access memory, and perform ECC check on the read data packet.

Specifically, the reading the data packet from the random access memory and performing ECC check on the read data packet includes: reading, by the random access memory, a data packet of at least one entry. ECC check is performed on the data packet of each entry read. Here, it is possible to pre-configure whether the read data packet of each entry needs to be subjected to ECC check, and the data packet that needs to be ECC-checked and the data packet that needs to be ECC-checked in step 101 are normally read. be consistent.

Here, reading the data message of the at least one entry from the random access memory includes: receiving, by the network processor, at least one scan message of the packetizer, each scan message and one strip The destination data packet corresponds to each other; each scan packet includes a lookup table index, and is used to search for a data packet of the corresponding entry in the random access memory, where the lookup table index is located in a certain field of the scan packet; Each scan message reads a data message of the corresponding entry from the random access memory.

Further, the parameter that the packet sending device sends the scan message may be pre-configured. Here, the parameter that the packet sending device sends the scan message includes the bandwidth of the scan packet sent by the packet sending device, and the packet sending device sends the scan report. The number of packets sent, the format of the packet, the length of the packet, the format of the packet, and the sending rate.

Specifically, the bandwidth of the scan packet sent by the packet sending device is determined according to the traffic of the network processor forwarding data at the current time obtained by the packet sending device, to ensure that the network processor receives the bandwidth of the scanned packet and the network processor forwards the data at the current moment. The sum of the bandwidths is within the set threshold. Thus, the network processor can simultaneously perform data forwarding and scan packet reception to ensure that the network processor can work normally. Here, the sender that sends the scan message is independent of the CPU, and thus does not consume CPU resources when transmitting the scan message.

The packet sending device can send the scanning packet according to a certain time frequency, and the number of the sending packet, the packet sending mode, and the packet length when the packet sending device scans the packet can be flexibly configured, and the sending packet sends the scan packet generated twice. The rules may be the same or different. The bandwidth of the scanning packets sent by the packet sending device twice or twice may be the same or different.

It should be noted that the ECC check algorithm of the data message of any one of the items read in this step and the data message of the corresponding item are the same as the ECC check algorithm before being written into the random access memory.

Step 103: Determine a fault detection result of the random access memory by comparing an ECC check result of the data message before writing to the random access memory and an ECC check result of the read data message.

The step specifically includes: comparing the ECC check result of the data message of each entry read and the ECC check result of the data message of the corresponding entry before writing to the random access memory, The failure detection result of the random access memory corresponding to the data message of the corresponding entry is determined. Here, the fault detection result of the random access memory corresponding to the data packet of the corresponding entry may be that the storage address of the random access memory corresponding to the data packet of the corresponding entry does not fail, or may be the random access memory corresponding to the data packet of the corresponding entry. The specific fault information when the storage address fails.

Specifically, if the ECC check result of the data message of any one of the read items and the data message of the corresponding item are not the same in the ECC check result before being written into the random access memory, the datagram of the corresponding item is indicated. The storage address of the random access memory corresponding to the text is faulty. At this time, the fault information of the random access memory corresponding to the data packet corresponding to the entry is determined, and the fault information of the random access memory corresponding to the data packet of the corresponding entry may be the data packet of the corresponding entry. The storage address in the random access memory. In this way, by comparing the ECC check result of the data message of each entry read and the ECC check result of the data message of the corresponding entry before writing to the random access memory, the specific fault in the random access memory can be known. information.

If the ECC check result of the data message of any one of the read items and the data message of the corresponding item are the same as the ECC check result before writing to the random access memory, the random data corresponding to the corresponding item is indicated. The memory address of the memory did not malfunction.

It should be noted that, if the ECC check result of the data message of each item read and the data message of the corresponding item are the same before the ECC check result before writing to the random access memory, the determined in this step is determined. The failure detection result of the random access memory is that the random access memory does not have a failure.

After comparing the ECC check result of the data message of each read item and the ECC check result of the data message of the corresponding item before writing to the random access memory, respectively, two ECC check results are not counted. The data message of the same entry, and the data message of the same entry of the two ECC check results, after which the network processor is used to store the statistical result and the determined fault information of the random access memory.

Further, the network processor stores the statistical result and the determined failure of the random access memory After the information, the data message of each read item and the stored statistical result are uploaded to the control plane together with the determined fault information of the random memory, and the control surface can analyze the received data by analyzing the received data. The specific situation in which a failure occurs in the random access memory, for example, can quickly locate the address of the failed memory in the random access memory based on the received data.

In the first embodiment of the present invention, if the data message received by the network processor is from the packetizer in step 100, the method of detecting the random memory failure is referred to as a fully automatic detection mode; when the automatic detection mode is adopted, the network processor is used. The obtained data packet and the scanned packet are sent by the packet sending device. Specifically, the packet sending device sends the scan packet to the network processor immediately after the data packet is sent.

If the data message received by the network processor is from the CPU in step 100, the method of detecting the random memory failure is referred to as a semi-automatic detection mode; when the semi-automatic detection mode is adopted, the CPU sends a data message to the network processor, and the packetizer is used for Send a scan message to the network processor.

In the first embodiment of the present invention, except for the process in which the CPU sends the write table index of the data message to the network processor and the process of analyzing the random memory failure at the control plane, the other implementation processes are completed on the forwarding surface, and thus, the detection is performed. The process of random access memory not only does not consume CPU resources, but also improves the speed of detecting random memory failures and shortens the positioning time of random memory failures. In addition, when the fully automatic detection mode is adopted, the failure of the random access memory can be detected at any time regardless of whether or not the forwarding surface of the network processor has forwarding traffic.

Second embodiment

In order to further embodies the object of the present invention, further exemplification will be made on the basis of the first embodiment of the present invention. In the second embodiment of the present invention, the random access memory is DDR3, and the fault in the DDR3 is detected by the fully automatic detection mode.

2 is a flow chart of a second embodiment of a method for detecting a random memory failure according to the present invention. As shown in FIG. 2, the method includes:

Step 201: The DDR3 controller in the network processor turns on the ECC check function.

Step 202: Send the data message of the i-th entry to the DDR3 controller in the network processor by using the packetizer, and the initial value of i is 1.

Step 203: The DDR3 controller extracts X-bit data of the data to be written of the data message of the i-th entry according to the bit width X bits of the read-write data, where X is a natural number greater than 1, and the bit width of the read-write data may be Pre-configuring; performing ECC check on the extracted X-bit data, and extracting the ECC check result of the X-bit data and the data message of the i-th entry based on the write table index of the data message of the i-th entry The data to be written is written into the storage space of DDR3.

Step 204: Determine whether the value of i is equal to N, N represents the total number of entries of the data packet that the packetizer needs to send to the DDR3 controller; if i is not equal to N, repeat steps 202 to 203 until the value of i is equal to N; If i is equal to N, the process of writing a data message to the DDR3 by the network processor is completed, and step 205 is performed.

Step 205: The DDR3 controller in the network processor receives the scan message from the jth entry of the packetizer, and the initial value of j is 1.

Step 206: The DDR3 controller reads the data packet of the corresponding entry from the DDR3 based on the lookup table index in the scan message of the jth entry; and extracts the corresponding entry in the data packet of the corresponding entry that is read out. The X-bit data of the data message is subjected to ECC check of the extracted X-bit data.

Step 207: Comparing the ECC check result of the data packet of the corresponding corresponding entry with the ECC check result of the data packet of the corresponding entry before writing to DDR3, and obtaining a comparison result, and the comparison result is the two ECCs. The verification results are the same or different.

If the ECC check result of the data packet of the corresponding entry is the same as the ECC check result of the data packet of the corresponding entry before the DDR3 is written, it indicates that the storage address of the random access memory corresponding to the data packet of the corresponding entry is not If a fault occurs, the data packet of the corresponding entry is recorded as a data packet in which no random memory failure occurs, and step 208 is performed.

If the ECC check result of the data packet of the corresponding entry is read and the datagram of the corresponding entry If the ECC check result before the DDR3 is written is different, the data packet of the corresponding entry is recorded as a data packet with a random memory failure, and step 209 is performed.

Step 208: Perform statistics counting on data packets that do not have a random memory failure, and perform step 210.

Step 209: Perform statistical counting on the data packet in which the memory of the machine is faulty, and determine the fault information of the random access memory corresponding to the data packet corresponding to the entry, and the fault information of the random access memory corresponding to the data packet of the corresponding entry may be the data of the corresponding entry. Step 210 is performed to store the address of the message in the random access memory.

Step 210: Determine whether the value of j is equal to M, where M represents the total number of entries of the scan message sent by the packetizer to the DDR3 controller; if j is not equal to M, repeat steps 205 to 209 until the value of j is equal to M; If j is equal to M, the process of detecting a random memory failure is completed, and the process ends.

It should be noted that, in step 210, M may be equal to N or less than N.

The method for detecting a random memory fault provided by the above two embodiments of the present invention can quickly locate the random access memory by comparing the ECC check result when the data message is written with the ECC check result when the data message is read. The location of the fault.

Third embodiment

For the method of the first embodiment of the present invention, an embodiment of the present invention further provides an apparatus for detecting a random memory failure. 3 is a schematic structural diagram of a device for detecting a random memory failure according to an embodiment of the present invention. As shown in FIG. 3, the device includes an obtaining module 300, a first verifying module 301, a second verifying module 302, and a fault determining module 303; among them,

The obtaining module 300 is configured to obtain a data packet.

The first verification module 301 is configured to perform error checking and correct ECC check on the data packet, and write the data packet into a random access memory.

The second verification module 302 is configured to read the data packet from the random access memory, and The read data packet is ECC checked.

The fault determining module 303 is configured to determine a fault detection result of the random access memory by comparing an ECC check result of the read data packet with an ECC check result of the data packet before writing the random memory. .

Specifically, the acquiring module 300 is configured to sequentially acquire data messages of multiple entries.

The first check module 301 is configured to perform ECC check on the data packet of each entry, and write the data packet of each entry into the random access memory.

The second verification module 302 is configured to read a data message of at least one entry from the random access memory, and perform ECC check on the read data packet of each entry.

The fault determining module 303 is configured to determine, by comparing the ECC check result of the data message of each entry that is read out and the ECC check result of the data message of the corresponding entry before writing to the random access memory, to determine the corresponding The failure detection result of the random access memory corresponding to the data message of the entry.

Specifically, in the data packet that sequentially acquires multiple entries, the data packet of each entry includes a write table index and data to be written; wherein the write table index carries the data to be written and needs to be stored. Address information in the random access memory.

The first check module 301 is configured to write the data to be written of the data message of the corresponding entry into the random access memory based on the write table index of the data message of the corresponding entry.

Specifically, the second check module 302 is further configured to receive at least one scan message, and read, according to each scan message, a data message of the corresponding item from the random memory; each scan message and Corresponding to the data message of an entry, each scan message includes a lookup table index for searching for a data message of the corresponding entry in the random access memory.

Specifically, the second verification module 302 is configured to receive, by using a network processor, at least one scan packet from the packet sending device, and the bandwidth of the scan packet sent by the packet sender is determined according to the current time network acquired by the packetizer. The flow of the processor forwarding data is determined.

Specifically, the fault determining module 303 is configured to read the number of any one of the entries. According to the ECC check result of the message and the data message of the corresponding entry, when the ECC check result before writing to the random access memory is different, the fault information of the random access memory corresponding to the data message of the corresponding entry is determined.

The device for detecting a random memory fault provided by the embodiment of the present invention can quickly locate the location where the random memory fails by comparing the ECC check result when the data message is written and the ECC check result when the data message is read. Improve the efficiency of locating random access memory failures.

In an actual application, the obtaining module 300, the first checking module 301, the second verifying module 302, and the fault determining module 303 may all be processed by a central processing unit (CPU) located in a network processor. (Micro Processor Unit, MPU), Digital Signal Processor (DSP), or Field Programmable Gate Array (FPGA).

Fourth embodiment

The embodiment of the invention further provides a network processor, which comprises any device for detecting a random memory failure in the third embodiment of the invention.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Realize A means of function specified in a flow or a flow and/or a block diagram of a block or blocks.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

Industrial applicability

The embodiment of the present invention compares the ECC check result of the error check and the corrected ECC check result and the data message before the data message is written into the random memory, and obtains the fault detection result of the random memory. Since the detection of random memory failure can be completed without the participation of the CPU, the consumption of CPU resources can be reduced; in addition, the implementation of the present invention is compared with the existing scheme of comparing the written and read test data. The example only needs to compare the ECC check result of the corresponding data, obviously can reduce the data calculation amount, improve the efficiency of detecting the random memory failure, and shorten the time of locating the random memory fault location.

Claims

A method for detecting a random memory failure, comprising:

Obtain data packets;

Performing error checking and correcting ECC check on the data packet, and writing the data packet into a random access memory;

Reading the data packet from the random access memory, and performing ECC check on the read data packet;

The failure detection result of the random access memory is determined by comparing an ECC check result of the data message before writing to the random access memory and an ECC check result of the read data message.
The method of claim 1, wherein the acquiring the data message comprises: sequentially acquiring data messages of the plurality of entries;

Performing an ECC check on the data packet, and writing the data packet to the random memory, including: performing ECC check on the data packet of each entry, and writing the data packet of each entry into the random Memory

The reading the data packet from the random access memory and performing the ECC check on the read data packet includes: reading a data packet of the at least one entry from the random access memory, and reading the data packet The data message of each entry is ECC checked;

Determining the fault detection result of the random access memory by comparing the ECC check result of the data message before the writing to the random access memory and the ECC check result of the read data message, including: Determining the random access memory corresponding to the data message of the corresponding entry by comparing the ECC check result of the data message of each entry read and the ECC check result of the data message of the corresponding entry before writing to the random access memory The fault detection result.
The method of claim 2, wherein said sequentially acquiring data of a plurality of entries In the message, the data message of each entry includes a write table index and data to be written; wherein the write table index carries the address information that the data to be written needs to be stored in the random access memory;

The writing the data message of each entry to the random access memory comprises: writing, to the random access memory, the data to be written of the data message of the corresponding entry based on the write table index of the data message of the corresponding entry.
The method of claim 2, wherein the reading the data message of the at least one entry from the random access memory comprises: sequentially receiving, by the network processor, at least one scan message from the packetizer, the packetizer Each scan message sent includes a lookup table index for searching data of the corresponding entry in the random access memory;

The reading the data message of the at least one entry from the random access memory further comprises: the network processor reading the data of the corresponding entry from the random access memory based on each received scan message.
The method according to claim 4, wherein the bandwidth of the scan packet sent by the packet sender is determined according to the traffic of the network processor forwarding data at the current time obtained by the packetizer.
The method according to claim 2, wherein said ECC check result by comparing the ECC check result of the data message of each entry read and the data message of the corresponding entry before writing to said random access memory As a result, determining the fault detection result of the random access memory corresponding to the data packet of the corresponding entry includes: if the ECC check result of the data message of any one of the read items and the data message of the corresponding entry are written in the random If the ECC check results before the memory are different, the fault information of the random access memory corresponding to the data message corresponding to the entry is determined.
The method according to any one of claims 1 to 6, wherein the ECC check algorithm of the data message before writing to the random access memory is the same as the ECC check algorithm of the read data message .
The method according to any one of claims 1 to 6, wherein, while the data message is written to the random access memory, the method further comprises: before the data message is written to the random access memory The ECC check result is stored.
An apparatus for detecting a random memory fault, comprising: an obtaining module, a first verifying module, a second verifying module, and a fault determining module; wherein

Obtaining a module, configured to obtain a data packet;

a first verification module, configured to perform error checking on the data packet and correct an ECC check, and write the data packet into a random access memory;

a second check module, configured to read the data packet from the random access memory, and perform ECC check on the read data packet;

The fault determining module is configured to determine a fault detection result of the random access memory by comparing an ECC check result of the read data message with an ECC check result of the data message before writing to the random access memory.
The apparatus according to claim 9, wherein the obtaining module is further configured to sequentially acquire data messages of a plurality of entries;

The first check module is further configured to perform ECC check on the data packet of each entry, and write the data packet of each entry into the random access memory;

The second verification module is further configured to: read a data packet of the at least one entry from the random access memory, and perform an ECC check on the read data packet of each entry;

The fault determining module is further configured to determine, by comparing the ECC check result of the data message of each entry read and the ECC check result of the data message of the corresponding entry before writing to the random access memory, to determine corresponding The failure detection result of the random access memory corresponding to the data message of the entry.
The apparatus according to claim 10, wherein, in the data message in which the plurality of entries are sequentially acquired, the data message of each entry includes a write table index and data to be written; wherein the write table index carries The data to be written needs address information stored in the random access memory;

The first verification module is further configured to write, to the random access memory, the data to be written of the data message of the corresponding entry based on the write table index of the data message of the corresponding entry.
The apparatus according to claim 10, wherein the second verification module is further configured to sequentially receive at least one scan message from the packetizer, and each scan message sent by the packetizer includes a lookup table index. Data for finding a corresponding entry in the random access memory;

The second verification module is further configured to read data of the corresponding entry from the random access memory based on each received scan message.
The apparatus according to claim 12, wherein the bandwidth of the scan packet sent by the packet sender is determined according to the traffic of the network processor forwarding data at the current time acquired by the packetizer.
The apparatus according to claim 10, wherein the failure determining module is further configured to write the randomized ECC check result of the data message of any one of the read items and the data message of the corresponding entry When the ECC check results before the memory are different, the fault information of the random access memory corresponding to the data message corresponding to the entry is determined.
A network processor comprising the apparatus of any one of claims 9 to 14.