WO2017008245A1 - Compensateur en série synchrone statique sans transformateur et procédé associé - Google Patents

Compensateur en série synchrone statique sans transformateur et procédé associé Download PDF

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Publication number
WO2017008245A1
WO2017008245A1 PCT/CN2015/083967 CN2015083967W WO2017008245A1 WO 2017008245 A1 WO2017008245 A1 WO 2017008245A1 CN 2015083967 W CN2015083967 W CN 2015083967W WO 2017008245 A1 WO2017008245 A1 WO 2017008245A1
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voltage
voltage source
alternating
value
master
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PCT/CN2015/083967
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WO2017008245A9 (fr
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Tinho LI
Hailian XIE
Nicklas Johansson
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Abb Technology Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/18—Arrangements for adjusting, eliminating or compensating reactive power in networks
    • H02J3/1807—Arrangements for adjusting, eliminating or compensating reactive power in networks using series compensators
    • H02J3/1814—Arrangements for adjusting, eliminating or compensating reactive power in networks using series compensators wherein al least one reactive element is actively controlled by a bridge converter, e.g. unified power flow controllers [UPFC]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/10—Flexible AC transmission systems [FACTS]

Definitions

  • the invention relates to transformer-less static synchronous series compensator (SSSC) for AC electrical power transmission system, and more particularly to the SSSC with scalable power converters and the method therefor.
  • SSSC transformer-less static synchronous series compensator
  • SC series compensation
  • FSC fixed series capacitor
  • CSC controllable series compensation
  • SSSC static synchronous series compensation
  • the compensator includes a transformer connected in series in an AC transmission line of AC electrical power transmission system, and a converter connected with the transformer in parallel. The converter can generate and inject into the AC transmission lines an alternating voltage with desired magnitude and phase angle.
  • An example of SSSC is provided in U.S. Pat. No. 5,814,975 entitled “Inverter Controlled Series Compensator” .
  • the transformer adds significantly to the cost and complexity of the apparatus and renders it less efficient.
  • the converter of the transformer-less SSSC comprises at least four self-commutated power semiconductor switches, each of which is shunted by a revers or anti-parallel connected diode.
  • IGBT is the popular power semiconductor switch due to the favourable characteristics of dynamic performance.
  • the current handling capability of single conventional IGBT module is limited to around 2kA rms.
  • IGCT can be alternative giving around 3.3kA rms current but the thermal resistance of the IGCT is roughly 2 times of IGBT, which limits the power density and requires much powerful cooling system. For high current applications especially when overcurrent handling ability is required in fault situations, it is desirable to increase current handling capability of the power converter.
  • a transformer-less static synchronous series compensator for an AC electrical power transmission system having a transmission line carrying an AC current, including: a multiple of voltage source converters, each of which having DC input and AC output and being configured to generate an alternating voltage with controllable magnitude and controllable phase angle across the AC output; wherein: the AC outputs of the multiple of voltage source converters are configured for parallel-injection of the generated alternating voltages into a phase of the transmission line.
  • it provides a method for compensating an impedance of a phase of a transmission line of an AC electrical power transmission system, including: (a) generating a multiple of alternating voltages each with controllable magnitude and controllable phase angle in consideration of measured value for alternating line current through the phase of the transmission line, measured value for alternating voltage injected into the phase of the transmission line and a predetermined reference value for effective impedance; and (b) injecting the generated multiple of alternating voltages in parallel into the phase of the transmission line so as to compensate its impedance.
  • the AC transmission line phase current can be distributed to the multiple of inputting the alternating voltages in parallel into the phase of the AC transmission line, and thus the current handling capability requirement for the power semiconductor switches used in each of the VSCs can be significantly reduced. Accordingly, as for high current applications especially when overcurrent handing ability is required in fault situations, the number of parallel-linked power modules for sharing the current flowing through phase legs of the VSC can be lowered dramatically.
  • the transformer-less static synchronous series compensator further includes an AC measuring device, being configured to measure a value for alternating line current flowing through the phase of the transmission line; an alternating voltage measuring device, being configured to measure a value for the alternating voltage generated by the multiple of voltage source converters and injected into the phase of the transmission line; and a control system, being configured to control each of the multiple of voltage source converters to generate the alternating voltage across its AC output in consideration of the measured value for the alternating line current, the measured value for the injected alternating voltage and a predetermined reference value for effective impedance.
  • an AC measuring device being configured to measure a value for alternating line current flowing through the phase of the transmission line
  • an alternating voltage measuring device being configured to measure a value for the alternating voltage generated by the multiple of voltage source converters and injected into the phase of the transmission line
  • a control system being configured to control each of the multiple of voltage source converters to generate the alternating voltage across its AC output in consideration of the measured value for the alternating line current, the measured value for the
  • Each of the voltage source converters includes at least one energy storage element being respectively coupled with its at least one DC input in parallel and at least one DC voltage measuring device being configured to respectively measure a value for DC voltage across its at least one DC input; and the control system is further configured to: control one of the multiple of voltage source converters as master in consideration of a predetermined master DC voltage reference and the measured value for the DC voltage across the DC input of the master; and control the other voltage source converter as slave in consideration of a filtered measured value for the DC voltage across the DC input of the master voltage source converter as slave DC voltage reference and the measured value for the DC voltage across the at least one DC input of the slave.
  • the alternating voltage generation step (a) includes: (al) generating one of the multiple of alternating voltages by a master voltage source converter in consideration of a predetermined master DC voltage reference and measured value for DC voltage of the master; and (a2) generating the other of the multiple of alternating voltages by a slave voltage source converter in consideration of a filtered measured value for DC voltage of the master voltage source converter as slave DC voltage reference and measured value for DC voltage of the slave.
  • the multiple of voltage source converters are configured to be modulated by PMW; and phase shifts are arranged among carrier signals respectively for the multiple of voltage source converters.
  • phase shifting the switching pattern between the VSCs By phase shifting the switching pattern between the VSCs, their output voltage and current ripples reduction can be achieved.
  • An appropriate angle of the phase shift can create the most significant ripple suppression effect.
  • the size of the filter can be shrunk; meanwhile high quality of the output voltage and current waveforms can be obtained.
  • Figure 1 illustrates an AC transmission system compensated by a transformer-less static synchronous series compensator according to an embodiment of present invention
  • Figure 2 depicts a circuit configuration of a transformer-less SSSC 10 electrically coupled with phase A of AC transmission line according to an embodiment of present invention
  • Figure 3A shows a more detailed schematic of an embodiment in accordance of figure 2;
  • FIG. 3B illustrates topology of NPC and T-type NPC
  • Figures 4A, 4B and 4C illustrate the block diagram of the control system according to the embodiment of figure 3A and 3Bbbb;
  • Figure 5A shows the output voltage switching waveform of dc/ac VSC 100a before the output filter and the waveform after the output filter;
  • Figure 5B shows the harmonics spectrum’s magnitude and phase angle information corresponding to the voltage waveform after the output filter
  • Figure 6A shows an example of the phase shifted carrier signals of the configuration with 3 VSCs in parallel
  • Figure 6B shows the concept of the harmonics cancellation methodology
  • Figures 7A and 7B show the normalized magnitude and phase information of the output voltage spectrum before the output filter
  • Figures 8A and 8B show the magnitude of the spectrums and phase plots of the 3 VSCs
  • Figure 9 shows a more detailed schematic of another embodiment in accordance of figure 2.
  • FIGS 10A, 10B, 10C and 10D illustrate the block diagram of the control system according to figure 9.
  • Figure 1 illustrates an AC transmission system compensated by a transformer-less static synchronous series compensator according to an embodiment of present invention.
  • the AC transmission system 1 includes three phases of AC transmission line A, B, C respectively for carrying current I A , I B , I C .
  • Three transformer-less SSSCs 10, 11, 12 are respectively electrically coupled with the respective phase A, B, C in series.
  • the three transformer-less SSSCs 10, 11, 12 are substantially similar both in circuit configuration and operation and can operate independently from each other.
  • FIG. 2 depicts a circuit configuration of a transformer-less SSSC 10 electrically coupled with phase A of AC transmission line according to an embodiment of present invention.
  • the transformer-less SSSC 10 includes a multiple of voltage source converters 100a, 100b ... 100n.
  • Each of the multiple of VSCs 100a, 100b ... 100n has DC input and AC output.
  • Each of the VSCs 100a, 100b ... 100n can be controlled to generate an alternating voltage with controllable magnitude and controllable phase angle across its AC output, and thus they can inject the generated alternating voltages into phase A of the transmission line in parallel so as to compensate the impedance of phase A.
  • the electrical-coupling paths along which the generated alternating voltages are in parallel fed into the transmission line phase A are indicated by the arrows Pa, Pb ... Pn in figure 2.
  • the AC transmission line phase current can be distributed to the multiple of VSCs 100a, 100b ... 100n inputting the alternating voltages in parallel into the phase of the AC transmission line, and thus the current handling capability requirement for the power semiconductor switches used in each of the VSCs can be significantly reduced. Accordingly, as for high current applications especially when overcurrent handing ability is required in fault situations, the number of parallel-linked power modules for sharing the current flowing through phase legs of the VSC can be lowered dramatically. In the preferable embodiment, the paralleling of the power semiconductor modules becomes unnecessary, since a single power semiconductor module can meet the required current handling capability.
  • Each of the paralleling VSCs has a controller controlling itself with respect to the given references, such as voltage, current, power and etc. Thus, no sophisticated gate driver is required as there is less or no current balancing problem between its power semiconductor modules.
  • the VSC 100a, 100b ... 100c can include a plurality of power semiconductor module pairs, and the power semiconductor can be IGBT, GTO, and IGCT.
  • An AC measuring device 102 measures a value for the AC transmission line current i L flowing through the phase A of the transmission line, using conventional current sensing device.
  • An alternating voltage measuring devices 103 measures a value for the alternating voltage injected into the AC transmission line, which is generated by the multiple of voltage source converters 100a, 100b ... 100n, by using conventional voltage sensing device.
  • a control system 105 receives the measured value for the alternating line current i L via a first control line 106 from the AC measuring device 102 and the measured values u inj for the alternating voltage injected into the transmission line phase A via a second control lines 107 from the alternating voltage measuring device 103.
  • the control system 105 controls each of the multiple of voltage source converters 100a, 100b ... 100n via a third control line 108a, 108b ... 108n to generate the alternating voltages across its AC output to the phase A of the AC transmission line.
  • the control algorithm varies from different topologies of each VSC, and thus will be described accompanying figures 3 and 9 afterwards.
  • FIG. 3A shows a more detailed schematic of an embodiment in accordance of figure 2.
  • the VSC 100a, 100b ... 100n uses topology of H-bridge without design of paralleling power semiconductor modules.
  • the skilled person shall understand that other topology, such as NPC and T-type NPC as shown in figure 3B, is applicable as well.
  • Each of the voltage source converters 100a, 100b ... 100n includes at least one energy storage element being respectively coupled with its DC input in parallel.
  • a capacitor 104a, 104b ... 104n is coupled to the DC input of VSCs 100a, 100b ... 100n in parallel for maintaining relatively constant DC voltage of the VSCs 100a, 100b ... 100n.
  • a DC voltage measuring device 108a, 108b ... 108n measures the value for DC voltage u DC_a , u DC_b ... u DC_n across the DC input of the VSCs 100a, 100b ... 100n, by using conventional DC voltage sensing device.
  • filter circuit 109 can be inserted between the phase A of the transmission line and each VSC.
  • VSCs 100a, 100b ... 100n are controlled individually without coordination thereof, measures need to be taken to suppress circulating energy though the VSCs.
  • the embodiment of present invention adopts master-slave control algorithm, where one of the VSCs 100a, 100b ... 100n is selected as the master and the others are selected as slaves; for example VSC 100a as master and VSC 100b ... 100n as slaves.
  • the control system 105 controls VSC 100a in consideration of a predetermined master DC voltage reference u DC_a_ref and the measured value for the DC voltage u DC_a across the DC input of the master 100a and controls the slaves 100b ...
  • Figures 4A, 4B and 4C illustrate the block diagrams of the control system according to figure 3.
  • the control system 105 takes the measured value for line current i L , measured value for injected voltage u inj , and the value for the measured DC voltage u DC_a , u DC_b ... u DC_n , a predetermined value for the DC voltage reference for the master u DC_a_ref and the reference reactance X SSSC, ref that the converter should produce as the input to calculate and provide the alternating voltage reference u AC_a_ref , u AC_b_ref ... u AC_n_ref for VSCs 100a, 100b ... 100n.
  • the alternating voltage reference u AC_a_ref , u AC_b_ref ... u AC_n_ref is sent to a PWM block PWMa, PWMb ... PWMn to generate gate signals for the VSCs 100a, 100b ... 100n.
  • phase current is assumed to contain a dc offset component and a sinusoidal component as shown below:
  • the single phase P. E. is utilized to obtain both the phasor component and the offset component.
  • the magnitude of the phasor component is then calculated as
  • the phasor of the injected voltage u inj is also estimated using the same method and the angle from the PLL.
  • the q component of the injected voltage divided by the magnitude of the current phasor gives the effective reactance X SSSC of the SSSC in this single phase.
  • the equivalent reactance is compared with its reference value X SSSC, ref .
  • the error is passed through a PI controller.
  • the output of the PI controller gives the reference of the q component of the S S S C voltage u′ q, ref .
  • VSC 100a In controlling the DC voltage of the VSC 100a, 100b ... 100n, the energy stored in the capacitor 104a, 104b ... 104n is controlled instead of the DC voltage itself.
  • the DC voltage control uses the master-slave control structure.
  • VSC 100a is the master unit and the other VSCs 100b ... 100n are the slave.
  • VSC 100a As shown in figure 4B, concerning the master control of VSC 100a, its capacitor energy is controlled by a PI controller.
  • the control system 105 output gives the d component of the VSC voltage u′ d, ref_a .
  • the reference of the d and q VSC voltage component are limited by the present DC voltage u DC_a .
  • the limited references are then transformed into ⁇ frame using the angle from the PLL.
  • the real part ( ⁇ component) is taken as the sinusoidal phase voltage and sent to the PWMa to generate gate signals for the power semiconductor modules of VSC 100a.
  • a value for filtered measured DC voltage u′ DDC_a of the VSC 100a (the master) is taken as the reference for the slave control.
  • the value for measured DC voltage u DC_b is compared with its own reference u′ DC_a in term of the capacitor energy.
  • the error is delivered to a second PI controller.
  • the sign will be adjusted.
  • the output from the second PI controller will be added to the output u′ d,ref_a from the PI controller of the master controller.
  • the limited references are then transformed into ⁇ frame using the angle from the PLL.
  • the real part ( ⁇ component) is taken as the sinusoidal phase voltage and sent to the PWMb for generation of gate signals.
  • Each of the VSCs 100a, 100b ... 100n is modulated by pulse with modulation (PWM) .
  • PWM pulse with modulation
  • passive filtering is not very effective. It is because from the passive filtering aspect, the switching frequency is close to the fundamental frequency (50Hz /60Hz) .
  • the switching component and its harmonics are difficult to be attenuated by passive filter due to the finite attenuation ability.
  • the physical size and cost of the filter increase accordingly with the current and voltage rating.
  • Output voltage and current ripples reduction can be achieved by phase shifting the switching pattern between the VSCs. An appropriate angle of the phase shift can create the most significant ripple suppression effect.
  • the size of the filter can be shrunk; meanwhile high quality of the output voltage and current waveforms can be obtained.
  • the proposed method is to phase shift the carrier signals between the VSCs by an appropriate angle.
  • the power semiconductor modules of each VSCs 100a, 100b ... 100n changes its conducting state following the gate signals modulated by PWM signals, and phase shifts are arranged among the carrier signals respectively for the VSCs.
  • Angle of the phase shift in the carrier signals has to be determined coordinately with the modulation method and the number of the VSCs in parallel.
  • the phase difference between the output voltages of the VSCs should be equaled to where N is the number of VSCs in parallel.
  • the phase difference between the carrier signals is equal to k f eff_L is the effective operating frequency across the output filter inductor. For instance, k equals to 0.5 or 1 for the modulations scheme with or without frequency doubling effect respectively.
  • Table I shows examples of the phase difference with bipolar and unipolar modulation for each of the H-bridges.
  • phase shifting modulation method can be applied directly to the topologies as shown in figure 3.
  • FIG. 5A shows the output voltage switching waveform of dc/ac VSC 100a before the output filter while the bottom window shows the waveform after the output filter.
  • Figure 5B shows the harmonics spectrum’s magnitude and phase angle information corresponding to the voltage waveform after the output filter.
  • Figure 6A shows an example of the phase shifted carrier signals of the configuration with 3 VSCs in parallel. The idea is to adjust the phase shift of the switching patterns between the VSCs to 120°. Therefore, the voltage harmonics components can be canceled effectively due to the magnitudes are similar.
  • Figure 6B shows the concept of the aforementioned harmonics cancellation methodology.
  • Figure 7A and 7B show the normalized magnitude and phase information of the output voltage spectrum before the output filter. It can be seen the magnitude of the spectrums, in figure 8A, of the 3 VSCs are almost the same but the phase plots, as shown in Figure 8B, are different. Table II shows the angle information of the most signification harmonics orders of the 3 VSCs. It can be seen that the difference of the angles between the VSCs is almost 120° or 240° for all the mentioned harmonics orders. It verified the concept shown in Figure 6B. It is due to the fact that the switching patterns, and thus the phase plots, are shifting corresponding with the shift in the carrier signal. The shift is minimal when comparing to the period of the fundamental frequency, therefore the magnitude plots of the converters are almost the same.
  • Figure 8A shows the vector sum of the converters voltage spectrums before the output filter. It can be seen that the magnitude is very small.
  • Figure 8B shows the output voltage waveforms after the output filter, waveform in blue is without the phase shift operation while the waveform in red is with the proposed phase shift operation. With the phase shift operation, the total harmonic distortion (vTHD) is 1.6%instead of 13.3%for the one without the phase shift operation.
  • FIG. 9 shows a more detailed schematic of another embodiment in accordance of figure 2.
  • the embodiment as shown in figure 9 is different from that of figure 3 in that the VSC 100a, 100b ... 100n uses topology of series connected H-bridge without design of paralleling power semiconductor modules.
  • each of the VSCs 100a, 100b ... 100n includes a plurality of VSC cells whose AC outputs are coupled in series forming the AC output of the VSC.
  • VSC 100a includes VSC cells 100a1, 100a2 ... 100am
  • VSC 100b includes VSC cells 100b1, 100b2 ... 100bm
  • VSC 100n includes VSC cells 100n1, 100n2 ... 100nm.
  • 100n includes a multiple of energy storage element being respectively coupled with its DC inputs in parallel.
  • a multiple of capacitors 104a1, 104a2 ... 104am are coupled to the DC inputs of VSC 100a
  • a multiple of capacitors 104b1, 104b2 ... 104bm are coupled to the DC inputs of VSC 100b
  • a multiple of capacitors 104n1, 104n2 ... 104nm are coupled to the DC inputs of VSC 100n.
  • a DC voltage measuring device 108a measures the value for DC voltage u DC_a1 , u DC_a2 ...
  • filter circuit 109 can be inserted between the phase A of the transmission line and each VSC.
  • the embodiment of present invention adopts master-slave control algorithm, where one of the VSCs 100a, 100b ... 100n is selected as the master and the others are selected as slave; for example VSC 100a as master
  • the control system 105 controls the VSC cells 100a1, 100a2 ... 100am of the VSC 100a (master VSC) in consideration of a predetermined master DC voltage reference u DC_a_ref and values for the measured DC voltages across the DC input of the VSC cells of the master u DC_a1 , u DC_a2 ... u DC_am .
  • VSC cell 100a1 it is controlled in consideration of the predetermined master DC voltage reference u DC_a_ref and values for the measured DC voltages across the DC input of the VSC cells of the master u DC_a1 , u DC_a2 ... u DC_am .
  • the control system 105 further controls a first VSC cell 100b1 ... 100n1 of the slave 100b ... 100n in consideration of an average value for the filtered measured DC voltages of the master u DC_a1 , u DC_a2 ... u DC_am and a value for the measured DC voltage at the DC input of the first VSC cell of the slave u DC_b1 ... u DC_n1 .
  • the first VSC cell 100b1 it is controlled in consideration of the average value for the filtered measured DC voltages of the master u′ DC_a1 , u′ DC_a2 ... u′ DC_am and the value for the measured DC voltage at the DC input of the first VSC cell of the slave u DC_b1 .
  • control system 105 controls a second VSC cell of the slave 100b2 ... 100bm, ... , 100n2 ... 100nm of the slave 100b ... 100n in consideration of a value for the filtered measured DC voltage of the first VSC cell of the same VSC u′ DC_b1 ... u′ DC_n1 as reference and a value for the measured DC voltage at the DC input of the second VSC cell of the slave u DC_b2 ... u DC_bm , ... , u DC_n2 ... u DC_nm .
  • VSC cell 100b2 it is controlled in consideration of the value for the filtered measured DC voltage of the first VSC cell of the same VSC u′ DC_b1 as reference and a value for the measured DC voltage at the DC input of the second VSC cell of the slave u DC_b2 .
  • Figures 10A, 10B, 10C and 10D illustrates the block diagram of the control system according to figure 9.
  • the embodiment according to figure 10A uses the same control algorithm of effective reactance control as that used for the embodiment according to figure 4. In order to avoid redundancy, it is not repeated here.
  • the control of the master VSC cell 100a1, 100a2 ... 100am shown in Figure 10B uses the same structure as that for the master VSC as shown in figure 4B.
  • Each of the m H-bridges in the master VSC 100a controls its own DC voltage.
  • the reference value is the average of the filtered DC voltages of all the m H-bridges 100a1, 100a2 ... 100am in the master 100a, i.e.,
  • the measured DC voltage u DC_i1 of the first H-bridgel00il in the VSC 100i is compared with u dc, ref_i1 in term of the capacitor energy.
  • the error is delivered to a second PI controller.
  • the sign will be adjusted.
  • the output from the second PI controller will be added to the output u′ d, ref_P1 , which is the average of the m outputs from the m PI controllers of the master controller, i.e.,
  • the limited references are then transformed into ⁇ frame using the angle from the PLL.
  • the real part ( ⁇ component) is taken as the sinusoidal phase voltage and sent to the PWM block for generation of gate signals.
  • the reference value is the filtered DC voltages u′ DC_i1 of the first H-bridge in the same VSC 100i.
  • the measured DC voltage u DC_ij of the jth H-bridge 100ij in the i th VSC 100i is compared with u′ DC_i1 in term of the capacitor energy.
  • the error is delivered to a third PI controller.
  • the output from the third PI controller will be added to the output u′ d, ref_i1 , which is the output from the second PI controller of the first HB.
  • the limited references are then transformed into ⁇ frame using the angle from the PLL.
  • the real part ( ⁇ component) is taken as the sinusoidal phase voltage and sent to the PWM block for generation of gate signals.
  • the third and the second PI controller may share the same controller parameters.
  • phase shifting can be applied to the series connected H-bridges in order to obtain even better output voltage quality.
  • the phase shifting angle can be determined in a similar way as described above. Cell phase shifts are arranged among carries signals respectively for the plurality of VSC cells of the VSC 100a, 100b ... 100n.

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Abstract

L'invention concerne un compensateur en série synchrone statique sans transformateur pour un système de transmission de puissance électrique en CA comportant une ligne de transmission transportant un courant alternatif et un procédé associé. Le compensateur en série synchrone statique sans transformateur inclut des convertisseurs de source de tension (100a, 100b… 100n) multiples, chacun d'entre eux comportant une entrée en CC et une sortie en CA et servant à générer une tension alternative dont l'amplitude peut être commandée et dont l'angle de phase peut être commandé aux bornes de la sortie en CA ; les sorties en CA des convertisseurs de source de tension multiples servant à l'injection en parallèle des tensions alternatives générées dans une phase de la ligne de transmission (A, B, C). Le courant de phase de la ligne de transmission en CA peut être distribué aux entrées multiples des tensions alternatives en parallèle dans la phase de la ligne de transmission en CA, et ainsi l'exigence de capacité de résistance au courant pour des commutateurs semi-conducteurs de puissance utilisés dans chacun des convertisseurs de source de tension peut être significativement réduite.
PCT/CN2015/083967 2015-07-14 2015-07-14 Compensateur en série synchrone statique sans transformateur et procédé associé WO2017008245A1 (fr)

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FR3083020A1 (fr) * 2018-06-26 2019-12-27 Ge Energy Power Conversion Technology Limited Systeme de compensation de tension pour circuit de distribution d'energie electrique multiphasee
EP3614519A3 (fr) * 2018-08-23 2020-04-29 Smart Wires Inc. Modules d'injection modulaires à synchronisation temporelle
CN111446868A (zh) * 2020-05-07 2020-07-24 福州大学 一种自耦电力电子变压器电路拓扑及其控制方法
CN111509788A (zh) * 2020-04-26 2020-08-07 太原理工大学 一种可变拓扑的改进型交直流混合微电网及其控制方法
CN112909965A (zh) * 2019-11-15 2021-06-04 智能电线股份有限公司 阻抗注入单元稳定性的自适应控制技术
CN114285056A (zh) * 2021-10-18 2022-04-05 国网浙江省电力有限公司丽水供电公司 一种储能变流器多机并联改进主从控制方法

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