WO2017006339A3 - System and method for controlling phase allignment of clock signals - Google Patents

System and method for controlling phase allignment of clock signals Download PDF

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Publication number
WO2017006339A3
WO2017006339A3 PCT/IN2016/000170 IN2016000170W WO2017006339A3 WO 2017006339 A3 WO2017006339 A3 WO 2017006339A3 IN 2016000170 W IN2016000170 W IN 2016000170W WO 2017006339 A3 WO2017006339 A3 WO 2017006339A3
Authority
WO
WIPO (PCT)
Prior art keywords
delay circuit
clock signals
phase
allignment
detector circuitry
Prior art date
Application number
PCT/IN2016/000170
Other languages
French (fr)
Other versions
WO2017006339A2 (en
Inventor
Prakash GYAN
Kumar NIDHIR
Reddy Vorugu Muniswara
Original Assignee
Gyan Prakash
Nidhir Kumar
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gyan Prakash, Nidhir Kumar filed Critical Gyan Prakash
Priority to US15/577,340 priority Critical patent/US10504569B2/en
Publication of WO2017006339A2 publication Critical patent/WO2017006339A2/en
Publication of WO2017006339A3 publication Critical patent/WO2017006339A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)

Abstract

A system and method for aligning clock signals in a DDR DRAM module is disclosed. The system includes a phase detector circuitry, a controllable delay circuit, a first delay circuit and a synchronizing circuit. A clock signal is simultaneously transmitted through the first delay circuit and the controllable delay circuit. Subsequently, the clock signals transmitted through the first delay circuit and the controllable delay circuit are captured at the output thereof, and fed as inputs to the phase detector circuitry. The phase detector circuitry determines whether the clock signals are in phase, and accordingly adjusts the delay associated with the controllable delay circuit until the two clock signals are determined to be in phase.
PCT/IN2016/000170 2015-07-03 2016-06-30 System and method for controlling phase allignment of clock signals WO2017006339A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/577,340 US10504569B2 (en) 2015-07-03 2016-06-30 System and method for controlling phase alignment of clock signals

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IN1782CH2015 2015-07-03
IN1782/CHE/2015 2015-07-03

Publications (2)

Publication Number Publication Date
WO2017006339A2 WO2017006339A2 (en) 2017-01-12
WO2017006339A3 true WO2017006339A3 (en) 2017-03-16

Family

ID=57686047

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IN2016/000170 WO2017006339A2 (en) 2015-07-03 2016-06-30 System and method for controlling phase allignment of clock signals

Country Status (2)

Country Link
US (1) US10504569B2 (en)
WO (1) WO2017006339A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111052241B (en) 2018-08-14 2023-11-17 联发科技股份有限公司 Delay tracking method and memory system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140181568A1 (en) * 2012-12-24 2014-06-26 Arm Limited Interface for controlling the phase alignment of clock signals for a recipient device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7671647B2 (en) * 2006-01-26 2010-03-02 Micron Technology, Inc. Apparatus and method for trimming static delay of a synchronizing circuit
US7816961B2 (en) * 2008-02-08 2010-10-19 Qimonda North America System and method for signal adjustment

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140181568A1 (en) * 2012-12-24 2014-06-26 Arm Limited Interface for controlling the phase alignment of clock signals for a recipient device

Also Published As

Publication number Publication date
US10504569B2 (en) 2019-12-10
US20190066740A1 (en) 2019-02-28
WO2017006339A2 (en) 2017-01-12

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