WO2017004910A1 - Procédé et appareil de réception de signal - Google Patents

Procédé et appareil de réception de signal Download PDF

Info

Publication number
WO2017004910A1
WO2017004910A1 PCT/CN2015/092324 CN2015092324W WO2017004910A1 WO 2017004910 A1 WO2017004910 A1 WO 2017004910A1 CN 2015092324 W CN2015092324 W CN 2015092324W WO 2017004910 A1 WO2017004910 A1 WO 2017004910A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
signals
channel
channels
splicing
Prior art date
Application number
PCT/CN2015/092324
Other languages
English (en)
Chinese (zh)
Inventor
赵丽娟
穆学禄
田珅
周虹
许盛全
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Publication of WO2017004910A1 publication Critical patent/WO2017004910A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits

Definitions

  • the present invention relates to the field of communications, and in particular to a method and apparatus for receiving a signal.
  • the receiver is an important component of the RF communication system.
  • the weak RF signal received by the receiver performs low noise amplification, down conversion, filtering, preamplifier amplification, and automatic gain control (AGC) amplification. Downconverting to the intermediate frequency, subsequent filtering and demodulation processing.
  • AGC automatic gain control
  • dynamic range is an important indicator.
  • the dynamic range of a wireless receiving system is the range between the maximum and minimum signals that the receiver can receive. Limited by the thermal noise of the circuit, the receiver cannot receive signals with infinitely small power, and the minimum signal that the receiver can receive is the receiver's receiving sensitivity. The receiver is also unable to receive signals with infinite power. As the received signal increases, it exceeds the linear range of each link of the receiver, generating nonlinearity, reducing the signal-to-noise ratio, and affecting subsequent demodulation.
  • the invention provides a method and a device for receiving signals, so as to at least solve the problem that the power received by the receiver in the related art is too large, which is easy to generate nonlinearity, reduce the signal to noise ratio, and affect the subsequent demodulation.
  • a method for receiving a signal including:
  • performing alignment splicing according to the amplitudes of the plurality of signals, and obtaining the output signals of the plurality of signals after splicing includes:
  • the plurality of linear signals are spliced into an output signal by time delay scaling.
  • acquiring a plurality of signals of different preset gains in the plurality of channels includes:
  • ADC analog to digital converter
  • the method includes:
  • the output signal is sent to the channel for re-extraction and processing.
  • the method before acquiring multiple signals of a plurality of different preset gain channels, the method includes:
  • a signal receiving apparatus including:
  • Obtaining a module configured to acquire a plurality of signals of different preset gains in the plurality of channels, wherein a magnitude of the preset gain is inversely proportional to a magnitude of the received signal of the channel;
  • Aligning a module configured to align the plurality of signal delays by a common receiving amplitude of the plurality of channels
  • the splicing module is configured to perform alignment splicing according to the amplitudes of the plurality of signals of the different preset gains to obtain an output signal of the plurality of signals after splicing.
  • the splicing module comprises:
  • a correction unit configured to perform a pre-distortion process on the plurality of signals to obtain a plurality of linear signals
  • a linear tiling unit configured to splicing the plurality of linear signals into an output signal by time delay scaling.
  • the obtaining module comprises:
  • the digital signal unit is configured to acquire a plurality of signals of different preset gains of the plurality of channels received by the analog-to-digital converter ADC.
  • the apparatus comprises:
  • a correction module configured to determine whether the output signal reaches a preset correction threshold
  • the first sending module is configured to send the output signal to the channel for re-extraction and processing if the output signal reaches the preset correction threshold.
  • the apparatus comprises:
  • a second sending module configured to send the preset gain and phase to the channel, wherein the phase is used to determine a location of a common receiving amplitude splicing of the multiple channels.
  • a plurality of signals of different preset gains of the plurality of channels are obtained, wherein the magnitude of the preset gain is inversely proportional to the amplitude of the received signal of the channel, and the common receiving amplitude of the plurality of channels is Multiple signal delay pairs Aligning and splicing according to the amplitudes of the plurality of signals of the different preset gains to obtain an output signal of the plurality of signals after splicing, which solves the problem that when the power of the received signal of the receiver is too large, nonlinearity is easily generated.
  • the signal-to-noise ratio is reduced, which affects the subsequent demodulation problem, and achieves distortion-free reception of large dynamic signals.
  • FIG. 1 is a flow chart of a method of receiving a signal according to an embodiment of the present invention
  • FIG. 2 is a block diagram showing the structure of a signal receiving apparatus according to an embodiment of the present invention.
  • FIG. 3 is a functional block diagram of an FPGA in accordance with a preferred embodiment of the present invention.
  • FIG. 4 is a schematic diagram of signal processing for a large dynamic multi-channel according to a preferred embodiment of the present invention.
  • Figure 5 is a schematic illustration of a system in accordance with a first embodiment of a preferred embodiment of the present invention
  • FIG. 6 is a schematic diagram of a system according to a second embodiment of a preferred embodiment of the present invention.
  • Figure 7 is a schematic illustration of a system in accordance with a third embodiment of a preferred embodiment of the present invention.
  • Figure 8 is a schematic illustration of a system of a fourth embodiment in accordance with a preferred embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a system according to a fifth embodiment of a preferred embodiment of the present invention.
  • Figure 10 is a flow diagram of system processing in accordance with a preferred embodiment of the present invention.
  • FIG. 1 is a flowchart of a method for receiving a signal according to an embodiment of the present invention. As shown in FIG. 1, the process includes the following steps:
  • Step S102 Acquire multiple signals of different preset gains in multiple channels, where the magnitude of the preset gain is inversely proportional to the amplitude of the received signal of the channel;
  • Step S104 aligning the plurality of signal delays by the common receiving amplitude of the multiple channels
  • Step S106 Perform alignment splicing according to the amplitudes of the plurality of signals of the different preset gains to obtain an output signal of the plurality of signals after splicing.
  • the two channels use the received signal to perform correlation operations in a Field-Programmable Gate Array (FPGA). Determine the delay of the respective channels and fill the delay difference between the two channels. This signal amplitude is acceptable for both channels and does not cause the respective channel to overflow.
  • the signal is generated by a calibrated transmit channel and is used to generate a signal that calibrates the receive channel.
  • the plurality of signals before the plurality of signals are aligned and spliced, the plurality of signals are subjected to post-predistortion processing to obtain a plurality of linear signals, and the plurality of linear signals are spliced into an output signal by delay calibration.
  • the pre-distortion of the latter term is the inverse model correction for the nonlinearity of the receiving channel
  • the inverse nonlinear model can use the inverse model of the nonlinearity of the amplifier in the related art, and the signal is emitted by the transmitting calibration channel, and the receiving channel Receiving, then performing nonlinear model calculation on the digital signal on the digital side to obtain the factor of the nonlinear model, and inverting the model to obtain the inverse model factor, the received data is sent to the transmitting calibration channel after being sent through the inverse model. Then, it is received by the receiving channel, and after repeating the above work for more than 10 times, it stops, and the final inverse nonlinear model factor is obtained.
  • the signals received by the normally operating receive channels in the following embodiments pass through this inverse nonlinear model. Thereby a linear received signal is obtained.
  • the delay calibration is the delay measurement and compensation of the receiving channel, which is equivalent to the function and function of the delay alignment in the above embodiment.
  • a plurality of signals of different preset gains of the plurality of channels received by the analog-to-digital converter ADC are obtained, wherein the analog-to-digital converter ADC converts the signal from an analog signal to a digital signal.
  • the output signal of the plurality of signals After the output signal of the plurality of signals is obtained, it is determined whether the output signal reaches a preset correction threshold, and when the output signal reaches the preset correction threshold, the output signal is sent to This channel is extracted and processed again.
  • the preset gain and phase are sent to the channel, wherein the phase is used to determine a position of the common reception amplitude splicing of the multiple channels.
  • a signal receiving device is also provided, which is used to implement the above embodiments and preferred embodiments, and has not been described again.
  • the term “module” may implement a combination of software and/or hardware of a predetermined function.
  • the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • FIG. 2 is a structural block diagram of a signal receiving apparatus according to an embodiment of the present invention. As shown in FIG. 2, the apparatus includes
  • the obtaining module 22 is configured to acquire multiple signals of different preset gains in the multiple channels, wherein the size of the preset gain is inversely proportional to the amplitude of the received signal of the channel;
  • Aligning module 24 configured to align the plurality of signal delays by a common receiving amplitude of the plurality of channels
  • the splicing module 26 is configured to perform alignment splicing according to the amplitudes of the plurality of signals of the different preset gains to obtain an output signal of the plurality of signals after splicing.
  • the delay alignment is performed according to the amplitudes of the plurality of signals of the different preset gains, and the output signals of the plurality of signals are obtained, thereby solving the problem that when the power of the received signal of the receiver is too large, nonlinearity is generated and the nonlinearity is reduced.
  • the signal-to-noise ratio affects the subsequent demodulation problem and achieves distortion-free reception of large dynamic signals.
  • the splicing module 26 includes:
  • a correction unit configured to perform post-predistortion processing on the plurality of signals to obtain a plurality of linear signals
  • a linear tiling unit configured to splicing the plurality of linear signals into an output signal by time delay scaling.
  • the obtaining module 22 includes:
  • the digital signal unit is configured to acquire a plurality of signals of different preset gains of the plurality of channels received by the analog-to-digital converter ADC.
  • the device further includes:
  • a correction module configured to determine whether the output signal reaches a preset correction threshold
  • the first sending module is configured to send the output signal to the channel for re-extraction and processing if the output signal reaches the preset correction threshold.
  • the second sending module is configured to send the preset gain and phase to the channel, wherein the phase is used to determine a location of the common receiving amplitude splicing of the multiple channels.
  • the preferred embodiment provides a Field-Programmable Gate Array (FPGA) for performing delay calibration on the received multi-channel data in a multi-channel receiver link. Distortion, and the combination of high and low data. Moreover, the present invention adopts multi-channel different gain reception, so that the maximum amplitude of the input signal of the magnitude and amplitude is improved, and the noise floor is not deteriorated, and then the signal splicing is used to complete a large input signal.
  • the receiver of the preferred embodiment is applicable to high intermediate frequency and zero intermediate frequency systems.
  • the preferred embodiment provides a receiver capable of processing multi-channel large dynamic data, and processes large dynamic multi-channel data, and realizes different gains of each signal by adjusting gain by multi-channel data, and receiving signal amplitude
  • the receiver also has a transmit auxiliary channel, which is used to help the receiving channel determine the channel gain and phase alignment, and realize on-line real-time auxiliary power calibration.
  • the preferred embodiment can also implement the offline mode calibration calibration, that is, the data of the amplitude phase calibration is saved and called as needed.
  • the receiving channel of the preferred embodiment is exemplified by two receiving channels in the implementation case, and the actual link needs to be received according to The dynamic range of the signal is determined.
  • the number of channels is 2 or more, which is subject to the complete reception of the large dynamic signal.
  • the receiver of the preferred embodiment is capable of receiving a large dynamic signal and achieving distortion-free reception of the signal by means of multiplexing and signal processing.
  • FIG. 3 is a functional block diagram of an FPGA according to a preferred embodiment of the present invention.
  • the FPGA first performs multi-channel fine alignment on the data transmitted by the ADC, and then determines the gain of different channels by gain scaling after the bit width is extended and output. Then, the received nonlinear signal is corrected by the pre-distortion processing of the latter item, and then the corrected data is spliced by amplitude alignment, and finally the bit width is expanded and output.
  • FIG. 4 is a schematic diagram of signal processing for a large dynamic multi-channel according to a preferred embodiment of the present invention.
  • a large dynamic signal it is usually limited by the gain control of the device, and the signal received by one channel cannot be received.
  • Two or more channels are used to intercept the signal.
  • Figure 4 is for two receiving channels. The signal can only accept a part of the signal according to the channel index limit of each link.
  • the large dynamic signal is divided into A and B is received in two parts. The two parts of A and B respectively have coincident parts. For the coincident parts, the delay is aligned, the gain is scaled, and the latter pre-distortion splicing the data to complete the final signal output.
  • Embodiment 1 is a schematic diagram of a system according to Embodiment 1 of the preferred embodiment of the present invention.
  • Embodiment 1 describes two channels, and Channel 1 includes an antenna ANT1, a filter FLT1, and a low noise amplifier LNA1.
  • the signal obtained from the antenna ANT1 is filtered out by the filter FLT1, the small signal is amplified by the low noise amplifier LNA1, and the gain of the signal is adjusted by the adjustable attenuator ATT1, so that the signal of the channel 1 is different from the signal gain of the channel 2.
  • Channel 2 includes antenna ANT2, filter FLT2, low noise amplifier LNA2, adjustable attenuator ATT2, filter FLT22, mixer MIX2, adjustable gain amplifier AMP2, analog to digital converter ADC2.
  • the signal obtained from the antenna ANT2 is filtered out by the filter FLT2, the small signal is amplified by the low noise amplifier LNA2, and the gain of the signal is adjusted by the adjustable attenuator ATT2, so that the signal of the channel 2 is different from the signal gain of the channel 1.
  • the filter FLT22 filters out the clutter signal
  • the spectrum of the signal is shifted by the mixer MIX2
  • the channel signal is amplified by the adjustable gain amplifier AMP2 and the gain is adjusted again to ensure that the signal gain of the path is within the required range.
  • the signal is analog-to-digital converted by ADC2, and finally the digital signal is sent to the FPGA for digital signal processing.
  • the FPGA receives two signals with different gains, and performs pre-distortion on the FPGA to make the signal become a linear signal. Then, the two channels of data are spliced and combined into one large dynamic signal by delay calibration.
  • Channel 3 is a transmit auxiliary circuit. Its main function is to help the receiving channel determine channel gain and phase alignment, and perform auxiliary power calibration in real time. The workflow is like this.
  • the FPGA determines that if the signal needs to be recalibrated, the switch SWITCH is turned on. It should be noted that the SWITCH normal state is off.
  • the switch After turning on the switch, enter the DAC for digital-to-analog conversion, filter the clutter signal through the filter FLT3, modulate the signal through the modulator MOD, and then amplify the signal through the adjustable gain amplifier AMP3, and adjust the signal to a large signal through the power amplifier POWER.
  • the circulator CIRCLE4 sends the signal to FLT4 for secondary filtering and then transmits it through ANT3. Because ANT3 and ANT2, ANT1 are very close, you can pass the day
  • the coupling between the lines sends the signal of channel 3 to channel 1 and channel 2 for signal split channel extraction and processing.
  • Embodiment 2 is a schematic diagram of a system according to Embodiment 2 of a preferred embodiment of the present invention.
  • a signal is acquired from an antenna ANT, and an interference signal is filtered by a filter FLT, and signals are respectively separated by a COUP coupler.
  • channel 1 includes low noise amplifier LNA1, adjustable attenuator ATT1, filter FLT11, mixer MIX1, adjustable gain amplifier AMP1, analog to digital converter ADC1.
  • the signal from the coupler COUP amplifies the small signal through the low noise amplifier LNA1, and adjusts the gain of the signal through the adjustable attenuator ATT1, so that the signal of channel 1 is different from the signal gain of channel 2.
  • Channel 2 includes low noise amplifier LNA2, adjustable attenuator ATT2, filter FLT22, mixer MIX2, adjustable gain amplifier AMP2, analog to digital converter ADC2.
  • the signal from the coupler COUP amplifies the small signal through the low noise amplifier LNA2, and adjusts the gain of the signal through the adjustable attenuator ATT2, so that the signal of the channel 2 is different from the signal gain of the channel 1.
  • the filter FLT22 filters out the clutter signal
  • the spectrum of the signal is shifted by the mixer MIX2
  • the channel signal is amplified by the adjustable gain amplifier AMP2 and the gain is adjusted again to ensure that the signal gain of the path is within the required range.
  • the signal is analog-to-digital converted by ADC2, and finally the digital signal is sent to the FPGA for digital signal processing.
  • the FPGA receives two signals with different gains, and performs pre-distortion on the two signals first, so that the signal becomes a linear signal.
  • the two channels of data are spliced and combined into one large dynamic signal by delay calibration.
  • Channel 3 is a transmit auxiliary circuit.
  • the FPGA determines that if the signal needs to be recalibrated, the switch SWITCH is turned on. It should be noted that the SWITCH normal state is off. After turning on the switch, enter the DAC for digital-to-analog conversion, filter the clutter signal through the filter FLT3, modulate the signal through the modulator MOD, and then amplify the signal through the adjustable gain amplifier AMP3 and send it to the FLT for secondary filter. The signal after the filter is sent to channel 1 and channel 2 through the coupler for sub-channel extraction and processing.
  • Embodiment 7 is a schematic diagram of a system according to Embodiment 3 of the preferred embodiment of the present invention.
  • the signal acquired from the antenna ANT is filtered by the filter FLT to filter out the interference signal, and the low noise LNA is small.
  • the signal is amplified, and the gain of the signal is adjusted by the adjustable attenuator ATT.
  • the spectrum is moved by the mixer MIX, and the signals are respectively divided into two channels by the power divider DIV.
  • Channel 1 includes an adjustable gain amplifier AMP1, analog to digital converter ADC1.
  • the signal from the power divider DIV is amplified by the adjustable gain amplifier AMP1 and the gain is adjusted again, so that the signal of channel 2 is different from the signal gain of channel 1, and then the signal is analog-to-digital converted by ADC1, and finally Digital signals are passed to the FPGA for digital signal processing.
  • Channel 2 includes an adjustable gain amplifier AMP2 and an analog to digital converter ADC2.
  • the signal from the power divider DIV is amplified by the adjustable gain amplifier AMP2 and the gain is adjusted again, so that the signal of channel 2 is different from the signal gain of channel 1, and then the signal is analog-to-digital converted by ADC2, and finally Digital signals are passed to the FPGA for digital signal processing.
  • the FPGA receives two signals with different gains, and performs pre-distortion on the two signals first, so that the signal becomes a linear signal. Then, the two channels of data are spliced and combined into one large dynamic signal by delay calibration.
  • Channel 3 is a transmit auxiliary circuit. Its main function is to help the receiving channel determine channel gain and phase alignment, and perform auxiliary power calibration in real time. The workflow is like this.
  • the FPGA determines if the signal needs to be recalibrated, then turn on the switch SWITCH. Note that the SWITCH is normal. The state is off.
  • Embodiment 4 is a schematic diagram of a system according to Embodiment 4 of the preferred embodiment of the present invention.
  • the signal acquired from the antenna ANT is filtered out by the filter FLT, and the interference signal is filtered through the low noise LNA.
  • the signal is amplified, and the gain of the signal is adjusted by the adjustable attenuator ATT.
  • the signal is divided into two channels by the power divider DIV, and the channel 1 includes the mixer MIX1.
  • Adjustable gain amplifier AMP1 analog to digital converter ADC1.
  • the signal from the power divider DIV is used to shift the signal through the mixer MIX1.
  • the channel signal is amplified by the adjustable gain amplifier AMP1 and the gain is adjusted again, so that the signal of channel 2 is different from the signal gain of channel 1.
  • the signal is analog-to-digital converted by ADC1, and finally the digital signal is sent to the FPGA for digital signal processing.
  • Channel 2 includes a mixer MIX2, an adjustable gain amplifier AMP2, and an analog to digital converter ADC2.
  • the signal from the power divider DIV is used to shift the signal through the mixer MIX2.
  • the channel signal is amplified by the adjustable gain amplifier AMP2 and the gain is adjusted again, so that the signal of channel 2 is different from the signal gain of channel 1.
  • the signal is analog-to-digital converted by ADC2, and finally the digital signal is sent to the FPGA for digital signal processing.
  • the FPGA receives two signals with different gains, and performs pre-distortion on the two signals first, so that the signal becomes a linear signal.
  • the two channels of data are spliced and merged into one large dynamic signal by time delay calibration.
  • Channel 3 is a transmit auxiliary circuit. Its main function is to help the receiving channel determine channel gain and phase alignment, and perform auxiliary power calibration in real time.
  • the workflow is like this.
  • the FPGA determines that if the signal needs to be recalibrated, the switch SWITCH is turned on. It should be noted that the SWITCH normal state is off.
  • Embodiment 9 is a schematic diagram of a system according to Embodiment 5 of the preferred embodiment of the present invention.
  • the signal acquired from the antenna ANT is filtered by the filter FLT to filter out the interference signal, and the low noise LNA is small.
  • Signal amplification, through the power divider DIV, the signal is divided into two channels, channel 1 includes adjustable attenuator ATT1, filter FLT1, mixer MIX1, adjustable gain amplifier AMP1, analog-to-digital converter ADC1.
  • the signal from the power divider DIV adjusts the gain of the signal through the adjustable attenuator ATT1.
  • Channel 2 includes an adjustable attenuator ATT2, a filter FLT2, a mixer MIX2, an adjustable gain amplifier AMP2, and an analog to digital converter ADC2.
  • the signal from the power divider DIV adjusts the gain of the signal through the adjustable attenuator ATT2.
  • the mixer MIX2 After filtering the clutter signal through the filter FLT2, the mixer MIX2 performs the spectrum shifting of the signal through the adjustable gain amplifier AMP2.
  • the channel signal is amplified and the gain is adjusted again, so that the signal of channel 2 is different from the signal gain of channel 1, and then the signal is analog-to-digital converted by ADC2, and finally the digital signal is sent to the FPGA for digital signal processing.
  • the FPGA receives two signals with different gains, and performs pre-distortion on the two signals first, so that the signal becomes a linear signal. Then, the two channels of data are spliced and combined into one large dynamic signal by delay calibration.
  • Channel 3 is a transmit auxiliary circuit.
  • the FPGA determines if the signal needs to be recalibrated, then turn on the switch SWITCH, It should be noted that the normal state of SWITCH is off. After turning on the switch, enter the DAC for digital-to-analog conversion, filter the clutter signal through the filter FLT3, modulate the signal through the modulator MOD, and then amplify the signal through the amplifier AMP3, then send it to the channel 1 and channel 2 through the DIV for sub-channel extraction. And processing.
  • FIG. 10 is a flowchart of a system process according to a preferred embodiment of the present invention.
  • a signal that is stable and completed by the system is subjected to open-loop calibration, a LUT (Look-Up-Table), and then an auxiliary transmission is started.
  • the signal outputs a scaling signal such that the signal falls into the multi-channel receiving common portion.
  • the two receivers respectively receive the common part, and after receiving the relevant processing, determine the delay.
  • the equalizer ensures that the amplitude-frequency characteristics of each receiving channel are the same, the amplitude of the receiving channel is scaled and the splicing relationship is determined, and then the signal is processed. Item predistortion.
  • the equalizer of the channel is ensured to ensure that the amplitude-frequency characteristics of each receiving channel are the same.
  • the transmitting signal is sent through the transmitting calibration channel, the receiving channel receives, the received signal is compared with the transmitted signal, and the error of the receiving equalizer is corrected by the error amount of the two, and the process is repeated until the error converges to the requirement.
  • the value is used to determine the final factor.
  • the transmit auxiliary signal can be turned off to enter normal operation. Then, through timing or status monitoring, it is judged whether recalibration is needed. If not, go directly to the normal working mode. If yes, continue to output the calibration signal from the transmitted signal, so that the signal falls into the multi-channel receiving common part.
  • the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, by hardware, but in many cases, the former is A better implementation.
  • the technical solution of the present invention which is essential or contributes to the prior art, may be embodied in the form of a software product stored in a storage medium (such as ROM/RAM, disk,
  • the optical disc includes a number of instructions for causing a terminal device (which may be a cell phone, a computer, a server, or a network device, etc.) to perform the methods described in various embodiments of the present invention.
  • Embodiments of the present invention also provide a storage medium.
  • the foregoing storage medium may be configured to store program code for performing the method steps of the above embodiment:
  • the foregoing storage medium may include, but not limited to, a USB flash drive, a Read-Only Memory (ROM), a Random Access Memory (RAM), a mobile hard disk, and a magnetic memory.
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • a mobile hard disk e.g., a hard disk
  • magnetic memory e.g., a hard disk
  • the processor executes the method steps of the foregoing embodiment according to the stored program code in the storage medium.
  • modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein.
  • the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.
  • multiple signals of different preset gains in multiple channels are acquired, wherein the size of the preset gain is inversely proportional to the amplitude of the channel received signal, and the multiple The common receiving amplitude of the channel is aligned with the plurality of signal delays, and the amplitudes of the plurality of signals of the different preset gains are aligned and spliced to obtain an output signal of the plurality of signals, and the receiver is solved.
  • the power of the received signal is too large, it is easy to generate nonlinearity, reduce the signal-to-noise ratio, affect the subsequent demodulation problem, and achieve distortion-free reception of large dynamic signals.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Amplifiers (AREA)

Abstract

La présente invention concerne un procédé et un appareil de réception de signal. Le procédé comprend les étapes consistant à : acquérir une pluralité de signaux ayant différents gains pré-établis dans une pluralité de canaux, les grandeurs des gains pré-établis étant inversement proportionnelles aux amplitudes de signal reçues des canaux ; aligner les retards de la pluralité de signaux à l'aide d'une amplitude reçue commune de la pluralité de canaux ; et exécuter une association alignée en fonction des amplitudes de la pluralité de signaux ayant différents gains pré-établis, de manière à obtenir un signal de sortie après que la pluralité de signaux est associée. Les problèmes de non-linéarité, de réduction d'un rapport signal sur bruit et de l'influence sur une démodulation ultérieure, lorsque la puissance de signal reçue d'un récepteur est trop élevée, sont résolus, et la réception sans distorsion d'un large signal dynamique est obtenue.
PCT/CN2015/092324 2015-07-07 2015-10-20 Procédé et appareil de réception de signal WO2017004910A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510395307.0A CN106341145B (zh) 2015-07-07 2015-07-07 信号的接收方法及装置
CN201510395307.0 2015-07-07

Publications (1)

Publication Number Publication Date
WO2017004910A1 true WO2017004910A1 (fr) 2017-01-12

Family

ID=57684798

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/092324 WO2017004910A1 (fr) 2015-07-07 2015-10-20 Procédé et appareil de réception de signal

Country Status (2)

Country Link
CN (1) CN106341145B (fr)
WO (1) WO2017004910A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111162809B (zh) * 2019-12-13 2022-04-15 西安易朴通讯技术有限公司 无线接收机及无线设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101247154A (zh) * 2008-03-20 2008-08-20 中兴通讯股份有限公司 实现削峰和数字预失真相互补偿的系统及方法
CN104486273A (zh) * 2014-12-11 2015-04-01 中国传媒大学 一种自适应直接正交变频调制误差校正方法
CN104506259A (zh) * 2014-12-30 2015-04-08 西安交通大学 宽带多天线通信系统接收通道间的时延差估计及校正方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7515888B2 (en) * 2005-10-06 2009-04-07 Nxp B.V. Systems and method for a highly integrated, multi-mode tuner
JP2008017009A (ja) * 2006-07-04 2008-01-24 Nec Corp 無線基地局及びこれを用いた送信電力制御方法
CN103595445B (zh) * 2010-03-10 2015-04-08 青岛东软载波科技股份有限公司 解调信号的增益控制方法、装置以及微控制器
CN102195681B (zh) * 2010-03-10 2014-03-19 青岛东软载波科技股份有限公司 解调信号的增益控制方法、装置以及微控制器
CN103118426B (zh) * 2011-11-17 2016-03-16 京信通信系统（中国）有限公司 宽带多通道功率控制方法及装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101247154A (zh) * 2008-03-20 2008-08-20 中兴通讯股份有限公司 实现削峰和数字预失真相互补偿的系统及方法
CN104486273A (zh) * 2014-12-11 2015-04-01 中国传媒大学 一种自适应直接正交变频调制误差校正方法
CN104506259A (zh) * 2014-12-30 2015-04-08 西安交通大学 宽带多天线通信系统接收通道间的时延差估计及校正方法

Also Published As

Publication number Publication date
CN106341145B (zh) 2020-04-21
CN106341145A (zh) 2017-01-18

Similar Documents

Publication Publication Date Title
CN102195567B (zh) 功率放大器线性化反馈方法和系统
DE102004005130B3 (de) Sende-/Empfangsanordnung und Verfahren zur Reduktion von Nichtlinearitäten in Ausgangssignalen einer Sende-/Empfangsanordnung
EP3211716B1 (fr) Procédé et appareil d'étalonnage de phase
WO2017186116A1 (fr) Émetteur et procédé de traitement de signal pour celui-ci
US10615827B2 (en) Local oscillator feedthrough signal correction apparatus and method, and microprocessor control unit
CN102281113B (zh) 通信中继装置及其驻波比检测装置和方法
US9537584B2 (en) Phased array device and calibration method therefor
CA2566644A1 (fr) Amplificateur de reseau cellulaire a gain variable commande par processeur
CN103765783A (zh) 用于多天线发射机中的发射机畸变校准的自适应干扰消除
CN102771053B (zh) 通信校正装置及方法
JP2009182441A (ja) 通信装置およびキャリブレーション方法
KR101603144B1 (ko) 아날로그 디지털 컨버터의 포화를 방지하기 위한 디지털 수신기
US20190013882A1 (en) Remote apparatus of distributed antenna system
CN103516322A (zh) 自动增益控制装置、自动增益控制的增益设定方法、无线通信收发器
US10637158B2 (en) Phased array calibration method and phased array calibration circuit
US8310304B1 (en) Power amplifier control system with gain calibration
US8903346B2 (en) External mounted amplifiers with active interference cancelation using diversity antennas
EP2738938B1 (fr) Système audio
WO2017004910A1 (fr) Procédé et appareil de réception de signal
CN111049487B (zh) 自动增益控制电路及控制方法
KR102005899B1 (ko) 신호 처리 장치
JP4063612B2 (ja) 送信機
EP2621086A2 (fr) Commande de gain automatique rapide
CN103873005B (zh) 射频信号源及其工作方法
KR102005898B1 (ko) 신호 처리 장치

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15897566

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15897566

Country of ref document: EP

Kind code of ref document: A1