WO2017004856A1 - 显示面板和用于显示面板的像素电路 - Google Patents

显示面板和用于显示面板的像素电路 Download PDF

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Publication number
WO2017004856A1
WO2017004856A1 PCT/CN2015/085342 CN2015085342W WO2017004856A1 WO 2017004856 A1 WO2017004856 A1 WO 2017004856A1 CN 2015085342 W CN2015085342 W CN 2015085342W WO 2017004856 A1 WO2017004856 A1 WO 2017004856A1
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Prior art keywords
pixel unit
color sub
capacitance value
liquid crystal
pixel
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English (en)
French (fr)
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陈彩琴
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of display panels, and more particularly to a display panel having a special pixel circuit.
  • FIG. 1 shows a schematic diagram of a display panel 100 in the prior art.
  • the display panel 100 includes a plurality of scan lines (gate Line)102s and several data lines (data Line) 102d, a plurality of scan lines 102s and a plurality of data lines 102d are interleaved to form a plurality of pixel units 104.
  • Each of the pixel units 104 includes three sub-pixel units 106 (a red sub-pixel unit R, a green sub-pixel unit G, and a blue sub-pixel unit B), each of the sub-pixel units 106 is provided with a thin film transistor 110 and the thin film transistor 110 is connected Pixel electrode 108.
  • each sub-pixel unit 106 is controlled by one scan line 102s and one data line 102d. That is, when the resolution of the display panel 100 is MxN, the display panel 100 must be provided with M strips. Scan line 102s and 3N data lines 102d. However, for a small-sized display panel, in order to increase the resolution of the display panel, a design in which a plurality of demultiplexers (demux) are connected to the data driver is employed to increase the number of pixel units in a limited space. .
  • the display panel 200 includes a data driver 210, a gate driver 220, a demultiplexer unit 230, and a pixel circuit 240.
  • the demultiplexer unit 230 has a plurality of demultiplexers 232, and the data driver 210 transmits drive signals to each demultiplexer through a plurality of main data lines (Dn, Dn+1...) 212, respectively. 232.
  • the demultiplexer 232 includes a first switch SW1, a second switch SW2, and a third switch SW3 for respectively responding to a first control signal Remux(R) and a second control signal Remux(G) input from the outside thereof And a third control signal Remux(B), and sequentially apply the driving signals received from the corresponding main data lines 212 to the three sub-data lines (S1, S2, S3) 234.
  • the pixel circuit 240 includes the plurality of sub-data lines 234 and a plurality of scan lines (Gn, Gn+1...) 222 connected to the gate driver 220.
  • the plurality of sub-data lines 234 and the plurality of scan lines 222 are interleaved to define a plurality of pixel units 242, and each of the pixel units 242 includes a red sub-pixel unit R and a green sub-pixel unit G arranged in sequence. And blue sub-pixel unit B.
  • the driving signal is transmitted from the secondary data line S1, the secondary data line S2, and the secondary data line S3 to the red sub-pixel unit R, the green sub-pixel unit G, and the blue sub-pixel unit B, respectively. .
  • the red sub-pixel unit R includes a first liquid crystal capacitor C(R)1 and a first storage capacitor C(R)2, and the green sub-pixel unit G includes a second liquid crystal capacitor C(G). 1 and the second storage capacitor C(G) 2, and the blue sub-pixel unit B includes a third liquid crystal capacitor C(B)1 and a third storage capacitor C(B)2.
  • the first liquid crystal capacitor C(R)1 of the red sub-pixel unit R is equal to the second liquid crystal capacitor C(G)1 of the green sub-pixel unit G and is equivalent to The third liquid crystal capacitor C(B)1 of the blue sub-pixel unit B is described.
  • the first storage capacitor C(R) 2 of the green sub-pixel unit G is equal to the second storage capacitor C(G) 2 of the green sub-pixel unit G and is equal to the blue The third storage capacitor C(B)2 of the sub-pixel unit B.
  • FIG. 3 shows a driving waveform diagram of the display panel 200 shown in FIG. 2.
  • the first switch SW1, the second switch SW2, and the first portion of the demultiplexer 232 The three switch SW3 is sequentially driven by the first control signal Remux (R), the second control signal Remux (G), and the third control signal Remux (B), and is corresponding to the secondary data Line 234 applies the drive signal input through the main data line 212.
  • the red sub-pixel unit R of the pixel circuit 240 is charged first.
  • a main object of the present invention is to provide a display panel and a pixel circuit for the display panel, by using a liquid crystal capacitor in a specific color sub-pixel unit in the pixel circuit of the display panel Or the capacitance value of the storage capacitor is set to be different from the capacitance value of the liquid crystal capacitor or the storage capacitor in the other color sub-pixel unit to compensate for the electrical property of the specific color sub-pixel unit, thereby improving the The difference in charging causes the screen of the display panel to exhibit color shift and color unevenness.
  • the present invention provides a pixel circuit for a display panel, comprising: a plurality of scan lines; a plurality of sub-data lines interlaced with the plurality of scan lines; and a plurality of pixel units, each The pixel unit at least includes: a first color sub-pixel unit and a second color sub-pixel unit, wherein the first color sub-pixel unit and the second color sub-pixel unit are electrically connected to the plurality of scans a first scan line in the line, and electrically connected to a first data line and a second time data line consecutively arranged in the plurality of sub data lines, wherein the first color sub-pixel unit comprises a first The liquid crystal capacitor and a first storage capacitor, and the second color sub-pixel unit includes a second liquid crystal capacitor and a second storage capacitor.
  • the capacitance value of the first liquid crystal capacitor of the first color sub-pixel unit is not equal to the capacitance value of the second liquid crystal capacitor of the second color sub-pixel unit, or the first color sub-pixel unit
  • the capacitance value of the first storage capacitor is not equal to the capacitance value of the second storage capacitor of the second color sub-pixel unit.
  • the first color sub-pixel unit When the capacitance value of the first storage capacitor of the first color sub-pixel unit is smaller than the capacitance value of the second storage capacitor of the second color sub-pixel unit, the first color sub-pixel unit
  • the capacitance value of the first liquid crystal capacitor is equal to the capacitance value of the second liquid crystal capacitor of the second color sub-pixel unit.
  • driving timing of the first color sub-pixel unit is earlier than driving timing of the second color sub-pixel unit.
  • the present invention also provides a pixel circuit for a display panel, the pixel circuit comprising: a plurality of scan lines; a plurality of sub-data lines interlaced with the plurality of scan lines; and a plurality of pixel units, each The pixel unit at least includes: a first color sub-pixel unit and a second color sub-pixel unit, wherein the first color sub-pixel unit and the second color sub-pixel unit are electrically connected to the plurality of scans a first scan line in the line, and electrically connected to a first data line and a second time data line consecutively arranged in the plurality of sub data lines, wherein the first color sub-pixel unit comprises a first a liquid crystal capacitor and a first storage capacitor, and the second color sub-pixel unit includes a second liquid crystal capacitor and a second storage capacitor; wherein a capacitance value of the first liquid crystal capacitor of the first color sub-pixel unit The capacitance value of the second liquid crystal capacitor of the second color sub-pixel unit is not equal, or the capacitance value of
  • a capacitance value of the first liquid crystal capacitor of the first color sub-pixel unit is greater than a capacitance value of the second liquid crystal capacitor of the second color sub-pixel unit.
  • a capacitance value of the first storage capacitor of the first color sub-pixel unit is equal to a capacitance value of the second storage capacitor of the second color sub-pixel unit.
  • a capacitance value of the first storage capacitor of the first color sub-pixel unit is smaller than a capacitance value of the second storage capacitor of the second color sub-pixel unit.
  • a capacitance value of the first liquid crystal capacitor of the first color sub-pixel unit is equal to a capacitance value of the second liquid crystal capacitor of the second color sub-pixel unit.
  • the driving timing of the first color sub-pixel unit is earlier than the driving timing of the second color sub-pixel unit.
  • each of the pixel units of the pixel circuit further includes a third color sub-pixel unit, the third color sub-pixel unit and the first color sub-pixel unit
  • the second color sub-pixel unit is electrically connected to the same one of the plurality of scan lines
  • the third color sub-pixel unit is further electrically connected to a first one after the second data line a third data line
  • the third color sub-pixel unit includes a third liquid crystal capacitor and a third storage capacitor, wherein a capacitance value of the first liquid crystal capacitor of the first color sub-pixel unit and the third The capacitance values of the third liquid crystal capacitors of the color sub-pixel unit are not equal, or the capacitance value of the first storage capacitor of the first color sub-pixel unit and the third value of the third color sub-pixel unit The capacitance values of the storage capacitors are not equal.
  • the capacitance value of the first liquid crystal capacitor of the first color sub-pixel unit is greater than the capacitance value of the third liquid crystal capacitor of the third color sub-pixel unit, and The capacitance value of the second liquid crystal capacitor of the second color sub-pixel unit is equal to the capacitance value of the third liquid crystal capacitor of the third color sub-pixel unit.
  • a capacitance value of the first storage capacitor of the first color sub-pixel unit is smaller than a capacitance value of the third storage capacitor of the third color sub-pixel unit, and The capacitance value of the second storage capacitor of the second color sub-pixel unit is equal to the capacitance value of the third storage capacitor of the third color sub-pixel unit.
  • the present invention further provides a display panel, the display panel comprising: a pixel circuit comprising: a plurality of scan lines; a plurality of sub-data lines interlaced with the plurality of scan lines; and a plurality of pixel units, each The pixel unit includes at least: a first color sub-pixel unit and a second color sub-pixel unit, wherein the first color sub-pixel unit and the second color sub-pixel unit are electrically connected to the plurality of scan lines The same scanning line is electrically connected to a first data line and a second time data line which are consecutively arranged in the plurality of secondary data lines, wherein the first color sub-pixel unit comprises a first liquid crystal capacitor And a first storage capacitor, and the second color sub-pixel unit comprises a second liquid crystal capacitor and a second storage capacitor; a data driver connected to the plurality of main data lines for transmitting a plurality of data driving signals; a gate driver connected to the plurality of scan lines for transmitting a plurality of gate drive signals; and a demultiplexer
  • a capacitance value of the first liquid crystal capacitor of the first color sub-pixel unit is greater than a capacitance value of the second liquid crystal capacitor of the second color sub-pixel unit.
  • a capacitance value of the first storage capacitor of the first color sub-pixel unit is equal to a capacitance value of the second storage capacitor of the second color sub-pixel unit.
  • a capacitance value of the first storage capacitor of the first color sub-pixel unit is smaller than a capacitance value of the second storage capacitor of the second color sub-pixel unit.
  • a capacitance value of the first liquid crystal capacitor of the first color sub-pixel unit is equal to a capacitance value of the second liquid crystal capacitor of the second color sub-pixel unit.
  • the demultiplexer sequentially inputs the corresponding data driving signal into the first color sub-pixel unit and the second color in response to the plurality of control signals
  • the sub-pixel unit is such that a driving timing of the first color sub-pixel unit is earlier than a driving timing of the second color sub-pixel unit.
  • each of the pixel units of the pixel circuit further includes a third color sub-pixel unit, the third color sub-pixel unit and the first color sub-pixel unit
  • the second color sub-pixel unit is electrically connected to the same one of the plurality of scan lines, and the third color sub-pixel unit is further electrically connected to a first one after the second data line a third data line
  • the third color sub-pixel unit includes a third liquid crystal capacitor and a third storage capacitor, and a capacitance value of the first liquid crystal capacitor of the first color sub-pixel unit and the third color
  • the capacitance values of the third liquid crystal capacitors of the sub-pixel unit are not equal, or the capacitance value of the first storage capacitor of the first color sub-pixel unit and the third storage of the third color sub-pixel unit The capacitance values of the capacitors are not equal.
  • the capacitance value of the first liquid crystal capacitor of the first color sub-pixel unit is greater than the capacitance value of the third liquid crystal capacitor of the third color sub-pixel unit, and The capacitance value of the second liquid crystal capacitor of the second color sub-pixel unit is equal to the capacitance value of the third liquid crystal capacitor of the third color sub-pixel unit.
  • a capacitance value of the first storage capacitor of the first color sub-pixel unit is smaller than a capacitance value of the third storage capacitor of the third color sub-pixel unit, and The capacitance value of the second storage capacitor of the second color sub-pixel unit is equal to the capacitance value of the third storage capacitor of the third color sub-pixel unit.
  • a main object of the present invention is to provide a display panel and a pixel circuit for a display panel, by setting a capacitance value of a liquid crystal capacitor or a storage capacitor in a specific color sub-pixel unit in a pixel circuit of the display panel to a phase Different from the capacitance value of the liquid crystal capacitor or the storage capacitor in the other color sub-pixel unit to compensate for the electrical properties of the specific color sub-pixel unit, thereby improving the display panel due to the difference in charging between the plurality of color sub-pixel units
  • the picture shows the phenomenon of color shift and uneven color.
  • Figure 1 shows a schematic view of a prior art display panel
  • FIG. 2 shows a schematic diagram of a display panel having a demultiplexer unit in the prior art
  • FIG. 3 is a diagram showing driving waveforms of the display panel shown in FIG. 2;
  • Figure 4 shows a schematic view of a display panel in accordance with the present invention
  • FIG. 5 is a schematic diagram showing a pixel unit of a pixel circuit in the display panel shown in FIG.
  • the display panel 300 includes a data driver 310, a gate driver 320, a demultiplexer unit 330, and a pixel circuit 340.
  • the data driver 310 is coupled to a plurality of main data lines (Dn, Dn+1...) 312 for communicating a plurality of data drive signals to the demultiplexer unit 330.
  • the gate driver 320 is coupled to a plurality of scan lines (Gn, Gn+1%) 322 for transmitting a plurality of gate drive signals.
  • the demultiplexer unit 330 includes a plurality of demultiplexers 332, and the data driver 310 transmits the data driving signals to each solution through a plurality of main data lines (Dn, Dn+1...) 312, respectively.
  • Multiplexer 332 The demultiplexer 332 includes a first switch SW1, a second switch SW2, and a third switch SW3 for respectively responding to a first control signal Remux(R) and a second control signal Remux(G) input from the outside thereof And a third control signal Remux(B), and sequentially applying the data driving signals received from the corresponding main data lines 312 to the three sub-data lines (S1, S2, S3) 334.
  • the pixel circuit 340 includes the plurality of scan lines 322, the plurality of sub-data lines 332, and a plurality of pixel units 342, and the plurality of scan lines 322 and the plurality of sub-data Lines 332 are interleaved to define the plurality of pixel units 342.
  • Each of the pixel units 342 includes a red sub-pixel unit R, a green sub-pixel unit G, and a blue sub-pixel unit B that are sequentially arranged.
  • the red sub-pixel unit R, the green sub-pixel unit G, and the blue sub-pixel unit B are electrically connected to the same scan line 322 of the plurality of scan lines 322, and are electrically connected to the respective a first data line, a second time data line, and a third time data line continuously arranged in the plurality of secondary data lines, for example, the successively arranged secondary data lines S1, the secondary data lines S2, and the secondary data lines S3.
  • the pixel unit 342 of the pixel circuit 340 drives the timing: first, driving the red sub-pixel unit R, then driving the green sub-pixel unit G, and finally, driving the blue Chromatographic pixel unit B.
  • each demultiplexer 332 of the demultiplexer unit 330 sequentially sequentially goes to three sub-data lines (S1, S2, S3). 334 applies the data drive signal.
  • each demultiplexer sequentially applies the data driving signals to the four sub-data lines, and so on, and details are not described herein.
  • the red sub-pixel unit R of the pixel unit 342 of the pixel circuit 340 includes a first pixel electrode 3422, a first liquid crystal capacitor C(R) 1, and a first storage capacitor C.
  • the green sub-pixel unit G includes a second pixel electrode 3424, a second liquid crystal capacitor C(G)1, and a second storage capacitor C(G)2
  • the blue sub-pixel unit B includes The third pixel electrode 3426, the third liquid crystal capacitor C(B)1, and the third storage capacitor C(B)2.
  • the first liquid crystal capacitor C(R)1 and the first storage capacitor C(R)2 pass through the first thin film transistor 3422, the second liquid crystal capacitor C(G)1, and the second storage capacitor C(G)2 is electrically connected to the third thin film transistor 3426 through the second thin film transistor 3424, and the third liquid crystal capacitor C(G)1 and the third storage capacitor C(G)2
  • the first liquid crystal capacitor C(R)1 in the red sub-pixel unit R of the pixel unit 342 of the pixel circuit 340 The capacitance value is greater than a capacitance value of the second liquid crystal capacitor C(G)1 in the green sub-pixel unit G, and larger than the third liquid crystal capacitance C(B) in the blue sub-pixel unit B.
  • the capacitance value of the second liquid crystal capacitor C(G)1 in the green sub-pixel unit G is equal to the capacitance value of the third liquid crystal capacitor C(B)1 in the blue sub-pixel unit B. .
  • the capacitance value of the first storage capacitor C(R)2 in the red sub-pixel unit R of the pixel unit 342 of the pixel circuit 340 is equal to the value in the green sub-pixel unit G.
  • the capacitance value of the second storage capacitor C(G)2 and the capacitance value of the third storage capacitor C(B)2 in the blue sub-pixel unit B is equal to the value in the green sub-pixel unit G.
  • the capacitance value of the first liquid crystal capacitor C(R)1 in the red sub-pixel unit R of the pixel unit 342 of the pixel circuit 340 is set to be larger than other colors.
  • a capacitance value of a plurality of liquid crystal capacitors in the sub-pixel unit such that when the red sub-pixel unit R, the green sub-pixel unit G, and the blue sub-pixel unit B are sequentially driven, the red sub-pixel
  • the holding voltages of the unit R, the green sub-pixel unit G, and the blue sub-pixel unit B are the same, thereby improving the RC due to RC.
  • the effect of the delay is such that the charging effect of the red sub-pixel unit R is smaller than that of the green sub-pixel unit G and the blue sub-pixel unit B, causing the screen of the display panel 300 to exhibit color shift and color unevenness. phenomenon.
  • the capacitance value of the first storage capacitor C(R)2 in the red sub-pixel unit R of the pixel unit 342 of the pixel circuit 340 is smaller than the green color.
  • the capacitance value of the second storage capacitor C(G)2 in the green sub-pixel unit G is equal to the capacitance value of the third storage capacitor C(B)2 in the blue sub-pixel unit B. .
  • the capacitance value of the first liquid crystal capacitor C(R)1 in the red sub-pixel unit R of the pixel unit 342 of the pixel circuit 340 is equal to the value in the green sub-pixel unit G.
  • the capacitance value of the first storage capacitor C(R) 2 in the red sub-pixel unit R of the pixel unit 342 of the pixel circuit 340 is set to be smaller than other colors.
  • a capacitance value of a plurality of storage capacitors within the sub-pixel unit such that when the red sub-pixel unit R, the green sub-pixel unit G, and the blue sub-pixel unit B are sequentially driven, the red sub-pixel
  • the holding voltages of the unit R, the green sub-pixel unit G, and the blue sub-pixel unit B are the same, thereby improving the RC due to RC.
  • the effect of the delay is such that the charging effect of the red sub-pixel unit R is smaller than that of the green sub-pixel unit G and the blue sub-pixel unit B, causing the screen of the display panel 300 to exhibit color shift and color unevenness. phenomenon.

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Abstract

提供了一种用于显示面板（300）以及该显示面板（300）所使用的像素电路（340），该像素电路（340）包含多条扫描线（322）、与其相互交错配置的多条次数据线（332）和多个像素单元（342）；每一像素单元（342）至少包含一第一颜色子像素单元和一第二颜色子像素单元，所述第一颜色子像素单元和所述第二颜色子像素单元电性连接至所述多条扫描线（322）中的同一扫描线，且分别电性连接至所述多条次数据线（332）中连续排列的一第一次数据线和一第二次数据线；第一颜色子像素单元的第一液晶电容的电容值与第二颜色子像素单元的第二液晶电容的电容值不相等，或者第一颜色子像素单元的第一存储电容的电容值与第二颜色子像素单元的第二存储电容的电容值不相等，以补偿特定颜色子像素单元的电性，进而改善由于若干颜色子像素单元之间的充电差异而造成所述显示面板（300）的画面呈现色偏和颜色不均匀的现象。

Description

显示面板和用于显示面板的像素电路 技术领域
本发明涉及显示面板领域，特别是涉及一种具有特殊像素电路的显示面板。
背景技术
请参照图1，其显示一种现有技术中显示面板100的示意图。所述显示面板100包括若干条扫描线(gate line)102s以及若干数据线(data line）102d，若干条扫描线102s以及若干条数据线102d互相交错以形成多个像素单元104。每一像素单元104包括三个子像素单元106(红色子像素单元R、绿色子像素单元G、蓝色子像素单元B)，每一子像素单元106设有一薄膜晶体管110以及连接所述薄膜晶体管110的像素电极108。
如图1所示，每一子像素单元106是由一条扫描线102s和一条数据线102d控制，即，当所述显示面板100的分辨率为MxN时，所述显示面板100必须设置有M条的扫描线102s和3N条的数据线102d。然而，对于小尺寸的显示面板而言，为了提升显示面板的分辨率，会采用将多个解复用器(demux)与数据驱动器相连接的设计，以在有限的空间中增加像素单元的数量。
请参照图2，其显示一种现有技术中具有解复用器单元230的显示面板200的示意图。所述显示面板200包含数据驱动器210、闸极驱动器220、解复用器单元230、和像素电路240。所述解复用器单元230具有多个解复用器232，且所述数据驱动器210通过多条主数据线(Dn、Dn+1…)212将驱动信号分别传递至每一解复用器232。所述解复用器232包括第一开关SW1、第二开关SW2、和第三开关SW3，用于分别响应从其外部输入的第一控制信号Remux(R)、第二控制信号Remux(G)、和第三控制信号Remux(B)，并且依序地向三条次数据线(S1、S2、S3)234施加从相应的主数据线212接收的所述驱动信号。
如图2所示，所述像素电路240包含所述多条次数据线234与多条和所述闸极驱动器220连接的扫描线(Gn、Gn+1…)222。所述多条次数据线234与所述多条扫描线222互相交错以界定多个像素单元242，每一所述像素单元242包含依序排列的红色子像素单元R、绿色子像素单元G、和蓝色子像素单元B。所述驱动信号由所述次数据线S1、次数据线S2、和次数据线S3分别传递至所述红色子像素单元R、所述绿色子像素单元G、和所述蓝色子像素单元B。
如图2所示，所述红色子像素单元R包含第一液晶电容C(R)1和第一存储电容C(R)2、所述绿色子像素单元G包含第二液晶电容C(G)1和第二存储电容C(G)2、以及所述蓝色子像素单元B包含第三液晶电容C(B)1和第三存储电容C(B)2。在现有技术中，所述红色子像素单元R的所述第一液晶电容C(R)1相等于所述绿色子像素单元G的所述第二液晶电容C(G)1且相等于所述蓝色子像素单元B的所述第三液晶电容C(B)1。同样地，所述绿色子像素单元G的所述第一存储电容C(R)2相等于所述绿色子像素单元G的所述第二存储电容C(G)2且相等于所述蓝色子像素单元B的所述第三存储电容C(B)2。
请参照图3，其显示图2所示的显示面板200的驱动波形图。当使用点反转的驱动方式驱动所述显示面板200或者是在重载图案的情况下，所述解复用器232的所述第一开关SW1、所述第二开关SW2、和所述第三开关SW3被所述第一控制信号Remux(R)、所述第二控制信号Remux(G)、和所述第三控制信号Remux(B)依序地驱动，并且向对应的所述次数据线234施加通过所述主数据线212输入的所述驱动信号。如图3所示，在所述显示面板200中，所述像素电路240的所述红色子像素单元R会先充电。然而，由于阻容迟滞现象(RC delay)的影响，使得所述红色子像素单元R的充电效果不如所述绿色子像素单元G和所述蓝色子像素单元B的充电效果。因此，当所述显示面板200显示画面时，原本纯白的画面会呈现偏青色。
有鉴于此，有必要提出一种显示面板，其能改善由于若干颜色子像素单元之间的充电差异而造成显示面板的画面呈现色偏和颜色不均匀的现象。
 技术问题
为解决上述现有技术的问题，本发明的主要目的在于提供一种显示面板和用于显示面板的像素电路，藉由将所述显示面板的像素电路中特定一颜色子像素单元内的液晶电容或存储电容的电容值设置为相异于其他颜色子像素单元内的液晶电容或存储电容的电容值，以补偿所述特定颜色子像素单元的电性，进而改善由于若干颜色子像素单元之间的充电差异而造成所述显示面板的画面呈现色偏和颜色不均匀的现象。
 技术解决方案
为了实现上述目的，本发明提供了一种用于显示面板的像素电路，包含：多条扫描线；多条次数据线，与所述多条扫描线相互交错配置；以及多个像素单元，每一所述像素单元至少包含：一第一颜色子像素单元和一第二颜色子像素单元，所述第一颜色子像素单元和所述第二颜色子像素单元电性连接至所述多条扫描线中的同一扫描线，且分别电性连接至所述多条次数据线中连续排列的一第一次数据线和一第二次数据线，所述第一颜色子像素单元包含一第一液晶电容和一第一存储电容，以及所述第二颜色子像素单元包含一第二液晶电容和一第二存储电容。所述第一颜色子像素单元的所述第一液晶电容的电容值与所述第二颜色子像素单元的所述第二液晶电容的电容值不相等，或者所述第一颜色子像素单元的所述第一存储电容的电容值与所述第二颜色子像素单元的所述第二存储电容的电容值不相等。当所述第一颜色子像素单元的所述第一液晶电容的电容值大于所述第二颜色子像素单元的所述第二液晶电容的电容值时，所述第一颜色子像素单元的所述第一存储电容的电容值等于所述第二颜色子像素单元的所述第二存储电容的电容值。当所述第一颜色子像素单元的所述第一存储电容的电容值小于所述第二颜色子像素单元的所述第二存储电容的电容值时，所述第一颜色子像素单元的所述第一液晶电容的电容值等于所述第二颜色子像素单元的所述第二液晶电容的电容值。以及所述第一颜色子像素单元的驱动时序早于所述第二颜色子像素单元的驱动时序。
本发明还提供了一种用于显示面板的像素电路，所述像素电路包含：多条扫描线；多条次数据线，与所述多条扫描线相互交错配置；以及多个像素单元，每一所述像素单元至少包含：一第一颜色子像素单元和一第二颜色子像素单元，所述第一颜色子像素单元和所述第二颜色子像素单元电性连接至所述多条扫描线中的同一扫描线，且分别电性连接至所述多条次数据线中连续排列的一第一次数据线和一第二次数据线，所述第一颜色子像素单元包含一第一液晶电容和一第一存储电容，以及所述第二颜色子像素单元包含一第二液晶电容和一第二存储电容；其中所述第一颜色子像素单元的所述第一液晶电容的电容值与所述第二颜色子像素单元的所述第二液晶电容的电容值不相等，或者所述第一颜色子像素单元的所述第一存储电容的电容值与所述第二颜色子像素单元的所述第二存储电容的电容值不相等。
在本发明的一优选实施例中，所述第一颜色子像素单元的所述第一液晶电容的电容值大于所述第二颜色子像素单元的所述第二液晶电容的电容值。
在本发明的一优选实施例中，所述第一颜色子像素单元的所述第一存储电容的电容值等于所述第二颜色子像素单元的所述第二存储电容的电容值。
在本发明的一优选实施例中，所述第一颜色子像素单元的所述第一存储电容的电容值小于所述第二颜色子像素单元的所述第二存储电容的电容值。
在本发明的一优选实施例中，所述第一颜色子像素单元的所述第一液晶电容的电容值等于所述第二颜色子像素单元的所述第二液晶电容的电容值。
在本发明的一优选实施例中，所述第一颜色子像素单元的驱动时序早于所述第二颜色子像素单元的驱动时序。
在本发明的一优选实施例中，所述像素电路的每一所述像素单元还包含一第三颜色子像素单元，所述第三颜色子像素单元与所述第一颜色子像素单元和所述第二颜色子像素单元电性连接至所述多条扫描线中的同一扫描线，且所述第三颜色子像素单元还电性连接至排列于所述第二次数据线之后的一第三次数据线，所述第三颜色子像素单元包含一第三液晶电容和一第三存储电容，其中所述第一颜色子像素单元的所述第一液晶电容的电容值与所述第三颜色子像素单元的所述第三液晶电容的电容值不相等，或者所述第一颜色子像素单元的所述第一存储电容的电容值与所述第三颜色子像素单元的所述第三存储电容的电容值不相等。
在本发明的一优选实施例中，所述第一颜色子像素单元的所述第一液晶电容的电容值大于所述第三颜色子像素单元的所述第三液晶电容的电容值，以及所述第二颜色子像素单元的所述第二液晶电容的电容值等于所述第三颜色子像素单元的所述第三液晶电容的电容值。
在本发明的一优选实施例中，所述第一颜色子像素单元的所述第一存储电容的电容值小于所述第三颜色子像素单元的所述第三存储电容的电容值，以及所述第二颜色子像素单元的所述第二存储电容的电容值等于所述第三颜色子像素单元的所述第三存储电容的电容值。
本发明还提供一种显示面板，所述显示面板包含：一像素电路包含：多条扫描线；多条次数据线与所述多条扫描线相互交错设置；以及多个像素单元，每一所述像素单元至少包含：一第一颜色子像素单元和一第二颜色子像素单元，所述第一颜色子像素单元和所述第二颜色子像素单元电性连接至所述多条扫描线中的同一扫描线，且分别电性连接至所述多条次数据线中连续排列的一第一次数据线和一第二次数据线，所述第一颜色子像素单元包含一第一液晶电容和一第一存储电容，以及所述第二颜色子像素单元包含一第二液晶电容和一第二存储电容；一数据驱动器，与多条主数据线相连接用于传递多个数据驱动信号；一闸极驱动器，与所述多条扫描线相连接用于传递多个闸极驱动信号；以及一解复用器单元，包含多个解复用器，其中之一解复用器通过所述多条主数据线的其中之一与所述数据驱动器连接，并且用于分别响应从其外部输入的多个控制信号，依序地向所述第一次数据线和所述第二次数据线施加从相应的所述主数据线接收的所述数据驱动信号；其中所述第一颜色子像素单元的所述第一液晶电容的电容值与所述第二颜色子像素单元的所述第二液晶电容的电容值不相等，或者所述第一颜色子像素单元的所述第一存储电容的电容值与所述第二颜色子像素单元的所述第二存储电容的电容值不相等。
在本发明的一优选实施例中，所述第一颜色子像素单元的所述第一液晶电容的电容值大于所述第二颜色子像素单元的所述第二液晶电容的电容值。
在本发明的一优选实施例中，所述第一颜色子像素单元的所述第一存储电容的电容值等于所述第二颜色子像素单元的所述第二存储电容的电容值。
在本发明的一优选实施例中，所述第一颜色子像素单元的所述第一存储电容的电容值小于所述第二颜色子像素单元的所述第二存储电容的电容值。
在本发明的一优选实施例中，所述第一颜色子像素单元的所述第一液晶电容的电容值等于所述第二颜色子像素单元的所述第二液晶电容的电容值。
在本发明的一优选实施例中，所述解复用器响应所述多个控制信号依序地将相对应的所述数据驱动信号输入所述第一颜色子像素单元和所述第二颜色子像素单元，使得所述第一颜色子像素单元的驱动时序早于所述第二颜色子像素单元的驱动时序。
在本发明的一优选实施例中，所述像素电路的每一所述像素单元还包含一第三颜色子像素单元，所述第三颜色子像素单元与所述第一颜色子像素单元和所述第二颜色子像素单元电性连接至所述多条扫描线中的同一扫描线，且所述第三颜色子像素单元还电性连接至排列于所述第二次数据线之后的一第三次数据线；所述第三颜色子像素单元包含一第三液晶电容和一第三存储电容，所述第一颜色子像素单元的所述第一液晶电容的电容值与所述第三颜色子像素单元的所述第三液晶电容的电容值不相等，或者所述第一颜色子像素单元的所述第一存储电容的电容值与所述第三颜色子像素单元的所述第三存储电容的电容值不相等。
在本发明的一优选实施例中，所述第一颜色子像素单元的所述第一液晶电容的电容值大于所述第三颜色子像素单元的所述第三液晶电容的电容值，以及所述第二颜色子像素单元的所述第二液晶电容的电容值等于所述第三颜色子像素单元的所述第三液晶电容的电容值。
在本发明的一优选实施例中，所述第一颜色子像素单元的所述第一存储电容的电容值小于所述第三颜色子像素单元的所述第三存储电容的电容值，以及所述第二颜色子像素单元的所述第二存储电容的电容值等于所述第三颜色子像素单元的所述第三存储电容的电容值。
 有益效果
本发明的主要目的在于提供一种显示面板和用于显示面板的像素电路，藉由将所述显示面板的像素电路中特定一颜色子像素单元内的液晶电容或存储电容的电容值设置为相异于其他颜色子像素单元内的液晶电容或存储电容的电容值，以补偿所述特定颜色子像素单元的电性，进而改善由于若干颜色子像素单元之间的充电差异而造成所述显示面板的画面呈现色偏和颜色不均匀的现象。
 附图说明
图1显示一种现有技术中显示面板的示意图；
图2显示一种现有技术中具有解复用器单元的显示面板的示意图；
图3显示图2所示的显示面板的驱动波形图；
图4显示一种根据本发明的显示面板的示意图；
图5显示图4所示的显示面板中像素电路的像素单元的示意图。
 本发明的最佳实施方式
本发明的优选实施例配合附图与下面的说明作详细描述，在不同的图式中，相同的组件符号表示相同或相似的组件。
请参照图4，其显示一种根据本发明的显示面板300的示意图。所述显示面板300包含一数据驱动器310、一闸极驱动器320、一解复用器单元330、和一像素电路340。所述数据驱动器310与多条主数据线(Dn、Dn+1…)312相连接用于将多个数据驱动信号传递至所述解复用器单元330。所述闸极驱动器320与多条扫描线(Gn、Gn+1…)322相连接用于传递多个闸极驱动信号。所述解复用器单元330包含多个解复用器332，且所述数据驱动器310通过多条主数据线(Dn、Dn+1…)312将所述数据驱动信号分别传递至每一解复用器332。所述解复用器332包括第一开关SW1、第二开关SW2、和第三开关SW3，用于分别响应从其外部输入的第一控制信号Remux(R)、第二控制信号Remux(G)、和第三控制信号Remux(B)，并且依序地向三条次数据线(S1、S2、S3)334施加从相应的所述主数据线312接收的所述数据驱动信号。
如图4所示，所述像素电路340包含所述多条扫描线322、所述多条次数据线332和多个像素单元342，且所述多条扫描线322和所述多条次数据线332互相交错以界定所述多个像素单元342。每一所述像素单元342包含依序排列的红色子像素单元R、绿色子像素单元G、蓝色子像素单元B。所述红色子像素单元R、所述绿色子像素单元G、和所述蓝色子像素单元B电性连接至所述多条扫描线322中的同一扫描线322，且分别电性连接至所述多条次数据线中连续排列的一第一次数据线、一第二次数据线、和一第三次数据线，例如连续排列的次数据线S1、次数据线S2、和次数据线S3。在驱动所述显示面板300时，所述像素电路340的像素单元342驱动时序为：首先，驱动所述红色子像素单元R，接着，驱动所述绿色子像素单元G，最后，驱动所述蓝色子像素单元B。应当注意的是，在本实施例中所包含的颜色子像素单元的种类数量仅是作为示意，不局限于此。更详言之，在其他实施例中，可包含多于三种的颜色子像素单元。再者，由于在本实施例中包括三种颜色子像素单元，故所述解复用器单元330的每一解复用器332是依序地向三条次数据线(S1、S2、S3)334施加所述数据驱动信号。然而，在其他实施例中，当包含四种颜色子像素单元时，每一解复用器是依序地向四条次数据线施加术数据驱动信号，以此类推，在此不加以赘述。
请参照图5，其显示图4所示的显示面板300中像素电路340的像素单元342的示意图。在所述显示面板300中，所述像素电路340的所述像素单元342的所述红色子像素单元R包含第一像素电极3422、第一液晶电容C(R)1、和第一存储电容C(R)2、所述绿色子像素单元G包含第二像素电极3424、第二液晶电容C(G)1、和第二存储电容C(G)2、以及所述蓝色子像素单元B包含第三像素电极3426、第三液晶电容C(B)1、和第三存储电容C(B)2。所述第一液晶电容C(R)1和所述第一存储电容C(R)2通过所述第一薄膜晶体管3422、所述第二液晶电容C(G)1和所述第二存储电容C(G)2通过所述第二薄膜晶体管3424、以及所述第三液晶电容C(G)1和所述第三存储电容C(G)2通过所述第三薄膜晶体管3426电性连接到所述多条扫描线322中的同一扫描线322，以及分别电性连接至连续排列的第一次数据线334(S1)、第二次数据线334(S2)、和第三次数据线334(S3)。
在本发明的一优选实施例中，在所述显示面板300中，所述像素电路340的所述像素单元342的所述红色子像素单元R内的所述第一液晶电容C(R)1的电容值大于所述绿色子像素单元G内的所述第二液晶电容C(G)1的电容值，以及大于所述蓝色子像素单元B内的所述第三液晶电容C(B)1的电容值。并且，所述绿色子像素单元G内的所述第二液晶电容C(G)1的电容值等于所述蓝色子像素单元B内的所述第三液晶电容C(B)1的电容值。再者，所述像素电路340的所述像素单元342的所述红色子像素单元R内的所述第一存储电容C(R)2的电容值等于所述绿色子像素单元G内的所述第二存储电容C(G)2的电容值，以及等于所述蓝色子像素单元B内的所述第三存储电容C(B)2的电容值。
在上述优选实施例中，藉由将所述像素电路340的所述像素单元342的所述红色子像素单元R内的所述第一液晶电容C(R)1的电容值设置为大于其他颜色子像素单元内的若干液晶电容的电容值，以使得当依序驱动所述红色子像素单元R、所述绿色子像素单元G、和所述蓝色子像素单元B时，所述红色子像素单元R、所述绿色子像素单元G、和所述蓝色子像素单元B的维持(holding)电压一致，进而改善由于阻容迟滞现象(RC delay)的影响，造成所述红色子像素单元R的充电效果小于所述绿色子像素单元G和所述蓝色子像素单元B而导致所述显示面板300的画面呈现色偏和颜色不均匀的现象。
在本发明的另一优选实施例中，所述像素电路340的所述像素单元342的所述红色子像素单元R内的所述第一存储电容C(R)2的电容值小于所述绿色子像素单元G内的所述第二存储电容C(G)2的电容值，以及小于所述蓝色子像素单元B内的所述第三存储电容C(B)2的电容值。并且，所述绿色子像素单元G内的所述第二存储电容C(G)2的电容值等于所述蓝色子像素单元B内的所述第三存储电容C(B)2的电容值。再者，所述像素电路340的所述像素单元342的所述红色子像素单元R内的所述第一液晶电容C(R)1的电容值等于所述绿色子像素单元G内的所述第二液晶电容C(G)1的电容值，以及等于所述蓝色子像素单元B内的所述第三液晶电容C(B)1的电容值。
在上述优选实施例中，藉由将所述像素电路340的所述像素单元342的所述红色子像素单元R内的所述第一存储电容C(R)2的电容值设置为小于其他颜色子像素单元内的若干存储电容的电容值，以使得当依序驱动所述红色子像素单元R、所述绿色子像素单元G、和所述蓝色子像素单元B时，所述红色子像素单元R、所述绿色子像素单元G、和所述蓝色子像素单元B的维持(holding)电压一致，进而改善由于阻容迟滞现象(RC delay)的影响，造成所述红色子像素单元R的充电效果小于所述绿色子像素单元G和所述蓝色子像素单元B而导致所述显示面板300的画面呈现色偏和颜色不均匀的现象。
尽管对本发明的示例性具体实施例进行了描述，但是应该理解地，本发明不局限于这些示例性具体实施例，凡在本发明的精神和原则之内，本领域普通技术人员所作的任何修改、等同替换、改进等，均应包含在本发明的权利要求范围之内。此外，术语“一”、“一个”等的使用并不表示数量的限制，而是表示存在至少一个的参考部件。

Claims (19)

  1. 一种用于显示面板的像素电路，包含：
    多条扫描线；
    多条次数据线，与所述多条扫描线相互交错配置；以及
    多个像素单元，每一所述像素单元至少包含：一第一颜色子像素单元和一第二颜色子像素单元，所述第一颜色子像素单元和所述第二颜色子像素单元电性连接至所述多条扫描线中的同一扫描线，且分别电性连接至所述多条次数据线中连续排列的一第一次数据线和一第二次数据线，所述第一颜色子像素单元包含一第一液晶电容和一第一存储电容，以及所述第二颜色子像素单元包含一第二液晶电容和一第二存储电容；
    其中所述第一颜色子像素单元的所述第一液晶电容的电容值与所述第二颜色子像素单元的所述第二液晶电容的电容值不相等，或者所述第一颜色子像素单元的所述第一存储电容的电容值与所述第二颜色子像素单元的所述第二存储电容的电容值不相等；
    当所述第一颜色子像素单元的所述第一液晶电容的电容值大于所述第二颜色子像素单元的所述第二液晶电容的电容值时，所述第一颜色子像素单元的所述第一存储电容的电容值等于所述第二颜色子像素单元的所述第二存储电容的电容值；
    当所述第一颜色子像素单元的所述第一存储电容的电容值小于所述第二颜色子像素单元的所述第二存储电容的电容值时，所述第一颜色子像素单元的所述第一液晶电容的电容值等于所述第二颜色子像素单元的所述第二液晶电容的电容值；以及
    所述第一颜色子像素单元的驱动时序早于所述第二颜色子像素单元的驱动时序。
  2. 一种用于显示面板的像素电路，包含：
    多条扫描线；
    多条次数据线，与所述多条扫描线相互交错配置；以及
    多个像素单元，每一所述像素单元至少包含：一第一颜色子像素单元和一第二颜色子像素单元，所述第一颜色子像素单元和所述第二颜色子像素单元电性连接至所述多条扫描线中的同一扫描线，且分别电性连接至所述多条次数据线中连续排列的一第一次数据线和一第二次数据线，所述第一颜色子像素单元包含一第一液晶电容和一第一存储电容，以及所述第二颜色子像素单元包含一第二液晶电容和一第二存储电容；
    其中所述第一颜色子像素单元的所述第一液晶电容的电容值与所述第二颜色子像素单元的所述第二液晶电容的电容值不相等，或者所述第一颜色子像素单元的所述第一存储电容的电容值与所述第二颜色子像素单元的所述第二存储电容的电容值不相等。
  3. 根据权利要求2所述像素电路，其中所述第一颜色子像素单元的所述第一液晶电容的电容值大于所述第二颜色子像素单元的所述第二液晶电容的电容值。
  4. 根据权利要求3所述像素电路，其中所述第一颜色子像素单元的所述第一存储电容的电容值等于所述第二颜色子像素单元的所述第二存储电容的电容值。
  5. 根据权利要求2所述像素电路，其中所述第一颜色子像素单元的所述第一存储电容的电容值小于所述第二颜色子像素单元的所述第二存储电容的电容值。
  6. 根据权利要求5所述像素电路，其中所述第一颜色子像素单元的所述第一液晶电容的电容值等于所述第二颜色子像素单元的所述第二液晶电容的电容值。
  7. 根据权利要求2所述像素电路，其中所述第一颜色子像素单元的驱动时序早于所述第二颜色子像素单元的驱动时序。
  8. 根据权利要求2所述像素电路，其中所述像素电路的每一所述像素单元还包含一第三颜色子像素单元，所述第三颜色子像素单元与所述第一颜色子像素单元和所述第二颜色子像素单元电性连接至所述多条扫描线中的同一扫描线，且所述第三颜色子像素单元还电性连接至排列于所述第二次数据线之后的一第三次数据线，所述第三颜色子像素单元包含一第三液晶电容和一第三存储电容，其中所述第一颜色子像素单元的所述第一液晶电容的电容值与所述第三颜色子像素单元的所述第三液晶电容的电容值不相等，或者所述第一颜色子像素单元的所述第一存储电容的电容值与所述第三颜色子像素单元的所述第三存储电容的电容值不相等。
  9. 根据权利要求8所述像素电路，其中所述第一颜色子像素单元的所述第一液晶电容的电容值大于所述第三颜色子像素单元的所述第三液晶电容的电容值，以及所述第二颜色子像素单元的所述第二液晶电容的电容值等于所述第三颜色子像素单元的所述第三液晶电容的电容值。
  10. 根据权利要求8所述像素电路，其中所述第一颜色子像素单元的所述第一存储电容的电容值小于所述第三颜色子像素单元的所述第三存储电容的电容值，以及所述第二颜色子像素单元的所述第二存储电容的电容值等于所述第三颜色子像素单元的所述第三存储电容的电容值。
  11. 一种显示面板，包含：
    一像素电路包含：
    多条扫描线；
    多条次数据线与所述多条扫描线相互交错设置；以及
    多个像素单元，每一所述像素单元至少包含：一第一颜色子像素单元和一第二颜色子像素单元，所述第一颜色子像素单元和所述第二颜色子像素单元电性连接至所述多条扫描线中的同一扫描线，且分别电性连接至所述多条次数据线中连续排列的一第一次数据线和一第二次数据线，所述第一颜色子像素单元包含一第一液晶电容和一第一存储电容，以及所述第二颜色子像素单元包含一第二液晶电容和一第二存储电容；
    一数据驱动器，与多条主数据线相连接用于传递多个数据驱动信号；
    一闸极驱动器，与所述多条扫描线相连接用于传递多个闸极驱动信号；以及
    一解复用器单元，包含多个解复用器，其中之一解复用器通过所述多条主数据线的其中之一与所述数据驱动器连接，并且用于分别响应从其外部输入的多个控制信号，依序地向所述第一次数据线和所述第二次数据线施加从相应的所述主数据线接收的所述数据驱动信号；
    其中所述第一颜色子像素单元的所述第一液晶电容的电容值与所述第二颜色子像素单元的所述第二液晶电容的电容值不相等，或者所述第一颜色子像素单元的所述第一存储电容的电容值与所述第二颜色子像素单元的所述第二存储电容的电容值不相等。
  12. 根据权利要求11所述显示面板，其中所述第一颜色子像素单元的所述第一液晶电容的电容值大于所述第二颜色子像素单元的所述第二液晶电容的电容值。
  13. 根据权利要求12所述显示面板，其中所述第一颜色子像素单元的所述第一存储电容的电容值等于所述第二颜色子像素单元的所述第二存储电容的电容值。
  14. 根据权利要求11所述显示面板，其中所述第一颜色子像素单元的所述第一存储电容的电容值小于所述第二颜色子像素单元的所述第二存储电容的电容值。
  15. 根据权利要求14所述显示面板，其中所述第一颜色子像素单元的所述第一液晶电容的电容值等于所述第二颜色子像素单元的所述第二液晶电容的电容值。
  16. 根据权利要求11所述显示面板，其中所述解复用器响应所述多个控制信号依序地将相对应的所述数据驱动信号输入所述第一颜色子像素单元和所述第二颜色子像素单元，使得所述第一颜色子像素单元的驱动时序早于所述第二颜色子像素单元的驱动时序。
  17. 根据权利要求11所述显示面板，其中所述像素电路的每一所述像素单元还包含一第三颜色子像素单元，所述第三颜色子像素单元与所述第一颜色子像素单元和所述第二颜色子像素单元电性连接至所述多条扫描线中的同一扫描线，且所述第三颜色子像素单元还电性连接至排列于所述第二次数据线之后的一第三次数据线；所述第三颜色子像素单元包含一第三液晶电容和一第三存储电容，所述第一颜色子像素单元的所述第一液晶电容的电容值与所述第三颜色子像素单元的所述第三液晶电容的电容值不相等，或者所述第一颜色子像素单元的所述第一存储电容的电容值与所述第三颜色子像素单元的所述第三存储电容的电容值不相等。
  18. 根据权利要求17所述显示面板，其中所述第一颜色子像素单元的所述第一液晶电容的电容值大于所述第三颜色子像素单元的所述第三液晶电容的电容值，以及所述第二颜色子像素单元的所述第二液晶电容的电容值等于所述第三颜色子像素单元的所述第三液晶电容的电容值。
  19. 根据权利要求17所述显示面板，其中所述第一颜色子像素单元的所述第一存储电容的电容值小于所述第三颜色子像素单元的所述第三存储电容的电容值，以及所述第二颜色子像素单元的所述第二存储电容的电容值等于所述第三颜色子像素单元的所述第三存储电容的电容值。
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