WO2017002432A1 - Silicon substrate, nitride semiconductor wafer using same, and nitride semiconductor device - Google Patents

Silicon substrate, nitride semiconductor wafer using same, and nitride semiconductor device Download PDF

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WO2017002432A1
WO2017002432A1 PCT/JP2016/062384 JP2016062384W WO2017002432A1 WO 2017002432 A1 WO2017002432 A1 WO 2017002432A1 JP 2016062384 W JP2016062384 W JP 2016062384W WO 2017002432 A1 WO2017002432 A1 WO 2017002432A1
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silicon substrate
nitride semiconductor
group iii
iii nitride
resistivity
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Japanese (ja)
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竜 海原
勝 久保
学 遠崎
淳 小河
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シャープ株式会社
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Definitions

  • the present invention relates to a silicon substrate capable of stacking nitride semiconductors, a nitride semiconductor wafer using the same, and a nitride semiconductor device.
  • a silicon (Si) substrate is doped with boron (B) at a high concentration, thereby reducing the resistivity of the silicon substrate to 0.01 ⁇ ⁇ cm or less.
  • boron (B) boron
  • This epitaxial wafer is harder than a high-purity silicon substrate to which no impurities are added by doping boron into the silicon substrate at a high concentration to increase the impurity concentration of the silicon substrate. Then, an epitaxial wafer is formed by epitaxially growing a nitride semiconductor on the hardened (that is, the resistivity is lowered) silicon substrate, thereby causing a difference in thermal expansion coefficient between Si and the nitride semiconductor. The warpage of the epitaxial wafer is reduced.
  • the conventional nitride semiconductor epitaxial wafer uses a silicon substrate having a high impurity concentration and a low resistivity, the nitride semiconductor layer is formed at the interface between the silicon substrate and the nitride semiconductor layer. There is a problem that the parasitic capacitance generated on the side cannot be reduced.
  • the absolute value of the wafer strength can be increased (for example, special characteristics).
  • JP 2012-66943 Patent Document 2
  • JP-A-2015-2329 Patent Document 3
  • the impurity concentration is low (for example, a region having an impurity concentration of 1 ⁇ 10 17 cm ⁇ 3 or less), the mechanical strength of the silicon substrate is constant and is very stable against changes in the impurity concentration. It has been known.
  • boron (B) doped on the Si surface is removed by pretreatment such as hydrogen fluoride cleaning before epitaxial growth and nitriding treatment at the initial stage of epitaxial growth.
  • pretreatment such as hydrogen fluoride cleaning before epitaxial growth and nitriding treatment at the initial stage of epitaxial growth.
  • the impurity concentration is high, there is a problem that the oxygen concentration mixed from the quartz crucible during the growth of the silicon crystal becomes unstable. It is known that the oxygen taken into the silicon substrate has a great influence on the mechanical strength of the silicon substrate. From the viewpoint of the oxygen concentration in the silicon substrate, in order to make the mechanical strength of the silicon substrate constant. It is desirable that the impurity concentration is low.
  • the impurity concentration of the silicon substrate is too low, that is, when the resistance becomes high (100 ⁇ ⁇ cm or more) (for example, Japanese Patent Application Laid-Open No. 2014-187086 (Patent Document 4)
  • the ground electrode Since the resistance of the substrate itself is high with respect to the silicon substrate that functions as the above, the substrate potential at the time of the switching operation of the transistor becomes unstable, and the transistor operation becomes unstable.
  • an object of the present invention is to reduce the variation in warpage of the epitaxial wafer when the nitride semiconductor layer is stacked, and to reduce the parasitic capacitance generated on the nitride semiconductor layer side at the interface with the nitride semiconductor layer,
  • An object of the present invention is to provide a silicon substrate capable of improving the stability at the time of switching of a field effect transistor formed of a nitride semiconductor layer.
  • Another object of the present invention is to provide a nitride semiconductor wafer and a nitride semiconductor device using the silicon substrate.
  • the silicon substrate of the present invention is A p-type silicon substrate capable of forming a group III nitride semiconductor layer on the surface,
  • the surface resistivity is 1 ⁇ ⁇ cm or more and less than 100 ⁇ ⁇ cm.
  • the surface resistivity is 1 ⁇ ⁇ cm or more and less than 30 ⁇ ⁇ cm.
  • the substrate thickness is 0.675 mm or more.
  • the nitride semiconductor wafer of the present invention is Any one of the above silicon substrates; And a group III nitride laminate including the group III nitride semiconductor layer formed on the surface of the silicon substrate.
  • the nitride semiconductor device of the present invention is Any one of the above silicon substrates; A group nitride laminate comprising the group III nitride semiconductor layer formed on the surface of the silicon substrate; A source electrode, a drain electrode, and a gate electrode formed on the group III nitride laminate are provided.
  • the thickness of the silicon substrate is 100 ⁇ m or more and 275 ⁇ m or less.
  • At least one of the group III nitride semiconductor layers constituting the group III nitride laminate has a region having a carbon concentration of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 20 cm ⁇ 3 or less. To do.
  • the silicon substrate of the present invention has a resistivity of 1 ⁇ ⁇ cm or more because the resistivity of the p-type silicon substrate is higher than that of the group III nitride laminate grown on the silicon substrate.
  • the parasitic capacitance generated on the group III nitride laminate side at the interface between the substrate and the group III nitride laminate formed on the surface of the silicon substrate can be reduced. Furthermore, the rate of change in mechanical strength due to manufacturing variations in impurity concentration can be suppressed.
  • a cutoff frequency which is a frequency at which the silicon substrate is in a floating state, is set. It can be higher than the switching frequency (10 kHz to 10 MHz).
  • the nitride semiconductor wafer according to the present invention is an interface between a silicon substrate and a group III nitride laminate when the group III nitride laminate is grown on the silicon substrate by using the silicon substrate according to the present invention.
  • the parasitic capacitance generated in the above can be reduced.
  • the amount of charge required when charging and discharging the parasitic capacitance can be reduced.
  • the rate of change in mechanical strength due to manufacturing variations in impurity concentration can be suppressed, and variations in warpage due to differences in thermal expansion coefficients between the silicon substrate and the group III nitride laminate can be suppressed.
  • the cutoff frequency can be made higher than the switching frequency.
  • the nitride semiconductor device of the present invention uses the nitride semiconductor wafer of the present invention, so that when the field effect transistor is formed by growing a group III nitride stacked body on a silicon substrate, the parasitic capacitance ( The drain output capacitance (Coss) can be reduced. As a result, the amount of charge required when charging and discharging the parasitic capacitance can be reduced, and the switching loss energy can be reduced. Furthermore, the variation rate of the said mechanical strength can be suppressed and the variation of the said curvature can be suppressed. As a result, it can be mass-produced stably with good reproducibility. Furthermore, the cutoff frequency can be made higher than the switching frequency. Therefore, harmonics and noise generated at the time of switching can be cut off and the operation can be stably performed.
  • the drain output capacitance Coss
  • FIG. 1 It is a schematic sectional drawing in the field effect transistor as an example of the nitride semiconductor device of 1st Embodiment of this invention. It is a figure which shows distribution of the parasitic capacitance in the field effect transistor shown in FIG. It is a figure which shows the dependence with respect to the drain voltage Vd in the drain output capacity Coss, and the resistivity Rsi of a silicon substrate. It is a figure which shows the dependence of the resistivity Rsi of a silicon substrate in drain output capacity Coss and cutoff frequency fc. It is a perspective view of the field effect transistor of the chip piece state of the first embodiment. It is a perspective view of the silicon substrate of 2nd Embodiment of this invention.
  • FIG. 1 is a schematic cross-sectional view of a field effect transistor as an example of a nitride semiconductor device according to the first embodiment.
  • the field effect transistor is an HFET (Hetero-junction Field Effect Transistor).
  • the field effect transistor includes a p-type silicon substrate 1, a plurality of nitride semiconductor layers 2 to 4 stacked on the p-type silicon substrate 1, and a plurality of nitride semiconductor layers 2 1 to 4 formed on the first nitride film 5, an opening 6 for forming the gate electrode 8, a second nitride film 7 formed on the first nitride film 5 and serving as a gate insulating film, and a gate An electrode 8, a first oxide film 12, an ohmic contact portion 9, a source ohmic electrode 10, and a drain ohmic electrode 11 are provided, on which a second oxide film (not shown), a source wiring electrode 13, and a drain are provided. Wiring electrode 14 is provided.
  • the p-type silicon substrate 1 is a p-type Si single crystal substrate having a resistivity of 99 ⁇ ⁇ cm doped with boron (carrier concentration: 1.01 ⁇ 10 14 cm ⁇ 3 ).
  • concentration of the semiconductor impurity is inversely proportional to the resistivity of the semiconductor
  • width of the semiconductor depletion layer is proportional to the square root of the impurity concentration.
  • the parasitic capacitance due to the depletion layer is inversely proportional to the width of the depletion layer.
  • the doping concentration is 1.01 ⁇ 10 14 cm ⁇ 3 over the entire thickness direction of the silicon substrate 1, but there is a problem even if only the surface in contact with the nitride semiconductor layer has a high resistance.
  • the width of the maximum depletion layer generated on the surface of the silicon substrate 1 is sufficient.
  • the plurality of stacked nitride semiconductor layers 2 to 4 are composed of an AlN / AlGaN superlattice buffer layer 2 formed using a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus and carbon (carbon) doped. These are the GaN layer 3 and the GaN channel layer 4. Further, a barrier layer (not shown) made of Al 0.2 Ga 0.8 N is formed on the GaN channel layer 4.
  • the AlN / AlGaN superlattice buffer layer 2, the carbon-doped (breakdown voltage) GaN layer 3, and the GaN channel layer 4 are sequentially stacked on the p-type silicon substrate 1 by epitaxial growth.
  • the source ohmic electrode 10 and the drain ohmic electrode 11 are ohmic electrodes made of a Ti / Al alloy.
  • the gate electrode 8 is an electrode having a W / WN laminated structure.
  • a single element of a field effect transistor (HFET) made of a nitride semiconductor is used as a transistor element.
  • HFET field effect transistor
  • FIG. 2 is a diagram showing the distribution of parasitic capacitance in the field effect transistor shown in FIG.
  • the drain output capacitance Coss is a capacitance between the “silicon substrate 1” and the “drain portion two-dimensional electron gas 15 and drain ohmic electrode 11 existing in the vicinity of the drain ohmic electrode (drain electrode) 11”. is there.
  • Vdd in the above formula (1) is a power supply voltage at the time of switching. In this embodiment, it is set to 400V. However, the power supply voltage can be adjusted depending on the application.
  • Coss in the above formula (1) indicates that the gate-drain portion 2 is formed by using the nitride laminated body 16 composed of the nitride semiconductor layers 2 to 4 as the nitride epitaxial layer as shown in FIG.
  • the total capacitance Cdb is a series capacitance of the two-dimensional electron gas capacitance Cdg, the source-drain capacitance Cds, the drain portion two-dimensional electron gas-nitride epitaxial interlayer capacitance Cepi, and the silicon substrate capacitance Csi.
  • the main factor that has the most influence on the “Coss” is the total capacity Cdb.
  • the silicon substrate capacity Csi formed in the silicon substrate 1 is very large, and the total capacity Cdb is determined by the sum of the drain portion two-dimensional electron gas-nitride epitaxial interlayer capacity Cepi, which is not preferable. .
  • the impurity concentration is 1 ⁇ 10 18 cm ⁇ 3
  • the depletion layer width W in that case is 0.3 ⁇ m.
  • the silicon substrate capacitance Csi becomes very large.
  • a device simulation was performed using ATLAS of Silvaco, which is a device simulator.
  • the structure of the field effect transistor used in this device simulation has a chip area of 2.00 mm ⁇ 2.15 mm and a two-dimensional electron gas concentration of 6.0 ⁇ 10 ⁇ 12 cm ⁇ 2 .
  • FIG. 3 shows the relationship between the simulated drain output capacitance Coss and the drain voltage Vd, and the dependency of the resistivity Rsi of the silicon substrate 1.
  • the cutoff frequency fc which is the frequency at which the silicon substrate 1 is in a floating state, is expressed by the following equation (3), where Rsi is the resistivity of the silicon substrate 1 and Cdb is the total capacitance of the epitaxial layer capacitance Cepi and the silicon substrate capacitance Csi. Can be expressed as
  • the cutoff frequency fc is 200 MHz, and the active region of the field effect transistor is in a floating state at a frequency lower than that.
  • the switching frequency is generally about 10 kHz to 10 MHz.
  • the two-dimensional electron gas formed by the nitride semiconductor has a high mobility, and the rise / fall of the voltage during switching is several nsec. Very short. For this reason, harmonics and noise generated during switching also increase. Therefore, if the resistivity Rsi of the silicon substrate 1 is too high, 1000 ⁇ ⁇ cm, the switching frequency becomes substantially the same value as the cutoff frequency fc, and the switching operation frequency itself becomes a floating state. As a result, it becomes difficult to operate stably.
  • the switching frequency should be several GHz, preferably 1 GHz or less.
  • FIG. 4 shows the relationship between the result of FIG. 3 and the cutoff frequency fc obtained by the above equation (3).
  • the drain output capacitance Coss tends to be lower as the resistivity Rsi of the silicon substrate 1 is higher, and the loss during switching can be reduced.
  • the cutoff frequency fc decreases to less than about 600 MHz when the resistivity Rsi of the silicon substrate 1 is 100 ⁇ ⁇ cm or more.
  • the resistivity Rsi of the silicon substrate 1 is desirably 1 ⁇ ⁇ cm or more in order to reduce the drain output capacitance Coss, and less than 100 ⁇ ⁇ cm in order to cut off harmonics and noise generated during switching. . Furthermore, if the resistivity Rsi of the silicon substrate 1 is in the range of 1 ⁇ ⁇ cm to less than 30 ⁇ ⁇ cm, the cutoff frequency fc is about 1 GHz, which is more desirable.
  • the silicon substrate 1 is a high-resistance substrate having a resistance of 1 ⁇ ⁇ cm or more, the depletion layer easily extends and the drain output capacitance Coss can be lowered.
  • the silicon substrate 1 having a high resistance of 1 ⁇ ⁇ cm or more has a low B concentration, it is difficult to form pits on the surface, so that surface variation can be improved and machining is facilitated.
  • the high resistance substrate such as the silicon substrate 1 can reduce the variation in mechanical strength, the variation in warpage after the epitaxial growth of the group III nitride semiconductor layer can also be reduced.
  • a high resistance substrate such as the silicon substrate 1 is easy to control the amount of oxygen mixed during silicon crystal growth, that is, it is easy to control the oxygen concentration largely related to the mechanical strength. As a result, the mechanical strength variation can be reduced.
  • the silicon substrate 1 has a single substrate structure, the cost can be reduced.
  • the stability of the transistor operation can be improved by not increasing the resistivity of the silicon substrate 1 too high.
  • the HFET which is a nitride semiconductor device has been described.
  • the nitride semiconductor device is not limited to this, and the present invention may be applied to field effect transistors having other configurations.
  • the silicon substrate 1 is formed by the method described in the second embodiment, and the nitride semiconductor layers 2 to 4 are formed by the method described in the third embodiment.
  • a first nitride film 5 mainly made of silicon nitride is deposited by plasma CVD to a thickness of 40 nm, and the first nitride film 5 in the region to be the gate portion is removed with hydrogen fluoride (0.5%) to form the opening 6.
  • a second nitride film 7 having a composition mainly of silicon nitride and acting as a gate insulating film is deposited by a plasma CVD method to a thickness of 20 nm.
  • W / WN W / WN thickness is 100 nm / 20 nm, respectively
  • the gate electrode 8 and the second nitride film (gate insulating film) 7 are formed into a desired shape by dry etching.
  • the etching depth at this time needs to sufficiently remove the Al 0.2 Ga 0.8 N barrier layer formed at least on the upper layer of the GaN channel layer 4.
  • a source ohmic electrode 10 and a drain ohmic electrode 11 mainly made of Ti / Al are formed on the ohmic contact portion 9.
  • the source ohmic electrode 10 and the drain ohmic electrode 11 form an ohmic electrical connection with the two-dimensional electron gas 15 (shown in FIG. 2) formed in the GaN channel layer 4.
  • a method different from the method using the ohmic electrode may be used as long as it is a method capable of forming an ohmic electrical connection with the two-dimensional electron gas 15.
  • a first oxide film 12 mainly made of silicon oxide is formed with a thickness of 1 ⁇ m by plasma CVD, and then a wiring mainly made of Al is processed into a desired shape to form a source wiring electrode. 13 and the drain wiring electrode 14 are formed.
  • the present field effect transistor HFET
  • the source wiring electrode 13 has a field plate structure extending in the lateral direction (left-right direction in FIG. 1) from the position of the gate electrode 8 toward the drain wiring electrode 14, and the electric field in the vicinity of the gate electrode 8.
  • the length is such that the strength can be optimized.
  • a thinning process for reducing the thickness of the silicon substrate 1 to 275 ⁇ m by a polishing process is performed on the wafer-like substrate on which the field effect transistor is formed as described above.
  • the thickness of the silicon substrate 1 is thin.
  • the degree is preferred. However, this is not the case when the Joule heat generated during operation of the field effect transistor is low.
  • FIG. 5 is a perspective view of a field effect transistor in a chip piece state.
  • the silicon substrate 1 is soldered to a TO-220 type lead frame, which is a standard transistor package, with a solder material made of SnAgCu, and the desired wiring is performed, followed by resin sealing to complete the transistor element. To do.
  • FIG. 6 is a perspective view of a silicon substrate 1 (silicon wafer) according to the second embodiment of the present invention.
  • a silicon substrate 1 desirable for forming a nitride semiconductor wafer of the present invention, particularly a nitride semiconductor device, and a method for manufacturing the same will be described.
  • silicon oxide is reduced to Si, and high-purity trichlorosilane (SiHCl 3 ) is generated using hydrogen chloride. Thereafter, heat treatment is performed to precipitate and purify high-purity Si. Then, the high-purity Si thus formed is introduced into a crucible made of quartz, and Si is melted at a high temperature of 1450 ° C. A seed crystal is attached to the molten Si solution and pulled up while rotating gently to form a Si single crystal ingot.
  • SiHCl 3 high-purity trichlorosilane
  • the raw material refining method as described above is a silicon ingot forming method called Czochralski method (Czochralski method (CZ method)).
  • Czochralski method CZ method
  • a floating zone method in which a Si single crystal ingot having a low oxygen concentration is grown without using a quartz crucible FZ method
  • Magnetic CZ method Magnetic CZ method in which a strong magnetic field is applied in the CZ method
  • desired boron (B) is introduced into the silicon substrate 1 cut out from the Si single crystal ingot, and B is melted with Si at about 1420 ° C., so that the B concentration in the silicon substrate 1 is increased.
  • a p-type Si crystal is manufactured by adjusting the resistivity to be greater than 1 ⁇ 10 14 cm ⁇ 3 and less than or equal to 1 ⁇ 10 16 cm ⁇ 3 , that is, the resistivity is 1 ⁇ ⁇ cm or more and less than 100 ⁇ ⁇ cm.
  • the resistivity of the high resistance silicon substrate 1 in the present embodiment needs to be 1 ⁇ ⁇ cm or more and less than 100 ⁇ ⁇ cm, more desirably 1 ⁇ ⁇ cm or more and less than 30 ⁇ ⁇ cm.
  • This resistivity of 1 ⁇ ⁇ cm or more and less than 100 ⁇ ⁇ cm can be realized by the CZ method.
  • the CZ method is more desirable from the viewpoint of manufacturing cost and manufacturing method, as described above, the Si crystal having the desired resistivity can be manufactured even by other silicon ingot forming methods.
  • a silicon substrate 1 is formed by performing an outer periphery polishing step, orientation flat (Orientation Flat) formation, slicing, polishing, and final cleaning steps.
  • the silicon substrate 1 is formed so that the plane orientation is (111). This is because when the nitride semiconductor multilayer film is formed later, the lattice orientation is the closest plane orientation.
  • the thickness of the silicon substrate 1 needs to be 625 ⁇ m or more for a substrate having a diameter of 6 inches, for example, and preferably 1 mm in order to withstand the mechanical stress difference with the nitride semiconductor during the subsequent epitaxial growth. The above is good.
  • the silicon substrate 1 in the wafer state is shown. Needless to say, however, the silicon substrate 1 in the chip piece state may be used as shown in FIG. 6 of the second embodiment.
  • FIG. 8 is a perspective view of a nitride semiconductor wafer 100 obtained by epitaxially growing a group III nitride laminate 16 on a silicon substrate 1 (silicon wafer) according to a third embodiment of the present invention.
  • a nitride semiconductor wafer 100 obtained by epitaxially growing a group III nitride stacked body 16 on the silicon substrate 1 manufactured by the manufacturing method shown in the second embodiment will be described.
  • a nitride semiconductor wafer 100 used for forming the field effect transistor of the first embodiment will be described.
  • 1 is a p-type silicon substrate
  • 2 is an AlN / AlGaN superlattice buffer layer
  • 3 is a carbon-doped GaN layer
  • 4 is a GaN channel layer.
  • 8 is a gate electrode
  • 10 is a source ohmic electrode (source electrode)
  • 11 is a drain ohmic electrode (drain electrode).
  • Each of the AlN / AlGaN superlattice buffer layer 2, the carbon-doped GaN layer 3, and the GaN channel layer 4 is an example of a group III nitride semiconductor layer.
  • the GaN channel layer 4 constitutes a group III nitride laminate 16.
  • the p-type silicon substrate 1 is formed by the method described in the second embodiment.
  • the group III nitride semiconductor layer is formed on the p-type silicon substrate 1 by using a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus.
  • MOCVD Metal Organic Chemical Vapor Deposition
  • a p-type substrate having a resistivity of 1 ⁇ ⁇ cm or more is used as the silicon substrate 1, so that the AlN / AlGaN superlattice buffer layer 2, carbon
  • the group III nitride laminate 16 composed of the doped GaN layer 3 and the GaN channel layer 4 is grown, it is generated on the group III nitride laminate 16 side at the interface between the silicon substrate 1 and the group III nitride laminate 16.
  • Parasitic capacitance can be reduced.
  • the amount of charge required when charging and discharging the parasitic capacitance can be reduced.
  • the rate of change in mechanical strength due to manufacturing variations in impurity concentration can be suppressed, and variations in warpage due to differences in thermal expansion coefficients between the silicon substrate 1 and the group III nitride laminate 16 can be suppressed.
  • a p-type substrate having a resistivity of less than 100 ⁇ ⁇ cm is used as the silicon substrate 1
  • the cutoff frequency is increased. fc can be made higher than the switching frequency (10 kHz to 10 MHz).
  • the nitride semiconductor wafer 100 (wafer state) is shown, but it goes without saying that it may be in a chip piece state as shown in FIG.
  • FIG. 9 the same reference numerals are given to the same components as those in FIG.
  • the silicon substrate of the present invention is A p-type silicon substrate 1 capable of forming group III nitride semiconductor layers 2, 3, and 4 on its surface,
  • the surface resistivity is 1 ⁇ ⁇ cm or more and less than 100 ⁇ ⁇ cm.
  • the resistivity of the p-type silicon substrate 1 is 1 ⁇ ⁇ cm or more, when the group III nitride laminate 16 is grown on the silicon substrate 1, The parasitic capacitance generated on the group III nitride laminate 16 side at the interface with the group III nitride laminate 16 formed on the surface of the silicon substrate 1 can be reduced. Furthermore, the rate of change in mechanical strength due to manufacturing variations in impurity concentration can be suppressed.
  • the cut-off frequency fc which is a higher frequency, can be made higher than the switching frequency (10 kHz to 10 MHz).
  • the surface resistivity is 1 ⁇ ⁇ cm or more and less than 30 ⁇ ⁇ cm.
  • the cutoff frequency fc can be set to about 1 GHz, and the operation can be performed more stably.
  • the substrate thickness is 0.675 mm or more.
  • the substrate thickness of the silicon substrate 1 is 0.675 mm or more, when the group III nitride laminate 16 is grown on the silicon substrate 1, the group III nitride laminate 16 and Can withstand the mechanical stress difference.
  • the nitride semiconductor wafer 100 of the present invention is Any one of the above silicon substrates 1, And a group III nitride laminate 16 composed of the group III nitride semiconductor layers 2, 3, 4 formed on the surface of the silicon substrate 1.
  • a p-type substrate having a resistivity of 1 ⁇ ⁇ cm or more is used as the silicon substrate 1, so that the group III nitride comprising the group III nitride semiconductor layers 2, 3, 4 on the silicon substrate 1 is used.
  • the product stack 16 is grown, the parasitic capacitance generated on the group III nitride stack 16 side at the interface between the silicon substrate 1 and the group III nitride stack 16 can be reduced.
  • the amount of charge required when charging and discharging the parasitic capacitance can be reduced.
  • the rate of change in mechanical strength due to manufacturing variations in impurity concentration can be suppressed, and variations in warpage due to differences in thermal expansion coefficients between the silicon substrate 1 and the group III nitride laminate 16 can be suppressed.
  • a p-type substrate having a resistivity of less than 100 ⁇ ⁇ cm is used as the silicon substrate 1
  • the cutoff frequency is increased. fc can be made higher than the switching frequency (10 kHz to 10 MHz).
  • the nitride semiconductor device of the present invention is Any one of the above silicon substrates 1, A group III nitride laminate 16 composed of the group III nitride semiconductor layers 2, 3, 4 formed on the surface of the silicon substrate 1, and A source electrode 10, a drain electrode 11, and a gate electrode 8 formed on the group III nitride laminate 16 are provided.
  • a group III nitride stack composed of group III nitride semiconductor layers 2, 3, and 4 is formed on the silicon substrate 1 by using a p-type substrate having a resistivity of 1 ⁇ ⁇ cm or more as the silicon substrate 1.
  • the parasitic capacitance drain output capacitance Coss
  • the parasitic capacitance generated on the group III nitride stack 16 side at the interface between the silicon substrate 1 and the group III nitride stack 16 is reduced. it can.
  • the amount of charge required when charging and discharging the parasitic capacitance can be reduced, and the switching loss energy can be reduced.
  • the rate of change in mechanical strength due to manufacturing variations in impurity concentration can be suppressed, and variations in warpage due to differences in thermal expansion coefficients between the silicon substrate 1 and the group III nitride laminate 16 can be suppressed. As a result, it can be mass-produced stably with good reproducibility.
  • the cutoff frequency fc can be higher than the switching frequency (10 kHz to 10 MHz). Therefore, harmonics and noise generated at the time of switching can be cut off and the operation can be stably performed.
  • the thickness of the silicon substrate 1 is not less than 100 ⁇ m and not more than 275 ⁇ m.
  • the thermal conductivity of the silicon substrate 1 can be improved and the Joule heat generated during operation can be radiated.
  • the thickness of the silicon substrate 1 is set to 100 ⁇ m or more, it is possible to prevent chipping and warping of the end face when the chip is formed.
  • At least one of the group III nitride semiconductor layers 2, 3, and 4 constituting the group III nitride stacked body 16 has a carbon concentration of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 20 cm ⁇ 3 or less.
  • At least one carbon concentration of the group III nitride semiconductor layers 2, 3, and 4 constituting the group III nitride stacked body 16 is set to 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 20. By setting it to cm ⁇ 3 or less, it is possible to prevent a decrease in dielectric strength and an increase in leakage current.

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Abstract

This p-type silicon substrate (1) has a surface on which group III nitride semiconductor layers (2, 3, 4) are able to be formed, and which has a resistivity of 1 Ω·cm or more but less than 100 Ω·cm. Consequently, the present invention provides a silicon substrate which is capable of reducing variation of warping of an epitaxial wafer in cases where a nitride semiconductor layer is laminated thereon, and which is capable of reducing the parasitic capacitance generated on the nitride semiconductor layer side at the interface between the epitaxial wafer and the nitride semiconductor layer, while being capable of improving the stability during switching of a field effect transistor that is formed of the nitride semiconductor layer.

Description

シリコン基板およびそれを用いた窒化物半導体ウェハ、並びに、窒化物半導体装置Silicon substrate, nitride semiconductor wafer using the same, and nitride semiconductor device
　この発明は、窒化物半導体を積層可能なシリコン基板およびそれを用いた窒化物半導体ウェハ、並びに、窒化物半導体装置に関する。 The present invention relates to a silicon substrate capable of stacking nitride semiconductors, a nitride semiconductor wafer using the same, and a nitride semiconductor device.
　従来、窒化物半導体エピタキシャルウェハとして、シリコン(Ｓi)基板にボロン(Ｂ)を高濃度にドーピングすることによって、シリコン基板の抵抗率を０.０１Ω・ｃｍ以下にする。そして、そのシリコン基板上に窒化物半導体層をエピタキシャル成長させたものがある(例えば、特開２０１０‐１５３８１７号公報(特許文献１))。 Conventionally, as a nitride semiconductor epitaxial wafer, a silicon (Si) substrate is doped with boron (B) at a high concentration, thereby reducing the resistivity of the silicon substrate to 0.01 Ω · cm or less. In addition, there is one in which a nitride semiconductor layer is epitaxially grown on the silicon substrate (for example, JP 2010-153817 A (Patent Document 1)).
　このエピタキシャルウェハにおいては、シリコン基板にボロンを高濃度にドーピングして上記シリコン基板の不純物濃度を大きくすることによって、不純物が添加されていない高純度のシリコン基板よりも硬くしている。そして、この硬化された(つまり、抵抗率が低下された)シリコン基板上に、窒化物半導体をエピタキシャル成長させることによりエピタキシャルウェハを形成することにより、Ｓiと窒化物半導体との熱膨張係数差によって生ずるエピタキシャルウェハの反りを低減するようにしている。 This epitaxial wafer is harder than a high-purity silicon substrate to which no impurities are added by doping boron into the silicon substrate at a high concentration to increase the impurity concentration of the silicon substrate. Then, an epitaxial wafer is formed by epitaxially growing a nitride semiconductor on the hardened (that is, the resistivity is lowered) silicon substrate, thereby causing a difference in thermal expansion coefficient between Si and the nitride semiconductor. The warpage of the epitaxial wafer is reduced.
　しかしながら、上記従来の窒化物半導体エピタキシャルウェハにおいては、不純物濃度を高くして抵抗率を小さくしたシリコン基板を使用しているので、上記シリコン基板と窒化物半導体層との界面において上記窒化物半導体層側に生ずる寄生容量を低減することができないという問題がある。 However, since the conventional nitride semiconductor epitaxial wafer uses a silicon substrate having a high impurity concentration and a low resistivity, the nitride semiconductor layer is formed at the interface between the silicon substrate and the nitride semiconductor layer. There is a problem that the parasitic capacitance generated on the side cannot be reduced.
　また、上記不純物濃度が高い場合、すなわち抵抗率が低い(例えば、不純物濃度１×１０１９ｃｍ－３以上の領域)場合は、ウェハ強度の絶対値を高くすることが可能である(例えば、特開２０１２‐６６９４３号公報(特許文献２)、特開２０１５‐２３２９号公報(特許文献３))。 In addition, when the impurity concentration is high, that is, when the resistivity is low (for example, a region having an impurity concentration of 1 × 10 19 cm −3 or more), the absolute value of the wafer strength can be increased (for example, special characteristics). JP 2012-66943 (Patent Document 2), JP-A-2015-2329 (Patent Document 3)).
　しかしながら、上記不純物濃度に対するウェハ強度の変化率が大きいため、不純物濃度が製造バラつきによって揺らいだ場合、機械的強度の変化率が高い(つまり反りのバラつきが大きい)ことが問題となって、再現性よく安定に量産することが難しくなるという課題が生ずる。 However, since the change rate of the wafer strength with respect to the impurity concentration is large, if the impurity concentration fluctuates due to manufacturing variations, the change rate of the mechanical strength is high (that is, the variation of warpage is large), and the reproducibility The problem that it becomes difficult to mass-produce well well arises.
　それに対し、上記不純物濃度が低い(例えば、不純物濃度１×１０１７ｃｍ－３以下の領域)場合には、シリコン基板の機械強度は一定となり、上記不純物濃度の変化に対して非常に安定することが知られている。 On the other hand, when the impurity concentration is low (for example, a region having an impurity concentration of 1 × 10 17 cm −3 or less), the mechanical strength of the silicon substrate is constant and is very stable against changes in the impurity concentration. It has been known.
　同時に、上記不純物濃度が高い場合には、Ｓi表面にドーピングされたボロン(Ｂ)が、エピタキシャル成長前のフッ化水素洗浄等の前処理およびエピタキシャル成長初期の窒化処理によって除去されてしまう。その結果、Ｓi表面における制御すべき表面状態が変化してしまうという問題も発生する。 At the same time, when the impurity concentration is high, boron (B) doped on the Si surface is removed by pretreatment such as hydrogen fluoride cleaning before epitaxial growth and nitriding treatment at the initial stage of epitaxial growth. As a result, there arises a problem that the surface state to be controlled on the Si surface changes.
　また、上記不純物濃度が高い場合には、シリコン結晶成長時に石英るつぼより混入する酸素濃度が不安定になるという問題も生じる。シリコン基板中に取り込まれた酸素は、シリコン基板の機械的強度に大きく影響することが知られており、このシリコン基板中の酸素濃度といった観点でも、シリコン基板の機械的強度を一定とするためには不純物濃度は低い方が望ましい。 Also, when the impurity concentration is high, there is a problem that the oxygen concentration mixed from the quartz crucible during the growth of the silicon crystal becomes unstable. It is known that the oxygen taken into the silicon substrate has a great influence on the mechanical strength of the silicon substrate. From the viewpoint of the oxygen concentration in the silicon substrate, in order to make the mechanical strength of the silicon substrate constant. It is desirable that the impurity concentration is low.
　一方で、上記シリコン基板の不純物濃度を下げた過ぎた場合、つまり高抵抗(１００Ω・ｃｍ以上)となった場合(例えば、特開２０１４‐１８７０８６号公報(特許文献４))には、接地電極として機能する上記シリコン基板に対して、基板自体の抵抗が高いため、トランジスタのスイッチング動作時の基板電位が不安定になり、トランジスタ動作が不安定になる。 On the other hand, when the impurity concentration of the silicon substrate is too low, that is, when the resistance becomes high (100 Ω · cm or more) (for example, Japanese Patent Application Laid-Open No. 2014-187086 (Patent Document 4)), the ground electrode Since the resistance of the substrate itself is high with respect to the silicon substrate that functions as the above, the substrate potential at the time of the switching operation of the transistor becomes unstable, and the transistor operation becomes unstable.
特開２０１０‐１５３８１７号公報JP 2010-153817 A 特開２０１２‐６６９４３号公報JP 2012-66943 A 特開２０１５‐２３２９号公報Japanese Patent Laid-Open No. 2015-2329 特開２０１４‐１８７０８６号公報JP 2014-1887086 A
　そこで、この発明の課題は、窒化物半導体層を積層する場合にエピタキシャルウェハの反りのばらつきを低減でき、その窒化物半導体層との界面において窒化物半導体層側に生ずる寄生容量を低減できると共に、窒化物半導体層により形成される電界効果トランジスタのスイッチング時の安定性が向上できるシリコン基板を提供することにある。 Accordingly, an object of the present invention is to reduce the variation in warpage of the epitaxial wafer when the nitride semiconductor layer is stacked, and to reduce the parasitic capacitance generated on the nitride semiconductor layer side at the interface with the nitride semiconductor layer, An object of the present invention is to provide a silicon substrate capable of improving the stability at the time of switching of a field effect transistor formed of a nitride semiconductor layer.
　また、この発明の課題は、上記シリコン基板を用いた窒化物半導体ウェハおよび窒化物半導体装置を提供することにある。 Another object of the present invention is to provide a nitride semiconductor wafer and a nitride semiconductor device using the silicon substrate.
　上記課題を解決するため、この発明のシリコン基板は、
　表面にIII族窒化物半導体層を形成可能なｐ型のシリコン基板であって、
　表面の抵抗率が１Ω・ｃｍ以上かつ１００Ω・ｃｍ未満であることを特徴とする。 In order to solve the above problems, the silicon substrate of the present invention is
A p-type silicon substrate capable of forming a group III nitride semiconductor layer on the surface,
The surface resistivity is 1 Ω · cm or more and less than 100 Ω · cm.
　また、一実施の形態のシリコン基板では、
　上記表面の抵抗率が１Ω・ｃｍ以上かつ３０Ω・ｃｍ未満である。 In the silicon substrate of one embodiment,
The surface resistivity is 1 Ω · cm or more and less than 30 Ω · cm.
　また、一実施の形態のシリコン基板では、
　基板厚さが０.６７５ｍｍ以上である。 In the silicon substrate of one embodiment,
The substrate thickness is 0.675 mm or more.
　また、この発明の窒化物半導体ウェハは、
　上記のいずれか１つのシリコン基板と、
　上記シリコン基板の上記表面に形成された上記III族窒化物半導体層からなるIII族窒化物積層体と
を備えたことを特徴とする。 The nitride semiconductor wafer of the present invention is
Any one of the above silicon substrates;
And a group III nitride laminate including the group III nitride semiconductor layer formed on the surface of the silicon substrate.
　また、この発明の窒化物半導体装置は、
　上記のいずれか１つのシリコン基板と、
　上記シリコン基板の表面に形成された上記III族窒化物半導体層からなる族窒化物積層体と、
　上記III族窒化物積層体上に形成されたソース電極,ドレイン電極およびゲート電極と
を備えたことを特徴とする。 The nitride semiconductor device of the present invention is
Any one of the above silicon substrates;
A group nitride laminate comprising the group III nitride semiconductor layer formed on the surface of the silicon substrate;
A source electrode, a drain electrode, and a gate electrode formed on the group III nitride laminate are provided.
　また、一実施の形態の窒化物半導体装置では、
　上記シリコン基板の厚さは、１００μｍ以上かつ２７５μｍ以下である。 In the nitride semiconductor device of one embodiment,
The thickness of the silicon substrate is 100 μm or more and 275 μm or less.
　また、一実施の形態の窒化物半導体装置では、
　上記III族窒化物積層体を構成するIII族窒化物半導体層の少なくとも１つは、炭素濃度が１×１０１８ｃｍ－３以上かつ１×１０２０ｃｍ－３以下の領域を有することを特徴とする。 In the nitride semiconductor device of one embodiment,
At least one of the group III nitride semiconductor layers constituting the group III nitride laminate has a region having a carbon concentration of 1 × 10 18 cm −3 or more and 1 × 10 20 cm −3 or less. To do.
　以上より明らかなように、この発明のシリコン基板は、ｐ型シリコン基板の抵抗率が１Ω・ｃｍ以上であるので、本シリコン基板上に上記III族窒化物積層体を成長させた場合に、シリコン基板とこのシリコン基板表面上に形成されたIII族窒化物積層体との界面におけるIII族窒化物積層体側に生ずる寄生容量を低減できる。さらに、不純物濃度の製造バラつきによる機械強度の変化率を抑制ことができる。 As is clear from the above, the silicon substrate of the present invention has a resistivity of 1 Ω · cm or more because the resistivity of the p-type silicon substrate is higher than that of the group III nitride laminate grown on the silicon substrate. The parasitic capacitance generated on the group III nitride laminate side at the interface between the substrate and the group III nitride laminate formed on the surface of the silicon substrate can be reduced. Furthermore, the rate of change in mechanical strength due to manufacturing variations in impurity concentration can be suppressed.
　さらに、上記ｐ型シリコン基板の抵抗率が１００Ω・ｃｍ未満であるので、シリコン基板上にIII族窒化物積層体を成長させた場合には、シリコン基板がフローティング状態となる周波数である遮断周波数をスイッチング周波数(１０ｋＨz～１０ＭＨz)よりも高めることができる。 Furthermore, since the resistivity of the p-type silicon substrate is less than 100 Ω · cm, when a group III nitride laminate is grown on the silicon substrate, a cutoff frequency, which is a frequency at which the silicon substrate is in a floating state, is set. It can be higher than the switching frequency (10 kHz to 10 MHz).
　また、この発明の窒化物半導体ウェハは、上記発明のシリコン基板を用いることによって、シリコン基板上にIII族窒化物積層体を成長させた場合に、シリコン基板とIII族窒化物積層体との界面に生ずる上記寄生容量を低減できる。その結果、上記寄生容量を充放電する際に必要な電荷量を低減することができる。さらに、不純物濃度の製造バラつきによる機械強度の変化率を抑制し、シリコン基板とIII族窒化物積層体との熱膨張係数差に起因する反りのバラつきを抑制できる。さらに、上記遮断周波数をスイッチング周波数よりも高めることができる。 The nitride semiconductor wafer according to the present invention is an interface between a silicon substrate and a group III nitride laminate when the group III nitride laminate is grown on the silicon substrate by using the silicon substrate according to the present invention. The parasitic capacitance generated in the above can be reduced. As a result, the amount of charge required when charging and discharging the parasitic capacitance can be reduced. Furthermore, the rate of change in mechanical strength due to manufacturing variations in impurity concentration can be suppressed, and variations in warpage due to differences in thermal expansion coefficients between the silicon substrate and the group III nitride laminate can be suppressed. Furthermore, the cutoff frequency can be made higher than the switching frequency.
　また、この発明の窒化物半導体装置は、上記発明の窒化物半導体ウェハを用いることによって、シリコン基板上にIII族窒化物積層体を成長させて電界効果トランジスタを形成した場合に、上記寄生容量(ドレイン出力容量Ｃoss)を低減できる。その結果、上記寄生容量を充放電する際に必要な電荷量を低減でき、スイッチング損失エネルギーを低減することができる。さらに、上記機械強度の変化率を抑制して、上記反りのバラつきを抑制できる。その結果、再現性良く安定して量産することができる。さらに、上記遮断周波数をスイッチング周波数よりも高めることができる。したがって、スイッチング時に発生する高調波および雑音を遮断し、安定に動作させることができる。 In addition, the nitride semiconductor device of the present invention uses the nitride semiconductor wafer of the present invention, so that when the field effect transistor is formed by growing a group III nitride stacked body on a silicon substrate, the parasitic capacitance ( The drain output capacitance (Coss) can be reduced. As a result, the amount of charge required when charging and discharging the parasitic capacitance can be reduced, and the switching loss energy can be reduced. Furthermore, the variation rate of the said mechanical strength can be suppressed and the variation of the said curvature can be suppressed. As a result, it can be mass-produced stably with good reproducibility. Furthermore, the cutoff frequency can be made higher than the switching frequency. Therefore, harmonics and noise generated at the time of switching can be cut off and the operation can be stably performed.
この発明の第１実施形態の窒化物半導体装置の一例としての電界効果トランジスタにおける概略断面図である。It is a schematic sectional drawing in the field effect transistor as an example of the nitride semiconductor device of 1st Embodiment of this invention. 図１に示す電界効果トランジスタにおける寄生容量の分布を示す図である。It is a figure which shows distribution of the parasitic capacitance in the field effect transistor shown in FIG. ドレイン出力容量Ｃossにおけるドレイン電圧Ｖdとの関係およびシリコン基板の抵抗率Ｒsiの依存性を示す図である。It is a figure which shows the dependence with respect to the drain voltage Vd in the drain output capacity Coss, and the resistivity Rsi of a silicon substrate. ドレイン出力容量Ｃossおよび遮断周波数ｆcにおけるシリコン基板の抵抗率Ｒsiの依存性を示す図である。It is a figure which shows the dependence of the resistivity Rsi of a silicon substrate in drain output capacity Coss and cutoff frequency fc. 上記第１実施形態のチップ片状態の電界効果トランジスタの斜視図である。It is a perspective view of the field effect transistor of the chip piece state of the first embodiment. この発明の第２実施形態のシリコン基板の斜視図である。It is a perspective view of the silicon substrate of 2nd Embodiment of this invention. 上記第２実施形態のチップ片状態のシリコン基板の斜視図である。It is a perspective view of the silicon substrate of the chip piece state of the said 2nd Embodiment. この発明の第３実施形態のシリコン基板上にIII族窒化物積層体をエピタキシャル成長させた窒化物半導体ウェハの斜視図である。It is a perspective view of the nitride semiconductor wafer which made the group III nitride laminated body epitaxially grow on the silicon substrate of 3rd Embodiment of this invention. 上記第３実施形態のチップ片状態を示す斜視図である。It is a perspective view which shows the chip piece state of the said 3rd Embodiment.
　以下、この発明のシリコン基板およびそれを用いた窒化物半導体ウェハ、並びに、窒化物半導体装置を図示の実施の形態により詳細に説明する。 Hereinafter, a silicon substrate of the present invention, a nitride semiconductor wafer using the silicon substrate, and a nitride semiconductor device will be described in detail with reference to the illustrated embodiments.
　〔第１実施形態〕
　図１は、本第１実施形態における窒化物半導体装置の一例としての電界効果トランジスタの概略断面図である。本電界効果トランジスタは、ＨＦＥＴ(Hetero-junction Field Effect Transistor：ヘテロ接合電界効果トランジスタ)である。 [First Embodiment]
FIG. 1 is a schematic cross-sectional view of a field effect transistor as an example of a nitride semiconductor device according to the first embodiment. The field effect transistor is an HFET (Hetero-junction Field Effect Transistor).
　図１に示すように、本電界効果トランジスタは、ｐ型シリコン基板１と、このｐ型シリコン基板１上に積層された複数の窒化物半導体層２～４と、この複数の窒化物半導体層２～４上に形成された第１窒化膜５と、ゲート電極８を形成するための開口部６と、第１窒化膜５上に形成されてゲート絶縁膜となる第２窒化膜７と、ゲート電極８と、第１酸化膜１２と、オーミックコンタクト部９と、ソースオーミック電極１０と、ドレインオーミック電極１１とを備え、その上に第２酸化膜(図示せず)とソース配線電極１３とドレイン配線電極１４とを備えている。 As shown in FIG. 1, the field effect transistor includes a p-type silicon substrate 1, a plurality of nitride semiconductor layers 2 to 4 stacked on the p-type silicon substrate 1, and a plurality of nitride semiconductor layers 2 1 to 4 formed on the first nitride film 5, an opening 6 for forming the gate electrode 8, a second nitride film 7 formed on the first nitride film 5 and serving as a gate insulating film, and a gate An electrode 8, a first oxide film 12, an ohmic contact portion 9, a source ohmic electrode 10, and a drain ohmic electrode 11 are provided, on which a second oxide film (not shown), a source wiring electrode 13, and a drain are provided. Wiring electrode 14 is provided.
　上記ｐ型シリコン基板１は、ボロンがドーピング(キャリア濃度１.０１×１０１４ｃｍ－３)された抵抗率が９９Ω・ｃｍのｐ型のＳi単結晶基板である。ここで、一般に、半導体の不純物の濃度は、半導体の抵抗率に反比例し、半導体の空乏層の幅は、上記不純物の濃度の平方根に比例する。また、上記空乏層による寄生容量は、上記空乏層の幅に反比例する。 The p-type silicon substrate 1 is a p-type Si single crystal substrate having a resistivity of 99 Ω · cm doped with boron (carrier concentration: 1.01 × 10 14 cm −3 ). Here, in general, the concentration of the semiconductor impurity is inversely proportional to the resistivity of the semiconductor, and the width of the semiconductor depletion layer is proportional to the square root of the impurity concentration. The parasitic capacitance due to the depletion layer is inversely proportional to the width of the depletion layer.
　本実施の形態においては、上記シリコン基板１の厚み方向全体に亘ってドーピング濃度を１.０１×１０１４ｃｍ－３としているが、上記窒化物半導体層と接する面のみを高抵抗としても問題はなく、シリコン基板１の表面に発生する最大空乏層の幅程度になっていればよい。しかしながら、シリコン基板１の機械的強度のバラつきを低減する目的では、シリコン基板１の厚み方向全体のドーピング濃度を制御した方がよいことは言うまでもない。 In the present embodiment, the doping concentration is 1.01 × 10 14 cm −3 over the entire thickness direction of the silicon substrate 1, but there is a problem even if only the surface in contact with the nitride semiconductor layer has a high resistance. The width of the maximum depletion layer generated on the surface of the silicon substrate 1 is sufficient. However, it goes without saying that it is better to control the doping concentration in the entire thickness direction of the silicon substrate 1 in order to reduce the variation in mechanical strength of the silicon substrate 1.
　上記積層された複数の窒化物半導体層２～４は、ＭＯＣＶＤ(Metal Organic Chemical Vapor Deposition：有機金属気相成長)装置を用いて形成されたＡlＮ／ＡlＧaＮ超格子バッファ層２とカーボン(炭素)ドープＧaＮ層３とＧaＮチャネル層４である。さらに、ＧaＮチャネル層４の上部にはＡl０.２Ｇa０.８Ｎから成る障壁層(図示せず)が形成されている。そして、ＡlＮ／ＡlＧaＮ超格子バッファ層２,カーボンドープ(耐圧)ＧaＮ層３およびＧaＮチャネル層４は、ｐ型シリコン基板１上に、順次エピタキシャル成長によって積層して形成されている。 The plurality of stacked nitride semiconductor layers 2 to 4 are composed of an AlN / AlGaN superlattice buffer layer 2 formed using a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus and carbon (carbon) doped. These are the GaN layer 3 and the GaN channel layer 4. Further, a barrier layer (not shown) made of Al 0.2 Ga 0.8 N is formed on the GaN channel layer 4. The AlN / AlGaN superlattice buffer layer 2, the carbon-doped (breakdown voltage) GaN layer 3, and the GaN channel layer 4 are sequentially stacked on the p-type silicon substrate 1 by epitaxial growth.
　上記ソースオーミック電極１０およびドレインオーミック電極１１は、Ｔi／Ａl合金からなるオーミック電極である。また、ゲート電極８は、Ｗ／ＷＮ積層構造からなる電極である。 The source ohmic electrode 10 and the drain ohmic electrode 11 are ohmic electrodes made of a Ti / Al alloy. The gate electrode 8 is an electrode having a W / WN laminated structure.
　本第１実施形態においては、窒化物半導体からなる電界効果トランジスタ(ＨＦＥＴ)の単一素子をトランジスタ素子としている。しかしながら、通常のＳi電界効果トランジスタとカスコード接続して複数素子を接続しても、スイッチング損失とシリコン基板の抵抗率の関係とは略同等であり、本発明を適用可能であることは言うまでもない。 In the first embodiment, a single element of a field effect transistor (HFET) made of a nitride semiconductor is used as a transistor element. However, even if a plurality of elements are connected by cascode connection with an ordinary Si field effect transistor, it goes without saying that the relationship between the switching loss and the resistivity of the silicon substrate is substantially the same, and the present invention can be applied.
　図２は、図１に示す上記電界効果トランジスタにおける寄生容量の分布を示した図である。電界効果トランジスタのスイッチング損失エネルギーの低減には、ドレイン出力容量Ｃossの充放電に必要な電荷量Ｑossを低減する必要がある。ここで、上記ドレイン出力容量Ｃossとは、「ドレインオーミック電極(ドレイン電極)１１付近に存在するドレイン部二次元電子ガス１５およびドレインオーミック電極１１」と、「シリコン基板１」との間の容量である。 FIG. 2 is a diagram showing the distribution of parasitic capacitance in the field effect transistor shown in FIG. In order to reduce the switching loss energy of the field effect transistor, it is necessary to reduce the charge amount Qoss necessary for charging / discharging the drain output capacitance Coss. Here, the drain output capacitance Coss is a capacitance between the “silicon substrate 1” and the “drain portion two-dimensional electron gas 15 and drain ohmic electrode 11 existing in the vicinity of the drain ohmic electrode (drain electrode) 11”. is there.
　上記「ドレイン出力容量Ｃoss」と「電荷量Ｑoss」との関係式は、下記の式(１)で表わされる。 The relational expression between the “drain output capacitance Coss” and the “charge amount Qoss” is expressed by the following equation (1).
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000001
　ここで、上記式(１)中における「Ｖdd」は、スイッチングを行う際における電源電圧である。本実施の形態においては４００Ｖとしている。しかしながら、用途によって電源電圧は調整することが可能である。 Here, “Vdd” in the above formula (1) is a power supply voltage at the time of switching. In this embodiment, it is set to 400V. However, the power supply voltage can be adjusted depending on the application.
　また、上記式(１)中における「Ｃoss」は、厳密には図２に示すように、窒化物半導体層２～４からなる窒化物積層体１６を窒化物エピタキシャル層として、ゲート‐ドレイン部二次元電子ガス間容量Ｃdgと、ソース‐ドレイン間容量Ｃdsと、ドレイン部二次元電子ガス‐窒化物エピタキシャル層間容量Ｃepiおよびシリコン基板容量Ｃsiの直列容量である合計容量Ｃdbとなる。しかしながら、そのうちで上記「Ｃoss」に最も影響を及ぼす主因子は、合計容量Ｃdbである。 In addition, strictly speaking, “Coss” in the above formula (1) indicates that the gate-drain portion 2 is formed by using the nitride laminated body 16 composed of the nitride semiconductor layers 2 to 4 as the nitride epitaxial layer as shown in FIG. The total capacitance Cdb is a series capacitance of the two-dimensional electron gas capacitance Cdg, the source-drain capacitance Cds, the drain portion two-dimensional electron gas-nitride epitaxial interlayer capacitance Cepi, and the silicon substrate capacitance Csi. However, the main factor that has the most influence on the “Coss” is the total capacity Cdb.
　上記シリコン基板１の抵抗率が低い、つまり不純物濃度が高い場合には、ドレイン電圧が印加された際にシリコン基板１の表面に発生する空乏層の厚みが小さくなる。そのため、シリコン基板１に形成されるシリコン基板容量Ｃsiは非常に大きく、合計容量Ｃdbは、ドレイン部二次元電子ガス‐窒化物エピタキシャル層間容量Ｃepiとの合計で決定されるために大きくなり、好ましくない。 When the resistivity of the silicon substrate 1 is low, that is, when the impurity concentration is high, the thickness of the depletion layer generated on the surface of the silicon substrate 1 when the drain voltage is applied becomes small. Therefore, the silicon substrate capacity Csi formed in the silicon substrate 1 is very large, and the total capacity Cdb is determined by the sum of the drain portion two-dimensional electron gas-nitride epitaxial interlayer capacity Cepi, which is not preferable. .
　また、上記シリコン基板１に印加される電圧をＶsiとした場合における不純物濃度Ｎaとシリコン基板容量Ｃsiとの関係は、下記式(２)で表わされる。 Further, the relationship between the impurity concentration Na and the silicon substrate capacitance Csi when the voltage applied to the silicon substrate 1 is Vsi is expressed by the following equation (2).
Figure JPOXMLDOC01-appb-M000002
 　　　　　但し、εsi：シリコン基板誘電率
　　　　　　　　　Ｓ：面積
　　　　　　　　　ｑ：電荷
Figure JPOXMLDOC01-appb-M000002
 Where ε si : dielectric constant of silicon substrate S: area q: charge
　例えば、上記シリコン基板１の抵抗率を０.０４Ω・ｃｍ(＜１Ω・ｃｍ)とした場合、その不純物濃度は１×１０１８ｃｍ－３であり、その場合の空乏層幅Ｗは０.３μｍしかなく、シリコン基板容量Ｃsiは非常に大きくなる。 For example, when the resistivity of the silicon substrate 1 is 0.04 Ω · cm (<1 Ω · cm), the impurity concentration is 1 × 10 18 cm −3 , and the depletion layer width W in that case is 0.3 μm. However, the silicon substrate capacitance Csi becomes very large.
　ここで、具体的なドレイン出力容量Ｃossの値を検証するために、デバイスシミュレータであるシルバコ社のＡＴＬＡＳを用いてデバイスシミュレーションを行った。本デバイスシミュレーションに用いた電界効果トランジスタの構造は、チップ面積が２.００ｍｍ×２.１５ｍｍであり、二次元電子ガス濃度が６.０×１０－１２ｃｍ－２である。 Here, in order to verify a specific value of the drain output capacitance Coss, a device simulation was performed using ATLAS of Silvaco, which is a device simulator. The structure of the field effect transistor used in this device simulation has a chip area of 2.00 mm × 2.15 mm and a two-dimensional electron gas concentration of 6.0 × 10 −12 cm −2 .
　図３は、上記シミュレーションされたドレイン出力容量Ｃossにおけるドレイン電圧Ｖdとの関係、および、シリコン基板１の抵抗率Ｒsiの依存性を示す。 FIG. 3 shows the relationship between the simulated drain output capacitance Coss and the drain voltage Vd, and the dependency of the resistivity Rsi of the silicon substrate 1.
　また、上記シリコン基板１を余りにも高抵抗にしてしまうと、通常接地されているべきシリコン基板１がフローティング状態となり、スイッチング時の高調波によって容易に誤動作を起こすという問題が発生する。シリコン基板１がフローティング状態となる周波数である遮断周波数ｆcは、シリコン基板１の抵抗率をＲsi、エピタキシャル層容量Ｃepiとシリコン基板容量Ｃsiとの合計容量をＣdbとすると、次式(３)のように表すことができる。 Further, if the silicon substrate 1 is made too high in resistance, the silicon substrate 1 that should normally be grounded will be in a floating state, causing a problem that malfunctions easily occur due to harmonics during switching. The cutoff frequency fc, which is the frequency at which the silicon substrate 1 is in a floating state, is expressed by the following equation (3), where Rsi is the resistivity of the silicon substrate 1 and Cdb is the total capacitance of the epitaxial layer capacitance Cepi and the silicon substrate capacitance Csi. Can be expressed as
Figure JPOXMLDOC01-appb-M000003
Figure JPOXMLDOC01-appb-M000003
　例えば、上記シリコン基板１の抵抗率Ｒsiを１０００Ω・ｃｍとすると、その遮断周波数ｆcは２００ＭＨzとなり、それ以下の周波数では本電界効果トランジスタの活性領域はフローティング状態となってしまう。 For example, if the resistivity Rsi of the silicon substrate 1 is 1000 Ω · cm, the cutoff frequency fc is 200 MHz, and the active region of the field effect transistor is in a floating state at a frequency lower than that.
　通常、電界効果トランジスタを電力変換素子として使用した場合、一般的にスイッチング周波数はおおよそ１０ｋＨz～１０ＭＨzである。また、窒化物半導体を用いた電界効果トランジスタの場合には、上記窒化物半導体が形成する二次元電子ガスが高い移動度を有しており、スイッチング時の電圧の立ち上がり／立ち下りは数ｎｓｅｃと非常に短い。そのために、スイッチング時に発生する高調波および雑音も増加する。したがって、シリコン基板１の抵抗率Ｒsiを１０００Ω・ｃｍと高くし過ぎた場合には、スイッチング周波数が上記遮断周波数ｆcと略同等の値となり、スイッチング動作の周波数自体でフローティング状態となってしまう。その結果、安定に動作することが困難となってしまう。 Usually, when a field effect transistor is used as a power conversion element, the switching frequency is generally about 10 kHz to 10 MHz. In the case of a field effect transistor using a nitride semiconductor, the two-dimensional electron gas formed by the nitride semiconductor has a high mobility, and the rise / fall of the voltage during switching is several nsec. Very short. For this reason, harmonics and noise generated during switching also increase. Therefore, if the resistivity Rsi of the silicon substrate 1 is too high, 1000Ω · cm, the switching frequency becomes substantially the same value as the cutoff frequency fc, and the switching operation frequency itself becomes a floating state. As a result, it becomes difficult to operate stably.
　以上のことより、望ましくは、スイッチング周波数を、スイッチング時における電圧の立ち上がり／立ち下りの時定数である数ｎｓｅｃ以上に、つまりスイッチング周波数は数ＧＨz望ましくは１ＧＨz以下に抑える必要がある。 From the above, it is desirable to suppress the switching frequency to several nsec or more, which is the time constant of voltage rise / fall during switching, that is, the switching frequency should be several GHz, preferably 1 GHz or less.
　図４は、図３の結果と上記式(３)で得られる遮断周波数ｆcとの関係を示したものである。図４より、ドレイン出力容量Ｃossに関しては、シリコン基板１の抵抗率Ｒsiが高いほど低くなる傾向があり、スイッチング時の損失を低減できる。一方、遮断周波数ｆcに関しては、シリコン基板１の抵抗率Ｒsiが１００Ω・ｃｍ以上になると、約６００ＭＨz未満まで低下する。 FIG. 4 shows the relationship between the result of FIG. 3 and the cutoff frequency fc obtained by the above equation (3). As shown in FIG. 4, the drain output capacitance Coss tends to be lower as the resistivity Rsi of the silicon substrate 1 is higher, and the loss during switching can be reduced. On the other hand, the cutoff frequency fc decreases to less than about 600 MHz when the resistivity Rsi of the silicon substrate 1 is 100 Ω · cm or more.
　そのために、上記シリコン基板１の抵抗率Ｒsiは、ドレイン出力容量Ｃossを低減するために１Ω・ｃｍ以上とし、スイッチング時に発生する高調波および雑音を遮断するために１００Ω・ｃｍ未満とすることが望ましい。さらには、上記シリコン基板１の抵抗率Ｒsiを１Ω・ｃｍ以上かつ３０Ω・ｃｍ未満の範囲とすれば、遮断周波数ｆcは１ＧＨz程度となり、より望ましい。 Therefore, the resistivity Rsi of the silicon substrate 1 is desirably 1 Ω · cm or more in order to reduce the drain output capacitance Coss, and less than 100 Ω · cm in order to cut off harmonics and noise generated during switching. . Furthermore, if the resistivity Rsi of the silicon substrate 1 is in the range of 1 Ω · cm to less than 30 Ω · cm, the cutoff frequency fc is about 1 GHz, which is more desirable.
　上述した効果を上記窒化物半導体層の厚膜化によって得ることは、応力による反りバラつき増加の観点から望ましくないことは言うまでもない。 Needless to say, obtaining the above-described effect by increasing the thickness of the nitride semiconductor layer is undesirable from the viewpoint of increasing warpage variation due to stress.
　上記シリコン基板１は、１Ω・ｃｍ以上の高抵抗基板であるため、空乏層が伸びやすく、ドレイン出力容量Cossを低くできる。 Since the silicon substrate 1 is a high-resistance substrate having a resistance of 1 Ω · cm or more, the depletion layer easily extends and the drain output capacitance Coss can be lowered.
　また、１Ω・ｃｍ以上の高抵抗のシリコン基板１は、Ｂ濃度が薄いため、表面にピットができにくいので、表面バラつきを改善することができ、機械加工が容易になる。 In addition, since the silicon substrate 1 having a high resistance of 1 Ω · cm or more has a low B concentration, it is difficult to form pits on the surface, so that surface variation can be improved and machining is facilitated.
　また、上記シリコン基板１のような高抵抗基板は、機械的強度のバラつきを小さくできるため、III族窒化物半導体層のエピタキシャル成長後の反りのバラつきも小さくできる。 Further, since the high resistance substrate such as the silicon substrate 1 can reduce the variation in mechanical strength, the variation in warpage after the epitaxial growth of the group III nitride semiconductor layer can also be reduced.
　また、上記シリコン基板１のような高抵抗基板は、シリコン結晶成長時の酸素が混入する量を制御しやすいため、すなわち、機械的強度に大きく関係する酸素濃度の制御が容易であるため、結果として機械強度のバラつき小さくできる。 Further, a high resistance substrate such as the silicon substrate 1 is easy to control the amount of oxygen mixed during silicon crystal growth, that is, it is easy to control the oxygen concentration largely related to the mechanical strength. As a result, the mechanical strength variation can be reduced.
　また、上記シリコン基板１は、単一の基板構造のため、コストを低減できる。 Moreover, since the silicon substrate 1 has a single substrate structure, the cost can be reduced.
　また、上記シリコン基板１の抵抗率を高くしすぎないことで、トランジスタ動作の安定性を向上できる。 Moreover, the stability of the transistor operation can be improved by not increasing the resistivity of the silicon substrate 1 too high.
　上記第１実施形態では、窒化物半導体装置であるＨＦＥＴについて説明したが、窒化物半導体装置はこれに限らず、他の構成の電界効果トランジスタにこの発明を適用してもよい。 In the first embodiment, the HFET which is a nitride semiconductor device has been described. However, the nitride semiconductor device is not limited to this, and the present invention may be applied to field effect transistors having other configurations.
　次に、上記構成を有する電界効果トランジスタの製造方法について説明する。 Next, a method for manufacturing a field effect transistor having the above configuration will be described.
　先ず、上記シリコン基板１を第２実施形態に記載の方法で形成し、さらに、窒化物半導体層２～４を第３実施形態に記載の方法で形成する。 First, the silicon substrate 1 is formed by the method described in the second embodiment, and the nitride semiconductor layers 2 to 4 are formed by the method described in the third embodiment.
　その後、プラズマＣＶＤ法によって、主に窒化ケイ素からなる第１窒化膜５を４０ｎｍ堆積し、ゲート部となる領域の第１窒化膜５をフッ化水素(０.５％)除去して開口部６を形成する。 Thereafter, a first nitride film 5 mainly made of silicon nitride is deposited by plasma CVD to a thickness of 40 nm, and the first nitride film 5 in the region to be the gate portion is removed with hydrogen fluoride (0.5%) to form the opening 6. Form.
　次に、プラズマＣＶＤ法によって、組成が主に窒化ケイ素であって、ゲート絶縁膜として作用する第２窒化膜７を２０ｎｍ堆積する。その後、スパッタリング法によってゲート電極８となるＷ／ＷＮ(Ｗ／ＷＮの厚さは夫々１００ｎｍ／２０ｎｍ)を堆積する。そうした後に、ドライエッチング法によって、ゲート電極８および第２窒化膜(ゲート絶縁膜)７を所望の形に成形する。 Next, a second nitride film 7 having a composition mainly of silicon nitride and acting as a gate insulating film is deposited by a plasma CVD method to a thickness of 20 nm. Thereafter, W / WN (W / WN thickness is 100 nm / 20 nm, respectively) to be the gate electrode 8 is deposited by sputtering. After that, the gate electrode 8 and the second nitride film (gate insulating film) 7 are formed into a desired shape by dry etching.
　その後、ソースコンタクト部およびドレインコンタクト部となる領域の第１窒化膜５を除去して、二箇所のオーミックコンタクト部９を所望の形状に形成する。その際におけるエッチングの深さは、少なくともＧaＮチャネル層４上層に形成されている上記Ａl０.２Ｇa０.８Ｎ障壁層を十分に取りきる必要があることは言うまでもない。 Thereafter, the first nitride film 5 in the region to be the source contact portion and the drain contact portion is removed, and the two ohmic contact portions 9 are formed in a desired shape. Needless to say, the etching depth at this time needs to sufficiently remove the Al 0.2 Ga 0.8 N barrier layer formed at least on the upper layer of the GaN channel layer 4.
　次に、上記オーミックコンタクト部９に、おもにＴi／Ａlからなる、ソースオーミック電極１０とドレインオーミック電極１１とを形成する。 Next, a source ohmic electrode 10 and a drain ohmic electrode 11 mainly made of Ti / Al are formed on the ohmic contact portion 9.
　上記ソースオーミック電極１０とドレインオーミック電極１１とは、ＧaＮチャネル層４中に形成される二次元電子ガス１５(図２に示す)とのオーミック性の電気的接続部を形成するものである。尚、上記二次元電子ガス１５とのオーミック性の電気的接続部を形成可能な方法であれば、上記オーミック電極による方法とは異なる方法を用いても差し支えない。 The source ohmic electrode 10 and the drain ohmic electrode 11 form an ohmic electrical connection with the two-dimensional electron gas 15 (shown in FIG. 2) formed in the GaN channel layer 4. A method different from the method using the ohmic electrode may be used as long as it is a method capable of forming an ohmic electrical connection with the two-dimensional electron gas 15.
　次に、プラズマＣＶＤ法によって、主に酸化ケイ素からなる第１酸化膜１２を厚さ１μｍで形成し、その後に、主にＡlを主原料とする配線を所望の形状に加工してソース配線電極１３とドレイン配線電極１４とを形成する。こうして、本電界効果トランジスタ(ＨＦＥＴ)が形成される。 Next, a first oxide film 12 mainly made of silicon oxide is formed with a thickness of 1 μm by plasma CVD, and then a wiring mainly made of Al is processed into a desired shape to form a source wiring electrode. 13 and the drain wiring electrode 14 are formed. Thus, the present field effect transistor (HFET) is formed.
　その場合、上記ソース配線電極１３は、横方向(図１中左右方向)にゲート電極８の位置よりもドレイン配線電極１４に向かって伸びるフィールドプレート構造を有しており、ゲート電極８付近の電界強度の最適化ができる長さにしている。 In that case, the source wiring electrode 13 has a field plate structure extending in the lateral direction (left-right direction in FIG. 1) from the position of the gate electrode 8 toward the drain wiring electrode 14, and the electric field in the vicinity of the gate electrode 8. The length is such that the strength can be optimized.
　さらに、上述のようにして電界効果トランジスタが形成されたウェハ状態の基板に対して、シリコン基板１の厚さを研磨処理によって２７５μｍに薄くする薄膜化処理を行う。ｐ型シリコン基板１の熱伝導率を向上させるためには、シリコン基板１の厚さは薄い方が望ましいのであるが、チップ化された場合における端面の欠けおよび反りを防止する観点から１００μｍ～２７５μｍ程度が好ましい。しかしながら、電界効果トランジスタにおける動作時に発生するジュール熱が低い場合には、その限りではない。 Further, a thinning process for reducing the thickness of the silicon substrate 1 to 275 μm by a polishing process is performed on the wafer-like substrate on which the field effect transistor is formed as described above. In order to improve the thermal conductivity of the p-type silicon substrate 1, it is desirable that the thickness of the silicon substrate 1 is thin. However, from the viewpoint of preventing chipping and warping of the end face when chipped, it is 100 μm to 275 μm. The degree is preferred. However, this is not the case when the Joule heat generated during operation of the field effect transistor is low.
　その後、上記ウェハ状態の基板上に複数形成されている電界効果トランジスタを各トランジスタに分離するために、ダイシングによってチップ化を図る。図５はチップ片状態の電界効果トランジスタの斜視図を示し、図５において、図１と同一の構成部には同一参照番号を付している。なお、図５では、第１酸化膜１２上の第２酸化膜,ソース配線電極１３およびドレイン配線電極１４は図示していない。 After that, in order to separate the plurality of field effect transistors formed on the wafer-state substrate into each transistor, dicing is performed to form a chip. FIG. 5 is a perspective view of a field effect transistor in a chip piece state. In FIG. 5, the same components as those in FIG. In FIG. 5, the second oxide film on the first oxide film 12, the source wiring electrode 13, and the drain wiring electrode 14 are not shown.
　そして、トランジスタの標準的パッケージであるＴＯ－２２０タイプのリードフレームにＳnＡgＣuを材料とする半田材料によってシリコン基板１を半田付けし、所望のワイヤリングを行った後に樹脂封止して、トランジスタ素子が完成する。 Then, the silicon substrate 1 is soldered to a TO-220 type lead frame, which is a standard transistor package, with a solder material made of SnAgCu, and the desired wiring is performed, followed by resin sealing to complete the transistor element. To do.
　〔第２実施形態〕
　図６はこの発明の第２実施形態のシリコン基板１(シリコンウェハ)の斜視図である。本第２実施形態においては、この発明の窒化物半導体ウェハ、特に窒化物半導体装置を形成するのに望ましいシリコン基板１およびその製造方法を示す。 [Second Embodiment]
FIG. 6 is a perspective view of a silicon substrate 1 (silicon wafer) according to the second embodiment of the present invention. In the second embodiment, a silicon substrate 1 desirable for forming a nitride semiconductor wafer of the present invention, particularly a nitride semiconductor device, and a method for manufacturing the same will be described.
　上記シリコン基板１の原料精製においては、先ず酸化ケイ素を還元してＳiとし、塩化水素を用いて高純度のトリクロロシラン(ＳiＨＣl３)を生成する。その後に、加熱処理を行って高純度のＳiを析出精製する。そして、こうして形成された高純度のＳiを石英製のルツボに導入し、１４５０℃の高温にしてＳiを溶融させる。その溶融Ｓi溶液に種結晶を付けて静かに回転しながら引き上げて、Ｓi単結晶インゴットを形成する。 In the raw material purification of the silicon substrate 1, first, silicon oxide is reduced to Si, and high-purity trichlorosilane (SiHCl 3 ) is generated using hydrogen chloride. Thereafter, heat treatment is performed to precipitate and purify high-purity Si. Then, the high-purity Si thus formed is introduced into a crucible made of quartz, and Si is melted at a high temperature of 1450 ° C. A seed crystal is attached to the molten Si solution and pulled up while rotating gently to form a Si single crystal ingot.
　上述のような原料精製の方法は、チョクラルスキー法(Czochralski法(ＣＺ法))と呼ばれるシリコンインゴット形成法である。しかしながら、他の手法として、石英ルツボを用いないことで低酸素濃度のＳi単結晶インゴットを成長させるフローティングゾーン法(Floating Zone法(ＦＺ法)および上記ＣＺ法において強力な磁場を掛けるMagnetic ＣＺ法(ＭＣＺ)法等を用いても問題ない。 The raw material refining method as described above is a silicon ingot forming method called Czochralski method (Czochralski method (CZ method)). However, as another method, a floating zone method in which a Si single crystal ingot having a low oxygen concentration is grown without using a quartz crucible (Floating に お い て Zone method (FZ method) and Magnetic CZ method in which a strong magnetic field is applied in the CZ method) There is no problem even if the MCZ method is used.
　上記ＣＺ法の場合には、上記Ｓi単結晶インゴットから切り出したシリコン基板１に所望のボロン(Ｂ)を導入し、約１４２０℃でＢをＳiと溶融させて、シリコン基板１中におけるＢ濃度が１×１０１４ｃｍ－３よりも大きくかつ１×１０１６ｃｍ－３以下、すなわち抵抗率が１Ω・ｃｍ以上かつ１００Ω・ｃｍ未満になるように調整し、ｐ型のＳi結晶を作製する。 In the case of the CZ method, desired boron (B) is introduced into the silicon substrate 1 cut out from the Si single crystal ingot, and B is melted with Si at about 1420 ° C., so that the B concentration in the silicon substrate 1 is increased. A p-type Si crystal is manufactured by adjusting the resistivity to be greater than 1 × 10 14 cm −3 and less than or equal to 1 × 10 16 cm −3 , that is, the resistivity is 1 Ω · cm or more and less than 100 Ω · cm.
　上述のように、本実施の形態における高抵抗シリコン基板１の抵抗率は、１Ω・ｃｍ以上かつ１００Ω・ｃｍ未満であり、より望ましくは１Ω・ｃｍ以上かつ３０Ω・ｃｍ未満である必要がある。この１Ω・ｃｍ以上かつ１００Ω・ｃｍ未満の抵抗率は、上記ＣＺ法で実現可能である。尚、製造コストや製造方法の観点からはＣＺ法がより望ましいが、上述したように、その他のシリコンインゴット形成法であっても上記所望の抵抗率のＳi結晶を作製することは可能である。 As described above, the resistivity of the high resistance silicon substrate 1 in the present embodiment needs to be 1 Ω · cm or more and less than 100 Ω · cm, more desirably 1 Ω · cm or more and less than 30 Ω · cm. This resistivity of 1 Ω · cm or more and less than 100 Ω · cm can be realized by the CZ method. Although the CZ method is more desirable from the viewpoint of manufacturing cost and manufacturing method, as described above, the Si crystal having the desired resistivity can be manufactured even by other silicon ingot forming methods.
　その後、外周研磨工程、オリフラ(オリエンテーションフラット：Orientation Flat)形成、スライス、研磨、最終洗浄工程を行って、シリコン基板１が形成される。その場合、シリコン基板１の面方位が(１１１)となるように形成する。これは、後に窒化物半導体積層膜を形成する場合に、格子定数の整合性が最も近い面方位であるからである。また、シリコン基板１の厚みは、例えば直径が６インチサイズの基板であれば、６２５μｍ以上にする必要があり、その後のエピタキシャル成長時における窒化物半導体との機械応力差に耐えるために、望ましくは１ｍｍ以上がよい。 Thereafter, a silicon substrate 1 is formed by performing an outer periphery polishing step, orientation flat (Orientation Flat) formation, slicing, polishing, and final cleaning steps. In that case, the silicon substrate 1 is formed so that the plane orientation is (111). This is because when the nitride semiconductor multilayer film is formed later, the lattice orientation is the closest plane orientation. Further, the thickness of the silicon substrate 1 needs to be 625 μm or more for a substrate having a diameter of 6 inches, for example, and preferably 1 mm in order to withstand the mechanical stress difference with the nitride semiconductor during the subsequent epitaxial growth. The above is good.
　なお、上記第２実施形態の図６では、ウェハ状態のシリコン基板１を示したが、図７に示すように、チップ片状態のシリコン基板１であってもよいことは言うまでもない。 In FIG. 6 of the second embodiment, the silicon substrate 1 in the wafer state is shown. Needless to say, however, the silicon substrate 1 in the chip piece state may be used as shown in FIG.
　〔第３実施形態〕
　図８はこの発明の第３実施形態のシリコン基板１(シリコンウェハ)上にIII族窒化物積層体１６をエピタキシャル成長させた窒化物半導体ウェハ１００の斜視図である。本第３実施形態においては、上記第２実施形態に示す製造方法で製造されたシリコン基板１上にIII族窒化物積層体１６をエピタキシャル成長させた窒化物半導体ウェハ１００を説明する。 [Third Embodiment]
FIG. 8 is a perspective view of a nitride semiconductor wafer 100 obtained by epitaxially growing a group III nitride laminate 16 on a silicon substrate 1 (silicon wafer) according to a third embodiment of the present invention. In the third embodiment, a nitride semiconductor wafer 100 obtained by epitaxially growing a group III nitride stacked body 16 on the silicon substrate 1 manufactured by the manufacturing method shown in the second embodiment will be described.
　この第３実施形態では、上記第１実施形態の電界効果トランジスタの形成に用いられる窒化物半導体ウェハ１００について説明する。 In the third embodiment, a nitride semiconductor wafer 100 used for forming the field effect transistor of the first embodiment will be described.
　図１において、１はｐ型シリコン基板、２はＡlＮ／ＡlＧaＮ超格子バッファ層、３はカーボンドープＧaＮ層、４はＧaＮチャネル層である。また、８はゲート電極、１０はソースオーミック電極(ソース電極)、１１はドレインオーミック電極(ドレイン電極)である。　 In FIG. 1, 1 is a p-type silicon substrate, 2 is an AlN / AlGaN superlattice buffer layer, 3 is a carbon-doped GaN layer, and 4 is a GaN channel layer. Further, 8 is a gate electrode, 10 is a source ohmic electrode (source electrode), and 11 is a drain ohmic electrode (drain electrode). *
　このＡlＮ／ＡlＧaＮ超格子バッファ層２、カーボンドープＧaＮ層３、ＧaＮチャネル層４の夫々は、III族窒化物半導体層の一例であり、ＡlＮ／ＡlＧaＮ超格子バッファ層２とカーボンドープＧaＮ層３およびＧaＮチャネル層４でIII族窒化物積層体１６を構成している。 Each of the AlN / AlGaN superlattice buffer layer 2, the carbon-doped GaN layer 3, and the GaN channel layer 4 is an example of a group III nitride semiconductor layer. The AlN / AlGaN superlattice buffer layer 2, the carbon-doped GaN layer 3, The GaN channel layer 4 constitutes a group III nitride laminate 16.
　上記ｐ型シリコン基板１は、上記第２実施形態で述べた方法によって形成している。 The p-type silicon substrate 1 is formed by the method described in the second embodiment.
　また、上記III族窒化物半導体層は、ｐ型シリコン基板１上にＭＯＣＶＤ(Metal Organic Chemical Vapor Deposition：有機金属気相成長)装置を用いて形成する。 The group III nitride semiconductor layer is formed on the p-type silicon substrate 1 by using a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus.
　上記構成の窒化物半導体ウェハ１００によれば、シリコン基板１として、抵抗率が１Ω・ｃｍ以上のｐ型基板を用いているので、シリコン基板１上に、ＡlＮ／ＡlＧaＮ超格子バッファ層２,カーボンドープＧaＮ層３およびＧaＮチャネル層４からなるIII族窒化物積層体１６を成長させた場合に、シリコン基板１とIII族窒化物積層体１６との界面におけるIII族窒化物積層体１６側に生ずる寄生容量を低減できる。その結果、上記寄生容量を充放電する際に必要な電荷量を低減することができる。さらに、不純物濃度の製造バラつきによる機械強度の変化率を抑制し、シリコン基板１とIII族窒化物積層体１６との熱膨張係数差に起因する反りのバラつきを抑制できる。 According to the nitride semiconductor wafer 100 having the above configuration, a p-type substrate having a resistivity of 1 Ω · cm or more is used as the silicon substrate 1, so that the AlN / AlGaN superlattice buffer layer 2, carbon When the group III nitride laminate 16 composed of the doped GaN layer 3 and the GaN channel layer 4 is grown, it is generated on the group III nitride laminate 16 side at the interface between the silicon substrate 1 and the group III nitride laminate 16. Parasitic capacitance can be reduced. As a result, the amount of charge required when charging and discharging the parasitic capacitance can be reduced. Furthermore, the rate of change in mechanical strength due to manufacturing variations in impurity concentration can be suppressed, and variations in warpage due to differences in thermal expansion coefficients between the silicon substrate 1 and the group III nitride laminate 16 can be suppressed.
　さらに、上記シリコン基板１として、抵抗率が１００Ω・ｃｍ未満であるｐ型基板を用いているので、上記シリコン基板１上にIII族窒化物積層体１６を成長させた場合には、上記遮断周波数ｆcをスイッチング周波数(１０ｋＨz～１０ＭＨz)よりも高めることができる。 Furthermore, since a p-type substrate having a resistivity of less than 100 Ω · cm is used as the silicon substrate 1, when the group III nitride laminate 16 is grown on the silicon substrate 1, the cutoff frequency is increased. fc can be made higher than the switching frequency (10 kHz to 10 MHz).
　なお、上記第３実施形態の図８では、窒化物半導体ウェハ１００(ウェハ状態)を示したが、図９に示すように、チップ片状態であってもよいことは言うまでもない。図９では、図１と同一の構成部に同一参照番号を付している。 In FIG. 8 of the third embodiment, the nitride semiconductor wafer 100 (wafer state) is shown, but it goes without saying that it may be in a chip piece state as shown in FIG. In FIG. 9, the same reference numerals are given to the same components as those in FIG.
　この発明の具体的な実施の形態について説明したが、この発明は上記第１～第３実施形態に限定されるものではなく、この発明の範囲内で種々変更して実施することができる。 Although specific embodiments of the present invention have been described, the present invention is not limited to the first to third embodiments, and various modifications can be made within the scope of the present invention.
　この発明および実施形態をまとめると、次のようになる。 The invention and the embodiment are summarized as follows.
　この発明のシリコン基板は、
　表面にIII族窒化物半導体層２,３,４を形成可能なｐ型のシリコン基板１であって、
　表面の抵抗率が１Ω・ｃｍ以上かつ１００Ω・ｃｍ未満であることを特徴とする。 The silicon substrate of the present invention is
A p-type silicon substrate 1 capable of forming group III nitride semiconductor layers 2, 3, and 4 on its surface,
The surface resistivity is 1 Ω · cm or more and less than 100 Ω · cm.
　上記構成によれば、上記ｐ型のシリコン基板１の抵抗率が１Ω・ｃｍ以上であるので、本シリコン基板１上に上記III族窒化物積層体１６を成長させた場合に、シリコン基板１とこのシリコン基板１表面に形成されたIII族窒化物積層体１６との界面におけるIII族窒化物積層体１６側に生ずる寄生容量を低減できる。さらに、不純物濃度の製造バラつきによる機械強度の変化率を抑制することができる。 According to the above configuration, since the resistivity of the p-type silicon substrate 1 is 1 Ω · cm or more, when the group III nitride laminate 16 is grown on the silicon substrate 1, The parasitic capacitance generated on the group III nitride laminate 16 side at the interface with the group III nitride laminate 16 formed on the surface of the silicon substrate 1 can be reduced. Furthermore, the rate of change in mechanical strength due to manufacturing variations in impurity concentration can be suppressed.
　さらに、上記ｐ型のシリコン基板１の抵抗率が１００Ω・ｃｍ未満とすることによって、本シリコン基板１上にIII族窒化物積層体１６を成長させた場合には、シリコン基板１がフローティング状態となる周波数である遮断周波数ｆcをスイッチング周波数(１０ｋＨz～１０ＭＨz)よりも高めることができる。 Further, by setting the resistivity of the p-type silicon substrate 1 to less than 100 Ω · cm, when the group III nitride laminate 16 is grown on the silicon substrate 1, the silicon substrate 1 is in a floating state. The cut-off frequency fc, which is a higher frequency, can be made higher than the switching frequency (10 kHz to 10 MHz).
　また、一実施の形態のシリコン基板では、
　上記表面の抵抗率が１Ω・ｃｍ以上かつ３０Ω・ｃｍ未満である。 In the silicon substrate of one embodiment,
The surface resistivity is 1 Ω · cm or more and less than 30 Ω · cm.
　この実施の形態によれば、上記ｐ型のシリコン基板１の抵抗率が３０Ω・ｃｍ未満であるので、上記遮断周波数ｆcを１ＧＨz程度にでき、より安定に動作させることができる。 According to this embodiment, since the resistivity of the p-type silicon substrate 1 is less than 30 Ω · cm, the cutoff frequency fc can be set to about 1 GHz, and the operation can be performed more stably.
　また、一実施の形態のシリコン基板１では、
　基板厚さが０.６７５ｍｍ以上である。 In the silicon substrate 1 of one embodiment,
The substrate thickness is 0.675 mm or more.
　この実施の形態によれば、シリコン基板１の基板厚さが０.６７５ｍｍ以上であるので、シリコン基板１上にIII族窒化物積層体１６を成長させる場合において、III族窒化物積層体１６との機械応力差に耐えることができる。 According to this embodiment, since the substrate thickness of the silicon substrate 1 is 0.675 mm or more, when the group III nitride laminate 16 is grown on the silicon substrate 1, the group III nitride laminate 16 and Can withstand the mechanical stress difference.
　また、この発明の窒化物半導体ウェハ１００は、
　上記のいずれか１つのシリコン基板１と、
　上記シリコン基板１の上記表面に形成された上記III族窒化物半導体層２,３,４からなるIII族窒化物積層体１６と
を備えたことを特徴とする。 The nitride semiconductor wafer 100 of the present invention is
Any one of the above silicon substrates 1,
And a group III nitride laminate 16 composed of the group III nitride semiconductor layers 2, 3, 4 formed on the surface of the silicon substrate 1.
　上記構成によれば、上記シリコン基板１として、抵抗率が１Ω・ｃｍ以上のｐ型基板を用いているので、シリコン基板１上にIII族窒化物半導体層２,３,４からなるIII族窒化物積層体１６を成長させた場合に、シリコン基板１とIII族窒化物積層体１６との界面におけるIII族窒化物積層体１６側に生ずる寄生容量を低減できる。その結果、上記寄生容量を充放電する際に必要な電荷量を低減することができる。さらに、不純物濃度の製造バラつきによる機械強度の変化率を抑制し、シリコン基板１とIII族窒化物積層体１６との熱膨張係数差に起因する反りのバラつきを抑制できる。 According to the above configuration, a p-type substrate having a resistivity of 1 Ω · cm or more is used as the silicon substrate 1, so that the group III nitride comprising the group III nitride semiconductor layers 2, 3, 4 on the silicon substrate 1 is used. When the product stack 16 is grown, the parasitic capacitance generated on the group III nitride stack 16 side at the interface between the silicon substrate 1 and the group III nitride stack 16 can be reduced. As a result, the amount of charge required when charging and discharging the parasitic capacitance can be reduced. Furthermore, the rate of change in mechanical strength due to manufacturing variations in impurity concentration can be suppressed, and variations in warpage due to differences in thermal expansion coefficients between the silicon substrate 1 and the group III nitride laminate 16 can be suppressed.
　さらに、上記シリコン基板１として、抵抗率が１００Ω・ｃｍ未満であるｐ型基板を用いているので、上記シリコン基板１上にIII族窒化物積層体１６を成長させた場合には、上記遮断周波数ｆcをスイッチング周波数(１０ｋＨz～１０ＭＨz)よりも高めることができる。 Furthermore, since a p-type substrate having a resistivity of less than 100 Ω · cm is used as the silicon substrate 1, when the group III nitride laminate 16 is grown on the silicon substrate 1, the cutoff frequency is increased. fc can be made higher than the switching frequency (10 kHz to 10 MHz).
　また、この発明の窒化物半導体装置は、
　上記のいずれか１つのシリコン基板１と、
　上記シリコン基板１の表面に形成された上記III族窒化物半導体層２,３,４からなるIII族窒化物積層体１６と、
　上記III族窒化物積層体１６上に形成されたソース電極１０,ドレイン電極１１およびゲート電極８と
を備えたことを特徴とする。 The nitride semiconductor device of the present invention is
Any one of the above silicon substrates 1,
A group III nitride laminate 16 composed of the group III nitride semiconductor layers 2, 3, 4 formed on the surface of the silicon substrate 1, and
A source electrode 10, a drain electrode 11, and a gate electrode 8 formed on the group III nitride laminate 16 are provided.
　上記構成によれば、シリコン基板１として、抵抗率が１Ω・ｃｍ以上のｐ型基板を用いることによって、シリコン基板１上にIII族窒化物半導体層２,３,４からなるIII族窒化物積層体１６を成長させて電界効果トランジスタを形成した場合に、シリコン基板１とIII族窒化物積層体１６との界面におけるIII族窒化物積層体１６側に生ずる寄生容量(ドレイン出力容量Ｃoss)を低減できる。その結果、上記寄生容量を充放電する際に必要な電荷量を低減でき、スイッチング損失エネルギーを低減することができる。さらに、不純物濃度の製造バラつきによる機械強度の変化率を抑制し、シリコン基板１とIII族窒化物積層体１６との熱膨張係数差に起因する反りのバラつきを抑制できる。その結果、再現性良く安定して量産することができる。 According to the above-described configuration, a group III nitride stack composed of group III nitride semiconductor layers 2, 3, and 4 is formed on the silicon substrate 1 by using a p-type substrate having a resistivity of 1 Ω · cm or more as the silicon substrate 1. When the field effect transistor is formed by growing the body 16, the parasitic capacitance (drain output capacitance Coss) generated on the group III nitride stack 16 side at the interface between the silicon substrate 1 and the group III nitride stack 16 is reduced. it can. As a result, the amount of charge required when charging and discharging the parasitic capacitance can be reduced, and the switching loss energy can be reduced. Furthermore, the rate of change in mechanical strength due to manufacturing variations in impurity concentration can be suppressed, and variations in warpage due to differences in thermal expansion coefficients between the silicon substrate 1 and the group III nitride laminate 16 can be suppressed. As a result, it can be mass-produced stably with good reproducibility.
　さらに、上記シリコン基板１として、抵抗率が１００Ω・ｃｍ未満であるｐ型基板を用いることによって、シリコン基板１上にIII族窒化物積層体１６を成長させて電界効果トランジスタを形成した場合に、上記遮断周波数ｆcをスイッチング周波数(１０ｋＨz～１０ＭＨz)よりも高めることができる。したがって、スイッチング時に発生する高調波および雑音を遮断し、安定に動作させることができる。 Furthermore, when a field effect transistor is formed by growing a group III nitride laminate 16 on the silicon substrate 1 by using a p-type substrate having a resistivity of less than 100 Ω · cm as the silicon substrate 1, The cutoff frequency fc can be higher than the switching frequency (10 kHz to 10 MHz). Therefore, harmonics and noise generated at the time of switching can be cut off and the operation can be stably performed.
　また、一実施の形態の窒化物半導体装置では、
　上記シリコン基板１の厚さは、１００μｍ以上かつ２７５μｍ以下である。 In the nitride semiconductor device of one embodiment,
The thickness of the silicon substrate 1 is not less than 100 μm and not more than 275 μm.
　この実施の形態によれば、シリコン基板１の厚さを２７５μｍ以下にすることによって、シリコン基板１の熱伝導率を向上させ、動作時に発生するジュール熱を放熱することができる。 According to this embodiment, by setting the thickness of the silicon substrate 1 to 275 μm or less, the thermal conductivity of the silicon substrate 1 can be improved and the Joule heat generated during operation can be radiated.
　さらに、上記シリコン基板１の厚さを１００μｍ以上にすることによって、チップ化した場合における端面の欠けおよび反りを防止することができる。 Furthermore, by setting the thickness of the silicon substrate 1 to 100 μm or more, it is possible to prevent chipping and warping of the end face when the chip is formed.
　また、一実施の形態の窒化物半導体装置では、
　上記III族窒化物積層体１６を構成するIII族窒化物半導体層２,３,４の少なくとも１つは、炭素濃度が１×１０１８ｃｍ－３以上かつ１×１０２０ｃｍ－３以下の領域を有する。 In the nitride semiconductor device of one embodiment,
At least one of the group III nitride semiconductor layers 2, 3, and 4 constituting the group III nitride stacked body 16 has a carbon concentration of 1 × 10 18 cm −3 or more and 1 × 10 20 cm −3 or less. Have
　この実施の形態によれば、III族窒化物積層体１６を構成するIII族窒化物半導体層２,３,４の少なくとも１つの炭素濃度を、１×１０１８ｃｍ－３以上かつ１×１０２０ｃｍ－３以下とすることによって、絶縁耐圧の減少およびリーク電流の増加を防止することができる。 According to this embodiment, at least one carbon concentration of the group III nitride semiconductor layers 2, 3, and 4 constituting the group III nitride stacked body 16 is set to 1 × 10 18 cm −3 or more and 1 × 10 20. By setting it to cm −3 or less, it is possible to prevent a decrease in dielectric strength and an increase in leakage current.
１…ｐ型シリコン基板
２…ＡlＮ／ＡlＧaＮ超格子バッファ層
３…カーボンドープＧaＮ層
４…ＧaＮチャネル層
５…第１窒化膜
６…開口部
７…第２窒化膜
８…ゲート電極
９…オーミックコンタクト部
１０…ソースオーミック電極
１１…ドレインオーミック電極
１２…第１酸化膜
１３…ソース配線電極
１４…ドレイン配線電極
１５…ドレイン部二次元電子ガス
１６…窒化物積層体
１００…窒化物半導体ウェハ
Ｃdg…ゲート‐ドレイン部二次元電子ガス間容量
Ｃds…ソース‐ドレイン間容量
Ｃepi…ドレイン部二次元電子ガス‐窒化物エピタキシャル層間容量
Ｃsi…シリコン基板容量
Ｃdb…合計容量 DESCRIPTION OF SYMBOLS 1 ... p-type silicon substrate 2 ... AlN / AlGaN superlattice buffer layer 3 ... Carbon dope GaN layer 4 ... GaN channel layer 5 ... 1st nitride film 6 ... Opening 7 ... 2nd nitride film 8 ... Gate electrode 9 ... Ohmic contact Part 10 ... Source ohmic electrode 11 ... Drain ohmic electrode 12 ... First oxide film 13 ... Source wiring electrode 14 ... Drain wiring electrode 15 ... Drain part two-dimensional electron gas 16 ... Nitride stack 100 ... Nitride semiconductor wafer Cdg ... Gate -Drain portion two-dimensional electron gas capacitance Cds ... Source-drain capacitance Cepi ... Drain portion two-dimensional electron gas-nitride epitaxial interlayer capacitance Csi ... Si substrate capacitance Cdb ... Total capacitance

Claims (5)

  1. 　表面にIII族窒化物半導体層を形成可能なｐ型のシリコン基板であって、
    　表面の抵抗率が１Ω・ｃｍ以上かつ１００Ω・ｃｍ未満であることを特徴とするシリコン基板。     A p-type silicon substrate capable of forming a group III nitride semiconductor layer on the surface,
    A silicon substrate having a surface resistivity of 1 Ω · cm or more and less than 100 Ω · cm.
  2. 　請求項１に記載のシリコン基板において、
    　上記表面の抵抗率が１Ω・ｃｍ以上かつ３０Ω・ｃｍ未満であることを特徴とするシリコン基板。     The silicon substrate according to claim 1,
    A silicon substrate having a surface resistivity of 1 Ω · cm or more and less than 30 Ω · cm.
  3. 　請求項１または請求項２に記載のシリコン基板において、
    　基板厚さが０.６７５ｍｍ以上であることを特徴とするシリコン基板。     The silicon substrate according to claim 1 or 2,
    A silicon substrate having a substrate thickness of 0.675 mm or more.
  4. 　請求項１から請求項３までのいずれか１つに記載のシリコン基板と、
    　上記シリコン基板の上記表面に形成された上記III族窒化物半導体層からなるIII族窒化物積層体と
    を備えたことを特徴とする窒化物半導体ウェハ。     A silicon substrate according to any one of claims 1 to 3, and
    A nitride semiconductor wafer comprising: a group III nitride laminated body made of the group III nitride semiconductor layer formed on the surface of the silicon substrate.
  5. 　請求項１から請求項３までのいずれか１つに記載のシリコン基板と、
    　上記シリコン基板の表面に形成された上記III族窒化物半導体層からなるIII族窒化物積層体と、
    　上記III族窒化物積層体上に形成されたソース電極,ドレイン電極およびゲート電極と
    を備えたことを特徴とする窒化物半導体装置。     A silicon substrate according to any one of claims 1 to 3, and
    A group III nitride laminate comprising the group III nitride semiconductor layer formed on the surface of the silicon substrate;
    A nitride semiconductor device comprising a source electrode, a drain electrode, and a gate electrode formed on the group III nitride laminate.
PCT/JP2016/062384 2015-06-30 2016-04-19 Silicon substrate, nitride semiconductor wafer using same, and nitride semiconductor device WO2017002432A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023127520A1 (en) * 2021-12-27 2023-07-06 ローム株式会社 Nitride semiconductor device and manufacturing method therefor

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JPH0517293A (en) * 1991-07-05 1993-01-26 Nippon Steel Corp Method for cooling cz silicon
WO2013125126A1 (en) * 2012-02-23 2013-08-29 日本碍子株式会社 Semiconductor element and method for manufacturing semiconductor element

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0517293A (en) * 1991-07-05 1993-01-26 Nippon Steel Corp Method for cooling cz silicon
WO2013125126A1 (en) * 2012-02-23 2013-08-29 日本碍子株式会社 Semiconductor element and method for manufacturing semiconductor element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023127520A1 (en) * 2021-12-27 2023-07-06 ローム株式会社 Nitride semiconductor device and manufacturing method therefor

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