WO2017000517A1 - 应用于固态硬盘阻变存储器缓存的纠错保护架构及方法 - Google Patents

应用于固态硬盘阻变存储器缓存的纠错保护架构及方法 Download PDF

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WO2017000517A1
WO2017000517A1 PCT/CN2015/098137 CN2015098137W WO2017000517A1 WO 2017000517 A1 WO2017000517 A1 WO 2017000517A1 CN 2015098137 W CN2015098137 W CN 2015098137W WO 2017000517 A1 WO2017000517 A1 WO 2017000517A1
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mapping table
address
cache
information
grained management
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PCT/CN2015/098137
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French (fr)
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孙宏滨
杨阳
张瑞智
郑南宁
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西安交通大学
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation

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  • the invention belongs to the field of non-volatile memory resistive memory design, and relates to an error correction protection architecture and method applied to a solid state hard disk resistive memory buffer.
  • the cache in the SSD system can effectively reduce the host's access to the flash memory, which plays an important role in improving the performance of the whole system.
  • the traditional dynamic random access memory-based cache has large leakage current, power loss information, and high static power.
  • the problem of consumption, non-volatile memory resistive memory has the advantages of high density, fast read/write speed, low power consumption, etc., and is considered as an ideal replacement for dynamic random access memory in SSD systems, but the resistive memory is reliable.
  • Sexual problems, especially the resistive memory memory of the cross-array structure as the length of the array increases, the crosstalk becomes larger and larger, and the reliability problem becomes more prominent.
  • non-volatile memory As a cache for external storage devices.
  • a typical cache mainly stores cached user data, and physical page number (PPP). ) and a small amount of other data such as firmware.
  • PPP physical page number
  • the memory device only has a user bit error rate lower than 10 -15 to meet the user's needs.
  • the resistive memory buffer has a high original bit error rate, it can be protected by the error correcting code to meet the user bit error rate requirement.
  • the codec coding and decoding principle the longer the code length, the higher the code rate, and the smaller the error correction code redundancy.
  • the bit error rate is 10 -4
  • the BCH codec with the traditional Galois field is 2
  • the code length is For 4B, 30-bit redundancy is required, and the same original bit error rate requires 416 bits for the 4 KB redundancy, so the error correction code length is different and the redundancy is very different.
  • the object of the present invention is to overcome the above disadvantages of the prior art, and to provide an error correction protection architecture and method for a solid state hard disk resistive memory cache, which can efficiently and reliably acquire read address table address information. And the redundant space consumed is limited.
  • the code length of the coarse-grained management mapping table used in the error correction protection architecture of the solid-state hard disk resistive memory cache is the same as the code length of the page cache data, and is coarse in the data processing process.
  • the mapping table address information of the granularity management mapping table whose access frequency is greater than the preset value is stored in the fine-grained management mapping table cache, and the entry of a coarse-grained management mapping table is formed by 1024 address mapping tables, and fine-grained management
  • Each entry in the mapping table cache includes a mapping table information and error correction code redundancy of a mapping table information;
  • the exchange data between the fine-grained management map cache and the coarse-grained management map is in page units, and all the one-page mapping table information read from the coarse-grained management mapping table is placed in the fine-grained management mapping table.
  • the one-page mapping table information is formed by splicing 1024 mapping table information, and the last 10 bits in the input logical address request are used as offset bits, and the remaining bits in the input logical address are used as index bits.
  • the error correction protection method applied to the solid state hard disk resistive memory cache according to the present invention includes the following steps:
  • the input logical address request is divided into an index bit and an offset bit, and the index bit is used to search the fine-grained management map cache.
  • the input logical address request is hit in the fine-grained management map cache, according to the input Offset address request from page containing request mapping table information Reading out the corresponding mapping table address information; when the input logical address request does not hit in the fine-grained management mapping table cache, the page containing the request mapping table information is found out from the coarse-grained management mapping table, when When the granularity management map cache has space, the page containing the request mapping table information is directly read out from the coarse-grained management mapping table, and the read page containing the request mapping table information is written to the fine-grained management policy.
  • Fine-grained management of the mapping table cache when there is no space in the fine-grained management mapping table cache, the last page in the fine-grained management mapping table cache is written back to the coarse-grained management mapping table according to the coarse-grained policy, Then, the page containing the request mapping table information is written into the fine-grained management mapping table cache according to the fine-grained management policy, and finally the corresponding mapping table address information is read out from the page containing the request mapping table information according to the offset address request.
  • the fine-grained management table cache can cache the mapping table address information of multiple pages, wherein the mapping table address information of each page is a flash physical address corresponding to 1024 consecutive logical addresses, and the mapping table address information of each page is The logical address corresponding to the first physical address of the flash memory is the logical address index of the page;
  • the size of each address information entry is composed of an address mapping information and an error correction code of the address mapping information.
  • index entries are stored in the static random access memory of the SSD system
  • the cache data mapping table and the mapping table cache index array are stored in the SRAM of the SSD system
  • the address mapping table information is stored in the off-chip cache resistive memory of the SSD system.
  • the error correction protection architecture and method applied to the solid state hard disk resistive memory cache when operating, the code length of the coarse-grained management mapping table is the same as the code length of the page cache data, and the mapping with a larger access frequency is used.
  • the table address information is stored in the fine-grained management mapping table, which greatly reduces the error correction redundancy loss and ensures the speed of the mapping table access.
  • an entry of a coarse-grained management mapping table is formed by 1024 address mapping tables, and the exchange data between the fine-grained management mapping table cache and the coarse-grained management mapping table is in units of pages, and one page at the same time.
  • mapping table information is spliced by 1024 mapping table information, thereby effectively improving the hit rate of the mapping table cache.
  • the present invention reduces the redundancy space loss of the error correction code in the mapping table and ensures the speed, and the performance of the overall solid state hard disk system is significantly improved.
  • the logical address corresponding to the first physical address of the flash memory in the mapping address information of each page is the logical address index of the page, which effectively increases the speed of the index and reduces the error rate of the index.
  • Figure 1 is a structural view of the present invention
  • Figure 2 is a flow chart of the present invention
  • FIG. 3 is a management structure diagram of a mapping table cache of fine-grained management in the present invention.
  • FIG. 4 is a structural diagram of a hybrid error correction protection solid state hard disk system on an on-chip index array.
  • the code length of the coarse-grained management mapping table in the error correction protection architecture applied to the solid-state hard disk resistive memory cache is the same as the code length of the page cache data, and coarse-grained in the data processing process.
  • the mapping table address information of the management mapping table whose access frequency is greater than the preset value is stored in the fine-grained management mapping table cache, and the entry of a coarse-grained management mapping table is formed by 1024 address mapping tables, and is finely managed.
  • Each entry in the mapping table cache contains a mapping table information and error correction code redundancy of a mapping table information; the exchange data between the fine-grained management mapping table cache and the coarse-grained management mapping table is in units of pages,
  • the one-page mapping table information read out from the coarse-grained management mapping table is all placed in the fine-grained management mapping table cache, wherein one-page mapping table information is formed by splicing 1024 mapping table information, and the logical address to be input is input.
  • the last 10 bits in the request are used as offset bits, and the remaining bits in the input logical address are used as index bits.
  • an error correction protection method applied to a solid state hard disk resistive memory cache includes the following steps:
  • the input logical address request is divided into an index bit and an offset bit, and the index bit is used to find a fine-grained management mapping table.
  • the shift address request reads the corresponding mapping table address information from the page containing the request mapping table information; when the input logical address request does not hit in the fine-grained management mapping table cache, it searches from the coarse-grained management mapping table A page containing the information of the request mapping table, when the fine-grained management map cache has space, the page containing the request mapping table information is directly read from the coarse-grained management mapping table, and the read-containing request mapping is mapped.
  • the pages of the table information are written to the fine-grained management map cache in a fine-grained management policy; If there is no space in the mapping table cache, the last page in the fine-grained management table cache is written back to the coarse-grained management mapping table according to the coarse-grained policy, and then the page containing the request mapping table information is The fine-grained management policy is written into the fine-grained management map cache, and finally the corresponding mapping table address information is read out from the page containing the request mapping table information according to the offset address request.
  • the fine-grained management mapping table cache can cache mapping table address information of multiple pages, wherein the mapping table address information of each page is a flash physical address corresponding to 1024 consecutive logical addresses, and mapping of each page
  • the logical address corresponding to the first flash physical address in the table address information is the logical address index of the page; when the accessed logical address request is hit in the fine-grained management map cache, according to the index number corresponding to the index bit,
  • the first address of the address mapping table information stored in the resistive memory, the size of each address information entry, and the location of the required address mapping table information in the page offset, wherein the location of the required address mapping table information resistive memory
  • the error correction code of the address mapping information is redundant.
  • the index entries are stored in the static random access memory of the SSD system
  • the cache data mapping table and the mapping table cache index array are stored in the SRAM of the SSD system
  • the address mapping table information is stored in the off-chip cache of the SSD system. Resistive memory.

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Abstract

一种应用于固态硬盘阻变存储器缓存的纠错保护架构及方法，粗粒度管理的映射表的码长与页缓存数据的码长相同，在数据处理过程中，将粗粒度管理的映射表中访问频率大于预设值的映射表地址信息存储到细粒度管理的映射表缓存中；细粒度管理的映射表缓存与粗粒度管理的映射表之间的交换数据以页为单位，将从粗粒度管理的映射表中读出的一页映射表信息全部放在细粒度管理的映射表缓存中，将输入的逻辑地址请求中的后10位作为偏移位，将输入的逻辑地址中的剩余位作为索引位。该纠错保护框架能够高效、可靠的获取读出映射表地址信息，并且消耗的冗余空间有限。

Description

应用于固态硬盘阻变存储器缓存的纠错保护架构及方法 技术领域
本发明属于非易失性存储器阻变存储器设计领域，涉及一种应用于固态硬盘阻变存储器缓存的纠错保护架构及方法。
背景技术
固态硬盘系统中的缓存能有效减少主机对闪存的访问，对提高整个系统的性能有重要作用，传统的基于动态随机存取存储器的缓存存在大的漏电流、断电丢失信息、高的静态功耗等问题，非易失性存储器阻变存储器具有密度高、读写速度快、低功耗等优点，被认为是固态硬盘系统中动态随机存取存储器的理想替代者，但是阻变存储器存在可靠性的问题，尤其交叉阵列结构的阻变存储器存储器，随着阵列长度的增加，串扰会越来越大，可靠性问题更加突出。
随着非易失性存储器的发展，使用非易失性存储器作为外部存储设备的缓存已经变得切实可行，典型的缓存中主要存放着缓存的用户数据，映射表信息(Physical page number，简称PPN)以及少量的固件等其它数据。
众所周知，存储器设备只有用户比特错误率低于10-15才能满足用户需求，虽然阻变存储器缓存原始比特错误率高，但是可以通过纠错码的保护来使其满足用户比特错误率的要求。根据纠错码编解码原理，码长越长码率越高那么纠错码冗余越小，比如，比特错误率为10-4，采用传统伽罗华域为2的BCH编解码，码长为4B时需要30bit的冗余，而同 样原始比特错误率，码长为4KB冗余需要416bit，所以纠错码码长不同其冗余相差很大。
发明内容
本发明的目的在于克服上述现有技术的缺点，提供了一种应用于固态硬盘阻变存储器缓存的纠错保护架构及方法，该架构及方法能够高效、可靠的获取读出映射表地址信息，并且消耗的冗余空间有限。
为达到上述目的，本发明所述的应用于固态硬盘阻变存储器缓存的纠错保护架构中粗粒度管理的映射表的码长与页缓存数据的码长相同，在数据处理过程中，将粗粒度管理的映射表中访问频率大于预设值的映射表地址信息存储到细粒度管理的映射表缓存中，一个粗粒度管理的映射表的条目由1024个地址映射表拼而成，细粒度管理的映射表缓存中的各条目均包含一个映射表信息以及一个映射表信息的纠错码冗余；
细粒度管理的映射表缓存与粗粒度管理的映射表之间的交换数据以页为单位，将从粗粒度管理的映射表中读出的一页映射表信息全部放在细粒度管理的映射表缓存中，其中，一页映射表信息由1024个映射表信息拼接而成，将输入的逻辑地址请求中的后10位作为偏移位，将输入的逻辑地址中的剩余位作为索引位。
本发明所述的应用于固态硬盘阻变存储器缓存的纠错保护方法包括以下步骤：
将输入的逻辑地址请求分为索引位和偏移位，通过索引位来查找细粒度管理的映射表缓存，当输入的逻辑地址请求在细粒度管理的映射表缓存中命中时，则根据输入的偏移地址请求从包含请求映射表信息的页 中读出对应的映射表地址信息；当输入的逻辑地址请求在细粒度管理的映射表缓存中没有命中时，则从粗粒度管理的映射表中找出包含请求映射表信息的页，当细粒度管理的映射表缓存有空间时，则直接将从粗粒度管理的映射表中读出包含请求映射表信息的页，并将读出的包含请求映射表信息的页按细粒度管理策略写到细粒度管理的映射表缓存中；当细粒度管理的映射表缓存中没有空间，则根据粗粒度策略将细粒度管理的映射表缓存中的最后一页写回到粗粒度管理的映射表中，然后再将包含请求映射表信息的页根据细粒度管理策略写到细粒度管理的映射表缓存中，最后根据偏移地址请求从包含请求映射表信息的页中读出对应的映射表地址信息。
细粒度管理的映射表缓存能够缓存多个页的映射表地址信息，其中，每一页的映射表地址信息均为1024个连续逻辑地址对应的闪存物理地址，每一页的映射表地址信息中的第一个闪存物理地址对应的逻辑地址为该页的逻辑地址索引；
当访问的逻辑地址请求在细粒度管理的映射表缓存中命中时，则根据索引位对应的索引号、阻变存储器中存放地址映射表信息的首地址、每个地址信息条目的大小、以及页内偏移得所需地址映射表信息所在位置，其中，所需地址映射表信息所在位置＝阻变存储器中存放地址映射表信息的首地址+每个地址信息条目的大小×1024×索引号+页内偏移×每个地址信息条目的大小。
每个地址信息条目的大小由一个地址映射信息和该地址映射信息的纠错码冗组成。
将索引条目存储到固态硬盘系统的静态随机存储器，高速缓存数据映射表及映射表缓存索引阵列存储到固态硬盘系统的SRAM中，地址映射表信息存储到固态硬盘系统的片外缓存阻变存储器中。
本发明具有以下有益效果：
本发明所述的应用于固态硬盘阻变存储器缓存的纠错保护架构及方法在操作时，粗粒度管理的映射表的码长与页缓存数据的码长相同，并且将访问频率较大的映射表地址信息存储到细粒度管理的映射表中，极大的减少纠错冗余损耗，同时保证映射表访问的速度。另外，一个粗粒度管理的映射表的条目由1024个地址映射表拼而成，同时在细粒度管理的映射表缓存与粗粒度管理的映射表之间的交换数据以页为单位，同时一页映射表信息由1024个映射表信息拼接而成，从而有效地提高映射表缓存的命中率。综上，本发明减少了映射表中纠错码冗余空间损耗又保证了速度，对整体固态硬盘系统性能有显著提升。
进一步，每一页的映射表地址信息中的第一个闪存物理地址对应的逻辑地址为该页的逻辑地址索引，有效的提高索引的速度，降低索引的出错率。
附图说明
图1为本发明的结构图；
图2为本发明的流程图；
图3为本发明中细粒度管理的映射表缓存的管理结构图；
图4为索引阵列在片上的混合纠错保护固态硬盘系统架构图。
具体实施方式
下面结合附图对本发明做进一步详细描述：
参考图1，本发明所述的应用于固态硬盘阻变存储器缓存的纠错保护架构中粗粒度管理的映射表的码长与页缓存数据的码长相同，在数据处理过程中，将粗粒度管理的映射表中访问频率大于预设值的映射表地址信息存储到细粒度管理的映射表缓存中，一个粗粒度管理的映射表的条目由1024个地址映射表拼而成，细粒度管理的映射表缓存中的各条目均包含一个映射表信息以及一个映射表信息的纠错码冗余；细粒度管理的映射表缓存与粗粒度管理的映射表之间的交换数据以页为单位，将从粗粒度管理的映射表中读出的一页映射表信息全部放在细粒度管理的映射表缓存中，其中，一页映射表信息由1024个映射表信息拼接而成，将输入的逻辑地址请求中的后10位作为偏移位，将输入的逻辑地址中的剩余位作为索引位。
参考图2，本发明所述的应用于固态硬盘阻变存储器缓存的纠错保护方法包括以下步骤：
将输入的逻辑地址请求分为索引位和偏移位，通过索引位来查找细粒度管理的映射表，当输入的逻辑地址请求在细粒度管理的映射表缓存中命中时，则根据输入的偏移地址请求从包含请求映射表信息的页中读出对应的映射表地址信息；当输入的逻辑地址请求在细粒度管理的映射表缓存中没有命中时，则从粗粒度管理的映射表中找出包含请求映射表信息的页，当细粒度管理的映射表缓存有空间时，则直接将从粗粒度管理的映射表中读出包含请求映射表信息的页，并将读出的包含请求映射表信息的页按细粒度管理策略写到细粒度管理的映射表缓存中；当细粒 度管理的映射表缓存中没有空间，则根据粗粒度策略将细粒度管理的映射表缓存中的最后一页写回到粗粒度管理的映射表中，然后再将包含请求映射表信息的页根据细粒度管理策略写到细粒度管理的映射表缓存中，最后根据偏移地址请求从包含请求映射表信息的页中读出对应的映射表地址信息。
参考图3，细粒度管理的映射表缓存能够缓存多个页的映射表地址信息，其中，每一页的映射表地址信息均为1024个连续逻辑地址对应的闪存物理地址，每一页的映射表地址信息中的第一个闪存物理地址对应的逻辑地址为该页的逻辑地址索引；当访问的逻辑地址请求在细粒度管理的映射表缓存中命中时，则根据索引位对应的索引号、阻变存储器中存放地址映射表信息的首地址、每个地址信息条目的大小、以及页内偏移得所需地址映射表信息所在位置，其中，所需地址映射表信息所在位置＝阻变存储器中存放地址映射表信息的首地址+每个地址信息条目的大小×1024×索引号+页内偏移×每个地址信息条目的大小，每个地址信息条目的大小由一个地址映射信息和该地址映射信息的纠错码冗余组成。
参考图4，将索引条目存储到固态硬盘系统的静态随机存储器，高速缓存数据映射表及映射表缓存索引阵列存储到固态硬盘系统的SRAM中，地址映射表信息存储到固态硬盘系统的片外缓存阻变存储器中。

Claims (5)

  1. 一种应用于固态硬盘阻变存储器缓存的纠错保护架构，其特征在于，粗粒度管理的映射表的码长与页缓存数据的码长相同，在数据处理过程中，将粗粒度管理的映射表中访问频率大于预设值的映射表地址信息存储到细粒度管理的映射表缓存中，一个粗粒度管理的映射表的条目由1024个地址映射表拼接而成，细粒度管理的映射表缓存中的各条目均包含一个映射表信息以及一个映射表信息的纠错码冗余；
    细粒度管理的映射表缓存与粗粒度管理的映射表之间的交换数据以页为单位，将从粗粒度管理的映射表中读出的一页映射表信息全部放在细粒度管理的映射表缓存中，其中，一页映射表信息由1024个映射表信息拼接而成，将输入的逻辑地址请求中的后10位作为偏移位，将输入的逻辑地址中的剩余位作为索引位。
  2. 一种应用于固态硬盘阻变存储器缓存的纠错保护方法，其特征在于，基于权利要求1所述的应用于固态硬盘阻变存储器缓存的纠错保护架构，包括以下步骤：
    将输入的逻辑地址请求分为索引位和偏移位，通过索引位来查找细粒度管理的映射表缓存，当输入的逻辑地址请求在细粒度管理的映射表缓存中命中时，则根据输入的偏移地址请求从包含请求映射表信息的页中读出对应的映射表地址信息；当输入的逻辑地址请求在细粒度管理的映射表缓存中没有命中时，则从粗粒度管理的映射表中找出包含请求映射表信息的页，当细粒度管理的映射表缓存有空间时，则直接从粗粒度管理的映射表中读出包含请求映射表信息的页，并将读出的包含请求映射表信息的页按细粒度管理策略写到细粒度管理的映射表缓存中；当细粒度管理的映射表缓存中没有空间，则根据粗粒度策略将细粒度管理的映射表缓存中的最后 一页写回到粗粒度管理的映射表中，然后再将包含请求映射表信息的页根据细粒度管理策略写到细粒度管理的映射表缓存中，最后根据偏移地址请求从包含请求映射表信息的页中读出对应的映射表地址信息。
  3. 根据权利要求2所述的应用于固态硬盘阻变存储器缓存的纠错保护方法，其特征在于，
    细粒度管理的映射表缓存能够缓存多个页的映射表地址信息，其中，每一页的映射表地址信息均为1024个连续逻辑地址对应的闪存物理地址，每一页的映射表地址信息中的第一个闪存物理地址对应的逻辑地址为该页的逻辑地址索引；
    当访问的逻辑地址请求在细粒度管理的映射表缓存中命中时，则根据索引位对应的索引号、阻变存储器中存放地址映射表信息的首地址、每个地址信息条目的大小、以及页内偏移得所需地址映射表信息所在位置，其中，所需地址映射表信息所在位置＝阻变存储器中存放地址映射表信息的首地址+每个地址信息条目的大小×1024×索引号+页内偏移×每个地址信息条目的大小。
  4. 根据权利要求3所述的应用于固态硬盘阻变存储器缓存的纠错保护方法，其特征在于，每个地址信息条目的大小由一个地址映射信息和该地址映射信息的纠错码冗余组成。
  5. 根据权利要求2所述的应用于固态硬盘阻变存储器缓存的纠错保护方法，其特征在于，将索引条目存储到固态硬盘系统的静态随机存储器，高速缓存数据映射表及映射表缓存索引阵列存储到固态硬盘系统的SRAM中，地址映射表信息存储到固态硬盘系统的片外缓存阻变存储器中。
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