WO2016206489A1 - 一种微引擎处理报文中间数据快照功能的实现方法及装置 - Google Patents

一种微引擎处理报文中间数据快照功能的实现方法及装置 Download PDF

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Publication number
WO2016206489A1
WO2016206489A1 PCT/CN2016/081616 CN2016081616W WO2016206489A1 WO 2016206489 A1 WO2016206489 A1 WO 2016206489A1 CN 2016081616 W CN2016081616 W CN 2016081616W WO 2016206489 A1 WO2016206489 A1 WO 2016206489A1
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Prior art keywords
snapshot
message
data
packet
intermediate data
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English (en)
French (fr)
Inventor
周峰
安康
王志忠
刘衡祁
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Sanechips Technology Co Ltd
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ZTE Microelectronics Technology Co Ltd
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Priority to US15/738,817 priority Critical patent/US11010277B2/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3636—Debugging of software by tracing the execution of the program
    • G06F11/364—Debugging of software by tracing the execution of the program tracing values on a bus

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  • the present invention relates to network processor technologies, and in particular, to a method and device for implementing a micro-engine (ME, Micro Engine) processing message intermediate data snapshot function, and a computer storage medium.
  • ME Micro-engine
  • the core routers in the backbone of the Internet have undergone one technological change.
  • network processors have become an irreplaceable part of the routing and forwarding engine with its outstanding packet processing performance and programmability.
  • the ME is the core component of the network processor, and is responsible for parsing and processing the message according to the Microcode Instructions. Since the microcode instruction is written by the user according to the requirements, it is inevitable that the error is before the valid verification. Therefore, the debugging technology of the ME is widely used in the field of software fault location, software code analysis and reverse engineering, which is crucial for the design and use of the processor. Important role.
  • Debugging software and microcode generally includes the following three aspects: setting a breakpoint in the microcode, causing the interrupt to be executed and stopping execution when the program executes to the breakpoint; the user can check whether the data in the middle of the message is correct or not; Perform a single step operation or get rid of the interrupt status and continue to execute. Continue to view the message intermediate data until the end of the program. Therefore, the implementation technology of the intermediate data snapshot function of the ME processing message is particularly important, and is the key to the debugging technology.
  • the structure is relatively simple, there are two obvious disadvantages: 1) For a network processor with a multi-ME parallel structure, the ME has a read port of the external bus, which is disadvantageous for the timing convergence of the chip and after The terminal wiring greatly limits the improvement of the ME main frequency; 2) PKT_RAM requires an additional read port for the bus to use, which increases the area of the PKT_RAM and increases the complexity of the PKT_RAM read logic, which is not conducive to timing closure.
  • the embodiment of the present invention is to provide a method and device for implementing a micro-engine processing message intermediate data snapshot function, and a computer storage medium, which at least solves the problems existing in the prior art, and is simple to implement, and can not only improve the chip frequency. And can also save chip area.
  • the snapshot of the intermediate data of the packet is completed by using the debugging command, and the packet snapshot data is obtained.
  • the storage and output of the message snapshot data is completed according to the software command, so that the message snapshot data is moved and stored in an external memory external to the microengine, and the bus output of the message snapshot data is completed in the external memory.
  • the debug instruction is a piece of instruction stored in the instruction memory for downloading and storing.
  • the snapshot of the intermediate data of the packet is completed by using the debugging instruction, and the packet snapshot data is obtained, and the method further includes:
  • Executing the debugging instruction extracting the intermediate data of the packet stored in the message storage, and moving the intermediate data of the packet to a snapshot cache of the micro engine for segmentation storage, and a total of N pieces of data are divided into N addresses. storage.
  • the snapshot of the intermediate data of the packet is obtained through the debugging instruction, and the snapshot data of the packet is obtained, and the method further includes:
  • the software driver sends a command to the microengine to cause the microengine to enter the debug mode, and the pipeline starts to execute the debug instruction, and each of the debug instructions completes the transfer of a part of the message intermediate data;
  • the intermediate data of the message is snapshotted, and the intermediate data of the message is moved from the message memory and stored in the snapshot cache of the micro engine.
  • the method further includes:
  • the pipeline executes a first debug instruction instr0 to download a segment of the intermediate data of the message from the first address in the message memory and store it in the address 0 of the snapshot cache;
  • the pipeline then executes a second debug instruction inst1 different from the first debug instruction instr0 to download a segment of the message intermediate data from the secondary address in the message store and store it in the snapshot cache address 1 position;
  • the N-1 debug instruction is executed to complete the movement and temporary storage of the intermediate data of the message from the message storage to the snapshot cache.
  • the storing and outputting the packet snapshot data according to the software command further includes:
  • the fragment of the packet snapshot data in the snapshot cache of the micro-engine is read in the order of the first address to the last address. ;
  • the software driver After receiving the completion signal, the software driver reads the packet snapshot data from the external memory to complete the output of the entire snapshot.
  • the fragment of the packet snapshot data in the snapshot cache of the micro engine is read in the order of the first address to the last address, and the method further includes:
  • the message scheduling module sequentially follows the address sequence from address 0. Sequencing the segment of the message snapshot data to the address N-1;
  • the message scheduling module stores the segments of each message snapshot data in the external memory in sequence according to the reading order, after each segment of the message snapshot data is read, corresponding to the address information.
  • the software command is a snapshot read command sent by the software driver to the micro engine, and includes at least one snapshot read command.
  • the snapshot read command includes: a read command and a read address information of an external memory
  • Each snapshot read command corresponds to a storage address in the external memory, corresponding to a snapshot data segment
  • the length of the packet snapshot data is constant, and is N segments. After the software driver reads N times, the packet snapshot data is completely read out.
  • An apparatus for implementing a message intermediate data snapshot function of a micro engine includes: a micro engine, a software driver, and an external memory; wherein
  • the micro engine is configured to complete the snapshot of the intermediate data of the packet by using the debugging instruction, and obtain the snapshot data of the packet; and output the snapshot data of the packet to the external memory according to the command sent by the software driver;
  • a software driver configured to issue a software command to the microengine
  • the external memory is configured to store the packet snapshot data and complete bus output of the message snapshot data.
  • the debug instruction is a piece of instruction stored in the instruction memory for downloading and storing.
  • the device further includes: a message storage, configured to store the intermediate data of the message;
  • the micro engine further includes a snapshot cache configured to execute the debugging instruction at the micro engine, and extract the intermediate data of the packet stored in the message storage, and store the packet from the message.
  • the intermediate data of the message moved by the device is stored in the form of segmented storage, and the data of the transferred message is stored in a total of N pieces of data, and is divided into N addresses for storage.
  • the device further includes: a message storage, configured to store the intermediate data of the message;
  • the micro engine further includes a pipeline and a snapshot cache; wherein
  • the pipeline is configured to start executing the debugging instruction after the software driver sends a command to the micro engine to enable the micro engine to enter the debugging mode, and each part of the debugging instruction completes the movement of a part of the message intermediate data;
  • the snapshot cache is configured to execute the debugging instruction in the micro engine, and after extracting the intermediate data of the packet stored in the message storage, storing the intermediate data of the packet moved from the message storage, and reporting After the text intermediate data is moved from the first address to the last address, the snapshot of the intermediate data of the message is completed.
  • the pipeline is further configured to:
  • the N-1 debug instruction is executed to complete the movement and temporary storage of the intermediate data of the message from the message storage to the snapshot cache.
  • the micro engine further includes a snapshot cache, configured to execute the debugging instruction after the micro engine executes, and after the intermediate data of the message stored in the message storage is extracted, the storage is moved from the message storage.
  • a snapshot cache configured to execute the debugging instruction after the micro engine executes, and after the intermediate data of the message stored in the message storage is extracted, the storage is moved from the message storage.
  • the micro-engine is configured to read the fragment of the packet snapshot data in the snapshot cache in the order of the first address to the last address, and the intermediate data of the packet is moved. After the snapshot is implemented, the packet snapshot data is sent; the fragment of the packet snapshot data is delivered to the external memory;
  • the external memory is further configured to: after receiving the fragment of the packet snapshot data, report the software driver completion signal, where the completion signal is used to indicate that the packet snapshot data has been delivered;
  • the software driver is further configured to: after receiving the completion signal, read the packet snapshot data from the external memory to complete output of the entire snapshot.
  • the micro engine further includes a message scheduling module, configured to sequentially read the message from address 0 to address N-1 in sequence according to the address sequence after the micro engine enters the snapshot outbound mode.
  • a segment of the snapshot data according to the readout order, after each segment of the message snapshot data is read, the corresponding address information is sequentially stored, and the segment of each message snapshot data is sequentially stored in the external memory.
  • the software command is a snapshot read command sent by the software driver to the micro engine, and includes at least one snapshot read command.
  • the snapshot read command includes: a read command and a read address information of an external memory
  • Each snapshot read command corresponds to a storage address in the external memory, corresponding to a snapshot data segment
  • the length of the packet snapshot data is constant, and is N segments. After the software driver reads N times, the packet snapshot data is completely read out.
  • the embodiment of the invention further provides a computer storage medium, wherein the computer executable instructions are configured to execute the method for implementing the micro-engine processing of the intermediate data snapshot function of the message.
  • the method for implementing the intermediate data snapshot function of the micro-engine processing packet of the embodiment of the present invention includes: performing a snapshot of the intermediate data of the packet by using the debugging instruction to obtain the packet snapshot data; and completing the storage and output of the packet snapshot data according to the software command. To move the message snapshot data to the micro In the external memory external to the engine, the bus output of the message snapshot data is completed in the external memory.
  • the snapshot of the intermediate data of the message is first completed by the debugging instruction instead of directly reading the data of the PKT_RAM through the external bus, thereby reducing the complexity of the network processor back-end wiring of the multi-core structure and increasing the ME main frequency;
  • the snapshot data can be moved and stored in the memory outside the ME, to avoid the PKT_RAM inside the ME to provide an additional read port, which saves the chip area of the PKT_RAM.
  • FIG. 1 is a flowchart of a method for implementing an intermediate data snapshot function of a packet according to an embodiment of the present invention
  • FIG. 2 is a structural diagram of an apparatus for implementing an intermediate data snapshot function of a message according to an embodiment of the present invention
  • FIG. 3 is a flowchart of a method for implementing an intermediate data snapshot of a packet according to an application example 1 of the embodiment of the present invention
  • FIG. 4 is a structural diagram of an apparatus for implementing an intermediate data snapshot of a packet according to an application example 1 of the embodiment of the present invention
  • FIG. 5 is a schematic diagram of execution of a debug instruction according to an application example 1 of an embodiment of the present invention.
  • FIG. 6 is a flowchart of external storage and output of message intermediate data according to application example 2 of the embodiment of the present invention.
  • FIG. 7 is a structural diagram of external storage and output of message intermediate data according to application example 2 of the embodiment of the present invention.
  • FIG. 8 is a schematic diagram of the operation of the message scheduling module according to the application example 2 of the embodiment of the present invention.
  • An implementation method for processing an intermediate data snapshot function of a message by a micro engine includes:
  • Step S11 completing a snapshot of the intermediate data of the packet by using a debugging instruction, and obtaining the snapshot data of the packet;
  • Step S12 The storage and output of the message snapshot data is completed according to the software command, so that the message snapshot data is moved and stored in an external memory external to the microengine, and the bus output of the message snapshot data is completed in the external memory.
  • the debug instruction is a piece of instructions stored in an instruction memory for downloading and storing.
  • the snapshot of the intermediate data of the packet is obtained by using the debugging instruction, and the packet snapshot data is obtained, and the method further includes:
  • Executing the debugging instruction extracting the intermediate data of the packet stored in the message storage, and moving the intermediate data of the packet to a snapshot cache of the micro engine for segmentation storage, and a total of N pieces of data are divided into N addresses. storage.
  • the snapshot of the intermediate data of the packet is obtained by using the debugging instruction, and the packet snapshot data is obtained, and the method further includes:
  • the software driver sends a command to the microengine to cause the microengine to enter the debug mode, and the pipeline starts to execute the debug instruction, and each of the debug instructions completes the transfer of a part of the message intermediate data;
  • the intermediate data of the message is snapshotted, and the intermediate data of the message is moved from the message memory and stored in the snapshot cache of the micro engine.
  • the method further includes:
  • the pipeline executes a first debug instruction instr0 to download a segment of the intermediate data of the message from the first address in the message memory and store it in the address 0 of the snapshot cache;
  • the pipeline then executes a second debug instruction inst1 different from the first debug instruction instr0 to download a segment of the message intermediate data from the secondary address in the message store and store it in the snapshot cache address 1 position;
  • the intermediate data of the message is completed from the message storage.
  • the storing and outputting the packet snapshot data according to the software command further includes:
  • the fragment of the packet snapshot data in the snapshot cache of the micro-engine is read in the order of the first address to the last address. ;
  • the software driver After receiving the completion signal, the software driver reads the packet snapshot data from the external memory to complete the output of the entire snapshot.
  • the fragment of the packet snapshot data in the snapshot cache of the micro-engine is read in the order of the first address to the last address, and the method further includes:
  • the message scheduling module sequentially reads the fragments of the packet snapshot data in sequence from the address 0 to the address N-1.
  • the message scheduling module stores the segments of each message snapshot data in the external memory in sequence according to the reading order, after each segment of the message snapshot data is read, corresponding to the address information.
  • the software command is a snapshot read command sent by the software driver to the micro engine, and includes at least one snapshot read command.
  • the snapshot read command includes: a read command and a read address information of an external memory
  • Each snapshot read command corresponds to a storage address in the external memory, corresponding to a snapshot data segment
  • the length of the packet snapshot data is constant, and is N segments, which are read by the software driver. After N times, the message snapshot data is completely read.
  • An apparatus for implementing a message intermediate data snapshot function of a micro engine includes: a micro engine, a software driver, and an external memory; wherein
  • the micro engine is configured to complete the snapshot of the intermediate data of the packet by using the debugging instruction, and obtain the snapshot data of the packet; and output the snapshot data of the packet to the external memory according to the command sent by the software driver;
  • a software driver configured to issue a software command to the microengine
  • the external memory is configured to store the packet snapshot data and complete bus output of the message snapshot data.
  • the debug instruction is a piece of instructions stored in an instruction memory for downloading and storing.
  • the device further includes: a message storage, configured to store the intermediate data of the message;
  • the micro engine further includes a snapshot cache configured to execute the debug instruction in the micro engine, and after extracting the intermediate data of the packet stored in the message storage, storing the packet moved from the message storage
  • the intermediate data is stored in the form of segmented storage, and the intermediate data of the moved message is divided into N pieces of data and stored in N addresses.
  • the device further includes: a message storage, configured to store the intermediate data of the message;
  • the micro engine further includes a pipeline and a snapshot cache; wherein
  • the pipeline is configured to start executing the debugging instruction after the software driver sends a command to the micro engine to enable the micro engine to enter the debugging mode, and each part of the debugging instruction completes the movement of a part of the message intermediate data;
  • the snapshot cache is configured to execute the debugging instruction in the micro engine, and after extracting the intermediate data of the message stored in the message storage, storing the report moved from the message storage
  • the intermediate data of the text completes the snapshot of the intermediate data of the message after the data in the middle of the message is moved from the first address to the last address.
  • the pipeline is further configured to:
  • the N-1 debug instruction is executed to complete the movement and temporary storage of the intermediate data of the message from the message storage to the snapshot cache.
  • the micro engine further includes a snapshot cache, configured to execute the debugging instruction in the micro engine, and extract the intermediate data of the packet stored in the message storage, and then store the The intermediate data of the message moved by the message storage;
  • the micro-engine is configured to read the fragment of the packet snapshot data in the snapshot cache in the order of the first address to the last address, and the intermediate data of the packet is completed after the snapshot is completed. Transmitting packet snapshot data; transmitting a fragment of the packet snapshot data to the external memory;
  • the external memory is further configured to: after receiving the fragment of the packet snapshot data, report the software driver completion signal, where the completion signal is used to indicate that the packet snapshot data has been delivered;
  • the software driver is further configured to: after receiving the completion signal, read the packet snapshot data from the external memory to complete output of the entire snapshot.
  • the micro engine further includes a message scheduling module, configured to sequentially sequence from address 0 to address N-1 in the order of addresses after the micro engine enters the snapshot outbound mode. Reading a segment of the message snapshot data; according to the reading order, in each newspaper After the segment of the snapshot data is read, the corresponding address information is loaded, and the segment of each message snapshot data is sequentially stored in the external memory.
  • a message scheduling module configured to sequentially sequence from address 0 to address N-1 in the order of addresses after the micro engine enters the snapshot outbound mode. Reading a segment of the message snapshot data; according to the reading order, in each newspaper After the segment of the snapshot data is read, the corresponding address information is loaded, and the segment of each message snapshot data is sequentially stored in the external memory.
  • the software command is a snapshot read command sent by the software driver to the micro engine, and includes at least one snapshot read command.
  • the snapshot read command includes: a read command and a read address information of an external memory
  • Each snapshot read command corresponds to a storage address in the external memory, corresponding to a snapshot data segment
  • the length of the packet snapshot data is constant, and is N segments. After the software driver reads N times, the packet snapshot data is completely read out.
  • a specific application scenario of the method for processing the intermediate data snapshot function of the micro-engine in the embodiment of the present invention may be: storing the intermediate data of the packet in the message memory, and acquiring the intermediate data of the packet by using the debugging instruction. Completing the snapshot of the intermediate data of the packet to obtain the snapshot data; and completing the storage and output of the snapshot data according to the command issued by the software driver, so that the snapshot data can be moved and stored in an external memory external to the microengine, the external The memory is used as the total memory used for the snapshot data storage, and the bus output of the snapshot data is completed in the external memory to avoid the prior art that the message memory inside the micro engine provides an additional external bus read port. The resulting chip frequency is slower and the chip design is complicated.
  • the embodiment of the present invention firstly completes the snapshot of the intermediate data of the message by using the debugging instruction instead of directly reading the intermediate data of the message stored in the message memory through the external bus, thereby reducing the network processor backend of the multi-core structure.
  • the complexity of the wiring improves the frequency of the micro-engine; in addition, the external storage and output of the snapshot data is completed according to the commands issued by the software driver, and the snapshot data can be moved and stored in the memory outside the micro-engine to avoid the internal of the micro-engine.
  • the message memory provides an additional read port, saving chip area.
  • FIG. 1 is a schematic diagram of an implementation method for processing an intermediate data snapshot function of a message by a micro engine according to an embodiment of the present invention
  • FIG. 2 is a structural diagram of an apparatus for implementing an intermediate data snapshot function in a packet according to an embodiment of the present invention. Based on the device composition of FIG. 2, the flow of the micro-engine processing packet intermediate data snapshot function of FIG. 1 includes:
  • Step 101 Perform a debugging instruction to complete a snapshot of the intermediate data of the message.
  • the debugging instruction includes:
  • a section of download and store instructions stored in the instruction memory By executing this instruction, the message intermediate data can be moved from the message memory to the ME snapshot cache.
  • the software driver drives the microengine to issue the command 201, and the microengine enters the debug mode 202, and the pipeline starts to execute the debug command.
  • Each part of the debugging instruction completes the movement of a part of the message.
  • the intermediate data of the message is moved from the first address to the last address, and the snapshot is completed.
  • the intermediate data of the message is stored in the micro-engine snapshot cache.
  • Step 102 The software driver sends a command, and the micro engine completes the storage and output of the snapshot.
  • the software driver sends a command 201 to the microengine, and the microengine enters the snapshot outbound mode 202 to complete the external storage and output 203 of the snapshot.
  • the hardware After the micro engine enters the snapshot outbound mode, the hardware reads the snapshot cache in the order of the first address to the last address, and passes the message fragment to the external memory.
  • the length of the message is fixed, so the number of message fragments is also fixed. , the number is set to N.
  • the external memory After receiving the N packet snapshot segments, the external memory reports the software driver completion signal, indicating that the snapshot delivery is complete. After receiving the signal, the software driver reads the packet snapshot from the external memory to complete the output of the entire snapshot.
  • FIG. 3 is a flowchart of a method for implementing an intermediate data snapshot of a packet according to an application example 1 of the embodiment of the present invention
  • FIG. 4 is a schematic diagram of a device for implementing an intermediate data snapshot of the packet according to the application example 1 of the embodiment of the present invention.
  • the flow of the intermediate data snapshot function of the microengine of FIG. 3 is based on the device composition structure shown in FIG.
  • Step 301 downloading a debugging instruction, and setting a breakpoint
  • the debug instruction is a download and store instruction stored in the instruction memory. Since the offset first address and the tail address of the message intermediate data in the PKT_RAM are fixed, a debug instruction is edited to complete the download and storage of the message, and the downloaded address points to the first of the intermediate data of the message in the PKT_RAM. Address to end address this interval.
  • the software driver pre-downloads the debug instructions to a special area 401 in the instruction memory via the bus.
  • the software driver issues debug breakpoints. Execution of the instruction to the breakpoint will suspend execution.
  • Step 302 the instruction is executed to the breakpoint, and jumps to the debugging instruction
  • Step 303 executing a debugging instruction, completing the moving and temporary storage of the intermediate data of the message
  • the instruction execution address jumps to the entry of the debug instruction, and the pipeline begins executing the debug instruction.
  • the pipeline executes the first debugging instruction to complete the movement of the message fragment corresponding to the first address of the intermediate data of the packet, and moves it to the snapshot cache 402.
  • each instruction completes the movement of a part of the message fragments until the execution of the debugging instructions is completed, and the data transfer in the middle of the message is completed 403.
  • FIG. 5 a schematic diagram of the execution of the debug instruction according to the application example 1 of the embodiment of the present invention is applied.
  • the pipeline executes the first debug instruction inst0, and the instruction is a download and store instruction, that is, the slave message.
  • the first address in the memory downloads a segment 501 of message intermediate data and stores it in address 0 of location 502 of the snapshot cache.
  • the pipeline then executes the second debug instruction inst1, which is also a download and store instruction.
  • the difference is that the completed action is to download a segment 501 of the message intermediate data from the secondary address in the message memory and store it. Go to address 1 location 502 of the snapshot cache.
  • the transfer and temporary storage of the intermediate data of the message to the snapshot cache is completed.
  • step 304 the snapshot is completed, and the interrupt signal is reported.
  • the intermediate data of the message is all stored in the snapshot cache, and the micro engine reports the snapshot completion signal to the software driver, where the completion signal may be the processor interrupt signal 404.
  • FIG. 6 is a flowchart of external storage and output of the intermediate data of the packet according to the application example 2 of the embodiment of the present invention
  • FIG. 7 is an application.
  • the structure diagram of the external storage and output of the intermediate data of the packet according to the application example 2 of the embodiment of the present invention is based on the device composition structure of FIG. 7, and the external storage and output process of the intermediate data of the message of FIG. 6 includes:
  • Step 601 the software driver sends a command, and the micro engine enters a snapshot outbound mode
  • the software driver sends a command to the microengine through the bus, and the microengine triggers the internal packet scheduling module to enter the snapshot outbound mode 701.
  • Step 602 Read the intermediate data of the message from the snapshot cache, and transfer the data to the external memory.
  • the message scheduling module inside the micro engine reads the snapshot cache in the order of the first address to the last address, and delivers the message fragment to the external memory 702.
  • FIG. 8 a schematic diagram of the operation of the message scheduling module according to the application example 2 of the embodiment of the present invention is applied, and the snapshot data segment is stored in the snapshot cache of the micro engine. A total of N pieces of data, divided into N address storage.
  • the message scheduling module sequentially reads the fragment 801 of the message snapshot data from the address 0 to the address N-1 in the order of the address.
  • the message scheduling module stores each snapshot segment in the external memory 802 in sequence according to the readout order, after each snapshot segment is read, corresponding to the address information.
  • Step 603 The external memory reports a transmission completion signal, and the software driver sends a read snapshot command.
  • the length of the snapshot data is constant, so the number of message fragments to be delivered is also constant, and the number is set to N.
  • the external memory receives N snapshot fragments and reports the soft
  • the piece drive completion signal 703 indicates that the snapshot transfer is complete. After receiving the signal, the software driver issues a read snapshot command 704.
  • Step 604 After receiving the snapshot read command, the external memory outputs the snapshot data to the software driver through the bus.
  • the software driver issues multiple snapshot read commands, wherein the snapshot read command includes read commands and read address information of the external memory, and each command corresponds to the external memory.
  • the length of the snapshot data is constant and is N segments. Therefore, after the software driver reads N times, the snapshot data is all read out. At this point, the snapshot output is completed.
  • the method for implementing the intermediate data snapshot function of the ME processing message completes the snapshot of the intermediate data of the packet by using the debugging instruction; and completes the storage and output of the snapshot data according to the command issued by the software driver.
  • the snapshot of the intermediate data of the message is first completed by the debugging instruction instead of directly reading the data of the PKT_RAM through the external bus, thereby reducing the complexity of the network processor back-end wiring of the multi-core structure and increasing the ME main frequency; According to the command issued by the software driver to complete the external storage and output of the snapshot data, the snapshot data can be moved to the external memory of the ME to avoid the extra read port provided by the PKT_RAM inside the ME, which saves the chip area of the PKT_RAM.
  • the solution is relatively simple to implement and easy to implement.
  • Each of the above units may be implemented by a central processing unit (CPU), a digital signal processor (DSP), or a field-programmable gate array (FPGA) in an electronic device.
  • CPU central processing unit
  • DSP digital signal processor
  • FPGA field-programmable gate array
  • the integrated modules described in the embodiments of the present invention may also be stored in a computer readable storage medium if they are implemented in the form of software functional modules and sold or used as separate products. Based on such understanding, the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions.
  • Make a computer device can be a personal computing The machine, server, or network device, etc.) performs all or part of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .
  • ROM read-only memory
  • RAM random access memory
  • magnetic disk or an optical disk, and the like.
  • the embodiment of the invention further provides a computer storage medium, wherein the computer executable instructions are configured to execute the method for implementing the micro-engine processing of the intermediate data snapshot function of the message.
  • the snapshot of the intermediate data of the message is first completed by the debugging instruction instead of directly reading the data of the PKT_RAM through the external bus, thereby reducing the complexity of the network processor back-end wiring of the multi-core structure and increasing the ME main frequency;
  • the snapshot data can be moved and stored in the memory outside the ME, to avoid the PKT_RAM inside the ME to provide an additional read port, which saves the chip area of the PKT_RAM.

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Abstract

一种微引擎处理报文中间数据快照功能的实现方法及装置、计算机存储介质，其中，所述方法包括：通过调试指令完成报文中间数据的快照，得到报文快照数据；根据软件命令完成所述报文快照数据的存储和输出，以将报文快照数据搬移存储到微引擎外部的外部存储器中，在外部存储器中完成报文快照数据的总线输出。

Description

一种微引擎处理报文中间数据快照功能的实现方法及装置 技术领域
本发明涉及网络处理器技术，尤其涉及一种微引擎(ME，Micro Engine)处理报文中间数据快照功能的实现方法及装置、计算机存储介质。
背景技术
为了满足未来网络发展的需要，提高路由器的性能，处于因特网(Internet)骨干位置的核心路由器进行了一个又一个的技术变革。尤其在高端路由器市场，网络处理器以其杰出的报文处理性能及可编程性已经成为构成路由转发引擎不可替代的部分。
在网络处理器系统中，ME是网络处理器的核心部件，负责根据微码指令(Microcode Instructions)完成对报文的解析与处理。由于微码指令是用户根据需求编写，在得到有效验证之前难免出错，所以ME的调试技术被广泛地应用于软件故障定位，软件代码分析以及逆向工程领域，对处理器的设计和使用有着至关重要的作用。
对软件和微码进行调试，一般包括以下三个方面内容：在微码中设置断点，使程序执行到断点时产生中断并停止执行；用户可以查看报文中间数据正确与否；对程序执行单步操作或使之摆脱中断状态继续往下执行，继续查看报文中间数据直至程序结束。所以ME处理报文中间数据快照功能的实现技术显得尤为重要，是调试技术的关键。
现有的ME处理报文中间数据快照功能的实现技术，最主要的方案是通过ME总线直接读取的方案，这种方案需要ME留有外部总线的读取端口，当指令执行到断点时产生中断并停止执行，用户通过总线读取报文存储器(PKT_RAM)数据，查看报文中间数据。
采用上述这种方案，虽然结构较为简单，但是存在两个明显的缺点：1)对于多ME并行结构的网络处理器而言，ME留有外部总线的读取端口不利于芯片的时序收敛和后端布线，极大的限制了ME主频的提高；2)PKT_RAM需要额外的读端口供总线使用，增大了PKT_RAM的面积，增加了PKT_RAM读逻辑的复杂度，不利于时序收敛。
发明内容
有鉴于此，本发明实施例希望提供一种微引擎处理报文中间数据快照功能的实现方法及装置、计算机存储介质，至少解决了现有技术存在的问题，实现简单，不仅可以提升芯片主频，而且还可以节省芯片面积。
本发明实施例的技术方案是这样实现的：
本发明实施例的一种微引擎处理报文中间数据快照功能的实现方法，该方法包括：
通过调试指令完成报文中间数据的快照，得到报文快照数据；
根据软件命令完成所述报文快照数据的存储和输出，以将报文快照数据搬移存储到微引擎外部的外部存储器中，在外部存储器中完成报文快照数据的总线输出。
上述方案中，所述调试指令为一段存储在指令存储器中用于下载和存储的指令。
上述方案中，所述通过调试指令完成报文中间数据的快照，得到报文快照数据，还包括：
执行所述调试指令，提取存储于报文存储器的所述报文中间数据，将所述报文中间数据搬移到微引擎的快照缓存中进行分段存储，一共N段数据，分为N个地址存储。
上述方案中，所通过调试指令完成报文中间数据的快照，得到报文快照数据，还包括：
软件驱动给微引擎下发命令使得微引擎进入调试模式，流水线开始执行所述调试指令，每执行一条调试指令完成一部分报文中间数据的搬移；
报文中间数据从首地址到尾地址搬移完成后完成所述报文中间数据的快照，报文中间数据从报文存储器中搬移存储在微引擎的快照缓存中。
上述方案中，所述方法还包括：
流水线执行第一条调试指令instr0，以从所述报文存储器中的首地址下载一个报文中间数据的片段，将其存储到快照缓存的地址0位置；
流水线接着执行不同于所述第一条调试指令instr0的第二条调试指令inst1，以从所述报文存储器中的次地址下载一个报文中间数据的片段，将其存储到快照缓存的地址1位置；
依次类推，执行完第N-1条调试指令，以完成报文中间数据从报文存储器到快照缓存的搬移和暂存。
上述方案中，所述根据软件命令完成所述报文快照数据的存储和输出，还包括：
微引擎进入快照外传模式后，按首地址到尾地址的顺序读取微引擎的快照缓存中的报文快照数据的片段，所述报文中间数据搬移完成实现快照后为所述报文快照数据；
将报文快照数据的片段传递到外部存储器，外部存储器接收完所述报文快照数据的片段后，上报给软件驱动完成信号，所述完成信号用于表征所述报文快照数据已经传递完成；
软件驱动接收到所述完成信号后，从外部存储器中读取出所述报文快照数据，完成整个快照的输出。
上述方案中，所述微引擎进入快照外传模式后，按首地址到尾地址的顺序读取微引擎的快照缓存中的报文快照数据的片段，还包括：
微引擎进入快照外传模式后，报文调度模块按地址顺序，依次从地址0 到地址N-1顺次读出所述报文快照数据的片段；
报文调度模块会根据读出顺序，在每一个报文快照数据的片段被读出后，对应的打上地址信息，将每个报文快照数据的片段顺次存储在外部存储器中。
上述方案中，所述软件命令为软件驱动下发给微引擎的快照读取命令，包括至少一个快照读取命令；
所述快照读取命令包含：外部存储器的读命令和读地址信息；
每一条快照读取命令对应外部存储器中的一个存储地址，对应一个快照数据片段；
所述报文快照数据的长度是一定的，为N个片段，在所述软件驱动读取N次后，所述报文快照数据被全部读出。
本发明实施例的一种微引擎处理报文中间数据快照功能的实现装置，所述装置包括：微引擎、软件驱动、外部存储器；其中，
微引擎，配置为通过调试指令完成报文中间数据的快照，得到报文快照数据；根据所述软件驱动下发的命令以完成所述报文快照数据存储至所述外部存储器中进行输出；
软件驱动，配置为下发软件命令给所述微引擎；
外部存储器，配置为存储所述报文快照数据，完成报文快照数据的总线输出。
上述方案中，所述调试指令为一段存储在指令存储器中用于下载和存储的指令。
上述方案中，所述装置还包括：报文存储器，配置为存储所述报文中间数据；
所述微引擎，还包括快照缓存，配置为在微引擎执行所述调试指令，提取存储于所述报文存储器的所述报文中间数据后，存储从所述报文存储 器搬移过来的报文中间数据，且以分段存储的形式存储搬移过来的报文中间数据，一共N段数据，分为N个地址存储。
上述方案中，所述装置还包括：报文存储器，配置为存储所述报文中间数据；
所述微引擎，还包括流水线和快照缓存；其中，
所述流水线，配置为在软件驱动给微引擎下发命令使得微引擎进入调试模式后，开始执行所述调试指令，每执行一条调试指令完成一部分报文中间数据的搬移；
所述快照缓存，配置为在微引擎执行所述调试指令，提取存储于所述报文存储器的所述报文中间数据后，存储从所述报文存储器搬移过来的报文中间数据，在报文中间数据从首地址到尾地址搬移完成后完成所述报文中间数据的快照中。
上述方案中，所述流水线，还配置为：
执行第一条调试指令instr0，以从所述报文存储器中的首地址下载一个报文中间数据的片段，将其存储到快照缓存的地址0位置；
接着执行不同于所述第一条调试指令instr0的第二条调试指令inst1，以从所述报文存储器中的次地址下载一个报文中间数据的片段，将其存储到快照缓存的地址1位置；
依次类推，执行完第N-1条调试指令，以完成报文中间数据从报文存储器到快照缓存的搬移和暂存。
上述方案中，所述微引擎，还包括快照缓存，配置为在微引擎执行所述调试指令，提取存储于所述报文存储器的所述报文中间数据后，存储从所述报文存储器搬移过来的报文中间数据；
所述微引擎，还配置为进入快照外传模式后，按首地址到尾地址的顺序读取所述快照缓存中的报文快照数据的片段，所述报文中间数据搬移完 成实现快照后为所述报文快照数据；将报文快照数据的片段传递到所述外部存储器；
所述外部存储器，还配置为接收完所述报文快照数据的片段后，上报给所述软件驱动完成信号，所述完成信号用于表征所述报文快照数据已经传递完成；
所述软件驱动，还配置为接收到所述完成信号后，从所述外部存储器中读取出所述报文快照数据，完成整个快照的输出。
上述方案中，所述微引擎，还包括报文调度模块，配置为在所述微引擎进入快照外传模式后，按地址顺序，依次从地址0到地址N-1顺次读出所述报文快照数据的片段；根据读出顺序，在每一个报文快照数据的片段被读出后，对应的打上地址信息，将每个报文快照数据的片段顺次存储在所述外部存储器中。
上述方案中，所述软件命令为软件驱动下发给微引擎的快照读取命令，包括至少一个快照读取命令；
所述快照读取命令包含：外部存储器的读命令和读地址信息；
每一条快照读取命令对应外部存储器中的一个存储地址，对应一个快照数据片段；
所述报文快照数据的长度是一定的，为N个片段，在所述软件驱动读取N次后，所述报文快照数据被全部读出。
本发明实施例还提供一种计算机存储介质，其中存储有计算机可执行指令，该计算机可执行指令配置执行上述一种微引擎处理报文中间数据快照功能的实现方法。
本发明实施例的微引擎处理报文中间数据快照功能的实现方法包括：通过调试指令完成报文中间数据的快照，得到报文快照数据；根据软件命令完成所述报文快照数据的存储和输出，以将报文快照数据搬移存储到微 引擎外部的外部存储器中，在外部存储器中完成报文快照数据的总线输出。
采用本发明实施例，首先通过调试指令完成报文中间数据的快照而不是直接通过外部总线读取PKT_RAM的数据，从而能够降低多核结构的网络处理器后端布线的复杂度提升ME主频频率；此外，根据软件驱动下发的命令完成快照数据的外部存储和输出，可以将快照数据搬移存储到ME外部的存储器中，避免ME内部的PKT_RAM提供额外的读端口，节省了PKT_RAM的芯片面积。
附图说明
图1为本发明实施例中报文中间数据快照功能实现方法的流程图；
图2为本发明实施例中报文中间数据快照功能实现装置的结构图；
图3为应用本发明实施例的应用实例一所述的报文中间数据快照实现方法的流程图；
图4为应用本发明实施例的应用实例一所述的报文中间数据快照实现装置的结构图；
图5为应用本发明实施例的应用实例一所述的调试指令执行的示意图；
图6为应用本发明实施例的应用实例二所述的报文中间数据外部存储和输出的流程图；
图7为应用本发明实施例的应用实例二所述的报文中间数据外部存储和输出的结构图；
图8为应用本发明实施例的应用实例二所述的报文调度模块工作的示意图。
具体实施方式
下面结合附图对技术方案的实施作进一步的详细描述。
本发明实施例的一种微引擎处理报文中间数据快照功能的实现方法， 该方法包括：
步骤S11、通过调试指令完成报文中间数据的快照，得到报文快照数据；
步骤S12、根据软件命令完成所述报文快照数据的存储和输出，以将报文快照数据搬移存储到微引擎外部的外部存储器中，在外部存储器中完成报文快照数据的总线输出。
在本发明实施例一实施方式中，所述调试指令为一段存储在指令存储器中用于下载和存储的指令。
在本发明实施例一实施方式中，所述通过调试指令完成报文中间数据的快照，得到报文快照数据，还包括：
执行所述调试指令，提取存储于报文存储器的所述报文中间数据，将所述报文中间数据搬移到微引擎的快照缓存中进行分段存储，一共N段数据，分为N个地址存储。
在本发明实施例一实施方式中，所述通过调试指令完成报文中间数据的快照，得到报文快照数据，还包括：
软件驱动给微引擎下发命令使得微引擎进入调试模式，流水线开始执行所述调试指令，每执行一条调试指令完成一部分报文中间数据的搬移；
报文中间数据从首地址到尾地址搬移完成后完成所述报文中间数据的快照，报文中间数据从报文存储器中搬移存储在微引擎的快照缓存中。
在本发明实施例一实施方式中，所述方法还包括：
流水线执行第一条调试指令instr0，以从所述报文存储器中的首地址下载一个报文中间数据的片段，将其存储到快照缓存的地址0位置；
流水线接着执行不同于所述第一条调试指令instr0的第二条调试指令inst1，以从所述报文存储器中的次地址下载一个报文中间数据的片段，将其存储到快照缓存的地址1位置；
依次类推，执行完第N-1条调试指令，以完成报文中间数据从报文存 储器到快照缓存的搬移和暂存。
在本发明实施例一实施方式中，所述根据软件命令完成所述报文快照数据的存储和输出，还包括：
微引擎进入快照外传模式后，按首地址到尾地址的顺序读取微引擎的快照缓存中的报文快照数据的片段，所述报文中间数据搬移完成实现快照后为所述报文快照数据；
将报文快照数据的片段传递到外部存储器，外部存储器接收完所述报文快照数据的片段后，上报给软件驱动完成信号，所述完成信号用于表征所述报文快照数据已经传递完成；
软件驱动接收到所述完成信号后，从外部存储器中读取出所述报文快照数据，完成整个快照的输出。
在本发明实施例一实施方式中，所述微引擎进入快照外传模式后，按首地址到尾地址的顺序读取微引擎的快照缓存中的报文快照数据的片段，还包括：
微引擎进入快照外传模式后，报文调度模块按地址顺序，依次从地址0到地址N-1顺次读出所述报文快照数据的片段；
报文调度模块会根据读出顺序，在每一个报文快照数据的片段被读出后，对应的打上地址信息，将每个报文快照数据的片段顺次存储在外部存储器中。
在本发明实施例一实施方式中，所述软件命令为软件驱动下发给微引擎的快照读取命令，包括至少一个快照读取命令；
所述快照读取命令包含：外部存储器的读命令和读地址信息；
每一条快照读取命令对应外部存储器中的一个存储地址，对应一个快照数据片段；
所述报文快照数据的长度是一定的，为N个片段，在所述软件驱动读 取N次后，所述报文快照数据被全部读出。
本发明实施例的一种微引擎处理报文中间数据快照功能的实现装置，所述装置包括：微引擎、软件驱动、外部存储器；其中，
微引擎，配置为通过调试指令完成报文中间数据的快照，得到报文快照数据；根据所述软件驱动下发的命令以完成所述报文快照数据存储至所述外部存储器中进行输出；
软件驱动，配置为下发软件命令给所述微引擎；
外部存储器，配置为存储所述报文快照数据，完成报文快照数据的总线输出。
在本发明实施例一实施方式中，所述调试指令为一段存储在指令存储器中用于下载和存储的指令。
在本发明实施例一实施方式中，所述装置还包括：报文存储器，配置为存储所述报文中间数据；
所述微引擎，还包括快照缓存，配置为在微引擎执行所述调试指令，提取存储于所述报文存储器的所述报文中间数据后，存储从所述报文存储器搬移过来的报文中间数据，且以分段存储的形式存储搬移过来的报文中间数据，一共N段数据，分为N个地址存储。
在本发明实施例一实施方式中，所述装置还包括：报文存储器，配置为存储所述报文中间数据；
所述微引擎，还包括流水线和快照缓存；其中，
所述流水线，配置为在软件驱动给微引擎下发命令使得微引擎进入调试模式后，开始执行所述调试指令，每执行一条调试指令完成一部分报文中间数据的搬移；
所述快照缓存，配置为在微引擎执行所述调试指令，提取存储于所述报文存储器的所述报文中间数据后，存储从所述报文存储器搬移过来的报 文中间数据，在报文中间数据从首地址到尾地址搬移完成后完成所述报文中间数据的快照中。
在本发明实施例一实施方式中，所述流水线，还配置为：
执行第一条调试指令instr0，以从所述报文存储器中的首地址下载一个报文中间数据的片段，将其存储到快照缓存的地址0位置；
接着执行不同于所述第一条调试指令instr0的第二条调试指令inst1，以从所述报文存储器中的次地址下载一个报文中间数据的片段，将其存储到快照缓存的地址1位置；
依次类推，执行完第N-1条调试指令，以完成报文中间数据从报文存储器到快照缓存的搬移和暂存。
在本发明实施例一实施方式中，所述微引擎，还包括快照缓存，配置为在微引擎执行所述调试指令，提取存储于所述报文存储器的所述报文中间数据后，存储从所述报文存储器搬移过来的报文中间数据；
所述微引擎，还配置为进入快照外传模式后，按首地址到尾地址的顺序读取所述快照缓存中的报文快照数据的片段，所述报文中间数据搬移完成实现快照后为所述报文快照数据；将报文快照数据的片段传递到所述外部存储器；
所述外部存储器，还配置为接收完所述报文快照数据的片段后，上报给所述软件驱动完成信号，所述完成信号用于表征所述报文快照数据已经传递完成；
所述软件驱动，还配置为接收到所述完成信号后，从所述外部存储器中读取出所述报文快照数据，完成整个快照的输出。
在本发明实施例一实施方式中，所述微引擎，还包括报文调度模块，配置为在所述微引擎进入快照外传模式后，按地址顺序，依次从地址0到地址N-1顺次读出所述报文快照数据的片段；根据读出顺序，在每一个报 文快照数据的片段被读出后，对应的打上地址信息，将每个报文快照数据的片段顺次存储在所述外部存储器中。
在本发明实施例一实施方式中，所述软件命令为软件驱动下发给微引擎的快照读取命令，包括至少一个快照读取命令；
所述快照读取命令包含：外部存储器的读命令和读地址信息；
每一条快照读取命令对应外部存储器中的一个存储地址，对应一个快照数据片段；
所述报文快照数据的长度是一定的，为N个片段，在所述软件驱动读取N次后，所述报文快照数据被全部读出。
以一个现实应用场景为例对本发明实施例阐述如下：
本发明实施例所述的微引擎处理报文中间数据快照功能的实现方法的一个具体应用场景可以为：在报文存储器中存储有报文中间数据，通过调试指令获取所述报文中间数据来完成报文中间数据的快照，得到快照数据；根据软件驱动下发的命令完成所述快照数据的存储和输出，从而可以将所述快照数据搬移存储到微引擎外部的外部存储器中，所述外部存储器作为所述快照数据存储使用的总的存储器，在外部存储器中完成快照数据的总线输出，以避免现有技术这种是在微引擎内部的报文存储器提供额外的外部总线的读取端口而导致的芯片主频变慢和芯片设计复杂的问题。
本应用场景采用本发明实施例，首先通过调试指令完成报文中间数据的快照而不是直接通过外部总线读取报文存储器中存储的报文中间数据，从而能够降低多核结构的网络处理器后端布线的复杂度，提升了微引擎的主频频率；此外，根据软件驱动下发的命令完成快照数据的外部存储和输出，可以将快照数据搬移存储到微引擎外部的存储器中，避免微引擎内部的报文存储器提供额外的读端口，节省了芯片面积。
图1为本发明实施例的微引擎处理报文中间数据快照功能的实现方法， 图2为本发明实施例中报文中间数据快照功能实现装置的结构图。基于图2的装置组成结构，图1的微引擎处理报文中间数据快照功能的流程，包括：
步骤101：执行调试指令完成报文中间数据的快照。
一具体实施例中，所述调试指令，包括：
一段存储在指令存储器中的下载和存储指令。执行该指令，可以将报文中间数据从报文存储器搬移到ME快照缓存中。
如图2所示，由软件驱动给微引擎下发命令201，微引擎进入调试模式202，流水线开始执行调试指令。每执行一条调试指令完成一部分报文中间的搬移。报文中间数据从首地址到尾地址搬移完成，快照也就完成，报文中间数据被存储在微引擎快照缓存中。
步骤102：软件驱动下发命令，微引擎完成快照的存储和输出。
如图2所示，由软件驱动给微引擎下发命令201，微引擎进入快照外传模式202，完成快照的外部存储和输出203。
微引擎进入快照外传模式后，硬件按首地址到尾地址的顺序读取快照缓存，将报文片段传递到外部存储器，其中，报文的长度是一定的，所以传递消息片段的数目也是一定的，该数目设为N。外部存储器接收N个报文快照片段后，上报软件驱动完成信号，表明快照传递完成。软件驱动接收到此信号后，从外部存储器中读取出报文快照，完成整个快照的输出。
分不同的具体应用实例分别对上述本发明实施例进行具体阐述如下：
应用实例一：
图3为应用本发明实施例的应用实例一所述的报文中间数据快照实现方法的流程图，图4为应用本发明实施例的应用实例一所述的报文中间数据快照实现装置的结构图，基于图4所示的装置组成结构，图3的微引擎处理报文中间数据快照功能的流程，包括：
步骤301，下载调试指令，设置断点；
在这里，调试指令是一段存储在指令存储器中的下载和存储指令。由于报文中间数据在PKT_RAM中的偏移首地址和尾地址是固定的，所以编辑一段调试指令，使其完成报文的下载和存储工作，下载的地址指向PKT_RAM中的报文中间数据的首地址到尾地址这个区间。
如图4所示，软件驱动通过总线将调试指令预先下载到指令存储器中的一个特殊的区域401。在调试模式时，软件驱动会下发调试断点。指令执行到断点处将会暂停往下执行。
步骤302，指令执行到断点处，跳转到调试指令；
指令执行到断点时，将不会继续往下执行剩余指令，而是跳转到预先下载到指令存储器中的特殊区域的调试指令的入口。
步骤303，执行调试指令，完成报文中间数据的搬移和暂存；
指令执行地址跳转到调试指令的入口，流水线开始执行调试指令。如图4所示，流水线执行第一条调试指令完成报文中间数据首地址对应的报文片段的搬移，将其搬移到快照缓存中402。按地址顺序，每一条指令完成一部分报文片段的搬移，直到调试指令执行完毕，报文中间数据搬移完成403。
具体地，如图5所示为应用本发明实施例的应用实例一所述的调试指令执行的示意图，流水线执行第一条调试指令inst0，该条指令为一条下载和存储指令，即从报文存储器中的首地址下载一个报文中间数据的片段501，将其存储到快照缓存的地址0位置502。流水线接着执行第二条调试指令inst1，该指令也同样为一条下载和存储指令，不同的是，完成的动作是从报文存储器中的次地址下载一个报文中间数据的片段501，将其存储到快照缓存的地址1位置502。依次类推，执行完第N-1条指令，即完成报文中间数据到快照缓存的搬移和暂存。
步骤304，快照完成，上报中断信号。
调试指令执行完毕后，报文中间数据全部存储在快照缓存中，微引擎向软件驱动上报快照完成信号，这里的完成信号可以是处理器中断信号404。
应用实例二：
本实施例中，报文中间数据需要被传输到外部存储器中完成输出，图6为应用本发明实施例的应用实例二所述的报文中间数据外部存储和输出的流程图，图7为应用本发明实施例的应用实例二所述的报文中间数据外部存储和输出的结构图，基于图7的装置组成结构，图6的报文中间数据外部存储和输出的流程，包括：
步骤601，软件驱动下发命令，微引擎进入快照外传模式；
如图7所示，软件驱动通过总线给微引擎下发命令，微引擎触发内部的报文调度模块进入快照外传模式701。
步骤602，从快照缓存中读出报文中间数据，传输到外部存储器中；
如图7所示，微引擎内部的报文调度模块按首地址到尾地址的顺序读取快照缓存，将报文片段传递到外部存储器702。
具体地，如图8所示为应用本发明实施例的应用实例二所述的报文调度模块工作的示意图，快照数据分段存储在微引擎的快照缓存中。一共N段数据，分为N个地址存储。
微引擎进入快照外传模式后，报文调度模块按地址顺序，依次从地址0到地址N-1顺次读出报文快照数据的片段801。
报文调度模块会根据读出顺序，在每一个快照片段被读出后，对应的打上地址信息，将每个快照片段顺次存储在外部存储器中802。
步骤603，外部存储器上报传输完成信号，软件驱动下发读取快照命令；
如图7所示，快照数据的长度是一定的，所以传递消息片段的数目也是一定的，该数目设为N。外部存储器接收N个报文快照片段后，上报软 件驱动完成信号703，表明快照传递完成。软件驱动接收到此信号后，下发读取快照命令704。
步骤604，外部存储器接收到快照读取命令后，将快照数据通过总线输出给软件驱动。
由于快照数据较大，而总线位宽有限，所以软件驱动会下发多个快照读取命令，其中，快照读取命令含有外部存储器的读命令和读地址信息，每一条命令对应外部存储器中的一个存储地址，对应一个快照数据片段。快照数据的长度是一定的，为N个片段，所以软件驱动读取N次后，快照数据全部被读出，至此，快照输出完成。
本发明上述实施例所述的ME处理报文中间数据快照功能的实现方法，通过调试指令完成报文中间数据的快照；根据软件驱动下发的命令完成快照数据的存储和输出。本发明实施例首先通过调试指令完成报文中间数据的快照而不是直接通过外部总线读取PKT_RAM的数据，从而能够降低多核结构的网络处理器后端布线的复杂度提升ME主频频率；此外，根据软件驱动下发的命令完成快照数据的外部存储和输出，可以将快照数据搬移存储到ME外部的存储器中，避免ME内部的PKT_RAM提供额外的读端口，节省了PKT_RAM的芯片面积。该方案实现相对简单，易实现。
上述各单元可以由电子设备中的中央处理器(Central Processing Unit，CPU)、数字信号处理器(Digital Signal Processor，DSP)或可编程逻辑阵列(Field－Programmable Gate Array，FPGA)实现。
本发明实施例所述集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实施例的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算 机、服务器、或者网络设备等)执行本发明各个实施例所述方法的全部或部分。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。这样，本发明实施例不限制于任何特定的硬件和软件结合。
本发明实施例还提供一种计算机存储介质，其中存储有计算机可执行指令，该计算机可执行指令配置执行上述一种微引擎处理报文中间数据快照功能的实现方法。
以上所述仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
采用本发明实施例，首先通过调试指令完成报文中间数据的快照而不是直接通过外部总线读取PKT_RAM的数据，从而能够降低多核结构的网络处理器后端布线的复杂度提升ME主频频率；此外，根据软件驱动下发的命令完成快照数据的外部存储和输出，可以将快照数据搬移存储到ME外部的存储器中，避免ME内部的PKT_RAM提供额外的读端口，节省了PKT_RAM的芯片面积。

Claims (17)

  1. 一种微引擎处理报文中间数据快照功能的实现方法，该方法包括：
    通过调试指令完成报文中间数据的快照，得到报文快照数据；
    根据软件命令完成所述报文快照数据的存储和输出，以将报文快照数据搬移存储到微引擎外部的外部存储器中，在外部存储器中完成报文快照数据的总线输出。
  2. 根据权利要求1所述的方法，其中，所述调试指令为一段存储在指令存储器中用于下载和存储的指令。
  3. 根据权利要求2所述的方法，其中，所述通过调试指令完成报文中间数据的快照，得到报文快照数据，还包括：
    执行所述调试指令，提取存储于报文存储器的所述报文中间数据，将所述报文中间数据搬移到微引擎的快照缓存中进行分段存储，一共N段数据，分为N个地址存储。
  4. 根据权利要求2所述的方法，其中，所通过调试指令完成报文中间数据的快照，得到报文快照数据，还包括：
    软件驱动给微引擎下发命令使得微引擎进入调试模式，流水线开始执行所述调试指令，每执行一条调试指令完成一部分报文中间数据的搬移；
    报文中间数据从首地址到尾地址搬移完成后完成所述报文中间数据的快照，报文中间数据从报文存储器中搬移存储在微引擎的快照缓存中。
  5. 根据权利要求3或4所述的方法，其中，所述方法还包括：
    流水线执行第一条调试指令instr0，以从所述报文存储器中的首地址下载一个报文中间数据的片段，将其存储到快照缓存的地址0位置；
    流水线接着执行不同于所述第一条调试指令instr0的第二条调试指令inst1，以从所述报文存储器中的次地址下载一个报文中间数据的片段，将其存储到快照缓存的地址1位置；
    依次类推，执行完第N-1条调试指令，以完成报文中间数据从报文存储器到快照缓存的搬移和暂存。
  6. 根据权利要求1所述的方法，其中，所述根据软件命令完成所述报文快照数据的存储和输出，还包括：
    微引擎进入快照外传模式后，按首地址到尾地址的顺序读取微引擎的快照缓存中的报文快照数据的片段，所述报文中间数据搬移完成实现快照后为所述报文快照数据；
    将报文快照数据的片段传递到外部存储器，外部存储器接收完所述报文快照数据的片段后，上报给软件驱动完成信号，所述完成信号用于表征所述报文快照数据已经传递完成；
    软件驱动接收到所述完成信号后，从外部存储器中读取出所述报文快照数据，完成整个快照的输出。
  7. 根据权利要求6所述的方法，其中，所述微引擎进入快照外传模式后，按首地址到尾地址的顺序读取微引擎的快照缓存中的报文快照数据的片段，还包括：
    微引擎进入快照外传模式后，报文调度模块按地址顺序，依次从地址0到地址N-1顺次读出所述报文快照数据的片段；
    报文调度模块会根据读出顺序，在每一个报文快照数据的片段被读出后，对应的打上地址信息，将每个报文快照数据的片段顺次存储在外部存储器中。
  8. 根据权利要求6所述的方法，其中，所述软件命令为软件驱动下发给微引擎的快照读取命令，包括至少一个快照读取命令；
    所述快照读取命令包含：外部存储器的读命令和读地址信息；
    每一条快照读取命令对应外部存储器中的一个存储地址，对应一个快照数据片段；
    所述报文快照数据的长度是一定的，为N个片段，在所述软件驱动读取N次后，所述报文快照数据被全部读出。
  9. 一种微引擎处理报文中间数据快照功能的实现装置，所述装置包括：微引擎、软件驱动、外部存储器；其中，
    微引擎，配置为通过调试指令完成报文中间数据的快照，得到报文快照数据；根据所述软件驱动下发的命令以完成所述报文快照数据存储至所述外部存储器中进行输出；
    软件驱动，配置为下发软件命令给所述微引擎；
    外部存储器，配置为存储所述报文快照数据，完成报文快照数据的总线输出。
  10. 根据权利要求9所述的装置，其中，所述调试指令为一段存储在指令存储器中用于下载和存储的指令。
  11. 根据权利要求10所述的装置，其中，所述装置还包括：报文存储器，配置为存储所述报文中间数据；
    所述微引擎，还包括快照缓存，配置为在微引擎执行所述调试指令，提取存储于所述报文存储器的所述报文中间数据后，存储从所述报文存储器搬移过来的报文中间数据，且以分段存储的形式存储搬移过来的报文中间数据，一共N段数据，分为N个地址存储。
  12. 根据权利要求10所述的装置，其中，所述装置还包括：报文存储器，配置为存储所述报文中间数据；
    所述微引擎，还包括流水线和快照缓存；其中，
    所述流水线，配置为在软件驱动给微引擎下发命令使得微引擎进入调试模式后，开始执行所述调试指令，每执行一条调试指令完成一部分报文中间数据的搬移；
    所述快照缓存，配置为在微引擎执行所述调试指令，提取存储于所述 报文存储器的所述报文中间数据后，存储从所述报文存储器搬移过来的报文中间数据，在报文中间数据从首地址到尾地址搬移完成后完成所述报文中间数据的快照中。
  13. 根据权利要求11或12所述的装置，其中，所述流水线，还配置为：
    执行第一条调试指令instr0，以从所述报文存储器中的首地址下载一个报文中间数据的片段，将其存储到快照缓存的地址0位置；
    接着执行不同于所述第一条调试指令instr0的第二条调试指令inst1，以从所述报文存储器中的次地址下载一个报文中间数据的片段，将其存储到快照缓存的地址1位置；
    依次类推，执行完第N-1条调试指令，以完成报文中间数据从报文存储器到快照缓存的搬移和暂存。
  14. 根据权利要求9所述的装置，其中，所述微引擎，还包括快照缓存，配置为在微引擎执行所述调试指令，提取存储于所述报文存储器的所述报文中间数据后，存储从所述报文存储器搬移过来的报文中间数据；
    所述微引擎，还配置为进入快照外传模式后，按首地址到尾地址的顺序读取所述快照缓存中的报文快照数据的片段，所述报文中间数据搬移完成实现快照后为所述报文快照数据；将报文快照数据的片段传递到所述外部存储器；
    所述外部存储器，还配置为接收完所述报文快照数据的片段后，上报给所述软件驱动完成信号，所述完成信号用于表征所述报文快照数据已经传递完成；
    所述软件驱动，还配置为接收到所述完成信号后，从所述外部存储器中读取出所述报文快照数据，完成整个快照的输出。
  15. 根据权利要求14所述的装置，其中，所述微引擎，还包括报文调 度模块，配置为在所述微引擎进入快照外传模式后，按地址顺序，依次从地址0到地址N-1顺次读出所述报文快照数据的片段；根据读出顺序，在每一个报文快照数据的片段被读出后，对应的打上地址信息，将每个报文快照数据的片段顺次存储在所述外部存储器中。
  16. 根据权利要求14所述的装置，其中，所述软件命令为软件驱动下发给微引擎的快照读取命令，包括至少一个快照读取命令；
    所述快照读取命令包含：外部存储器的读命令和读地址信息；
    每一条快照读取命令对应外部存储器中的一个存储地址，对应一个快照数据片段；
    所述报文快照数据的长度是一定的，为N个片段，在所述软件驱动读取N次后，所述报文快照数据被全部读出。
  17. 一种计算机存储介质，其中存储有计算机可执行指令，该计算机可执行指令配置执行上述权利要求1至8任一项所述的微引擎处理报文中间数据快照功能的实现方法。
PCT/CN2016/081616 2015-06-25 2016-05-10 一种微引擎处理报文中间数据快照功能的实现方法及装置 Ceased WO2016206489A1 (zh)

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