WO2016206143A1 - 基于ltps的传输门多路复用电路及液晶显示面板 - Google Patents

基于ltps的传输门多路复用电路及液晶显示面板 Download PDF

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WO2016206143A1
WO2016206143A1 PCT/CN2015/083985 CN2015083985W WO2016206143A1 WO 2016206143 A1 WO2016206143 A1 WO 2016206143A1 CN 2015083985 W CN2015083985 W CN 2015083985W WO 2016206143 A1 WO2016206143 A1 WO 2016206143A1
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Prior art keywords
transmission gate
multiplexing circuit
inverter
display panel
type transistor
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French (fr)
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田勇
赵莽
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to an LTPS-based transmission gate multiplexing circuit and a liquid crystal display panel.
  • LTPS low temperature polysilicon
  • SOP System on Panel
  • the control signals of the general transmission gate type Demux (multiplexer) circuit in the LTPS display panel all need to be extracted from the IC (integrated circuit), which will cause excessive IC control signals in the LTPS display panel, and increase the IC. Design difficulty.
  • the present invention provides a transmission gate multiplexing circuit and a liquid crystal display panel based on LTPS, which are used to reduce the number of IC control signals and reduce the difficulty of IC design.
  • an LTPS-based transmission gate multiplexing circuit comprising:
  • a transfer gate comprising a pair of N-type transistors and P-type transistors having complementary structures
  • An inverter is disposed on a switch side of the transmission gate such that the same turn-on signal before and after the inversion performs control of the transmission gate multiplexing circuit.
  • the inverter is disposed in an array wiring area of the display panel.
  • the same turn-on signal is transmitted to the transfer gate multiplexing circuit through a wiring of a pad extension wiring region.
  • the same turn-on signal is transmitted through a wiring provided by the pad extension wiring region.
  • a wiring for transmitting the same turn-on signal in the pad extension wiring region extends to the array wiring region and is divided into two branches, one of which is reversed by the inverter The phase then reaches a switch side of the transmission gate and the other branch directly reaches the other switch side of the transmission gate.
  • the inverter is disposed on a switching side of the N-type transistor.
  • the inverter is disposed on a switching side of the P-type transistor.
  • the N-type transistor and the P-type transistor are MOSFET tubes.
  • the N-type transistor and the P-type transistor are TFT thin film transistors.
  • a liquid crystal display panel using the transmission gate multiplexing circuit of any of the above is also provided.
  • the invention reduces the number of control signals drawn from the IC side under the premise of ensuring the normal operation of the transmission gate multiplexing circuit, thereby reducing the number of control signal lines drawn from the IC side.
  • the invention effectively utilizes the vacant part of the WOA area for the design of the inverter for controlling the inversion processing of the signal before entering the transmission gate multiplexing circuit, thereby avoiding the vacant part of the bulk of the WOA area and reducing the The load effect phenomenon caused by uneven metal etching.
  • the transmission gate multiplexing circuit trace design provided by the invention reduces the input of the IC side control signal line, effectively shortens the height of the FOUT area, reduces the length of the lower border of the display panel, and is favorable for the display panel to be narrow. The design of the border.
  • FIG. 1 is a schematic structural diagram of a structure of an LTPS display panel in the prior art
  • FIG. 2 is a schematic diagram showing the design of a Demux circuit input to the AA area in the prior art
  • FIG. 3 is a schematic diagram of a Demux circuit design based on a transmission gate in the prior art
  • FIG. 5 is a schematic diagram of driving of a LTPS-based transmission gate multiplexing circuit in accordance with one embodiment of the present invention.
  • the GOA technology is a technology for realizing the progressive scan driving of the gate line by using the existing thin film transistor liquid crystal display Array (array substrate) process to fabricate the gate line scanning driving signal circuit on the Array substrate.
  • the present invention is described by taking an LTPS display panel having a GOA structure as an example, but the scope of application of the present invention is not limited thereto.
  • FIG. 1 is a schematic structural diagram of a LTPS display panel in the prior art, and includes: an AA area, a GOA area, a FOUT area, a WOA area, an IC area, and an FPC area.
  • the AA area is a display area for screen display, and is internally provided with a plurality of pixel units composed of red sub-pixels, green sub-pixels and blue sub-pixels;
  • the GOA area is a gate array area for generating TFTs in the display panel The gate drive signal of the (thin film transistor);
  • the FOUT area is the pad extension wiring area for the trace connection of the IC and the AA area data line;
  • the WOA (Wire On Array) area is the array wiring area for display The connection of the traces around the panel;
  • the IC area is an integrated circuit area for the binding of the IC, and the circuit and the TFT in the panel are driven by the IC;
  • the FPC (Flexible Printed Circuit Board) area is the flexible
  • FIG. 2 is a schematic diagram showing the design of a Demux (multiplexer selector) circuit input to the AA area in the prior art.
  • the Demux circuit uses a time-sharing principle to control one data line for three columns of pixels, such as R (red), G (green), and B (blue) in three columns of pixels.
  • the Demux circuit uses an NMOS type device for control of the Demux circuit. When a single NMOS or PMOS is used for transmission gate switch control, the parasitic capacitances Cgd and Cgs cause a feedthrough effect on the control signal line, causing severe distortion of the signal input to the AA area.
  • FIG. 3 is a schematic diagram of a Demux circuit design based on a transmission gate in the prior art.
  • the Demux circuit utilizes the complementary characteristics of the NMOS and the PMOS to ensure that the waveform of the D signal at the output of the data line signal is normally output. Since the feedthrough effects caused by the parasitic capacitances of NMOS and PMOS cancel each other out, the output waveform does not deform.
  • this Demux circuit control method has a disadvantage in that the number of required CK (clock) control signal lines will be twice that of the single NMOS or PMOS Demux circuit of FIG.
  • FIG. 4 is a schematic diagram of driving of a Demux circuit generally based on a transmission gate in the prior art.
  • each sub-pixel requires a Demux circuit.
  • the unit requires six CK control signal lines to be led out from the IC side.
  • the six CK control signal lines reach the Demux circuit control port via the FOUT area and the WOA area.
  • the circuit in Figure 4 adds three CK control signal lines relative to a single pass gate NMOS or PMOS Demux circuit. The resulting effect is that the IC control signal is too much, increasing the design difficulty of the IC.
  • FIG. 5 is a schematic diagram showing the driving of the LTPS-based transmission gate multiplexing circuit according to an embodiment of the present invention. The present invention will be described in detail below with reference to FIG. Wherein, one transmission gate multiplexing circuit corresponds to one sub-pixel in the control pixel unit.
  • the LTPS-based transmission gate multiplexing circuit includes a transmission gate and an inverter.
  • the transfer gate is composed of a pair of N-type transistors and P-type transistors having complementary structures.
  • the inverter is disposed on a switch side of the transmission gate such that the same turn-on signal before and after the inversion realizes control of the transmission gate multiplexing circuit. Specifically, the same turn-on signal directly reaches the switch side of one transistor in the transfer gate before inverting, and the same turn-on signal is inverted by the inverter and reaches the switch side of the other transistor in the transfer gate.
  • the inverter is disposed within the array wiring area of the display panel, that is, the inverter of FIG. 5 is disposed in the WOA area of FIG.
  • the inverter in the transmission gate multiplexing circuit is placed in the WOA area, effectively utilizing the free portion of the WOA area, avoiding wasting a large vacant portion of the WOA area. Since the inverter is disposed in the WOA region, the concentration of the etching liquid is reduced when the metal layer of the WOA region is formed, and the metal etching unevenness due to the uneven concentration of the etching liquid is reduced, thereby reducing Loading Effect due to uneven metal etching.
  • the same turn-on signal is transmitted to the transfer gate multiplexing circuit through the wiring of the pad extension wiring region.
  • the turn-on signal generated by the IC reaches the inverter located in the WOA area through the wiring disposed in the FOUT area.
  • the turn-on signal is inverted by the inverter and reaches the switch terminal of the N-type transistor or the P-type transistor in the transfer gate multiplexing circuit.
  • the same turn-on signal generated by the IC goes directly through the other branch to the switch terminal of the other transistor in the multiplexer circuit.
  • the same open letter is transmitted through a wiring provided by the pad extension wiring area. number.
  • the same turn-on signal generated by the IC is transmitted through a wire in the FOUT region, and after the wire enters the WOA region, the branch is led to the inverter. Setting a wire to transmit the same turn-on signal in the FOUT area can reduce the number of traces in the FOUT area, effectively shorten the height of the FOUT area, and reduce the length of the lower border of the display panel, which is beneficial to the design of the narrow frame.
  • the GOA is located on the left and right sides of the display panel, when the CK signal is used to control the GOA, it is more suitable to set the inverter in the transmission gate multiplexing circuit on both sides. WOA area.
  • a branch in the transmission gate where no inverter is provided is disposed in the WOA area, and the idle portion in the WOA area is utilized more fully to reduce the wiring setting in the FOUT area. That is to say, a wiring that transmits the same turn-on signal in the FOUT region extends to the WOA region and is divided into two branches, one of which is inverted by the inverter and reaches the switching side of a transistor in the transmission gate multiplexing circuit. The other branch directly reaches the switching side of the other transistor in the transmission gate multiplexing circuit.
  • the inverter is disposed on the switching side of the N-type transistor, that is, the output of the inverter disposed in the WOA region is coupled to the switching side of the N-type transistor.
  • the turn-on signal output by the IC is inverted by the inverter and reaches the switch side of the N-type transistor, and the same turn-on signal output by the IC directly reaches the switch side of the P-type transistor.
  • the inverter is disposed on the switching side of the P-type transistor, that is, the output of the inverter disposed in the WOA region is coupled to the switching side of the P-type transistor.
  • the turn-on signal output by the IC is inverted by the inverter and reaches the switch side of the P-type transistor.
  • the same turn-on signal output by the IC directly reaches the switch side of the N-type transistor.
  • the inverter is disposed on the switching side of the N-type transistor in the transmission gate or on the switching side of the P-type transistor, and is related to the set ON signal level.
  • the N-type transistor and the P-type transistor are MOSFET tubes. Specifically, a pair of N-type MOSFETs and P-type MOSFETs having complementary structures are used to form a transfer gate in the multiplexer circuit.
  • the N-type transistor and the P-type transistor are TFT thin film transistors. Specifically, a pair of transmission gates in a multiplexing circuit are fabricated using a pair of N-type TFT thin film transistors having complementary structures and P-type TFT thin film transistors. On the liquid crystal display panel, especially when more and more driving circuits are fabricated on an Array substrate by an Array process, a TFT thin film transistor is preferable.
  • the MOSFET can also be used when the pass gate multiplexing circuit is not disposed on the array substrate or in other types of circuits.
  • a liquid crystal display panel employing the above transmission gate multiplexing circuit.
  • the liquid crystal display panel reduces the number of CK control signal lines drawn from the IC side under the premise of ensuring the normal operation of the transmission gate multiplexing circuit.
  • the liquid crystal display panel also effectively utilizes the vacant part of the WOA area to design the inverter for inverting processing before the CK control signal enters the transmission gate multiplexing circuit, thereby avoiding the vacant part of the WOA area and reducing the vacant part of the WOA area. Small load effect due to uneven metal etching.
  • the liquid crystal display panel The input of the IC side signal line is reduced, the height of the FOUT area is effectively shortened, and the length of the lower border of the display panel is reduced, which is advantageous for the design of the narrow frame.

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  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
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Abstract

一种基于LTPS的传输门多路复用电路及液晶显示面板，该电路包括：传输门，其由一对具有互补结构的N型晶体管和P型晶体管构成；反相器，其设置于传输门的一开关侧，使得反相前后的同一开启信号实现对传输门多路复用电路的控制。减少了引出控制信号线的数量，有效地缩短FOUT区域的高度，减小显示面板下边框的长度，有利于窄边框的设计，还避免了WOA区域大块的空余部位，减小了由于金属刻蚀不均造成的负载效应现象。

Description

基于LTPS的传输门多路复用电路及液晶显示面板
相关技术的交叉引用
本申请要求享有2015年6月26日提交的名称为“基于LTPS的传输门多路复用电路及液晶显示面板”的中国专利申请201510364820.3的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及液晶显示技术领域，具体地说，涉及一种基于LTPS的传输门多路复用电路及液晶显示面板。
背景技术
随着LTPS(低温多晶硅)半导体薄膜晶体管的发展，以及LTPS半导体本身超高载流子迁移率的特性，相应的LTPS显示面板周边集成电路也成为大家关注的焦点。越来越多地人投入到SOP(System on Panel，系统面板)的相关技术研究中。
LTPS显示面板中一般的传输门类型Demux(多路复用选择器)电路的控制信号全部都需要从IC(集成电路)引出，由此会造成LTPS显示面板中IC控制信号过多，增加了IC的设计难度。
发明内容
为解决以上问题，本发明提供了一种基于LTPS的传输门多路复用电路及液晶显示面板，用以减少IC控制信号数量，减少IC设计难度。
根据本发明的一个方面，提供了一种基于LTPS的传输门多路复用电路，包括：
传输门，其由一对具有互补结构的N型晶体管和P型晶体管构成；
反相器，其设置于所述传输门的一开关侧，使得反相前后的同一开启信号实现对所述传输门多路复用电路的控制。
根据本发明的一个实施例，所述反相器设置于显示面板的阵列布线区域内。
根据本发明的一个实施例，通过焊盘延伸布线区域的布线传输所述同一开启信号至所述传输门多路复用电路。
根据本发明的一个实施例，通过所述焊盘延伸布线区域设置的一条布线来传输所述同一开启信号。
根据本发明的一个实施例，所述焊盘延伸布线区域内传输所述同一开启信号的一条布线延伸至所述阵列布线区域后分为两支路，其中一支路经所述反相器反相后到达所述传输门的一开关侧，另一支路直接到达所述传输门的另一开关侧。
根据本发明的一个实施例，所述反相器设置于所述N型晶体管的开关侧。
根据本发明的一个实施例，所述反相器设置于所述P型晶体管的开关侧。
根据本发明的一个实施例，所述N型晶体管和所述P型晶体管为MOSFET管。
根据本发明的一个实施例，所述N型晶体管和所述P型晶体管为TFT薄膜晶体管。
根据本发明的另一个方面，还提供了一种采用以上任一项所述传输门多路复用电路的液晶显示面板。
本发明在保证传输门多路复用电路正常工作的前提下，减少了从IC侧引出的控制信号的数量，进而减少了IC侧引出控制信号线的数量。本发明有效地利用WOA区域的空余部位进行反相器的设计，用于控制信号进入到传输门多路复用电路前的反相处理，避免了WOA区域大块的空余部位，减小了由于金属刻蚀不均造成的负载效应现象。本发明提供的传输门多路复用电路走线设计，由于减少了IC侧控制信号线的输入，有效地缩短了FOUT区域的高度，减小了显示面板下边框的长度，有利于显示面板窄边框的设计。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：
图1是现有技术中一种LTPS显示面板的组成结构示意图；
图2是现有技术中输入到AA区的Demux电路设计示意图；
图3是现有技术中一种基于传输门的Demux电路设计示意图；
图4是现有技术中一般传输门Demux电路的驱动示意图；以及
图5是根据本发明的一个实施例的基于LTPS的传输门多路复用电路的驱动示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下结合附图对本发明作进一步地详细说明。
随着LTPS半导体薄膜晶体管的发展，而且由于LTPS半导体本身超高载流子迁移率的特性，相应的液晶显示面板周边集成电路也成为大家关注的焦点。越来越多人投入到SOP的相关技术研究中，并使得SOP技术逐步成为现实。其中，作为LTPS周边电路的GOA(Gate Driver On Array，阵列基板行驱动)技术也越来越受到重视。GOA技术就是利用现有薄膜晶体管液晶显示器Array(阵列基板)制程将栅线行扫描驱动信号电路制作在Array基板上，实现对栅线逐行扫描驱动的一项技术。
本发明以具有GOA结构的LTPS显示面板为例进行说明，但本发明的应用范围不限于此。
如图1所示为现有技术中一种LTPS显示面板的组成结构示意图，该显示面板包括：AA区域、GOA区域、FOUT区域、WOA区域、IC区域和FPC区域。其中，AA区域为显示区域，用于画面显示，其内部设有多个由红子像素、绿子像素和蓝子像素构成的像素单元；GOA区域为栅阵列区域，用于产生显示面板内TFT(薄膜晶体管)的栅极驱动信号；FOUT区域为焊盘延伸布线区域，用于IC与AA区域数据线的走线连接；WOA(Wire On Array，阵列布线)区域为阵列布线区域，用于显示面板周围走线的连接；IC区域为集成电路区域，用于IC的绑定，并通过IC驱动面板内的电路与TFT；FPC(挠性印制线路板)区域为挠性电路板布线区域，用于FPC的绑定，IC通过FPC连接显示主板。
如图2所示为现有技术中输入到AA区的Demux(多路复用选择器)电路设计示意图。该Demux电路利用分时原理将一条数据线用于三列像素的控制，如图2中的R(红)、G(绿)和B(蓝)三列像素。该Demux电路使用的是NMOS类型的器件进行Demux电路的控制。当利用单一NMOS或者PMOS进行传输门开关控制时，寄生电容Cgd和Cgs会对控制的信号线造成Feedthrough(馈通)影响，使输入到AA区内的信号发生严重的变形。
如图3所示是现有技术中一种基于传输门的Demux电路设计示意图。该Demux电路利用NMOS和PMOS互补的特性，保证数据线信号输出端的D信号的波形正常输出。由于NMOS和PMOS的寄生电容造成的Feedthrough效应正好相互抵消，输出的波形不会发生变形。但是，这种Demux电路的控制方法有一个缺点，那就是所需要的CK(时钟)控制信号线的数量将会是图2中单一NMOS或者PMOS的Demux电路的两倍。
如图4所示是现有技术中一般基于传输门的Demux电路的驱动示意图。如图4所示，对于包括3个子像素的像素单元，每个子像素都需要一个Demux电路。这样，一个像素 单元就需要6条CK控制信号线从IC侧引出。这6条CK控制信号线经由FOUT区域和WOA区域到达Demux电路控制端口。相对于单传输门NMOS或者PMOS的Demux电路，图4中的电路增加了3条CK控制信号线。由此造成的影响便是使得IC控制信号过多，增加IC的设计难度。IC控制信号过多，增加IC控制信号线数量，使得经由FOUT区域的布线数量增多。FOUT区域的布线数量增多导致FOUT区域的高度增加，使得显示面板的下边框变大，不利于窄边框的设计。
如图5所示为根据本发明的一个实施例的基于LTPS的传输门多路复用电路的驱动示意图，以下参考图5来对本发明进行详细说明。其中，一个传输门多路复用电路对应控制像素单元中的一个子像素。
如图5所示，该基于LTPS的传输门多路复用电路包括传输门和反相器。其中，传输门由一对具有互补结构的N型晶体管和P型晶体管构成。反相器设置于该传输门的一开关侧，使得反相前后的同一开启信号实现对传输门多路复用电路的控制。具体的，该同一开启信号在反相前直接到达传输门中的一个晶体管的开关侧，同时，该同一开启信号经反相器反相后到达传输门中的另一个晶体管的开关侧。由于N型晶体管和P型晶体管的开启电压极性相反，通过设置一反相器，可以通过控制同一开启信号实现同时打开一对N型晶体管和P型晶体，从而使得数据线信号输出端的波形正常输出。
在这种情况下，只需要3个开启信号就能控制一个像素单元中对应3个子像素的3个传输门多路复用电路。相对于图4，本发明所需的开启信号减少，有利于简化产生开启信号的IC的设计，降低IC的设计难度。
在本发明的一个实施例中，该反相器设置于显示面板的阵列布线区域内，也就是将图5中的反相器设置于图1中的WOA区域。将传输门多路复用电路中的反相器设置于WOA区域内，有效利用了WOA区域的空闲部分，避免浪费WOA区域大块空余部分。由于在WOA区设置了反相器，在形成WOA区域的金属层时，使得刻蚀液的浓度降低变小，减小了由于刻蚀液浓度不均导致的金属刻蚀不均，从而减小由于金属刻蚀不均造成的Loading Effect(负载效应)现象。
在本发明的一个实施例中，通过焊盘延伸布线区域的布线传输同一开启信号至传输门多路复用电路。具体的，IC产生的开启信号通过设置于FOUT区域的布线到达位于WOA区域的反相器。该开启信号经该反相器反相后到达传输门多路复用电路中的N型晶体管或P型晶体管的开关端。同时，IC产生的同一开启信号通过另一支路直接到达多路复用电路中另一晶体管的开关端。
在本发明的一个实施例中，通过焊盘延伸布线区域设置的一条布线来传输同一开启信 号。具体的，IC产生的同一开启信号在FOUT区域内通过一条布线进行传输，在该条布线进入WOA区域后引出分支到达反相器。在FOUT区域内设置一条布线传输同一开启信号，可以减少FOUT区域的走线数量，有效地缩短FOUT区域的高度，减小显示面板下边框的长度，有利于窄边框的设计。
当采用具有GOA结构的LTPS显示面板时，由于GOA位于显示面板的左右两侧，当采用CK信号对GOA控制时，更适合于将传输门多路复用电路中的反相器设置于两侧的WOA区域。同时，将传输门中未设置反相器的支路设置于该WOA区域中，更充分利用WOA区域中的空闲部分，减少FOUT区域中的布线设置。也就是说，FOUT区域内传输同一开启信号的一条布线延伸至WOA区域后分为两支路，其中一支路经反相器反相后到达传输门多路复用电路中一晶体管的开关侧，另一支路直接到达传输门多路复用电路中另一晶体管的开关侧。
在本发明的一个实施例中，该反相器设置于N型晶体管的开关侧，即设置于WOA区域的反相器的输出端与N型晶体管的开关侧连接。IC输出的开启信号经该反相器反相后到达N型晶体管的开关侧，IC输出的同一开启信号直接到达P型晶体管的开关侧。
在本发明的一个实施例中，该反相器设置于P型晶体管的开关侧，即设置于WOA区域的反相器的输出端与P型晶体管的开关侧连接。IC输出的开启信号经该反相器反相后到达P型晶体管的开关侧，IC输出的同一开启信号直接到达N型晶体管的开关侧。
该反相器设置于传输门中N型晶体管的开关侧，还是设置于P型晶体管的开关侧，与设定的开启信号电平有关。
在本发明的一个实施例中，该N型晶体管和该P型晶体管为MOSFET管。具体的，采用一对具有互补结构的N型MOSFET管和P型MOSFET管制成多路复用电路中的传输门。在本发明的另一个实施例中，该N型晶体管和该P型晶体管为TFT薄膜晶体管。具体的，采用一对具有互补结构的N型TFT薄膜晶体管和P型TFT薄膜晶体管制成多路复用电路中的传输门。在液晶显示面板上，尤其是越来越多的将驱动电路采用Array制程制作在Array基板上时，优选TFT薄膜晶体管。当该传输门多路复用电路不设置在阵列基板上，或应用在其他类型的电路中，则也可以采用MOSFET管。
根据本发明的另一个方面，还提供了一种采用以上传输门多路复用电路的液晶显示面板。该液晶显示面板在在保证传输门多路复用电路正常工作的前提下，减少了从IC侧引出的CK控制信号线的数量。该液晶显示面板还有效的利用WOA区域的空余部位进行反相器的设计，用于CK控制信号进入到传输门多路复用电路前的反相处理，避免WOA区域大块的空余部位，减小由于金属刻蚀不均造成的负载效应现象。同时，该液晶显示面板 减少了IC侧信号线的输入，有效地缩短FOUT区域的高度，减小显示面板下边框的长度，有利于窄边框的设计。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (13)

  1. 一种基于LTPS的传输门多路复用电路，包括：
    传输门，其由一对具有互补结构的N型晶体管和P型晶体管构成；
    反相器，其设置于所述传输门的一开关侧，使得反相前后的同一开启信号实现对所述传输门多路复用电路的控制。
  2. 根据权利要求1所述的传输门多路复用电路，其中，所述反相器设置于显示面板的阵列布线区域内。
  3. 根据权利要求2所述的传输门多路复用电路，其中，通过焊盘延伸布线区域的布线传输所述同一开启信号至所述传输门多路复用电路。
  4. 根据权利要求3所述的传输门多路复用电路，其中，通过所述焊盘延伸布线区域设置的一条布线来传输所述同一开启信号。
  5. 根据权利要求4所述的传输门多路复用电路，其中，所述焊盘延伸布线区域内传输所述同一开启信号的一条布线延伸至所述阵列布线区域后分为两支路，其中一支路经所述反相器反相后到达所述传输门的一开关侧，另一支路直接到达所述传输门的另一开关侧。
  6. 根据权利要求1所述的传输门多路复用电路，其中，所述反相器设置于所述N型晶体管的开关侧。
  7. 根据权利要求1所述的传输门多路复用电路，其中，所述反相器设置于所述P型晶体管的开关侧。
  8. 根据权利要求1所述的传输门多路复用电路，其中，所述N型晶体管和所述P型晶体管为MOSFET管。
  9. 根据权利要求1所述的传输门多路复用电路，其中，所述N型晶体管和所述P型晶体管为TFT薄膜晶体管。
  10. 根据权利要求2所述的传输门多路复用电路，其中，所述反相器设置于所述N型晶体管的开关侧。
  11. 根据权利要求2所述的传输门多路复用电路，其中，所述反相器设置于所述P型晶体管的开关侧。
  12. 一种液晶显示面板，包括基于LTPS的传输门多路复用电路，所述传输门多路复用电路包括：
    传输门，其由一对具有互补结构的N型晶体管和P型晶体管构成；
    反相器，其设置于所述传输门的一开关侧，使得反相前后的同一开启信号实现对所述 传输门多路复用电路的控制。
  13. 根据权利要求12所述的液晶显示面板，其中，所述反相器设置于显示面板的阵列布线区域内。
PCT/CN2015/083985 2015-06-26 2015-07-14 基于ltps的传输门多路复用电路及液晶显示面板 Ceased WO2016206143A1 (zh)

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