WO2016203175A1 - Electronic structure on ceramic support - Google Patents

Electronic structure on ceramic support Download PDF

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Publication number
WO2016203175A1
WO2016203175A1 PCT/FR2016/051484 FR2016051484W WO2016203175A1 WO 2016203175 A1 WO2016203175 A1 WO 2016203175A1 FR 2016051484 W FR2016051484 W FR 2016051484W WO 2016203175 A1 WO2016203175 A1 WO 2016203175A1
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WO
WIPO (PCT)
Prior art keywords
support
elements
conductive
silicon
semiconductor
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Application number
PCT/FR2016/051484
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French (fr)
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WO2016203175A4 (en
Inventor
Alain Straboni
Alioune SOW
Guocai Sun
Jean-Baptiste BRETTE
Original Assignee
S'tile
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Application filed by S'tile filed Critical S'tile
Publication of WO2016203175A1 publication Critical patent/WO2016203175A1/en
Publication of WO2016203175A4 publication Critical patent/WO2016203175A4/en

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    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12043Photo diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Definitions

  • the present application relates to the field of semi ⁇ conductors, including semiconductor structures used in various fields, such as electronics, micro- or nanoelectronics, optics, optoelectronics, thermoelectric and in the photovoltaic field.
  • French Patent Application No. 03/04676 (B5957) describes in particular a method of manufacturing silicon wafers by sintering silicon powders.
  • European Patent No. 2368265 (B9167) discloses a structure comprising a sintered silicon layer surmounted by a monocrystalline silicon layer.
  • European Patent Application No. 10/192917 discloses a photovoltaic module comprising a plurality of photovoltaic cells integrated on a sintered silicon support.
  • the present invention aims to overcome all or part of the disadvantages of the prior art, and / or to propose an alternative to what exists in the prior art.
  • the present invention provides an electronic structure, a method and a device for making the structure.
  • an embodiment provides a structure comprising a ceramic support comprising one or more conductive boxes electrically insulated from each other and at least one semiconductor element connected to the support by a conductive substance, the conductive substance cooperating with one or more several boxes of the support to ensure an electrical connection.
  • the support is made of sintered silicon and results from the sintering of silicon powders, with or without added silicon oxide powders, silicon nitride and / or silicon carbide, and / or the support is at least partially porous.
  • the conductive substance is a metal layer or metal alloys, or a paste or an adhesive added with conductive materials such as metal powders, and / or conductive compounds or can become conductive by treatment thermal, or the conductive substance is made of a eutectic alloy, such as an aluminum / silicon alloy and / or gold / silicon.
  • the caissons of the support comprise doping substances or pastes containing powders or metal products, these substances or pastes being present in certain determined areas of the support in order to render them conductive.
  • the semiconductor elements comprise elements such as silicon, silicon alloys, and / or III-V or II-VI type semiconductors respectively associating elements of the semiconductor elements.
  • columns III and V or elements of columns II and VI of the Mendeleev table may include passive components, such as one or more capacitors, and / or one or more resistors, and / or one or more coils having a coefficient of self -induction, and / or active components, such as one or more photodiodes, one or more photovoltaic cells, one or more memory elements, one or more integrated circuits, one or more LED light-emitting diode devices, one or more thermoelectric compound elements. silicon and / or silicon alloys and / or one or more other elements.
  • the conductive substance forms a discontinuous layer and connects the support boxes to conductive areas of the semiconductor elements, the semiconductor elements being connected to the support boxes via their rear face. via the conductive substance and / or via conductive layers at least partially covering the edges of the semiconductor elements.
  • the semiconductor elements are connected in series or in parallel or in series-parallel, and / or the support comprises pads allowing the connection to elements external to the structure, the elements external to the structure being for example one or more components, one or more complex systems and / or one or more other structures of the same type as the structure.
  • At least one semiconductor element is a photovoltaic cell comprising an N-type or P-type absorber, an emitter and collector elements on the upper face of the photovoltaic cell or elements of the photovoltaic cell.
  • emitter and interdigitated collector elements and located on the rear face of the semiconductor element close to the support, the junction being of homojunction type, composed of a doped crystalline silicon layer of a certain type associated with a doped crystalline silicon layer of opposite type, or of heterojunction type, junction where the layers are of different nature, such as an amorphous silicon layer and a crystalline silicon layer.
  • the present invention also relates to a method for producing a structure comprising a ceramic support and one or more semiconductor elements arranged on the support, comprising the following steps:
  • step c) comprises a heat treatment such that the conductive substance forms a eutectic between the support and the semiconductor element or elements.
  • pressure is exerted between the support and at least one of the semiconductor elements during step c).
  • the support is at least partially porous and pumping is carried out during step c) from the face of the support not receiving the semiconductor element or elements.
  • the conductive substance is disposed in distinct areas on the support and / or the conductive substance occupies a larger area than or equal to the surface of the semiconductor element ⁇ conductors with which she cooperates.
  • the present invention also relates to an apparatus comprising an enclosure enclosing a frame, the frame being adapted to receive an assembly formed by a ceramic support comprising one or more insulated conductors casing electrically from each other and at least one semi ⁇ conductor element connected to the support by a conductive substance so as to form a chamber, wherein the apparatus further comprises:
  • the present invention also relates to a photovoltaic cell comprising a plurality of photovoltaic sub-cells integrated on a support and connected together, in which the links between the photovoltaic sub-cells are provided by conducting boxes of the support and by a conductive substance ensuring the fixation of the photovoltaic cells. sub-picture ⁇ voltaic cells on the support.
  • Figures 1 to 3 and 4 to 6 illustrate steps of providing a structure according to the present invention
  • Fig. 7 shows a device usable in the present invention.
  • FIGS 8 to 11 illustrate further steps of providing a structure according to the present invention.
  • FIGS 12 to 16 illustrate steps of making photovoltaic modules according to the present invention.
  • reference numeral 1 denotes a ceramic substrate serving as a support.
  • the substrate or support 1 may be of sintered silicon, but also of any other suitable ceramic, such as, for example, a suitable silicon aluminate.
  • the support 1 is insulating or semi-insulating. If by nature the support 1 is too conductive, treatments such as surface oxidation and / or volume can be made to make it sufficiently insulating.
  • the support 1 is made of sintered silicon, it may have been obtained by sintering only silicon powders, or by sintering silicon powders to which silicon oxide, silicon nitride and / or silicon oxide powders have been added. silicon carbide, etc.
  • the support 1 can also be slightly doped, if it remains sufficiently insulating.
  • the support 1 comprises conductive boxes 3, 5 and 7.
  • the boxes 3, 5 and 7 are formed in the upper part of the support 1. They are separate and electrically isolated from each other.
  • the boxes 3, 5 and 7 can be made in different ways.
  • doping substances or pastes containing powders or metallic products are reported on the surface of the support 1 by means of a deposit, or printing techniques such as by laser printer or by serigraphy.
  • the support 1 may be at least partially porous and a conductive paste is inserted into the pores where a well is desired.
  • conductive powders such as powders of doping substances or metal powders or containing metallic products, can be inserted at the desired locations during the production of the support 1.
  • the upper surface 8 of the support 1 carries a conducting layer 9 formed of several sections 10, 12 and 14.
  • the sections 10, 12 and 14 are isolated from one another and in contact with at least one of the support boxes. .
  • the section 10 is in contact with the caisson 3
  • the section 12 is in contact with the caisson 5
  • the section 14 is in contact with the caisson 7.
  • elements 16 and 18 are semiconductor elements.
  • the semiconductor element 16 comprises a lower face 20 and an upper face 22.
  • the lower face 20 comprises a contact 25.
  • the upper face 22 comprises two contacts 27 and 28.
  • the lower face 20 is disposed substantially on the section 10 of the conductive layer 9, so that the contact 25 is electrically connected to the box 3.
  • the semiconductor element 18 comprises a lower face 30 and an upper face 32.
  • the lower face 30 comprises three contacts 34, 35 and 36.
  • the upper face 32 comprises three contacts 37, 38 and 39.
  • the lower face 30 is disposed substantially on the sections 12 and 14 of the conductive layer 9.
  • the contacts 34 and 35 of the element 18 are electrically connected to the box 5 and the contact 36 is electrically connected to the box 7.
  • Semiconductor elements 16 and 18 may comprise a variety of materials. For example, they may be based on silicon, one or more silicon alloys such as silicon / germanium alloy, or type III semiconductors. V or II-VI, which combine elements of columns III and V or elements of columns II and VI of Mendeleev's table.
  • the semiconductor elements 16 and 18 may also be very diverse in nature. Contacts 25, 27, 28, 34, 35, 36, 37, 38 and 39 can be connected to the internal components of semiconductor elements 16 and 18.
  • the semiconductor elements ⁇ conductors 16 and 18 will not be detailed. For example, they may be discrete components, such as one or more resistors, one or more capacitors, one or more self-inductive coils or a mixture of these various components.
  • the semiconductor elements 16 and 18 may also be active components, such as one or more photodiodes, one or more photovoltaic cells, one or more memory elements, one or more integrated circuits, one or more LED light-emitting diode devices, one or more thermoelectric elements composed of silicon and / or silicon alloys, a mixture of the preceding elements and / or one or more other elements.
  • the semi elements ⁇ conductors 16 and 18 may also comprise a mixture of active and passive components.
  • the semiconductor elements 16 and 18 may be doped differently, for example one of the semiconductor elements is doped P or P + type and the other type N or N +.
  • a contact 40 and a conductive connection 42 are shown in Figure 3 and a contact 40 and a conductive connection 42.
  • the contact 40 optional, is in contact with the box 7 and allows the connection of the box 7 with one or more external elements, not shown.
  • the link 42 makes it possible to electrically connect the contact 25 of the semiconductor element 16 to the contact 37 of the semiconductor element 18 via the conductive zone 3 of the support 1.
  • the link 42 can be made in various ways.
  • the bond 42 may be made by deposition and / or using conventional photolithography means. It can also be achieved by means of welded son, welding tapes or using printing means by laser printer or screen printing. In FIG. 3, only an example of link 42 is shown. It goes without saying that any desired connection is possible.
  • portions of the semiconductor elements 16 and 18 may be connected in series, in parallel, or in serial / parallel association.
  • the connections have been established, the layers can be deposited on all elements semiconductor ⁇ conductors to protect them from radiation, chemical, oxidation, or passivate, for photovoltaic cells to form one or more anti-reflective layers.
  • contacts of the type of the contact 40 may be present although this is not shown. These contacts allow connection to external elements such as components, complex systems such as integrated circuits, or other carriers of the type of support 1.
  • the semiconductor elements 16 and 18 are a priori made completely before their insertion on the support 1 and are reported individually. However it is conceivable that some phases of the embodiment of semiconductor elements 16 and 18 are made after the postponement on the carrier 1. It is also conceivable that the semiconductor elements ⁇ conductors 16 and 18 are part of a set and reported simultaneously on the support 1.
  • the conductive layer 9 thus has a dual function: to allow the passage of an electric current and to allow the attachment of the semiconductor elements. Note that the conductive layer 9 can be placed on the semiconductor element ⁇ driver and / or on the support and it can occupy a smaller surface area, greater than or equal to that of the semiconductor element fix on the support.
  • the conductive layer 9 can be made in various ways.
  • semiconductor elements 16 and 18 may be glued or soldered using filler materials such as glues, pastes, or screen-printing inks.
  • the semiconductor elements 16 and 18 may also be soldered with layers deposited on the underside or on the support surface prior to fixing the semi ⁇ conductor elements on the support.
  • the semiconductor elements 16 and 18 can be made integral with the support 1 by eutectic bonding.
  • the conductive layer 9 is formed of a layer of metal, such as aluminum or gold, which in melting forms an alloy with the materials of the support and the semiconductor element, making the connection particularly solid.
  • Eutectic bonding has various advantages. For example, the formation of a eutectic makes the connection very conductive. Also, the eutectic bonding connection is able to withstand subsequent heat treatments, whether the treatment temperature is lower or even slightly higher than the eutectic forming temperature, which is 577 ° C in the case of the eutectic aluminum / silicon.
  • the various modes of attachment described above are particularly advantageous if the support is at least slightly porous, which is easy to achieve if the support is based on sintered silicon. Indeed, in this case, the material or materials of the conductive layer penetrate the porosity channels of the support and form a solid and conductive assembly.
  • a support 50 corresponds to the support 1 of FIG. 1.
  • the support 50 is made of sintered silicon. As is generally the case for sintered silicon, the support 50 is slightly porous and has porosity channels.
  • an aluminum layer 52 On the upper face 51 of the support 50 is arranged an aluminum layer 52 in several sections 54, 56 and 58.
  • the aluminum layer 52 may for example be deposited under vacuum or by any means of screen printing or jet printing. of ink using pastes or liquids containing aluminum.
  • the aluminum layer 52 is of low thickness, typically from a few fractions of a micrometer (0.5 ⁇ m for example) to a few tens of microns (30 ⁇ m for example).
  • the aluminum of the layer 52 is then heated in an oven during a heat treatment step.
  • the oven is set at a temperature suitable for the formation of a eutectic, for example between 700 and 800 ° C.
  • a large part of the aluminum enters the porosity channels and reacts with the silicon.
  • the aluminum penetrates to a considerable depth, for example of the order of 10 to 150 ⁇ m.
  • the aluminum remains both in metal form and forms a silicon / aluminum alloy in contact with the silicon surrounding the porosity channels. This results in the formation of conductive boxes in the support 50.
  • the aluminum also forms an alloy in contact with the silicon of the surface 51 of the support.
  • the support 50 comprises conductive boxes 60, 62 and 64.
  • the boxes 60, 62 and 64 are isolated from each other.
  • the boxes 60, 62 and 64 may have a irregular shape, but they are deep, which allows them to ensure their role as drivers.
  • the casings 60, 62 and 64 respectively result from the sections 54, 56 and 58 of the aluminum layer 52.
  • what remains of the sections 54, 56 and 58 on the surface 52 is reduced to little and is referenced 54 ', 56' and 58 '. If desired, surfacing can be performed to remove any traces 54 ', 56' and 58 '.
  • semiconductor elements 66 and 68 are prepared to be fixed on the support 50.
  • the semiconductor elements 66 and 68 respectively correspond to the semiconductor elements 16 and 18 of FIG. semiconductor elements 66 and 68 are less detailed than the semiconductor elements 16 and 18 and are shown only with rear contacts 70, 72, 73 and 74 respectively corresponding to the contacts 25, 34, 35 and 36 of the semiconductor elements.
  • Aluminum for example in paste form, is disposed at the rear of the semiconductor elements 66 and 68.
  • the aluminum forms a layer 76 on the entire rear face of the semiconductor element 66.
  • the aluminum forms two disjointed sections 78 and 79.
  • the semiconductor elements 66 and 68 are then presented to occupy on the support 50 a place corresponding to the place of the semiconductor elements 16 and 18 of Figure 3.
  • the assembly thus formed is designated by the reference 80.
  • the assembly 80 formed by the support 50 and the semiconductor elements 66 and 68 can be placed in a conventional furnace. If necessary, the semiconductor elements 66 and 68 will be pressed to press them onto the support 50 and, if possible, to expel the gas molecules between the support 50 and the semiconductor elements 66 and 68.
  • the assembly 80 can also be placed in a modified furnace, as will be explained with reference to FIG.
  • an apparatus 84 comprises an enclosure 85.
  • the apparatus 84 comprises heating means for raising the temperature in the enclosure 85, which is symbolized by the letter "T".
  • the temperature rise can for example be achieved by resistive heating or radiation.
  • the enclosure 85 has an opening 87 allowing the introduction of one or more gases.
  • the gas or gases chosen may be, for example, nitrogen and / or argon, gases which do not react with silicon and which make it possible to prevent its oxidation.
  • the value of the pressure P of the selected gas or gases, indicated by the letter "P" in FIG. 7, is of little importance. It may be less than, equal to or greater than the atmospheric pressure.
  • the pressure P can be between 1 and several atmospheres.
  • the enclosure 85 contains a frame 90 defining a chamber 92.
  • the frame 90 is adapted to receive the assembly 80 formed by the support 50 and the semiconductor elements 66 and 68 prepared for adhesion.
  • the assembly 80 has been shown as a simple plate in Figure 7. Nevertheless, the various elements of Figure 6 and their references may be used in the following.
  • the assembly 80 forms a kind of cover of the frame 90 and closes the chamber 92.
  • the assembly 80 preferably rests on a seal 94.
  • the seal 94 is annular .
  • the support 50 is a support obtained by sintering, it can have any shape, for example square or rectangular.
  • a plate 95 may be disposed between the assembly 80 and the seal 94 or the frame 90, in order to avoid any deformation of the wafer.
  • the plate 95 is perforated with openings 95 ', allowing the passage of a gas flow.
  • the frame 90 has an opening 96 putting the chamber 92 in communication with the outside.
  • the opening 96 makes it possible to create a depression in the chamber 92, for example by pumping.
  • the pressure P 'in the chamber 92 is then less than P pressure in the enclosure 85.
  • the pressure difference between P and P ' is of little importance. What is important is that the pressure P 'is less than the pressure P. For example, a pressure P' a hundred times lower than the pressure P is suitable.
  • the rise in temperature causes the formation of eutectic within the sections 76, 78 and 79 of the conductive layer disposed on the underside of the semiconductor elements 66 and 68.
  • the pressure difference PP 'between the inside the enclosure 85 and the chamber 92 causes a gas flow through the support of the assembly 80.
  • the pressure difference PP ' has a triple function.
  • the pressure difference PP ' provides a plating of the semiconductor elements 66 and 68 on the support 50.
  • the semiconductor elements 66 and 68 can thus be held firmly in place and it is useless to exert extra force on them during bonding.
  • the pressure difference PP ' also causes suction of the molten conductive material by the porosity channels.
  • the conductive material thus enters the support 50 and forms a eutectic as has been described in connection with the formation of the caissons of FIGS. 4 and 5. It will be noted that the formation of the conductive caissons does not clog all the pores, and that sufficient number of pores remains open to allow aspiration.
  • the bonding material is aluminum
  • a eutectic is formed with silicon alloy and aluminum at the interface between the semiconductor elements and the support, whether this interface brings into play a box or not.
  • the apparatus 84 can also be used to form the conductive boxes. To do this, the support 50 surmounted by the conductive layer 52 shown in FIG. 4 is placed on the frame 90 in place of the assembly 80. After heating and suction due to the pressure difference PP ', conductive boxes are obtained. in the support 50, like those shown in FIG.
  • a porous or semi-porous ceramic support 100 corresponds to the support 1 of FIG. 1 or to the support 50 of FIG. 4.
  • the support 100 is covered with a conductive layer 102 formed of several disjointed sections 104, 106 and 108.
  • the sections 104, 106 and 108 of the conductive layer 102 extend over ranges corresponding to the bonding areas of the semiconductor elements and the conductive boxes to which they are connected.
  • semiconductor elements 110 and 112 are placed in the desired position on the conductive layer 102 of the medium 100 to form an assembly 113.
  • the elements semiconductor 110 and 112 correspond to the semiconductor elements ⁇ conductors 66 and 68 of Figure 6 and the semiconductor elements ⁇ conductors 16 and 18 of Figure 3.
  • the assembly 113 is placed in the apparatus 84. After treatment, the set 113 has the appearance shown in Figure 10 .
  • Figure 11 shows a partial and enlarged view of the interface between the substrate 100 and the semiconductor element ⁇ leads 110 after bonding.
  • the support 100 is separated from the semiconductor element 110 by an interface 120.
  • the support 100 comprises porosity channels 122.
  • the porosity channels 122 are filled with aluminum to a depth e, forming a conductive layer 124.
  • a silicon-aluminum alloy is formed on the walls of the porosity channels and on either side of the interface 120 to form an irregularly shaped layer 126, bounded by dashes in FIG. 11.
  • the depth e of the layer 124 is sufficient to ensure the desired electrical conduction.
  • the thickness e is between 10 and 50 ⁇ m.
  • the semiconductor element is in the form of a wafer of a shape substantially equal to that of the support.
  • the support may be of sintered silicon, other elements may be joined to silicon.
  • the semiconductor element may for example be a wafer of monocrystalline silicon, polycrystalline silicon, or amorphous silicon or any other semiconductor material.
  • a conductive layer ensuring the bonding and the formation of a Conductive box can be placed between support and semiconductor element and the assembly can be placed in a device like that of Figure 7 for gluing.
  • the silicon can be deposited on a support already provided with a conductive box.
  • the conductive box which can extend substantially over the entire support, may extend beyond the semiconductor element to allow the establishment of an electrical contact.
  • FIGS. 12 and 13 An embodiment of a photovoltaic cell according to the present invention will now be described in relation with FIGS. 12 and 13.
  • a support 150 is, like the supports 1 and 100, made of insulating or semi-insulating ceramic.
  • the support 150 is made of sintered silicon.
  • the support 150 comprises conducting chambers 152, 154 and 156.
  • a contact zone 158 is on the caisson 152 and a contact zone 159 is on the caisson 156.
  • the contact zones 158 and 159 allow the connection of the cell with external elements.
  • a conductive bonding layer 160 formed of two sections 162 and 164.
  • a semiconductor element 166 is placed on the bonding layer 160.
  • the semiconductor element 166 extends substantially on all the support 150, with the exception of the contact zones 158 and 159.
  • the semiconductor element 166 is a photovoltaic cell.
  • the semiconductor element 166 comprises in particular an overdoped rear-face layer (BSF) 170, a passivation layer 168, an absorber 172, a transmitter 174.
  • BSF overdoped rear-face layer
  • the passivation layer 168 consists for example of an oxide or a nitride, and serves to avoid surface recombinations.
  • the passivation layer 168 generally insulating, is pierced with a multitude of small holes 176 filled with a conductive material, for example aluminum.
  • the holes 176 completely pass through the passivation layer 168.
  • the holes 176 are for example made by laser and can be 0.1 mm in diameter; their total area is small compared to the surface total of the passivation layer.
  • the holes 176 are made only where the passivation layer 168 is in contact with the conductive layer 160.
  • the BSF layer 170 may have a thickness of 1.5 ⁇ m.
  • the absorber 172 is preferably a moderately doped monocrystalline silicon layer. Its thickness is, for example, between 10 and 200 ⁇ m. On the absorber 172 is the transmitter 174. The transmitter 174 is thin. The emitter interface 174 / absorber 172 produces a pn junction producing carriers in the presence of adequate illumination. The absorber can be doped with P type and the doped transmitter type N or vice versa.
  • the semiconductor element 166 also comprises collector comb elements 177 and 178, as well as an antireflection layer 179.
  • the collector comb elements 177 and 178 are also comprise collector comb elements 177 and 178, as well as an antireflection layer 179.
  • the collector comb elements 177 and 178 are also comprise collector comb elements 177 and 178, as well as an antireflection layer 179.
  • the anti-reflective layer 178 are on the transmitter 174.
  • the comb members 177 are interconnected; they are located on the part of the transmitter 174 which is above the section 162 of the conductive layer 160.
  • the comb elements 178 are interconnected; they are located on the part of the transmitter 174 which is above the section 164 of the conductive layer 160.
  • the comb elements 177 and 178, as well as the anti-reflective layer 179, can also be made at a later stage of the formation of the photovoltaic cell.
  • the support 150 and the semiconductor element 166 are then fixed by a method according to the present invention, for example using the apparatus 84 of FIG. 7.
  • two laser stripes 180 and 182 intersect the semiconductor element 166 so as to individualize two photovoltaic sub-cells 184 and 186.
  • the portion 188 of the semiconductor element 166 located between the two sub-cells photovoltaic 184 and 186 is then easily removed because it is not fixed to the support 150. Indeed, the layer conductive 160 is discontinuous and is not present under the portion 188 of the semiconductor element 166.
  • Figure 13 shows the finished photovoltaic cell.
  • the insulating plates 190, 191, 193 and 194 are placed on the sidewalls of the photovoltaic subcells 184 and 186 so as to avoid possible electrical shorting .
  • Insulating boards 190 and 193 are optional.
  • the link 196 connects the comb 177 to the caisson 154 and the link 198 connects the comb 178 to the caisson 156.
  • the photovoltaic cell shown in FIG. 13 thus comprises two photovoltaic sub-cells connected in series.
  • the contact areas 158 and 159 constitute the terminals of the photovoltaic cell.
  • the contact zone 158 is connected to the absorber of the photovoltaic sub-cell 184 via the conductive box 152, the conductive section 162 or what remains after fixing and through holes 176 the passivation layer of the sub-cell 184.
  • the comb 177 of the sub-cell 184, connected to the emitter of the sub-cell 184, is connected to the conducting box 154, itself connected to the absorber of the sub-cell 188 via the conductive section 164 or what remains after fixation and conducting holes 176 passing through the passivation layer of the sub-cell 188.
  • the comb 178 of the sub-cell 186, connected to the transmitter of the sub-cell 186, is connected to the conductive box 156, connected to the contact zone 159.
  • a photovoltaic cell according to the present invention may comprise more than two photovoltaic sub-cells.
  • a photovoltaic cell of about 20 cm by 20 cm can have five photovoltaic sub-cells of about 4 cm by 20 cm connected in series.
  • the serial connection of the sub-cells although not necessary, has the advantage, at equal power, of reducing the intensity circulating within the cell or between the cells in case several cells according to the present invention are connected within a module.
  • the combs and their connections can be thinner, which results in space saving and better exposure to light radiation, as well as very low resistive losses in conductive layers and ribbons, hence a significant increase in the efficiency of the cell or the module.
  • a photovoltaic cell according to the present invention can be made in other ways than the cell described in connection with FIGS. 12 and 13.
  • the connections of the photovoltaic sub-cells of a cell according to the present invention can be buried, as will be described below in connection with Figures 14 to 16.
  • a ceramic support 200 is shown in plan view.
  • the support 200 is intended to carry two photovoltaic sub-cells and comprises three interdigitated boxes 202, 204 and 206.
  • the boxes 202, 204 and 206 have been represented with different graphics to facilitate understanding.
  • the support 200 is shown in section along the axis AA of FIG. 14.
  • the caissons of the support 200 thus have sections 202-i, 204-j and 206-k.
  • the casing 202 has sections 202-1, 202-2 and 202-3, the casing 204 of the sections 204-1 to 204-5 and the casing 206 of the sections 206-1, 206-2 and 206-3.
  • the wafer 208 is of monocrystalline or multicrystalline silicon and is intended to form two photovoltaic sub-cells.
  • the wafer 208 comprises a photon absorber 210, a passivation layer 211, a first set of collector elements 212-1 to 212-3, a first set of emitter elements 214-1 to 214-5, a second set of transmitter elements 216-1 to 216-3 and a second set of collector elements 218-1 to 218-3. If the absorber 210 is P-type doped, the emitter elements 214-i and 216-i are N- or N-type doped.
  • the collector elements 212-i and 218-i are doped for example of the P + type.
  • the passivation layer 211 is absent under the collector elements 212-i, 218-i and the emitter elements 214-i, 216-i and replaced by a conductive material, shown in black in FIG. 15. To do this, the passivation layer 211 is for example first deposited on the entire lower surface of the absorber 212 comprising the collector elements and the transmitter elements. Then, the passivation layer 211 is pierced at the collector elements and emitter elements and is filled with a conductive substance, such as aluminum.
  • the layer of the conductive substance ensuring the attachment of the wafer 208 to the support 200 has not been shown in FIG. 15. It goes without saying that it may be present under each collector element and each transmitter element. The layer of conductive substance may also be present under the passivation layer, if care is taken that it does not cause a short circuit between the conductive elements (caissons, collector elements and transmitter elements).
  • the collector elements are wide, for example 1 mm.
  • the transmitter elements are wider, for example 5 mm.
  • the collector elements 212-1, 212-2 and 212-3 are respectively on the caissons 202-1, 202-2 and 202-3, and are in electrical contact with them.
  • the transmitter elements 214-1, 214-2 and 214-3 are respectively on the caissons 204-1, 204-2 and 204-3 and are in electrical contact with them.
  • the transmitter elements 216-1, 216-2 and 216-3 are respectively on the casings 206-1, 206-2 and 206-3 and are in electrical contact with them.
  • the collector element 218-1 is located on the caisson 204-3 and is electrically connected to the emitter element 214-3 via the caisson 204-3.
  • Collector elements 218-2 and 218-3 are located respectively on the caissons 204-4 and 204-5 and are in electrical contact with them.
  • Contact zones 220 and 222 are respectively in contact with the box sections 202-1 and 206-3.
  • the contact areas 220 and 222 constitute the output terminals of the photovoltaic module.
  • the absorber 208 comprises on the upper face an antireflection layer, not shown in Figure 15 for the sake of clarity.
  • a laser stripe L intersects the absorber so as to isolate two photovoltaic subcells C1 and C2.
  • the laser streak L is optional, because a priori the charge carriers remain confined in the two regions C1 and C2 of the absorber without creating a short circuit at this level.
  • FIG. 16 shows a view from above of the support 200, comprising the collector elements 212-i, 218-i, the emitter elements 214-i, 216-i and their connections.
  • the collector elements 212-i, 218-i and the emitter elements 214-i, 216-i cover parts of the caissons 202, 204 and 206.
  • the uncovered parts of the caissons bear the same distinctive signs as in FIG. 14.
  • the collector elements 212-1, 212-2 and 212-3 are connected by a conductive element 230.
  • the conductive element 230 may, for example, be of the same type and made at the same time as the collector elements 210. -i; the conductive member 230 may also result from a groove formed in the passivation layer 211 and filled with a conductive material.
  • the emitter elements 214-1, 214-2 and 214-3 are connected by a conductive element 232.
  • the conductive element 232 may for example be of the same type and made at the same time as the emitter elements 214-i.
  • the conductive element 232 may also consist of metal tracks, for example reported, or by any means, such as by photolithography, screen printing, printing or deposition, or result from a groove of the passivation layer 211 filled with a conductive substance .
  • the collector elements 218-1, 218-2 and 218-3 are connected by a conductive element 234, which may be of the same nature as the conductive element 230.
  • the transmitter elements 216-1, 216-2 and 216-3 are connected by a conductive element 236, which may be of the same nature as the Conductive element 232.
  • the conductive elements 230, 232, 234 and 236 are optional because the boxes 202, 204 and 206 can be charged to electrically connect the collector or transmitter elements that are arranged on them.
  • the conductive elements 230, 232, 234 and 236 may nevertheless be preferred to ensure better conduction.
  • the laser stripe L is represented by a bold line which stops at the level of the box 204 and isolates, as has been said, the photovoltaic subcells C1 and C2.
  • photovoltaic subcells C1 and C2 are connected in series and form a photovoltaic cell having the contact areas 220 and 222 as their terminals.
  • the contact zone 220 is in contact with the collector elements 212-i of the sub-cell C1 via the caisson 202.
  • the PN junction of the cell C1 is formed by the contact between the elements of transmitter 214-i and the absorber 210.
  • the transmitter elements 214-i are connected to the collector elements 218-i of the cell C2 via the caisson 204.
  • the PN junction of the cell C2 is realized by the contact between the transmitter elements 216-i and the absorber 210.
  • the transmitter elements 216-i are connected to the contact zone
  • a photovoltaic cell according to the present invention may comprise more than two sub-cells connected in series.
  • the sub-cells of the cell can also be connected in parallel or series-parallel, etc.
  • several cells according to the present invention can be grouped into a module forming part of the present invention.
  • a photovoltaic cell or module according to the present invention may also include semiconductor elements other than photovoltaic sub-cells.
  • a cell or a module according to the present invention may comprise protection, measurement, regulation or integrated circuits for transmitting and / or receiving electromagnetic or light waves, position control elements, such as GPS, control elements for theft prevention, etc.
  • the support 1 of FIGS. 1 to 5 may comprise any number of semiconductor elements.
  • the support 1 may comprise only one element to semi ⁇ conductor. It can also include several hundred.

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Abstract

The invention concerns a structure comprising a ceramic support. The support comprises one or more conductive enclosures electrically insulated from each other. At least one semi-conductor element is connected to the support by a conductive substance (10, 12, 14) that cooperates with one or more enclosures of the support to provide an electrical connection.

Description

STRUCTURE ELECTRONIQUE SUR SUPPORT CERAMIQUE  ELECTRONIC STRUCTURE ON CERAMIC SUPPORT
La présente demande de brevet revendique la priorité de la demande de brevet français FR15/55520 qui sera considérée comme faisant partie intégrante de la présente description. The present patent application claims the priority of the French patent application FR15 / 55520 which will be considered as an integral part of the present description.
Domaine Field
La présente demande concerne le domaine des semi¬ conducteurs, et notamment les structures semi-conductrices utilisables dans divers domaines, comme en électronique, micro- ou nanoélectronique, optique, optoélectronique, thermoélectrique et dans le domaine photovoltaïque . The present application relates to the field of semi ¬ conductors, including semiconductor structures used in various fields, such as electronics, micro- or nanoelectronics, optics, optoelectronics, thermoelectric and in the photovoltaic field.
Exposé de 1 ' art antérieur Presentation of the prior art
La demande de brevet français N° 03/04676 (B5957) décrit notamment un procédé de fabrication de plaquettes de silicium par frittage de poudres de silicium.  French Patent Application No. 03/04676 (B5957) describes in particular a method of manufacturing silicon wafers by sintering silicon powders.
Le brevet européen N° 2368265 (B9167 décrit une structure comprenant une couche en silicium fritté surmontée d'une couche en silicium monocristallin.  European Patent No. 2368265 (B9167) discloses a structure comprising a sintered silicon layer surmounted by a monocrystalline silicon layer.
La demande de brevet européen N° 10/192917 (B9936) décrit un module photovoltaïque comportant plusieurs cellules photovoltaïques intégrées sur un support en silicium fritté. Résumé European Patent Application No. 10/192917 (B9936) discloses a photovoltaic module comprising a plurality of photovoltaic cells integrated on a sintered silicon support. summary
La présente invention vise à pallier tout ou partie des inconvénients de l'art antérieur, et/ou à proposer une alternative à ce qui existe dans l'art antérieur. Ainsi, la présente invention propose une structure électronique, un procédé et un dispositif pour fabriquer la structure.  The present invention aims to overcome all or part of the disadvantages of the prior art, and / or to propose an alternative to what exists in the prior art. Thus, the present invention provides an electronic structure, a method and a device for making the structure.
Ainsi, un mode de réalisation prévoit une structure comprenant un support en céramique comportant un ou plusieurs caissons conducteurs isolés électriquement les uns des autres et au moins un élément à semi-conducteurs lié au support par une substance conductrice, la substance conductrice coopérant avec un ou plusieurs caissons du support pour assurer une liaison électrique .  Thus, an embodiment provides a structure comprising a ceramic support comprising one or more conductive boxes electrically insulated from each other and at least one semiconductor element connected to the support by a conductive substance, the conductive substance cooperating with one or more several boxes of the support to ensure an electrical connection.
Selon un mode de réalisation de la présente invention, le support est en silicium fritté et résulte du frittage de poudres de silicium additionnées ou non de poudres d'oxyde de silicium, de nitrure de silicium et/ou de carbure de silicium, et/ou le support est au moins partiellement poreux.  According to one embodiment of the present invention, the support is made of sintered silicon and results from the sintering of silicon powders, with or without added silicon oxide powders, silicon nitride and / or silicon carbide, and / or the support is at least partially porous.
Selon un mode de réalisation de la présente invention, la substance conductrice est une couche métallique ou d'alliages métalliques, ou une pâte ou une colle additionnée de matériaux conducteurs comme des poudres métalliques, et/ou de composés conducteurs ou pouvant devenir conducteurs par traitement thermique, ou la substance conductrice est constituée d'un alliage eutectique, comme un alliage aluminium/silicium ou/et or/silicium.  According to one embodiment of the present invention, the conductive substance is a metal layer or metal alloys, or a paste or an adhesive added with conductive materials such as metal powders, and / or conductive compounds or can become conductive by treatment thermal, or the conductive substance is made of a eutectic alloy, such as an aluminum / silicon alloy and / or gold / silicon.
Selon un mode de réalisation de la présente invention, les caissons du support comprennent des substances dopantes ou des pâtes contenant des poudres ou des produits métalliques, ces substances ou ces pâtes étant présentes dans certaines zones déterminées du support afin de les rendre conductrices .  According to one embodiment of the present invention, the caissons of the support comprise doping substances or pastes containing powders or metal products, these substances or pastes being present in certain determined areas of the support in order to render them conductive.
Selon un mode de réalisation de la présente invention, les éléments à semi-conducteurs comportent des éléments tels que du silicium, des alliages de silicium, et/ou des semi-conducteurs de type III-V ou II-VI associant respectivement des éléments des colonnes III et V ou des éléments des colonnes II et VI du tableau de Mendeleïev, et peuvent comprendre des composants passifs, comme une ou plusieurs capacités, et/ou une ou plusieurs résistances, et/ou un ou plusieurs enroulements présentant un coefficient de self-induction, et/ou des composants actifs, comme une ou plusieurs photodiodes, une ou plusieurs cellules photovoltaïques, un ou plusieurs éléments de mémoire, un ou plusieurs circuits intégrés, un ou plusieurs dispositifs à diode électroluminescente LED, un ou plusieurs éléments thermoélectriques composés de silicium et/ou d'alliages de silicium et/ou d'un ou plusieurs autres éléments . According to one embodiment of the present invention, the semiconductor elements comprise elements such as silicon, silicon alloys, and / or III-V or II-VI type semiconductors respectively associating elements of the semiconductor elements. columns III and V or elements of columns II and VI of the Mendeleev table, and may include passive components, such as one or more capacitors, and / or one or more resistors, and / or one or more coils having a coefficient of self -induction, and / or active components, such as one or more photodiodes, one or more photovoltaic cells, one or more memory elements, one or more integrated circuits, one or more LED light-emitting diode devices, one or more thermoelectric compound elements. silicon and / or silicon alloys and / or one or more other elements.
Selon un mode de réalisation de la présente invention, la substance conductrice forme une couche discontinue et relie des caissons du support à des zones conductrices des éléments à semi-conducteurs, les éléments à semi-conducteurs étant connectés aux caissons du support via leur face arrière par l'intermédiaire de la substance conductrice et/ou par l'intermédiaire de couches conductrices recouvrant au moins partiellement les bords des éléments à semi-conducteurs.  According to one embodiment of the present invention, the conductive substance forms a discontinuous layer and connects the support boxes to conductive areas of the semiconductor elements, the semiconductor elements being connected to the support boxes via their rear face. via the conductive substance and / or via conductive layers at least partially covering the edges of the semiconductor elements.
Selon un mode de réalisation de la présente invention, les éléments à semi-conducteurs sont connectés en série ou en parallèle ou en série-parallèle, et/ou le support comporte des plots permettant la connexion à des éléments externes à la structure, les éléments externes à la structure étant par exemple un ou plusieurs composants, un ou plusieurs systèmes complexes et/ou une ou plusieurs autres structures de même type que la structure .  According to one embodiment of the present invention, the semiconductor elements are connected in series or in parallel or in series-parallel, and / or the support comprises pads allowing the connection to elements external to the structure, the elements external to the structure being for example one or more components, one or more complex systems and / or one or more other structures of the same type as the structure.
Selon un mode de réalisation de la présente invention, au moins un élément à semi-conducteurs est une cellule photovoltaïque comportant un absorbeur de type N ou P, un émetteur et des éléments de collecteur sur la face supérieure de la cellule photovoltaïque ou des éléments d'émetteur et des éléments de collecteur interdigités et situés sur la face arrière de l'élément à semi-conducteurs proche du support, la jonction étant de type homoj onction, composée d'une couche de silicium cristallin dopée d'un certain type associée à une couche de silicium cristallin dopée de type opposé, ou de type hétéroj onction, jonction où les couches sont de nature différente, comme une couche de silicium amorphe et une couche de silicium cristallin. According to one embodiment of the present invention, at least one semiconductor element is a photovoltaic cell comprising an N-type or P-type absorber, an emitter and collector elements on the upper face of the photovoltaic cell or elements of the photovoltaic cell. emitter and interdigitated collector elements and located on the rear face of the semiconductor element close to the support, the junction being of homojunction type, composed of a doped crystalline silicon layer of a certain type associated with a doped crystalline silicon layer of opposite type, or of heterojunction type, junction where the layers are of different nature, such as an amorphous silicon layer and a crystalline silicon layer.
La présente invention concerne aussi un procédé pour réaliser une structure comportant un support en céramique et un ou plusieurs éléments à semi-conducteurs disposés sur le support, comportant les étapes suivantes :  The present invention also relates to a method for producing a structure comprising a ceramic support and one or more semiconductor elements arranged on the support, comprising the following steps:
a) réaliser sur le support un ou plusieurs caissons conducteurs isolés électriquement les uns des autres ;  a) carrying on the support one or more conductive boxes electrically insulated from each other;
b) disposer, sur une face du support et/ou une face du ou des éléments à semi-conducteurs, une substance conductrice permettant une fixation;  b) disposing, on one side of the support and / or one face of the semiconductor element or elements, a conductive substance for fixing;
c) fixer le ou les éléments à semi-conducteurs sur le support de sorte que la substance conductrice coopère avec un ou plusieurs caissons du support pour assurer une liaison électrique.  c) fixing the semiconductor element or elements on the support so that the conductive substance cooperates with one or more boxes of the support to provide an electrical connection.
Selon un mode de réalisation de la présente invention, l'étape c) comporte un traitement thermique tel que la substance conductrice forme un eutectique entre le support et le ou les éléments à semi-conducteurs.  According to one embodiment of the present invention, step c) comprises a heat treatment such that the conductive substance forms a eutectic between the support and the semiconductor element or elements.
Selon un mode de réalisation de la présente invention, une pression est exercée entre le support et au moins un des éléments à semi-conducteurs au cours de l'étape c) .  According to one embodiment of the present invention, pressure is exerted between the support and at least one of the semiconductor elements during step c).
Selon un mode de réalisation de la présente invention, le support est au moins partiellement poreux et un pompage est réalisé au cours de l'étape c) à partir de la face du support ne recevant pas le ou les éléments à semi-conducteurs.  According to one embodiment of the present invention, the support is at least partially porous and pumping is carried out during step c) from the face of the support not receiving the semiconductor element or elements.
Selon un mode de réalisation de la présente invention, la substance conductrice est disposée en zones distinctes sur le support et/ou la substance conductrice occupe une surface plus grande, plus petite ou égale à la surface de l'élément à semi¬ conducteurs avec laquelle elle coopère. According to one embodiment of the present invention, the conductive substance is disposed in distinct areas on the support and / or the conductive substance occupies a larger area than or equal to the surface of the semiconductor element ¬ conductors with which she cooperates.
La présente invention concerne aussi un appareil comprenant une enceinte renfermant un bâti, le bâti étant adapté à recevoir un ensemble formé par un support en céramique comportant un ou plusieurs caissons conducteurs isolés électriquement les uns des autres et au moins un élément à semi¬ conducteurs lié au support par une substance conductrice de façon à former une chambre, dans lequel l'appareil comprend en outre : The present invention also relates to an apparatus comprising an enclosure enclosing a frame, the frame being adapted to receive an assembly formed by a ceramic support comprising one or more insulated conductors casing electrically from each other and at least one semi ¬ conductor element connected to the support by a conductive substance so as to form a chamber, wherein the apparatus further comprises:
a) des moyens pour porter la température de l'enceinte à une valeur déterminée ;  a) means for raising the temperature of the enclosure to a determined value;
b) des moyens permettant d'introduire dans l'enceinte un gaz à la pression P non réactif avec ledit ensemble ;  b) means for introducing into the chamber a gas at the pressure P not reactive with said assembly;
c) des moyens permettant de créer une dépression dans la chambre.  c) means for creating a depression in the chamber.
La présente invention concerne aussi une cellule photovoltaïque comportant plusieurs sous-cellules photovoltaïques intégrées sur un support et connectées entre elles, dans lequel les liaisons entre les sous-cellules photovoltaïques sont assurées par des caissons conducteurs du support et par une substance conductrice assurant la fixation des sous-cellules photo¬ voltaïques sur le support. The present invention also relates to a photovoltaic cell comprising a plurality of photovoltaic sub-cells integrated on a support and connected together, in which the links between the photovoltaic sub-cells are provided by conducting boxes of the support and by a conductive substance ensuring the fixation of the photovoltaic cells. sub-picture ¬ voltaic cells on the support.
Brève description des dessins Brief description of the drawings
Ces caractéristiques et avantages, ainsi que d'autres, seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non limitatif en relation avec les figures jointes parmi lesquelles :  These and other features and advantages will be set forth in detail in the following description of particular embodiments in a non-limiting manner with reference to the accompanying drawings in which:
les figures 1 à 3 et 4 à 6 illustrent des étapes de réalisation d'une structure selon la présente invention ;  Figures 1 to 3 and 4 to 6 illustrate steps of providing a structure according to the present invention;
la figure 7 représente un dispositif utilisable dans la présente invention ; et  Fig. 7 shows a device usable in the present invention; and
les figures 8 à 11 illustrent d'autres étapes de réalisation d'une structure selon la présente invention ; et  Figures 8 to 11 illustrate further steps of providing a structure according to the present invention; and
les figures 12 à 16 illustrent des étapes de réalisation de modules photovoltaïques selon la présente invention.  Figures 12 to 16 illustrate steps of making photovoltaic modules according to the present invention.
Description détaillée  detailed description
De mêmes éléments peuvent avoir été désignés par de mêmes références aux différentes figures et, de plus, les diverses figures ne sont pas tracées à l'échelle. Par souci de clarté, seuls les éléments qui sont utiles à la compréhension des modes de réalisation décrits ont été représentés et sont détaillés. The same elements may have been designated by the same references in the various figures and, in addition, the various figures are not drawn to scale. For the sake of clarity, only the elements that are useful for understanding the described embodiments have been shown and are detailed.
Dans la description qui suit, lorsque l'on fait référence à des qualificatifs de position absolue, tels que les termes "avant", "arrière", "haut", "bas", "gauche", "droite", etc., ou relative, tels que les termes "dessus", "dessous", "supérieur", "inférieur", etc., ou à des qualificatifs d'orientation, tels que les termes "horizontal", "vertical", etc., il est fait référence à l'orientation des figures ou à un état dans une position normale d'utilisation. Sauf précision contraire, les expressions "approximativement", "sensiblement", et "de l'ordre de" signifient à 10 % près, de préférence à 5 % près.  In the description which follows, when reference is made to absolute position qualifiers, such as the terms "before", "backward", "up", "down", "left", "right", etc., or relative, such as the terms "above", "below", "upper", "lower", etc., or with qualifiers for orientation, such as the terms "horizontal", "vertical", etc., it refers to the orientation of the figures or a state in a normal position of use. Unless otherwise specified, the terms "approximately", "substantially", and "of the order of" mean within 10%, preferably within 5%.
En figure 1, la référence 1 désigne un substrat en céramique servant de support. Le substrat ou support 1 peut être en silicium fritté, mais aussi en toute autre céramique appropriée, comme par exemple un aluminate de silicium adéquat.  In FIG. 1, reference numeral 1 denotes a ceramic substrate serving as a support. The substrate or support 1 may be of sintered silicon, but also of any other suitable ceramic, such as, for example, a suitable silicon aluminate.
Le support 1 est isolant ou semi-isolant. Si par nature le support 1 est trop conducteur, des traitements comme une oxydation en surface et/ou en volume peuvent être réalisés pour le rendre suffisamment isolant.  The support 1 is insulating or semi-insulating. If by nature the support 1 is too conductive, treatments such as surface oxidation and / or volume can be made to make it sufficiently insulating.
Si le support 1 est en silicium fritté, il peut avoir été obtenu par frittage de poudres de silicium uniquement, ou par frittage de poudres de silicium auxquelles ont été ajoutées des poudres d'oxyde de silicium, de nitrure de silicium, et/ou de carbure de silicium, etc. Le support 1 peut être aussi légèrement dopé, s'il reste suffisamment isolant.  If the support 1 is made of sintered silicon, it may have been obtained by sintering only silicon powders, or by sintering silicon powders to which silicon oxide, silicon nitride and / or silicon oxide powders have been added. silicon carbide, etc. The support 1 can also be slightly doped, if it remains sufficiently insulating.
Le support 1 comporte des caissons conducteurs 3, 5 et 7. Les caissons 3, 5 et 7 sont réalisés dans la partie supérieure du support 1. Ils sont distincts et isolés électriquement les uns des autres.  The support 1 comprises conductive boxes 3, 5 and 7. The boxes 3, 5 and 7 are formed in the upper part of the support 1. They are separate and electrically isolated from each other.
Les caissons 3, 5 et 7 peuvent être réalisés de différentes manières. Par exemple, des substances dopantes ou des pâtes contenant des poudres ou des produits métalliques sont rapportés en surface du support 1 à l'aide d'un dépôt, ou de techniques d'impression comme par imprimante laser ou par sérigraphie. Aussi, le support 1 peut être au moins partiellement poreux et une pâte conductrice est insérée dans les pores là où un caisson est souhaité. Aussi, si le support 1 résulte du frittage de poudres, des poudres conductrices, comme des poudres de substances dopantes ou des poudres métalliques ou contenant des produits métalliques, peuvent être insérées aux endroits souhaités lors de la réalisation du support 1. The boxes 3, 5 and 7 can be made in different ways. For example, doping substances or pastes containing powders or metallic products are reported on the surface of the support 1 by means of a deposit, or printing techniques such as by laser printer or by serigraphy. Also, the support 1 may be at least partially porous and a conductive paste is inserted into the pores where a well is desired. Also, if the support 1 results from the sintering of powders, conductive powders, such as powders of doping substances or metal powders or containing metallic products, can be inserted at the desired locations during the production of the support 1.
En figure 2, la surface supérieure 8 du support 1 porte une couche conductrice 9 formée de plusieurs tronçons 10, 12 et 14. Les tronçons 10, 12 et 14 sont isolés les uns des autres et en contact avec au moins un des caissons du support. En figure 2, le tronçon 10 est en contact avec le caisson 3, le tronçon 12 est en contact avec le caisson 5 et le tronçon 14 est en contact avec le caisson 7.  In FIG. 2, the upper surface 8 of the support 1 carries a conducting layer 9 formed of several sections 10, 12 and 14. The sections 10, 12 and 14 are isolated from one another and in contact with at least one of the support boxes. . In FIG. 2, the section 10 is in contact with the caisson 3, the section 12 is in contact with the caisson 5 and the section 14 is in contact with the caisson 7.
En figure 3, outre les éléments de la figure 2, sont représentés des éléments 16 et 18. Les éléments 16 et 18 sont des éléments à semi-conducteurs .  In Figure 3, in addition to the elements of Figure 2, are shown elements 16 and 18. The elements 16 and 18 are semiconductor elements.
L'élément à semi-conducteurs 16 comprend une face inférieure 20 et une face supérieure 22. La face inférieure 20 comprend un contact 25. La face supérieure 22 comprend deux contacts 27 et 28. La face inférieure 20 est disposée sensiblement sur le tronçon 10 de la couche conductrice 9, ce qui fait que le contact 25 est connecté électriquement au caisson 3.  The semiconductor element 16 comprises a lower face 20 and an upper face 22. The lower face 20 comprises a contact 25. The upper face 22 comprises two contacts 27 and 28. The lower face 20 is disposed substantially on the section 10 of the conductive layer 9, so that the contact 25 is electrically connected to the box 3.
L'élément à semi-conducteurs 18 comprend une face inférieure 30 et une face supérieure 32. La face inférieure 30 comprend trois contacts 34, 35 et 36. La face supérieure 32 comprend trois contacts 37, 38 et 39. La face inférieure 30 est disposée sensiblement sur les tronçons 12 et 14 de la couche conductrice 9. Les contacts 34 et 35 de l'élément 18 sont connectés électriquement au caisson 5 et le contact 36 est connecté électriquement au caisson 7.  The semiconductor element 18 comprises a lower face 30 and an upper face 32. The lower face 30 comprises three contacts 34, 35 and 36. The upper face 32 comprises three contacts 37, 38 and 39. The lower face 30 is disposed substantially on the sections 12 and 14 of the conductive layer 9. The contacts 34 and 35 of the element 18 are electrically connected to the box 5 and the contact 36 is electrically connected to the box 7.
Les éléments à semi-conducteurs 16 et 18 peuvent comporter des matériaux très divers. Par exemple, ils peuvent être à base de silicium, d'un ou plusieurs alliages de silicium comme l'alliage silicium/germanium, ou de semi-conducteurs de type III- V ou II-VI, qui associent des éléments des colonnes III et V ou des éléments de colonnes II et VI du tableau de Mendeleïev. Semiconductor elements 16 and 18 may comprise a variety of materials. For example, they may be based on silicon, one or more silicon alloys such as silicon / germanium alloy, or type III semiconductors. V or II-VI, which combine elements of columns III and V or elements of columns II and VI of Mendeleev's table.
Les éléments à semi-conducteurs 16 et 18 peuvent aussi être de nature très diverse. Les contacts 25, 27, 28, 34, 35, 36, 37, 38 et 39 peuvent être connectés à des éléments internes des éléments à semi-conducteurs 16 et 18. Les éléments à semi¬ conducteurs 16 et 18 ne seront pas détaillés. Par exemple, ils peuvent être des composants discrets, comme une ou plusieurs résistances, une ou plusieurs capacités, une ou plusieurs bobines auto-inductives ou un mélange de ces divers composants. Les éléments à semi-conducteurs 16 et 18 peuvent aussi être des composants actifs, comme une ou plusieurs photodiodes, une ou plusieurs cellules photovoltaïques, un ou plusieurs éléments de mémoire, un ou plusieurs circuits intégrés, un ou plusieurs dispositifs à diode électroluminescente LED, un ou plusieurs éléments thermoélectriques composés de silicium et/ou d'alliages de silicium, d'un mélange des éléments précédents et/ou d'un ou plusieurs autres éléments. Bien entendu, les éléments à semi¬ conducteurs 16 et 18 peuvent aussi comprendre un mélange de composants actifs et passifs. On notera en outre que les éléments à semi-conducteurs 16 et 18 peuvent être dopés différemment, par exemple un des éléments à semi-conducteurs est dopé de type P ou P+ et 1 ' autre de type N ou N+ . The semiconductor elements 16 and 18 may also be very diverse in nature. Contacts 25, 27, 28, 34, 35, 36, 37, 38 and 39 can be connected to the internal components of semiconductor elements 16 and 18. The semiconductor elements ¬ conductors 16 and 18 will not be detailed. For example, they may be discrete components, such as one or more resistors, one or more capacitors, one or more self-inductive coils or a mixture of these various components. The semiconductor elements 16 and 18 may also be active components, such as one or more photodiodes, one or more photovoltaic cells, one or more memory elements, one or more integrated circuits, one or more LED light-emitting diode devices, one or more thermoelectric elements composed of silicon and / or silicon alloys, a mixture of the preceding elements and / or one or more other elements. Of course, the semi elements ¬ conductors 16 and 18 may also comprise a mixture of active and passive components. Note further that the semiconductor elements 16 and 18 may be doped differently, for example one of the semiconductor elements is doped P or P + type and the other type N or N +.
En outre, en figure 3 sont représentés un contact 40 et une liaison conductrice 42. Le contact 40, optionnel, est en contact avec le caisson 7 et permet la connexion du caisson 7 avec un ou plusieurs éléments extérieurs, non représentés. La liaison 42 permet de relier électriquement le contact 25 de l'élément à semi-conducteurs 16 au contact 37 de l'élément à semi-conducteurs 18 par l'intermédiaire de la zone conductrice 3 du support 1. La liaison 42 peut être réalisée de diverses manières. Par exemple, la liaison 42 peut être réalisée par dépôt et/ou à l'aide de moyens classiques de photolithographie. Elle peut être aussi réalisée au moyen de fils soudés, de rubans de soudure ou à l'aide de moyens d'impression par imprimante laser ou sérigraphie. En figure 3, seul est représenté un exemple de liaison 42. Il va de soi que toute liaison souhaitée est possible. Par exemple, des parties des éléments à semi-conducteurs 16 et 18 peuvent être connectées en série, en parallèle ou en association série/parallèle. Les connections ayant été établies, des couches peuvent être déposées sur l'ensemble des éléments à semi¬ conducteurs afin de les protéger des rayonnements, des attaques chimiques, de l'oxydation, de les passiver ou bien, pour les cellules photovoltaïques, pour former une ou plusieurs couches antireflets. On notera qu'il peut aussi ne pas y avoir de liaisons du type de la liaison 42, toutes les connexions des éléments à semi-conducteurs se faisant par la face inférieure. In addition, in Figure 3 are shown a contact 40 and a conductive connection 42. The contact 40, optional, is in contact with the box 7 and allows the connection of the box 7 with one or more external elements, not shown. The link 42 makes it possible to electrically connect the contact 25 of the semiconductor element 16 to the contact 37 of the semiconductor element 18 via the conductive zone 3 of the support 1. The link 42 can be made in various ways. For example, the bond 42 may be made by deposition and / or using conventional photolithography means. It can also be achieved by means of welded son, welding tapes or using printing means by laser printer or screen printing. In FIG. 3, only an example of link 42 is shown. It goes without saying that any desired connection is possible. For example, portions of the semiconductor elements 16 and 18 may be connected in series, in parallel, or in serial / parallel association. The connections have been established, the layers can be deposited on all elements semiconductor ¬ conductors to protect them from radiation, chemical, oxidation, or passivate, for photovoltaic cells to form one or more anti-reflective layers. It will be noted that there may also be no links of the type of the link 42, all the connections of the semiconductor elements being made by the lower face.
Aussi, plusieurs contacts du type du contact 40 peuvent être présents bien que cela ne soit pas représenté. Ces contacts permettent la connexion à des éléments extérieurs comme des composants, des systèmes complexes tels que des circuits intégrés, ou d' autres supports du type du support 1.  Also, several contacts of the type of the contact 40 may be present although this is not shown. These contacts allow connection to external elements such as components, complex systems such as integrated circuits, or other carriers of the type of support 1.
En figure 3, les éléments à semi-conducteurs 16 et 18 sont a priori réalisés totalement avant leur insertion sur le support 1 et sont rapportés de manière individuelle. On peut cependant envisager que certaines phases de la réalisation des éléments à semi-conducteurs 16 et 18 sont faites après leur report sur le support 1. On peut aussi envisager que les éléments à semi¬ conducteurs 16 et 18 font partie d'un ensemble et reportés simultanément sur le support 1. In Figure 3, the semiconductor elements 16 and 18 are a priori made completely before their insertion on the support 1 and are reported individually. However it is conceivable that some phases of the embodiment of semiconductor elements 16 and 18 are made after the postponement on the carrier 1. It is also conceivable that the semiconductor elements ¬ conductors 16 and 18 are part of a set and reported simultaneously on the support 1.
L'adhésion des éléments à semi-conducteurs 16 et 18 sur le support 1 est assurée par les tronçons 10, 12 et 14 de la couche conductrice 9.  The adhesion of the semiconductor elements 16 and 18 to the support 1 is ensured by the sections 10, 12 and 14 of the conductive layer 9.
La couche conductrice 9 assure ainsi une double fonction : permettre le passage d'un courant électrique et permettre la fixation des éléments à semi-conducteurs. On notera que la couche conductrice 9 peut être placée sur l'élément à semi¬ conducteur et/ou sur le support et qu'elle peut occuper une surface plus petite, plus grande ou égale à celle de l'élément à semi-conducteur à fixer sur le support. La couche conductrice 9 peut être réalisée de diverses manières . The conductive layer 9 thus has a dual function: to allow the passage of an electric current and to allow the attachment of the semiconductor elements. Note that the conductive layer 9 can be placed on the semiconductor element ¬ driver and / or on the support and it can occupy a smaller surface area, greater than or equal to that of the semiconductor element fix on the support. The conductive layer 9 can be made in various ways.
Par exemple, les éléments à semi-conducteurs 16 et 18 peuvent être collés ou soudés à l'aide de matériaux d'apport comme des colles, des pâtes, ou des encres de sérigraphie. Les éléments à semi-conducteurs 16 et 18 peuvent être aussi brasés à l'aide de couches déposées sur leur face inférieure ou sur la surface du support, préalablement à la fixation des éléments à semi¬ conducteurs sur le support . For example, semiconductor elements 16 and 18 may be glued or soldered using filler materials such as glues, pastes, or screen-printing inks. The semiconductor elements 16 and 18 may also be soldered with layers deposited on the underside or on the support surface prior to fixing the semi ¬ conductor elements on the support.
Aussi, les éléments à semi-conducteurs 16 et 18 peuvent être rendus solidaires du support 1 par collage eutectique. Dans ce mode de réalisation, la couche conductrice 9 est formée d'une couche de métal, comme l'aluminium ou l'or, qui en fondant forme un alliage avec les matériaux du support et de l'élément à semi- conducteurs, rendant la connexion particulièrement solide.  Also, the semiconductor elements 16 and 18 can be made integral with the support 1 by eutectic bonding. In this embodiment, the conductive layer 9 is formed of a layer of metal, such as aluminum or gold, which in melting forms an alloy with the materials of the support and the semiconductor element, making the connection particularly solid.
Le collage eutectique présente divers avantages . Par exemple, la formation d'un eutectique rend la connexion très conductrice. Aussi, la connexion par collage eutectique est capable de résister à des traitements thermiques ultérieurs, que la température de traitement soit inférieure ou même légèrement supérieure à la température de formation de 1 ' eutectique, qui est de 577 °C dans le cas de l' eutectique aluminium/silicium.  Eutectic bonding has various advantages. For example, the formation of a eutectic makes the connection very conductive. Also, the eutectic bonding connection is able to withstand subsequent heat treatments, whether the treatment temperature is lower or even slightly higher than the eutectic forming temperature, which is 577 ° C in the case of the eutectic aluminum / silicon.
Les divers modes de fixation décrits ci-dessus sont particulièrement avantageux si le support est au moins légèrement poreux, ce qui est facile à réaliser si le support est à base de silicium fritté. En effet, dans ce cas, le ou les matériaux de la couche conductrice pénètrent dans les canaux de porosité du support et forment un ensemble solide et conducteur.  The various modes of attachment described above are particularly advantageous if the support is at least slightly porous, which is easy to achieve if the support is based on sintered silicon. Indeed, in this case, the material or materials of the conductive layer penetrate the porosity channels of the support and form a solid and conductive assembly.
Pour mieux expliciter ce qui précède, on va maintenant décrire un mode de réalisation de la présente invention en relation avec les figures 4 à 6, dans lesquels le support est en silicium fritté et la couche conductrice en aluminium.  To better explain the foregoing, we will now describe an embodiment of the present invention in connection with Figures 4 to 6, wherein the support is of sintered silicon and the conductive layer of aluminum.
En figure 4, un support 50 correspond au support 1 de la figure 1. Le support 50 est en silicium fritté. Comme cela est généralement le cas pour le silicium fritté, le support 50 est légèrement poreux et présente des canaux de porosité. In FIG. 4, a support 50 corresponds to the support 1 of FIG. 1. The support 50 is made of sintered silicon. As is generally the case for sintered silicon, the support 50 is slightly porous and has porosity channels.
Sur la face supérieure 51 du support 50 est disposée une couche d'aluminium 52 en plusieurs tronçons 54, 56 et 58. La couche d' aluminium 52 peut par exemple être déposée sous vide ou par tout moyen de sérigraphie ou d'impression par jet d'encre en utilisant des pâtes ou liquides contenant de l'aluminium. La couche d'aluminium 52 est d'épaisseur faible, typiquement de quelques fractions de micromètre (0,5 ym par exemple) à quelques dizaines de micromètres (30 ym par exemple) .  On the upper face 51 of the support 50 is arranged an aluminum layer 52 in several sections 54, 56 and 58. The aluminum layer 52 may for example be deposited under vacuum or by any means of screen printing or jet printing. of ink using pastes or liquids containing aluminum. The aluminum layer 52 is of low thickness, typically from a few fractions of a micrometer (0.5 μm for example) to a few tens of microns (30 μm for example).
L' aluminium de la couche 52 est ensuite chauffé dans un four lors d'une étape de traitement thermique. Le four est réglé à une température apte à la formation d'un eutectique, par exemple entre 700 et 800°C. En fondant, une grande partie de l'aluminium pénètre dans les canaux de porosité et réagit avec le silicium. L'aluminium pénètre sur une profondeur assez importante, par exemple de l'ordre de 10 à 150 um. Dans les canaux de porosité, l'aluminium reste à la fois sous forme de métal et forme un alliage silicium/aluminium au contact du silicium entourant les canaux de porosité. Il en résulte la formation de caissons conducteurs dans le support 50. L'aluminium forme aussi un alliage au contact du silicium de la surface 51 du support.  The aluminum of the layer 52 is then heated in an oven during a heat treatment step. The oven is set at a temperature suitable for the formation of a eutectic, for example between 700 and 800 ° C. When melting, a large part of the aluminum enters the porosity channels and reacts with the silicon. The aluminum penetrates to a considerable depth, for example of the order of 10 to 150 μm. In the porosity channels, the aluminum remains both in metal form and forms a silicon / aluminum alloy in contact with the silicon surrounding the porosity channels. This results in the formation of conductive boxes in the support 50. The aluminum also forms an alloy in contact with the silicon of the surface 51 of the support.
Dans les zones de surface où se trouve une grande proportion d'aluminium, la morphologie et les propriétés physiques du matériau, en général du silicium fritté, changent notablement. In surface areas where a large proportion of aluminum is found, the morphology and physical properties of the material, generally sintered silicon, change significantly.
En effet, pendant l'étape de recuit où l' eutectique aluminium/silicium est liquide, les mécanismes de diffusion sont fortement accélérés ; il en résulte une croissance des grains de silicium et une diminution ou une disparition complète de la porosité. Ces deux modifications permettent d'augmenter la conductivité électrique du milieu situé à l'interface entre les éléments à semi-conducteurs et le support, ce qui est bénéfique. Indeed, during the annealing step where the aluminum / silicon eutectic is liquid, the diffusion mechanisms are strongly accelerated; this results in a growth of the silicon grains and a decrease or a complete disappearance of the porosity. These two modifications make it possible to increase the electrical conductivity of the medium located at the interface between the semiconductor elements and the support, which is beneficial.
En figure 5, le support 50 comporte des caissons conducteurs 60, 62 et 64. Les caissons 60, 62 et 64 sont isolés les uns des autres. Les caissons 60, 62 et 64 peuvent avoir une forme irrégulière, mais ils sont profonds, ce qui leur permet de bien assurer leur rôle de conducteurs. Les caissons 60, 62 et 64 résultent respectivement des tronçons 54, 56 et 58 de la couche d'aluminium 52. En figure 5, ce qui reste des tronçons 54, 56 et 58 sur la surface 52 est réduit à peu de chose et est référencé 54', 56' et 58'. Si cela est souhaité, un surfaçage peut être réalisé pour retirer toute trace des tronçons 54', 56' et 58'. In Figure 5, the support 50 comprises conductive boxes 60, 62 and 64. The boxes 60, 62 and 64 are isolated from each other. The boxes 60, 62 and 64 may have a irregular shape, but they are deep, which allows them to ensure their role as drivers. The casings 60, 62 and 64 respectively result from the sections 54, 56 and 58 of the aluminum layer 52. In FIG. 5, what remains of the sections 54, 56 and 58 on the surface 52 is reduced to little and is referenced 54 ', 56' and 58 '. If desired, surfacing can be performed to remove any traces 54 ', 56' and 58 '.
En figure 6, des éléments à semi-conducteurs 66 et 68 sont préparés pour être fixés sur le support 50. Les éléments à semi-conducteurs 66 et 68 correspondent respectivement aux éléments à semi-conducteurs 16 et 18 de la figure 3. Les éléments à semi-conducteurs 66 et 68 sont moins détaillés que les éléments à semi-conducteurs 16 et 18 et sont représentés uniquement avec des contacts arrière 70, 72, 73 et 74 correspondant respectivement aux contacts 25, 34, 35 et 36 des éléments à semi-conducteurs 16 et 18.  In FIG. 6, semiconductor elements 66 and 68 are prepared to be fixed on the support 50. The semiconductor elements 66 and 68 respectively correspond to the semiconductor elements 16 and 18 of FIG. semiconductor elements 66 and 68 are less detailed than the semiconductor elements 16 and 18 and are shown only with rear contacts 70, 72, 73 and 74 respectively corresponding to the contacts 25, 34, 35 and 36 of the semiconductor elements. -conductors 16 and 18.
De l'aluminium, par exemple sous forme de pâte, est disposé à l'arrière des éléments à semi-conducteurs 66 et 68. L'aluminium forme une couche 76 sur toute la face arrière de l'élément à semi-conducteurs 66. Sur la face arrière de l'élément à semi-conducteurs 68, l'aluminium forme deux tronçons disjoints 78 et 79. Les éléments à semi-conducteurs 66 et 68 sont ensuite présentés pour occuper sur le support 50 une place correspondant à la place des éléments à semi-conducteurs 16 et 18 de la figure 3. L'ensemble ainsi formé est désigné par la référence 80.  Aluminum, for example in paste form, is disposed at the rear of the semiconductor elements 66 and 68. The aluminum forms a layer 76 on the entire rear face of the semiconductor element 66. On the rear face of the semiconductor element 68, the aluminum forms two disjointed sections 78 and 79. The semiconductor elements 66 and 68 are then presented to occupy on the support 50 a place corresponding to the place of the semiconductor elements 16 and 18 of Figure 3. The assembly thus formed is designated by the reference 80.
Pour réaliser l'étape thermique permettant de former l'eutectique aluminium/silicium, on peut placer l'ensemble 80 formé par le support 50 et les éléments à semi-conducteurs 66 et 68 dans un four usuel. Le cas échéant, on exercera une pression sur les éléments à semi-conducteurs 66 et 68 pour bien les plaquer sur le support 50 et chasser si possible les molécules de gaz se trouvant entre le support 50 et les éléments à semi-conducteurs 66 et 68. On peut aussi placer l'ensemble 80 dans un four modifié, comme cela va être expliqué en relation avec la figure 7. En figure 7, un appareil 84 comprend une enceinte 85. L'appareil 84 comprend des moyens de chauffage permettant d'élever la température dans l'enceinte 85, ce qui est symbolisé par la lettre « T ». L'élévation de température peut par exemple être réalisée par chauffage résistif ou par rayonnement. L'enceinte 85 comporte une ouverture 87 permettant l'introduction d'un ou plusieurs gaz. Le ou les gaz choisis peuvent être par exemple de l'azote et/ou de l'argon, gaz qui ne réagissent pas avec le silicium et qui permettent d'éviter son oxydation. Dans l'enceinte 85, la valeur de la pression P du ou des gaz choisis, indiquée par la lettre « P » en figure 7, a peu d'importance. Elle peut être inférieure, égale ou supérieure à la pression atmosphérique. Par exemple, la pression P peut être comprise entre 1 et plusieurs atmosphères . To carry out the thermal step for forming the aluminum / silicon eutectic, the assembly 80 formed by the support 50 and the semiconductor elements 66 and 68 can be placed in a conventional furnace. If necessary, the semiconductor elements 66 and 68 will be pressed to press them onto the support 50 and, if possible, to expel the gas molecules between the support 50 and the semiconductor elements 66 and 68. The assembly 80 can also be placed in a modified furnace, as will be explained with reference to FIG. In Figure 7, an apparatus 84 comprises an enclosure 85. The apparatus 84 comprises heating means for raising the temperature in the enclosure 85, which is symbolized by the letter "T". The temperature rise can for example be achieved by resistive heating or radiation. The enclosure 85 has an opening 87 allowing the introduction of one or more gases. The gas or gases chosen may be, for example, nitrogen and / or argon, gases which do not react with silicon and which make it possible to prevent its oxidation. In the enclosure 85, the value of the pressure P of the selected gas or gases, indicated by the letter "P" in FIG. 7, is of little importance. It may be less than, equal to or greater than the atmospheric pressure. For example, the pressure P can be between 1 and several atmospheres.
L'enceinte 85 renferme un bâti 90 définissant une chambre 92. Le bâti 90 est adapté à recevoir l'ensemble 80 formé par le support 50 et les éléments à semi-conducteurs 66 et 68 préparés pour adhésion. Pour simplifier, l'ensemble 80 a été représenté comme une simple plaquette en figure 7. Néanmoins, les divers éléments de la figure 6 ainsi que leurs références pourront être utilisés dans ce qui suit.  The enclosure 85 contains a frame 90 defining a chamber 92. The frame 90 is adapted to receive the assembly 80 formed by the support 50 and the semiconductor elements 66 and 68 prepared for adhesion. For simplicity, the assembly 80 has been shown as a simple plate in Figure 7. Nevertheless, the various elements of Figure 6 and their references may be used in the following.
Une fois mis en place, l'ensemble 80 forme un genre de couvercle du bâti 90 et ferme la chambre 92. L'ensemble 80 repose de préférence sur un joint 94. Si le support 50 est de forme circulaire, le joint 94 est annulaire. On rappelle ici que le support 50 étant un support obtenu par frittage, il peut avoir une forme quelconque, par exemple carrée ou rectangulaire. Aussi, une plaque 95 peut être disposée entre l'ensemble 80 et le joint 94 ou le bâti 90, afin d'éviter toute déformation éventuelle de la plaquette. La plaque 95 est perforée d'ouvertures 95', permettant le passage d'un flux gazeux.  Once put in place, the assembly 80 forms a kind of cover of the frame 90 and closes the chamber 92. The assembly 80 preferably rests on a seal 94. If the support 50 is circular in shape, the seal 94 is annular . It is recalled here that the support 50 is a support obtained by sintering, it can have any shape, for example square or rectangular. Also, a plate 95 may be disposed between the assembly 80 and the seal 94 or the frame 90, in order to avoid any deformation of the wafer. The plate 95 is perforated with openings 95 ', allowing the passage of a gas flow.
Le bâti 90 possède une ouverture 96 mettant la chambre 92 en communication avec l'extérieur. L'ouverture 96 permet de créer une dépression dans la chambre 92, par exemple par pompage. La pression P' dans la chambre 92 est alors inférieure à la pression P dans l'enceinte 85. La différence de pression entre P et P' a peu d'importance. Ce qui importe, c'est que la pression P' soit inférieure à la pression P. Par exemple, une pression P' cent fois inférieure à la pression P convient. The frame 90 has an opening 96 putting the chamber 92 in communication with the outside. The opening 96 makes it possible to create a depression in the chamber 92, for example by pumping. The pressure P 'in the chamber 92 is then less than P pressure in the enclosure 85. The pressure difference between P and P 'is of little importance. What is important is that the pressure P 'is less than the pressure P. For example, a pressure P' a hundred times lower than the pressure P is suitable.
En fonctionnement, la montée en température provoque la formation d'eutectique au sein des tronçons 76, 78 et 79 de la couche conductrice disposée sur la face inférieure des éléments à semi-conducteurs 66 et 68. La différence de pression P-P' entre l'intérieur de l'enceinte 85 et la chambre 92 provoque un flux gazeux à travers le support de l'ensemble 80. La différence de pression P-P' a une triple fonction.  In operation, the rise in temperature causes the formation of eutectic within the sections 76, 78 and 79 of the conductive layer disposed on the underside of the semiconductor elements 66 and 68. The pressure difference PP 'between the inside the enclosure 85 and the chamber 92 causes a gas flow through the support of the assembly 80. The pressure difference PP 'has a triple function.
D'une part, la différence de pression P-P' assure un placage des éléments à semi-conducteurs 66 et 68 sur le support 50. Les éléments à semi-conducteurs 66 et 68 peuvent ainsi être maintenus fermement en place et il est inutile d'exercer une force supplémentaire sur eux pendant le collage.  On the one hand, the pressure difference PP 'provides a plating of the semiconductor elements 66 and 68 on the support 50. The semiconductor elements 66 and 68 can thus be held firmly in place and it is useless to exert extra force on them during bonding.
Ensuite, la différence de pression P-P' fait qu'une aspiration se produit par l'intermédiaire des canaux de porosité du support 50, ce qui fait que des molécules résiduelles de gaz piégées sous les éléments à semi-conducteurs 66 et 68 sont évacuées . On notera que cet effet présente un intérêt très important. En effet, le piégeage de gaz entre deux parties lors d'un collage est un problème gênant et mal résolu dans l'art antérieur. Dans la présente invention, grâce au dispositif de la figure 7 et au fait que le support soit poreux, ce problème est entièrement résolu.  Then, the pressure difference P-P 'causes suction to occur through the support porosity channels 50, whereby residual gas molecules trapped under the semiconductor elements 66 and 68 are evacuated. It should be noted that this effect is of very great interest. Indeed, the trapping of gas between two parts during a bonding is an annoying problem and poorly resolved in the prior art. In the present invention, thanks to the device of Figure 7 and the fact that the support is porous, this problem is completely solved.
Enfin, la différence de pression P-P' provoque aussi une aspiration du matériau conducteur de collage fondu par les canaux de porosité. Le matériau conducteur pénètre ainsi dans le support 50 et forme un eutectique comme cela a été décrit en relation avec la formation des caissons des figures 4 et 5. On notera que la formation des caissons conducteurs ne bouche pas tous les pores, et qu'un nombre suffisant de pores reste ouvert pour permettre l'aspiration. Dans le cas où le matériau de collage est de l'aluminium, il se forme un eutectique avec alliage de silicium et d'aluminium à l'interface entre les éléments à semi-conducteurs et le support, que cette interface mette en jeu un caisson ou non. Finally, the pressure difference PP 'also causes suction of the molten conductive material by the porosity channels. The conductive material thus enters the support 50 and forms a eutectic as has been described in connection with the formation of the caissons of FIGS. 4 and 5. It will be noted that the formation of the conductive caissons does not clog all the pores, and that sufficient number of pores remains open to allow aspiration. In the case where the bonding material is aluminum, a eutectic is formed with silicon alloy and aluminum at the interface between the semiconductor elements and the support, whether this interface brings into play a box or not.
On notera que l'appareil 84 peut aussi servir à former les caissons conducteurs. Pour ce faire, le support 50 surmonté de la couche conductrice 52 représenté en figure 4 est placé sur le bâti 90 à la place de l'ensemble 80. Après chauffage et aspiration due à la différence de pression P-P' , on obtient des caissons conducteurs dans le support 50, comme ceux représentés en figure 5.  Note that the apparatus 84 can also be used to form the conductive boxes. To do this, the support 50 surmounted by the conductive layer 52 shown in FIG. 4 is placed on the frame 90 in place of the assembly 80. After heating and suction due to the pressure difference PP ', conductive boxes are obtained. in the support 50, like those shown in FIG.
On notera aussi que la formation des caissons et que le collage des éléments à semi-conducteurs peuvent être réalisés au cours d'une même étape. Cela va être détaillé en relation avec les figures 8 à 10.  It will also be noted that the formation of the boxes and that the gluing of the semiconductor elements can be carried out during the same step. This will be detailed in relation to FIGS. 8 to 10.
En figure 8, un support 100 en céramique poreuse ou semi-poreuse correspond au support 1 de la figure 1 ou au support 50 de la figure 4. Le support 100 est recouvert d'une couche conductrice 102 formée de plusieurs tronçons disjoints 104, 106 et 108. Les tronçons 104, 106 et 108 de la couche conductrice 102 s'étendent sur des plages correspondant aux plages de collage des éléments à semi-conducteurs et des caissons conducteurs auxquels ils sont reliés.  In FIG. 8, a porous or semi-porous ceramic support 100 corresponds to the support 1 of FIG. 1 or to the support 50 of FIG. 4. The support 100 is covered with a conductive layer 102 formed of several disjointed sections 104, 106 and 108. The sections 104, 106 and 108 of the conductive layer 102 extend over ranges corresponding to the bonding areas of the semiconductor elements and the conductive boxes to which they are connected.
En figure 9, des éléments à semi-conducteurs 110 et 112 sont placés à la position souhaitée sur la couche conductrice 102 du support 100 pour former un ensemble 113. Les éléments à semi- conducteurs 110 et 112 correspondent aux éléments à semi¬ conducteurs 66 et 68 de la figure 6 ainsi qu'aux éléments à semi¬ conducteurs 16 et 18 de la figure 3. L'ensemble 113 est placé dans l'appareil 84. Après traitement, l'ensemble 113 présente l'aspect représenté en figure 10. In Figure 9, semiconductor elements 110 and 112 are placed in the desired position on the conductive layer 102 of the medium 100 to form an assembly 113. The elements semiconductor 110 and 112 correspond to the semiconductor elements ¬ conductors 66 and 68 of Figure 6 and the semiconductor elements ¬ conductors 16 and 18 of Figure 3. the assembly 113 is placed in the apparatus 84. After treatment, the set 113 has the appearance shown in Figure 10 .
En figure 10, les tronçons 104, 106 et 108 de la couche conductrice 102 ont disparu ou restent présents de manière résiduelle et ne sont pas représentés . Lors de la formation de l'eutectique liquide, les matériaux de la couche 102 ont pénétré dans les pores du support 100 et forment des caissons conducteurs 114, 116 et 118. Le caisson 114 est dû au tronçon 104 de la couche 102. De même, les caissons 116 et 118 sont dus respectivement aux tronçons 106 et 108 de la couche 102. Le rôle des caissons 114, 116 et 108 est le même que celui des caissons 3, 5 et 7 des figures 1 à 3. Les caissons 114, 116 et 118 sont a priori plus allongés que les caissons 2, 5 et 7, sauf si la couche conductrice 9 de la figure 2 est suffisamment épaisse. Si les matériaux de la couche conductrice 102 ont été choisis de façon à former un eutectique avec la céramique du support 100, l'interface entre le support 100 et les éléments à semi-conducteurs 110 et 112 présente une structure particulière, comme cela est expliqué en relation avec la figure 11. In Figure 10, the sections 104, 106 and 108 of the conductive layer 102 have disappeared or remain residual and are not shown. During the formation of the liquid eutectic, the materials of the layer 102 have penetrated into the pores of the support 100 and form conducting boxes 114, 116 and 118. The box 114 is due to the section 104 of the layer 102. Similarly, the boxes 116 and 118 are due respectively to the sections 106 and 108 of the layer 102. The role of the boxes 114, 116 and 108 is the same as that of the boxes 3, 5 and 7 of Figures 1 to 3. Boxes 114, 116 and 118 are a priori more elongated than boxes 2, 5 and 7, unless the conductive layer 9 of Figure 2 is sufficiently thick. If the materials of the conductive layer 102 have been chosen to form a eutectic with the ceramic of the support 100, the interface between the support 100 and the semiconductor elements 110 and 112 has a particular structure, as explained in connection with Figure 11.
La figure 11 représente une vue partielle et agrandie de l'interface entre le support 100 et l'élément à semi¬ conducteurs 110 après collage. Figure 11 shows a partial and enlarged view of the interface between the substrate 100 and the semiconductor element ¬ leads 110 after bonding.
En figure 11, le support 100 est séparé de l'élément à semi-conducteurs 110 par une interface 120. Le support 100 comporte des canaux de porosité 122. Les canaux de porosité 122 sont remplis d'aluminium sur une profondeur e, formant une couche conductrice 124. Un alliage de silicium et d'aluminium se forme sur les parois des canaux de porosité et de part et d'autre de l'interface 120 pour former une couche de forme irrégulière 126, limitée par des tirets en figure 11. La profondeur e de la couche 124 est suffisante pour assurer la conduction électrique souhaitée. Par exemple, l'épaisseur e est comprise entre 10 et 50 ym.  In FIG. 11, the support 100 is separated from the semiconductor element 110 by an interface 120. The support 100 comprises porosity channels 122. The porosity channels 122 are filled with aluminum to a depth e, forming a conductive layer 124. A silicon-aluminum alloy is formed on the walls of the porosity channels and on either side of the interface 120 to form an irregularly shaped layer 126, bounded by dashes in FIG. 11. The depth e of the layer 124 is sufficient to ensure the desired electrical conduction. For example, the thickness e is between 10 and 50 μm.
On notera ici que le cas où il n' y a qu'un seul élément à semi-conducteurs sur le support fait aussi partie de la présente invention. Dans ce cas, l'élément à semi-conducteurs se présente sous la forme d'une plaquette de forme sensiblement égale à celle du support. Comme précédemment, le support peut être en silicium fritté, d'autres éléments pouvant être joints au silicium. L'élément à semi-conducteurs peut par exemple être une plaquette de silicium monocristallin, de silicium poly-cristallin, ou de silicium amorphe ou tout autre matériau semi-conducteur . Une couche conductrice assurant le collage et la formation d'un caisson conducteur peut être placée entre support et élément à semi-conducteurs et l'ensemble peut être placé dans un appareil comme celui de la figure 7 pour collage. On notera que, dans le cas du silicium amorphe, le silicium peut être déposé sur un support déjà pourvu d'un caisson conducteur. On notera aussi que le caisson conducteur, qui peut s'étendre sensiblement sur tout le support, peut déborder de l'élément à semi-conducteurs pour permettre l'établissement d'un contact électrique. It should be noted here that the case where there is only one semiconductor element on the support is also part of the present invention. In this case, the semiconductor element is in the form of a wafer of a shape substantially equal to that of the support. As before, the support may be of sintered silicon, other elements may be joined to silicon. The semiconductor element may for example be a wafer of monocrystalline silicon, polycrystalline silicon, or amorphous silicon or any other semiconductor material. A conductive layer ensuring the bonding and the formation of a Conductive box can be placed between support and semiconductor element and the assembly can be placed in a device like that of Figure 7 for gluing. Note that, in the case of amorphous silicon, the silicon can be deposited on a support already provided with a conductive box. Note also that the conductive box, which can extend substantially over the entire support, may extend beyond the semiconductor element to allow the establishment of an electrical contact.
On va maintenant décrire un mode de réalisation d'une cellule photovoltaïque selon la présente invention en relation avec les figures 12 et 13.  An embodiment of a photovoltaic cell according to the present invention will now be described in relation with FIGS. 12 and 13.
En figure 12, un support 150 est, comme les supports 1 et 100, en céramique isolante ou semi-isolante. Par exemple, le support 150 est en silicium fritté. Le support 150 comporte des caissons conducteurs 152, 154 et 156. Une zone de contact 158 se trouve sur le caisson 152 et une zone de contact 159 se trouve sur le caisson 156. Les zones de contact 158 et 159 permettent la connexion de la cellule avec des éléments extérieurs.  In FIG. 12, a support 150 is, like the supports 1 and 100, made of insulating or semi-insulating ceramic. For example, the support 150 is made of sintered silicon. The support 150 comprises conducting chambers 152, 154 and 156. A contact zone 158 is on the caisson 152 and a contact zone 159 is on the caisson 156. The contact zones 158 and 159 allow the connection of the cell with external elements.
Sur le support 150, est placée une couche conductrice de collage 160 formée de deux tronçons 162 et 164. Sur la couche de collage 160, est placé un élément à semi-conducteurs 166. L'élément à semi-conducteurs 166 s'étend pratiquement sur tout le support 150, à l'exception des zones de contact 158 et 159.  On the support 150 is placed a conductive bonding layer 160 formed of two sections 162 and 164. On the bonding layer 160, is placed a semiconductor element 166. The semiconductor element 166 extends substantially on all the support 150, with the exception of the contact zones 158 and 159.
L'élément à semi-conducteurs 166 est une cellule photovoltaïque. L'élément à semi-conducteurs 166 comporte notamment une couche surdopée de face arrière (BSF) 170, une couche de passivation 168, un absorbeur 172, un émetteur 174.  The semiconductor element 166 is a photovoltaic cell. The semiconductor element 166 comprises in particular an overdoped rear-face layer (BSF) 170, a passivation layer 168, an absorber 172, a transmitter 174.
La couche de passivation 168 est constituée par exemple d'un oxyde ou d'un nitrure, et sert à éviter des recombinaisons de surface. La couche de passivation 168, isolante en général, est percée d'une multitude de petits trous 176 remplis d'un matériau conducteur, par exemple de l'aluminium. Les trous 176 traversent totalement la couche de passivation 168. Les trous 176 sont par exemple réalisés par laser et peuvent faire 0,1 mm de diamètre ; leur surface totale est faible par rapport à la surface totale de la couche de passivation. De préférence, mais non obligatoirement, les trous 176 ne sont pratiqués que là où la couche de passivation 168 est en contact avec la couche conductrice 160. La couche BSF 170 peut avoir une épaisseur de 1,5 ym. The passivation layer 168 consists for example of an oxide or a nitride, and serves to avoid surface recombinations. The passivation layer 168, generally insulating, is pierced with a multitude of small holes 176 filled with a conductive material, for example aluminum. The holes 176 completely pass through the passivation layer 168. The holes 176 are for example made by laser and can be 0.1 mm in diameter; their total area is small compared to the surface total of the passivation layer. Preferably, but not necessarily, the holes 176 are made only where the passivation layer 168 is in contact with the conductive layer 160. The BSF layer 170 may have a thickness of 1.5 μm.
L' absorbeur 172 est de préférence une couche de silicium monocristallin moyennement dopé. Son épaisseur est par exemple comprise entre 10 et 200 um. Sur l' absorbeur 172 se trouve l'émetteur 174. L'émetteur 174 est peu épais. L'interface émetteur 174 / absorbeur 172 réalise une jonction pn produisant des porteurs en présence d'un éclairement adéquat. L' absorbeur peut être dopé de type P et l'émetteur dopé de type N ou vice versa.  The absorber 172 is preferably a moderately doped monocrystalline silicon layer. Its thickness is, for example, between 10 and 200 μm. On the absorber 172 is the transmitter 174. The transmitter 174 is thin. The emitter interface 174 / absorber 172 produces a pn junction producing carriers in the presence of adequate illumination. The absorber can be doped with P type and the doped transmitter type N or vice versa.
En figure 12, l'élément à semi-conducteurs 166 comporte aussi des éléments de peigne collecteur 177 et 178, ainsi qu'une couche antireflet 179. Les éléments de peigne collecteur 177 et In FIG. 12, the semiconductor element 166 also comprises collector comb elements 177 and 178, as well as an antireflection layer 179. The collector comb elements 177 and
178 se trouvent sur l'émetteur 174. Les éléments de peigne 177 sont reliés entre eux ; ils sont situés sur la partie de l'émetteur 174 qui se trouve au-dessus du tronçon 162 de la couche conductrice 160. Les éléments de peigne 178 sont reliés entre eux ; ils sont situés sur la partie de l'émetteur 174 qui se trouve au-dessus du tronçon 164 de la couche conductrice 160. La couche antireflet178 are on the transmitter 174. The comb members 177 are interconnected; they are located on the part of the transmitter 174 which is above the section 162 of the conductive layer 160. The comb elements 178 are interconnected; they are located on the part of the transmitter 174 which is above the section 164 of the conductive layer 160. The anti-reflective layer
179 se trouve sur l'émetteur 174. Les éléments de peigne 177 et 178, ainsi que la couche antireflet 179, peuvent aussi être réalisés à un stade ultérieur de la formation de la cellule photovoltaïque . 179 is located on the transmitter 174. The comb elements 177 and 178, as well as the anti-reflective layer 179, can also be made at a later stage of the formation of the photovoltaic cell.
Le support 150 et l'élément à semi-conducteurs 166 sont ensuite fixés par un procédé selon la présente invention, par exemple à l'aide de l'appareil 84 de la figure 7.  The support 150 and the semiconductor element 166 are then fixed by a method according to the present invention, for example using the apparatus 84 of FIG. 7.
Après fixation, deux rayures laser 180 et 182 coupent l'élément à semi-conducteurs 166 de façon à individualiser deux sous-cellules photovoltaïques 184 et 186. La partie 188 de l'élément à semi-conducteurs 166 située entre les deux sous- cellules photovoltaïques 184 et 186 est alors facilement enlevée car elle n'est pas fixée au support 150. En effet, la couche conductrice 160 est discontinue et n'est pas présente sous la partie 188 de l'élément à semi-conducteur 166. After fixation, two laser stripes 180 and 182 intersect the semiconductor element 166 so as to individualize two photovoltaic sub-cells 184 and 186. The portion 188 of the semiconductor element 166 located between the two sub-cells photovoltaic 184 and 186 is then easily removed because it is not fixed to the support 150. Indeed, the layer conductive 160 is discontinuous and is not present under the portion 188 of the semiconductor element 166.
La figure 13 représente la cellule photovoltaïque terminée .  Figure 13 shows the finished photovoltaic cell.
Après enlèvement de la partie 188 de l'élément à semi¬ conducteurs 166, des lames isolantes 190, 191, 193 et 194 sont placées sur les parois latérales des sous-cellules photovoltaïques 184 et 186 de façon à éviter un éventuel court-circuit électrique. Les lames isolantes 190 et 193 sont optionnelles. After removal of the portion 188 of the semiconductor element ¬ conductors 166, the insulating plates 190, 191, 193 and 194 are placed on the sidewalls of the photovoltaic subcells 184 and 186 so as to avoid possible electrical shorting . Insulating boards 190 and 193 are optional.
Ensuite, des liaisons électriques 196 et 198 sont réalisées. La liaison 196 relie le peigne 177 au caisson 154 et la liaison 198 relie le peigne 178 au caisson 156.  Then, electrical connections 196 and 198 are made. The link 196 connects the comb 177 to the caisson 154 and the link 198 connects the comb 178 to the caisson 156.
La cellule photovoltaïque représentée en figure 13 comprend ainsi deux sous-cellules photovoltaïques connectées en série. Les zones de contact 158 et 159 constituent les bornes de la cellule photovoltaïque. En effet, la zone de contact 158 est connectée à l'absorbeur de la sous-cellule photovoltaïque 184 par l'intermédiaire du caisson conducteur 152, du tronçon conducteur 162 ou de ce qu'il en reste après fixation et des trous conducteurs 176 traversant la couche de passivation de la sous-cellule 184. Le peigne 177 de la sous-cellule 184, connecté à l'émetteur de la sous-cellule 184, est relié au caisson conducteur 154, lui-même relié à l'absorbeur de la sous-cellule 188 par l'intermédiaire du tronçon conducteur 164 ou de ce qu'il en reste après fixation et des trous conducteurs 176 traversant la couche de passivation de la sous-cellule 188. Le peigne 178 de la sous-cellule 186, connecté à l'émetteur de la sous-cellule 186, est relié au caisson conducteur 156, connecté à la zone de contact 159.  The photovoltaic cell shown in FIG. 13 thus comprises two photovoltaic sub-cells connected in series. The contact areas 158 and 159 constitute the terminals of the photovoltaic cell. Indeed, the contact zone 158 is connected to the absorber of the photovoltaic sub-cell 184 via the conductive box 152, the conductive section 162 or what remains after fixing and through holes 176 the passivation layer of the sub-cell 184. The comb 177 of the sub-cell 184, connected to the emitter of the sub-cell 184, is connected to the conducting box 154, itself connected to the absorber of the sub-cell 188 via the conductive section 164 or what remains after fixation and conducting holes 176 passing through the passivation layer of the sub-cell 188. The comb 178 of the sub-cell 186, connected to the transmitter of the sub-cell 186, is connected to the conductive box 156, connected to the contact zone 159.
Bien entendu, une cellule photovoltaïque selon la présente invention peut comporter plus de deux sous-cellules photovoltaïques. Par exemple, une cellule photovoltaïque d'environ 20 cm par 20 cm peut comporter cinq sous-cellules photovoltaïques d'environ 4 cm par 20 cm connectées en série. La connexion en série des sous-cellules, bien que non nécessaire, présente l'avantage, à puissance égale, de diminuer l'intensité circulant au sein de la cellule ou entre les cellules au cas où plusieurs cellules selon la présente invention sont connectées au sein d'un module. Il en résulte que les peignes et leurs liaisons peuvent être plus fins, ce qui se traduit par un gain de place et une meilleure exposition aux radiations lumineuses, ainsi que par des pertes résistives très réduites dans les couches et les rubans conducteurs, d'où un accroissement sensible du rendement de la cellule ou du module. Of course, a photovoltaic cell according to the present invention may comprise more than two photovoltaic sub-cells. For example, a photovoltaic cell of about 20 cm by 20 cm can have five photovoltaic sub-cells of about 4 cm by 20 cm connected in series. The serial connection of the sub-cells, although not necessary, has the advantage, at equal power, of reducing the intensity circulating within the cell or between the cells in case several cells according to the present invention are connected within a module. As a result, the combs and their connections can be thinner, which results in space saving and better exposure to light radiation, as well as very low resistive losses in conductive layers and ribbons, hence a significant increase in the efficiency of the cell or the module.
Bien entendu, une cellule photovoltaïque selon la présente invention peut être réalisée d'autres manières que la cellule décrite en relation avec les figures 12 et 13. Par exemple, les connexions des sous-cellules photovoltaïques d'une cellule selon la présente invention peuvent être enterrées, comme cela va être décrit ci-dessous en relation avec les figures 14 à 16.  Of course, a photovoltaic cell according to the present invention can be made in other ways than the cell described in connection with FIGS. 12 and 13. For example, the connections of the photovoltaic sub-cells of a cell according to the present invention can be buried, as will be described below in connection with Figures 14 to 16.
En figure 14, un support 200 en céramique est représenté en vue de dessus. Le support 200 est destiné à porter deux sous- cellules photovoltaïques et comporte trois caissons interdigités 202, 204 et 206. Les caissons 202, 204 et 206 ont été représentés avec des graphismes différents pour faciliter la compréhension.  In Figure 14, a ceramic support 200 is shown in plan view. The support 200 is intended to carry two photovoltaic sub-cells and comprises three interdigitated boxes 202, 204 and 206. The boxes 202, 204 and 206 have been represented with different graphics to facilitate understanding.
En figure 15, le support 200 est représenté en coupe selon l'axe AA de la figure 14. Les caissons du support 200 présentent ainsi des tronçons 202-i, 204-j et 206-k. Le caisson 202 présente des tronçons 202-1, 202-2 et 202-3, le caisson 204 des tronçons 204-1 à 204-5 et le caisson 206 des tronçons 206-1, 206-2 et 206-3.  In FIG. 15, the support 200 is shown in section along the axis AA of FIG. 14. The caissons of the support 200 thus have sections 202-i, 204-j and 206-k. The casing 202 has sections 202-1, 202-2 and 202-3, the casing 204 of the sections 204-1 to 204-5 and the casing 206 of the sections 206-1, 206-2 and 206-3.
Sur le support 200, est fixée une plaquette 208 par un procédé de fixation selon la présente invention. La plaquette 208 est en silicium monocristallin ou multicristallin et est destinée à former deux sous-cellules photovoltaïques. La plaquette 208 comprend un absorbeur de photons 210, une couche de passivation 211, une première série d'éléments de collecteur 212-1 à 212-3, une première série d'éléments d'émetteur 214-1 à 214-5, une deuxième série d'éléments d'émetteur 216-1 à 216-3 et une deuxième série d'éléments de collecteur 218-1 à 218-3. Si l'absorbeur 210 est dopé de type P, les éléments d'émetteur 214-i et 216-i sont dopés de type N ou N+. Les éléments de collecteur 212-i et 218-i, assurant un rôle de contact ohmique, sont dopés par exemple de type P+. La couche de passivation 211 est absente sous les éléments de collecteur 212-i, 218-i et les éléments d'émetteur 214-i, 216-i et remplacée par une matière conductrice, représentée en noir en figure 15. Pour ce faire, la couche de passivation 211 est par exemple d'abord déposée sur toute la surface inférieure de l'absorbeur 212 comportant les éléments de collecteur et les éléments d'émetteur. Ensuite, la couche de passivation 211 est percée à l'endroit des éléments de collecteur et des éléments d'émetteur et est remplie d'une substance conductrice, comme l'aluminium. On the support 200, a plate 208 is fixed by a fixing method according to the present invention. The wafer 208 is of monocrystalline or multicrystalline silicon and is intended to form two photovoltaic sub-cells. The wafer 208 comprises a photon absorber 210, a passivation layer 211, a first set of collector elements 212-1 to 212-3, a first set of emitter elements 214-1 to 214-5, a second set of transmitter elements 216-1 to 216-3 and a second set of collector elements 218-1 to 218-3. If the absorber 210 is P-type doped, the emitter elements 214-i and 216-i are N- or N-type doped. The collector elements 212-i and 218-i, ensuring a role of ohmic contact, are doped for example of the P + type. The passivation layer 211 is absent under the collector elements 212-i, 218-i and the emitter elements 214-i, 216-i and replaced by a conductive material, shown in black in FIG. 15. To do this, the passivation layer 211 is for example first deposited on the entire lower surface of the absorber 212 comprising the collector elements and the transmitter elements. Then, the passivation layer 211 is pierced at the collector elements and emitter elements and is filled with a conductive substance, such as aluminum.
Pour des questions de clarté, la couche de la substance conductrice assurant la fixation de la plaquette 208 sur le support 200 n'a pas été représentée en figure 15. Il va de soi qu'elle peut être présente sous chaque élément de collecteur et chaque élément d'émetteur. La couche de substance conductrice peut aussi être présente sous la couche de passivation, si l'on prend garde à ce qu'elle ne provoque pas de court-circuit entre les éléments conducteurs (caissons, éléments de collecteur et éléments d' émetteur) .  For reasons of clarity, the layer of the conductive substance ensuring the attachment of the wafer 208 to the support 200 has not been shown in FIG. 15. It goes without saying that it may be present under each collector element and each transmitter element. The layer of conductive substance may also be present under the passivation layer, if care is taken that it does not cause a short circuit between the conductive elements (caissons, collector elements and transmitter elements).
Les éléments de collecteur sont larges par exemple de 1 mm. Les éléments d'émetteur sont plus larges, par exemple 5 mm. Les éléments de collecteur 212-1, 212-2 et 212-3 se trouvent respectivement sur les caissons 202-1, 202-2 et 202-3, et sont en contact électrique avec eux. De même, les éléments d'émetteur 214- 1, 214-2 et 214-3 se trouvent respectivement sur les caissons 204- 1, 204-2 et 204-3 et sont en contact électrique avec eux. Les éléments d'émetteur 216-1, 216-2 et 216-3 se trouvent respectivement sur les caissons 206-1, 206-2 et 206-3 et sont en contact électrique avec eux. L'élément de collecteur 218-1 se trouve sur le caisson 204-3 et est relié électriquement à l'élément d'émetteur 214-3 par l'intermédiaire du caisson 204-3. Les éléments de collecteur 218-2 et 218-3 se trouvent respectivement sur les caissons 204-4 et 204-5 et sont en contact électrique avec eux. The collector elements are wide, for example 1 mm. The transmitter elements are wider, for example 5 mm. The collector elements 212-1, 212-2 and 212-3 are respectively on the caissons 202-1, 202-2 and 202-3, and are in electrical contact with them. Similarly, the transmitter elements 214-1, 214-2 and 214-3 are respectively on the caissons 204-1, 204-2 and 204-3 and are in electrical contact with them. The transmitter elements 216-1, 216-2 and 216-3 are respectively on the casings 206-1, 206-2 and 206-3 and are in electrical contact with them. The collector element 218-1 is located on the caisson 204-3 and is electrically connected to the emitter element 214-3 via the caisson 204-3. Collector elements 218-2 and 218-3 are located respectively on the caissons 204-4 and 204-5 and are in electrical contact with them.
Des zones de contact 220 et 222 se trouvent respectivement en contact avec les tronçons de caisson 202-1 et 206-3. Les zones de contact 220 et 222 constituent les bornes de sortie du module photovoltaïque . L' absorbeur 208 comporte en face supérieure une couche antireflet, non représentée en figure 15 pour des raisons de clarté.  Contact zones 220 and 222 are respectively in contact with the box sections 202-1 and 206-3. The contact areas 220 and 222 constitute the output terminals of the photovoltaic module. The absorber 208 comprises on the upper face an antireflection layer, not shown in Figure 15 for the sake of clarity.
En figure 15, une rayure laser L coupe l' absorbeur de façon à isoler deux sous-cellules photovoltaïques Cl et C2. La rayure laser L est optionnelle, car a priori les porteurs de charge restent confinés dans les deux régions Cl et C2 de 1' absorbeur sans créer de court-circuit à ce niveau.  In FIG. 15, a laser stripe L intersects the absorber so as to isolate two photovoltaic subcells C1 and C2. The laser streak L is optional, because a priori the charge carriers remain confined in the two regions C1 and C2 of the absorber without creating a short circuit at this level.
En figure 16, est représentée une vue de dessus du support 200, comportant les éléments de collecteur 212-i, 218-i, les éléments d'émetteur 214-i, 216-i et leurs connexions. Les éléments de collecteur 212-i, 218-i et les éléments d'émetteur 214-i, 216-i recouvrent des parties des caissons 202, 204 et 206. Les parties non recouvertes des caissons portent les mêmes signes distinctifs qu'en figure 14.  FIG. 16 shows a view from above of the support 200, comprising the collector elements 212-i, 218-i, the emitter elements 214-i, 216-i and their connections. The collector elements 212-i, 218-i and the emitter elements 214-i, 216-i cover parts of the caissons 202, 204 and 206. The uncovered parts of the caissons bear the same distinctive signs as in FIG. 14.
En figure 16, les éléments de collecteur 212-1, 212-2 et 212-3 sont reliés par un élément conducteur 230. L'élément conducteur 230 peut par exemple être de même nature et réalisé en même temps que les éléments de collecteur 210-i ; l'élément conducteur 230 peut aussi résulter d'une rainure pratiquée dans la couche de passivation 211 puis remplie d'un matériau conducteur. Les éléments d'émetteur 214-1, 214-2 et 214-3 sont reliés par un élément conducteur 232. L'élément conducteur 232 peut par exemple être de même nature et réalisé en même temps que les éléments d'émetteur 214-i ; l'élément conducteur 232 peut aussi être constitué de pistes métalliques, par exemple rapportées, ou par tout moyen, comme par photolithographie, sérigraphie, impression ou dépôt, ou résulter d'une rainure de la couche de passivation 211 remplie d'une substance conductrice. Les éléments de collecteur 218-1, 218-2 et 218-3 sont reliés par un élément conducteur 234, qui peut être de même nature que l'élément conducteur 230. Les éléments d'émetteur 216-1, 216-2 et 216-3 sont reliés par un élément conducteur 236, qui peut être de même nature que l'élément conducteur 232. On notera que les éléments conducteurs 230, 232, 234 et 236 sont optionnels, car les caissons 202, 204 et 206 peuvent se charger de connecter électriquement les éléments de collecteur ou d'émetteur qui sont disposés sur eux. Les éléments conducteurs 230, 232, 234 et 236 peuvent néanmoins être préférés pour assurer une meilleure conduction. In FIG. 16, the collector elements 212-1, 212-2 and 212-3 are connected by a conductive element 230. The conductive element 230 may, for example, be of the same type and made at the same time as the collector elements 210. -i; the conductive member 230 may also result from a groove formed in the passivation layer 211 and filled with a conductive material. The emitter elements 214-1, 214-2 and 214-3 are connected by a conductive element 232. The conductive element 232 may for example be of the same type and made at the same time as the emitter elements 214-i. ; the conductive element 232 may also consist of metal tracks, for example reported, or by any means, such as by photolithography, screen printing, printing or deposition, or result from a groove of the passivation layer 211 filled with a conductive substance . The collector elements 218-1, 218-2 and 218-3 are connected by a conductive element 234, which may be of the same nature as the conductive element 230. The transmitter elements 216-1, 216-2 and 216-3 are connected by a conductive element 236, which may be of the same nature as the Conductive element 232. Note that the conductive elements 230, 232, 234 and 236 are optional because the boxes 202, 204 and 206 can be charged to electrically connect the collector or transmitter elements that are arranged on them. The conductive elements 230, 232, 234 and 236 may nevertheless be preferred to ensure better conduction.
En figure 16, la rayure laser L est représentée par un trait gras qui s'arrête au niveau du caisson 204 et isole comme cela a été dit les sous-cellules photovoltaïques Cl et C2.  In FIG. 16, the laser stripe L is represented by a bold line which stops at the level of the box 204 and isolates, as has been said, the photovoltaic subcells C1 and C2.
On notera que les sous-cellules photovoltaïques Cl et C2 sont connectées en série et forment une cellule photovoltaïque ayant pour bornes les zones de contact 220 et 222.  It will be noted that the photovoltaic subcells C1 and C2 are connected in series and form a photovoltaic cell having the contact areas 220 and 222 as their terminals.
En effet, la zone de contact 220 est en contact avec les éléments de collecteur 212-i de la sous-cellule Cl par l'intermédiaire du caisson 202. La jonction PN de la cellule Cl est réalisée par le contact entre les éléments d'émetteur 214-i et l'absorbeur 210. Les éléments d'émetteur 214-i sont reliés aux éléments de collecteur 218-i de la cellule C2 par l'intermédiaire du caisson 204. La jonction PN de la cellule C2 est réalisée par le contact entre les éléments d'émetteur 216-i et l'absorbeur 210. Les éléments d'émetteur 216-i sont reliés à la zone de contact Indeed, the contact zone 220 is in contact with the collector elements 212-i of the sub-cell C1 via the caisson 202. The PN junction of the cell C1 is formed by the contact between the elements of transmitter 214-i and the absorber 210. The transmitter elements 214-i are connected to the collector elements 218-i of the cell C2 via the caisson 204. The PN junction of the cell C2 is realized by the contact between the transmitter elements 216-i and the absorber 210. The transmitter elements 216-i are connected to the contact zone
222 par l'intermédiaire du caisson 206. 222 through the casing 206.
Bien entendu, une cellule photovoltaïque selon la présente invention peut comporter plus de deux sous-cellules connectées en série. Les sous-cellules de la cellule peuvent aussi être connectées en parallèle ou série-parallèle, etc. Aussi, plusieurs cellules selon la présente invention peuvent être groupées en un module faisant partie de la présente invention.  Of course, a photovoltaic cell according to the present invention may comprise more than two sub-cells connected in series. The sub-cells of the cell can also be connected in parallel or series-parallel, etc. Also, several cells according to the present invention can be grouped into a module forming part of the present invention.
Une cellule ou un module photovoltaïque selon la présente invention peut aussi comporter des éléments à semi- conducteurs autres que des sous-cellules photovoltaïques. Par exemple, une cellule ou un module selon la présente invention peut comporter des organes de protection, de mesure, de régulation ou des circuits intégrés pour l'émission et/ou la réception d'ondes électromagnétiques ou lumineuses, des éléments de contrôle de position, tels que GPS, des éléments de contrôle pour la prévention contre le vol, etc. A photovoltaic cell or module according to the present invention may also include semiconductor elements other than photovoltaic sub-cells. By for example, a cell or a module according to the present invention may comprise protection, measurement, regulation or integrated circuits for transmitting and / or receiving electromagnetic or light waves, position control elements, such as GPS, control elements for theft prevention, etc.
Des modes de réalisation particuliers ont été décrits. Diverses variantes et modifications apparaîtront à l'homme de l'art. En particulier, le support 1 des figures 1 à 5 peut comporter un nombre quelconque d'éléments à semi-conducteurs. Ainsi, le support 1 peut ne comporter qu'un seul élément à semi¬ conducteur. Il peut en comporter aussi plusieurs centaines. Particular embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, the support 1 of FIGS. 1 to 5 may comprise any number of semiconductor elements. Thus, the support 1 may comprise only one element to semi ¬ conductor. It can also include several hundred.
Divers modes de réalisation avec diverses variantes ont été décrits ci-dessus. On notera que l'homme de l'art pourra combiner divers éléments de ces divers modes de réalisation et variantes sans faire preuve d'activité inventive.  Various embodiments with various variants have been described above. It will be appreciated that those skilled in the art may combine various elements of these various embodiments and variants without demonstrating inventive step.

Claims

REVENDICATIONS
1. Structure comprenant un support en céramique (1, 50, 100, 150, 200) comportant un ou plusieurs caissons conducteurs isolés électriquement les uns des autres (2, 5, 7, 60, 62, 64, 114, 116, 118, 152, 154, 156, 202, 204, 206) et au moins un élément à semi-conducteurs (16, 18, 66, 68, 110, 112, 166, 208) lié au support par une substance conductrice (10, 12, 14, 76, 78, 79, 104, 106, 108, 162, 164) , la substance conductrice coopérant avec un ou plusieurs caissons du support pour assurer une liaison électrique . A structure comprising a ceramic support (1, 50, 100, 150, 200) having one or more electrically insulated conductive housings (2, 5, 7, 60, 62, 64, 114, 116, 118, 152, 154, 156, 202, 204, 206) and at least one semiconductor element (16, 18, 66, 68, 110, 112, 166, 208) connected to the support by a conductive substance (10, 12, 14, 76, 78, 79, 104, 106, 108, 162, 164), the conductive substance cooperating with one or more boxes of the support to provide an electrical connection.
2. Structure selon la revendication 1, dans laquelle le support est en silicium fritté et résulte du frittage de poudres de silicium additionnées ou non de poudres d'oxyde de silicium, de nitrure de silicium et/ou de carbure de silicium, et/ou dans laquelle le support est au moins partiellement poreux.  2. Structure according to claim 1, wherein the support is sintered silicon and results from the sintering of silicon powders with or without silicon oxide powders, silicon nitride and / or silicon carbide, and / or wherein the support is at least partially porous.
3. Structure selon la revendication 1 et 2, dans laquelle la substance conductrice est une couche métallique ou d'alliages métalliques, ou une pâte ou une colle additionnée de matériaux conducteurs comme des poudres métalliques, et/ou de composés conducteurs ou pouvant devenir conducteurs par traitement thermique, ou dans laquelle la substance conductrice est constituée d'un alliage eutectique, comme un alliage aluminium/silicium ou/et or/silicium.  3. Structure according to claim 1 and 2, wherein the conductive substance is a metal layer or metal alloys, or a paste or an adhesive supplemented with conductive materials such as metal powders, and / or conductive compounds or can become conductive by heat treatment, or in which the conductive substance is made of a eutectic alloy, such as an aluminum / silicon alloy and / or gold / silicon.
4. Structure selon l'une quelconque des revendications précédentes, dans laquelle les caissons du support comprennent des substances dopantes ou des pâtes contenant des poudres ou des produits métalliques, ces substances ou ces pâtes étant présentes dans certaines zones déterminées du support afin de les rendre conductrices .  4. Structure according to any one of the preceding claims, wherein the boxes of the support comprise doping substances or pastes containing powders or metal products, these substances or pastes being present in certain areas of the support to make them conductive.
5. Structure selon l'une quelconque des revendications précédentes, dans laquelle les éléments à semi-conducteurs comportent des éléments tels que du silicium, des alliages de silicium, et/ou des semi-conducteurs de type III-V ou II-VI associant respectivement des éléments des colonnes III et V ou des éléments des colonnes II et VI du tableau de Mendeleïev, et peuvent comprendre des composants passifs, comme une ou plusieurs capacités, et/ou une ou plusieurs résistances, et/ou un ou plusieurs enroulements présentant un coefficient de self- induction, et/ou des composants actifs, comme une ou plusieurs photodiodes, une ou plusieurs cellules photovoltaïques, un ou plusieurs éléments de mémoire, un ou plusieurs circuits intégrés, un ou plusieurs dispositifs à diode électroluminescente LED, et un ou plusieurs éléments thermoélectriques. 5. Structure according to any one of the preceding claims, wherein the semiconductor elements comprise elements such as silicon, silicon alloys, and / or type III-V or II-VI semiconductors combining respectively of the elements of columns III and V or the elements of columns II and VI of Mendeleyev's table, and may include passive components, such as one or more capacitors, and / or one or more resistors, and / or one or more coils having a self-induction coefficient, and / or active components, such as one or more photodiodes, one or more a plurality of photovoltaic cells, one or more memory elements, one or more integrated circuits, one or more LED light emitting diode devices, and one or more thermoelectric elements.
6. Structure selon l'une quelconque des revendications précédentes, dans laquelle la substance conductrice forme une couche discontinue et relie des caissons du support à des zones conductrices des éléments à semi-conducteurs, les éléments à semi¬ conducteurs étant connectés aux caissons du support via leur face arrière par l'intermédiaire de la substance conductrice et/ou par l'intermédiaire de couches conductrices (42, 196, 198) recouvrant au moins partiellement les bords des éléments à semi-conducteurs . 6. Structure according to any one of the preceding claims, wherein the conductive material forms a discontinuous layer, and connects boxes support to conductive areas of the semiconductor elements, semi ¬ conductor elements being connected to the casing of the support via their back side via the conductive substance and / or via conductive layers (42, 196, 198) at least partially covering the edges of the semiconductor elements.
7. Structure selon l'une quelconque des revendications précédentes, dans laquelle les éléments à semi-conducteurs sont connectés en série ou en parallèle ou en série-parallèle, et/ou dans laquelle le support comporte des plots (40, 158, 159, 220, 222) permettant la connexion à des éléments externes à la structure, les éléments externes à la structure étant par exemple un ou plusieurs composants, un ou plusieurs systèmes complexes et/ou une ou plusieurs autres structures de même type que la structure.  7. Structure according to any one of the preceding claims, in which the semiconductor elements are connected in series or in parallel or in series-parallel, and / or in which the support comprises pads (40, 158, 159, 220, 222) allowing the connection to elements external to the structure, the elements external to the structure being for example one or more components, one or more complex systems and / or one or more other structures of the same type as the structure.
8. Structure selon l'une quelconque des revendications précédentes, dans laquelle au moins un élément à semi-conducteurs est une cellule photovoltaïque (Cl, C2) comportant un absorbeur de type N ou P, un émetteur (174) et des éléments de collecteur (177, 178) sur la face supérieure de la cellule photovoltaïque ou des éléments d'émetteur (214-i, 216-i) et des éléments de collecteur (212-i, 218-i) interdigités et situés sur la face arrière de l'élément à semi-conducteurs proche du support, la jonction étant de type homojonction, composée d'une couche de silicium cristallin dopée d'un certain type associée à une couche de silicium cristallin dopée de type opposé, ou de type hétérojonction, jonction où les couches sont de nature différente, comme une couche de silicium amorphe et une couche de silicium cristallin . 8. Structure according to any one of the preceding claims, wherein at least one semiconductor element is a photovoltaic cell (C1, C2) having an N or P type absorber, a transmitter (174) and collector elements. (177, 178) on the upper face of the photovoltaic cell or emitter elements (214-i, 216-i) and interdigitated collector elements (212-i, 218-i) and located on the back side of the the semiconductor element close to the support, the junction being of the homojunction type, composed of a doped crystalline silicon layer of a certain type associated with a layer doped crystalline silicon of opposite type, or of heterojunction type, junction where the layers are of different nature, such as an amorphous silicon layer and a crystalline silicon layer.
9. Procédé pour réaliser une structure comportant un support (1, 50, 100, 150, 200) en céramique et un ou plusieurs éléments à semi-conducteurs (16, 18, 66, 68, 110, 112, 166, 208) disposés sur le support, comportant les étapes suivantes :  Process for producing a structure comprising a ceramic support (1, 50, 100, 150, 200) and one or more semiconductor elements (16, 18, 66, 68, 110, 112, 166, 208) arranged on the medium, comprising the following steps:
a) réaliser sur le support un ou plusieurs caissons conducteurs (2, 5, 7, 60, 62, 64, 114, 116, 118, 152, 154, 156, a) carrying on the support one or more conductive boxes (2, 5, 7, 60, 62, 64, 114, 116, 118, 152, 154, 156,
202, 204, 206) isolés électriquement les uns des autres ; 202, 204, 206) electrically isolated from each other;
b) disposer, sur une face du support et/ou une face du ou des éléments à semi-conducteurs, une substance conductrice permettant une fixation ; et  b) disposing, on one side of the support and / or one face of the semiconductor element or elements, a conductive substance for fixing; and
c) fixer le ou les éléments à semi-conducteurs sur le support de sorte que la substance conductrice coopère avec un ou plusieurs caissons du support pour assurer une liaison électrique.  c) fixing the semiconductor element or elements on the support so that the conductive substance cooperates with one or more boxes of the support to provide an electrical connection.
10. Procédé selon la revendication 9, dans lequel l'étape c) comporte un traitement thermique tel que la substance conductrice forme un eutectique entre le support et le ou les éléments à semi-conducteurs .  The method of claim 9 wherein step c) comprises a heat treatment such that the conductive substance forms a eutectic between the support and the one or more semiconductor elements.
11. Procédé selon la revendication 9 ou 10, dans lequel une pression est exercée entre le support et au moins un des éléments à semi-conducteurs au cours de l'étape c) .  The method of claim 9 or 10, wherein pressure is exerted between the support and at least one of the semiconductor elements during step c).
12. Procédé selon l'une quelconque des revendications 12. Process according to any one of the claims
9 à 11, dans lequel le support est au moins partiellement poreux et un pompage est réalisé au cours de l'étape c) à partir de la face du support ne recevant pas le ou les éléments à semi¬ conducteurs . 9 to 11, wherein the carrier is at least partially porous and pumping is carried out during step c) from the side of the support not receiving or semi ¬ conductive elements.
13. Procédé selon l'une quelconque des revendications 13. Process according to any one of the claims
9 à 12, dans lequel la substance conductrice est disposée en zones distinctes sur le support et/ou dans lequel la substance conductrice occupe une surface plus grande, plus petite ou égale à la surface de l'élément à semi-conducteurs avec laquelle elle coopère. 9 to 12, wherein the conductive substance is arranged in discrete areas on the support and / or wherein the conductive substance occupies a larger area, smaller or equal to the surface of the semiconductor element with which it co-operates .
14. Appareil (84) pour la mise en œuvre du procédé selon l'une quelconque des revendications 9 à 13, comprenant une enceinte (85) renfermant un bâti (90) , le bâti étant adapté à recevoir un ensemble formé par un support en céramique (1, 50, 100, 150, 200) comportant un ou plusieurs caissons conducteurs isolés électriquement les uns des autres (2, 5, 7, 60, 62, 64, 114, 116, 118, 152, 154, 156, 202, 204, 206) et au moins un élément à semi-conducteurs (16, 18, 66, 68, 110, 112, 166, 208) lié au support par une substance conductrice (10, 12, 14, 76, 78, 79, 104, 106, 108, 162, 164) de façon à former une chambre (92), dans lequel l'appareil comprend en outre : 14. Apparatus (84) for implementing the method according to any one of claims 9 to 13, comprising a housing (85) enclosing a frame (90), the frame being adapted to receive an assembly formed by a support in ceramic (1, 50, 100, 150, 200) having one or more electrically insulated conductive housings (2, 5, 7, 60, 62, 64, 114, 116, 118, 152, 154, 156, 202 204, 206) and at least one semiconductor element (16, 18, 66, 68, 110, 112, 166, 208) connected to the support by a conductive substance (10, 12, 14, 76, 78, 79 , 104, 106, 108, 162, 164) to form a chamber (92), wherein the apparatus further comprises:
a) des moyens pour porter la température de l'enceinte à une valeur déterminée ;  a) means for raising the temperature of the enclosure to a determined value;
b) des moyens (87) permettant d'introduire dans l'enceinte un gaz à une pression déterminée (P) , non réactif avec ledit ensemble ;  b) means (87) for introducing into the chamber a gas at a predetermined pressure (P), non-reactive with said assembly;
c) des moyens (96) permettant de créer une dépression dans la chambre (92) .  c) means (96) for creating a depression in the chamber (92).
PCT/FR2016/051484 2015-06-17 2016-06-17 Electronic structure on ceramic support WO2016203175A1 (en)

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FR1555520 2015-06-17

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1555520A (en) 1967-05-03 1969-01-31
US20080020224A1 (en) * 2004-11-12 2008-01-24 Yasuyuki Yamamoto Process For Producing Metallized Aluminum Nitride Substrate And Substrate Obtained Thereby
WO2010112782A2 (en) * 2009-04-02 2010-10-07 S'tile Electronic structure including an epitaxial layer on sintered silicon
EP2328182A1 (en) 2009-11-27 2011-06-01 S'Tile Photovoltaic module comprising built-in photovoltaic cells
EP2368265A1 (en) 2008-12-22 2011-09-28 S'Tile Semiconductor structure
WO2013018357A1 (en) * 2011-08-01 2013-02-07 日本特殊陶業株式会社 Semiconductor power module, method for manufacturing semiconductor power module, and circuit board

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1555520A (en) 1967-05-03 1969-01-31
US20080020224A1 (en) * 2004-11-12 2008-01-24 Yasuyuki Yamamoto Process For Producing Metallized Aluminum Nitride Substrate And Substrate Obtained Thereby
EP2368265A1 (en) 2008-12-22 2011-09-28 S'Tile Semiconductor structure
WO2010112782A2 (en) * 2009-04-02 2010-10-07 S'tile Electronic structure including an epitaxial layer on sintered silicon
EP2328182A1 (en) 2009-11-27 2011-06-01 S'Tile Photovoltaic module comprising built-in photovoltaic cells
WO2013018357A1 (en) * 2011-08-01 2013-02-07 日本特殊陶業株式会社 Semiconductor power module, method for manufacturing semiconductor power module, and circuit board

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