EP2965350A1 - Monolithic semi-conductor substrate based on silicon, divided into sub-cells - Google Patents
Monolithic semi-conductor substrate based on silicon, divided into sub-cellsInfo
- Publication number
- EP2965350A1 EP2965350A1 EP14713264.1A EP14713264A EP2965350A1 EP 2965350 A1 EP2965350 A1 EP 2965350A1 EP 14713264 A EP14713264 A EP 14713264A EP 2965350 A1 EP2965350 A1 EP 2965350A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- substrate
- wafer
- type
- zones
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- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000000758 substrate Substances 0.000 title claims abstract description 109
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 50
- 239000010703 silicon Substances 0.000 title claims abstract description 50
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 49
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 40
- 239000001301 oxygen Substances 0.000 claims abstract description 40
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 40
- 238000010292 electrical insulation Methods 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 34
- 238000010438 heat treatment Methods 0.000 claims description 25
- 239000002800 charge carrier Substances 0.000 claims description 19
- 238000001994 activation Methods 0.000 claims description 16
- 230000004913 activation Effects 0.000 claims description 16
- 238000006243 chemical reaction Methods 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000002955 isolation Methods 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 9
- 238000011282 treatment Methods 0.000 claims description 6
- 238000007725 thermal activation Methods 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 82
- 238000000137 annealing Methods 0.000 description 12
- 238000001465 metallisation Methods 0.000 description 11
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 10
- 239000001257 hydrogen Substances 0.000 description 10
- 229910052739 hydrogen Inorganic materials 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 230000008901 benefit Effects 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- 239000000969 carrier Substances 0.000 description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000013532 laser treatment Methods 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 230000005355 Hall effect Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000009849 deactivation Effects 0.000 description 2
- 238000004090 dissolution Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000000691 measurement method Methods 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000007711 solidification Methods 0.000 description 2
- 230000008023 solidification Effects 0.000 description 2
- 230000009466 transformation Effects 0.000 description 2
- MARUHZGHZWCEQU-UHFFFAOYSA-N 5-phenyl-2h-tetrazole Chemical compound C1=CC=CC=C1C1=NNN=N1 MARUHZGHZWCEQU-UHFFFAOYSA-N 0.000 description 1
- 229910004613 CdTe Inorganic materials 0.000 description 1
- 238000004566 IR spectroscopy Methods 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000002679 ablation Methods 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 125000000896 monocarboxylic acid group Chemical group 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000002926 oxygen Chemical class 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 230000007847 structural defect Effects 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 238000002604 ultrasonography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/02—Heat treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
- H01L31/03529—Shape of the potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention relates to a new silicon-based monolithic semiconductor substrate, vertically divided into several sub-cells isolated from each other, and to different process variants for its preparation.
- Such a substrate is particularly advantageous in the context of the development of photovoltaic cells and modules.
- PV photovoltaic modules
- PV modules of reasonable size of the order of the m 2 , the size standard for the wafers (156 x 156 mm) makes the open circuit voltages (V oc in English terminology) of the PV modules are limited. a few tens of volts.
- a first option could be to use materials other than crystalline silicon (Si), in particular semiconductors with band gap amplitudes exceeding 1, 1 eV (electronvolt).
- silicon such as an amorphous Si type material on crystalline Si, resulting from the so-called heterojunction technology, or even CdTe type materials (cadmium telluride).
- CdTe type materials cadmium telluride
- Goetzberger [1] proposes to carry out an electrical separation, either by doping or by electron bombardment to create a zone of structural defects of high resistivity.
- these solutions have the major disadvantage of creating recombinant centers for minority carriers.
- nothing in the document [1] makes it possible to judge the effectiveness of the electrical insulation thus produced; it is mentioned that the separation may not be totally effective.
- Pozner et al. [2] have modeled the serialization of cells with vertical p-n junction planes, unlike the configuration of conventional wafers where the junction plane is horizontal.
- the advantage of this approach is to be able to consider a collective type of treatment, monolithic substrate, for the realization of cells.
- many technical questions remain open as to the practical realization of such a structure, the cost of which, moreover, may be very high.
- the present invention aims precisely to propose a new semiconductor device based on monolithic silicon, subdivided into several electrically isolated sub-cells from each other, and to overcome the aforementioned drawbacks, as well as methods for accessing such a device . More specifically, the present invention relates, according to a first of its aspects, to a silicon-based monolithic semiconductor substrate, vertically divided into sub-cells isolated from each other, comprising a p-type or n-type silicon base.
- n + and / or p + overdopic boxes at at least one of its faces, characterized in that at least one zone of the substrate, interposed between two successive caissons and extending over the entire thickness of the substrate, is an electrical insulation zone having a concentration of thermal donors based on interstitial oxygen distinct from that of the base .
- the method according to the invention takes advantage of the activation of thermal donors, unlike conventional microelectronics processes which previously implement a high temperature thermal annealing, precisely to overcome the effects of thermal donors.
- the wafer, the semiconductor substrate and the device are characterized when they are observed in their horizontal position.
- the substrate according to the invention is defined as being vertically divided into sub-cells, in a vertical sectional plane of the horizontally positioned substrate.
- electrical insulation zone is meant an area of the substrate having a high resistivity, in particular greater than or equal to 2 k ⁇ cm and advantageously greater than or equal to 10 k ⁇ cm. Ideally, such a zone may be an intrinsic zone, in which the concentrations of electron-type charge carriers and hole-like charge carriers are similar.
- the present invention provides methods making it possible to easily access such a substrate, by controlling the local concentrations of thermal donors based on interstitial oxygen.
- Thermal donors based on interstitial oxygen are small agglomerates of oxygen, typically formed from the combination of 3 to 20 oxygen atoms, which behave as electron donors in silicon. It is known [3] that, in silicon wafers containing oxygen, thermal anneals at temperatures of 400-500 ° C allow the formation of these thermal donors. When these donors thermal are generated in the p-type silicon, they can then cause a compensation of the material and its change of conductivity.
- thermal donors or more simply under the abbreviation "DT", the thermal donors based on interstitial oxygen.
- a substrate according to the invention can be prepared from a wafer of standard silicon of p-type homogeneous initial electrical conductivity, but also from silicon wafers. high resistivity, in particular greater than 1 k ⁇ .cm, or even so-called intrinsic silicon wafers, in which the concentrations of holes and electrons in the material are similar.
- wafer will be used to designate the starting material, intended to undergo a plurality of steps, as detailed in the remainder of the text, to form the final "substrate” according to the invention in which the n + and p + overdopped boxes and the electrical insulation zones are integrated.
- the term “final substrate” is understood to mean the final material obtained at the end of the various processing steps of the starting wafer, and in which the boxes and the electrical insulation zones are integrated.
- the term “p-type substrate” (or n-type substrate) is understood to mean a substrate comprising a major part (called “base”) doped according to a type p (respectively a type n) and in which at least the electrical insulation zones and the overdoped boxes n + and / or p + are integrated.
- the present invention relates to a semiconductor device comprising a substrate as defined above.
- a semiconductor device according to the invention is advantageously a photovoltaic cell.
- It may be a front-side transmitter cell, a bifacial cell, a rear-sided transmitter cell, a rear-panel contact (RCC) cell, in particular an interdigital back contact (IBC) type structure, or MWT type structure ("Metallization Wrap Through” in English), or a heterojunction cell type a-Si: H on c-Si.
- a front-side transmitter cell a bifacial cell, a rear-sided transmitter cell, a rear-panel contact (RCC) cell, in particular an interdigital back contact (IBC) type structure, or MWT type structure ("Metallization Wrap Through" in English), or a heterojunction cell type a-Si: H on c-Si.
- IBC interdigital back contact
- MWT Metallization Wrap Through
- the devices according to the invention divided into a plurality of sub-cells of controlled sizes, advantageously make it possible to produce PV modules exhibiting a increased open circuit voltage, while maintaining a reasonable standard size of the order of m 2 .
- FIG. 1 shows, schematically, in a vertical sectional plane, the structure of a semiconductor substrate according to the invention, according to a particular embodiment
- FIG. 2 schematically represents, in a vertical sectional plane, the structure of devices according to the invention according to two particular embodiments (FIG. 2a: case of a bifacial cell; FIG. 2b: case of a RCC cell);
- FIG. 3 shows schematically the various steps of a method of preparing a substrate according to the invention, according to a first embodiment
- FIG. 4 is a schematic representation of the various steps of a method for preparing a substrate according to the invention, according to a second embodiment
- FIG. 5 schematically represents the various steps of a method for preparing a substrate according to the invention, according to a third embodiment
- FIG. 6 schematically represents the various steps of a method for preparing a substrate according to the invention, according to a fourth embodiment
- FIG. 7 is a schematic representation of the various steps of the method for preparing a device according to the invention, implemented in example 1;
- FIG. 8 schematically represents the various steps of the method for preparing a device according to the invention, implemented in example 2.
- the silicon-based monolithic semiconductor substrate (10) comprises a p-type or n-type silicon base (1), that is, it comprises a p-type or n-type doped major part.
- the base of the p-doped substrate may more particularly comprise a concentration of majority charge carriers of the hole type between 10 14 and 5.10 16 cm -3 , in particular from 10 14 to 10 16 .
- the concentration of hole-type charge carriers can be deduced by the Hall effect measurement method.
- the base of the doped substrate n may more particularly comprise a concentration of majority electron-content charge carriers of between 10 14 and 2.10 16 cm -3 , in particular 14 14 -16 .
- the content of electron-type charge carriers can for example be determined by measuring the Hall effect (which makes it possible to determine the type of doping).
- a substrate (10) according to the invention may have a thickness (e) ranging from 100 to 500 ⁇ , in particular from 150 to 300 ⁇ .
- L p total length ranging from 10 to 30 cm, in particular from 12.5 to 15.6 cm.
- the base (1) of the substrate according to the invention comprises an interstitial oxygen concentration of between 10 17 and 2.10 18 cm -3 , in particular between 5.10 17 and 1.1010 18 cm- 3 .
- the substrate (10) according to the invention has, at at least one of its faces, overdoped boxes n + and / or p +, not contiguous with respect to each other.
- non-contiguous is meant that the caissons integrated in the substrate at the same face are not adjacent to each other. They are spaced apart by an electrical insulation zone, as shown in a vertical sectional plane in FIG. 1. In other words, the caissons integrated at the same face do not form a continuous doped layer.
- the n + wells may have a doping level in n-type dopants, such as phosphorus, greater than or equal to 1.10 19 cm "3, in particular from 10 19 to 2.10 20 cm- 3.
- n-type dopants such as phosphorus
- the p + wells may have a doping level in p-type dopants, such as boron, greater than or equal to 1.10 19 cm "3, in particular from 10 19 to 2.10 20 cm" 3. It is up to those skilled in the art to adjust the arrangement of the caissons and electrical insulation zones of the substrate of the invention, in particular with regard to the architecture of the semiconductor device, in particular the photovoltaic cell, which it wishes to form from this substrate.
- p-type dopants such as boron
- the substrate may comprise, at each of its faces, an alternation of overdoped boxes n + and p +.
- each n + or p + overdoped box integrated into the substrate at one of its faces, faces a box of opposite conductivity p + or n +, integrated in the substrate at the opposite face.
- all the successive boxes at the same face may be of the same nature.
- the substrate of the invention can present at one of its faces, a succession of overdoped boxes n + and, at the opposite side, a succession of overdoped boxes p +, as shown for example in Figures 3c , 4b, 5c and 6b.
- successive boxes we mean two non-contiguous boxes that follow each other at the same face. In other words, two successive boxes are spaced apart from each other by an electrical insulation zone (3).
- the substrate of the invention may have, at each of its faces, successive boxes of alternating conductivity n + and p +, as is the case for example for the substrate shown in Figure 1.
- electrical insulation zones (3) may be formed at each of the zones of the substrate sandwiched between two successive caissons.
- the substrate of the invention can be divided into alternating sub-cells (2) of type n + / n / p + and p + / n / n + isolated from each other by isolation zones.
- electrical (3) as shown in Figure 1, or of type n + / p / p + and p + / p / n + isolated from each other by electrical insulation areas.
- Such a configuration is for example implemented for the manufacture of a bifacial photovoltaic cell as illustrated in FIG. 2a.
- the width (L c ) of the boxes integrated in the substrate can be adapted to the structure of the desired photovoltaic cell.
- each of the overdoped boxes n + and / or p + may have, in a vertical sectional plane, a width (L c ) of at least 1 mm, in particular ranging from 1 mm to 10 cm, and more especially from 5 mm to 5 cm.
- the substrate of the invention can present, at one of its two faces, an alternation of overdoped boxes n + and p +.
- n + or p + may have, at the opposite side to the boxes, a continuous layer doped n + or p +.
- Such an architecture can be implemented, for example, for the manufacture of a photovoltaic cell with contacts and rear-panel junctions (RCC), for example with interdigital back contacts (IBC).
- the width (L c ) of the boxes n + and p + is generally between 200 and 1500 ⁇ .
- the device (100) according to the invention may comprise electrical insulation zones (3) every 15 to 20 elements of symmetry, so as to obtain an element complete sub-cell width between 5 mm and 5 cm.
- element of symmetry is meant, in the vertical sectional plane, the assembly formed of a p + box, a n + box and the substrate area separating the two successive boxes.
- the average width, in the plane of section, of the symmetry element may for example be about 1500 ⁇ .
- FIG. 2b Such a cell variant is shown schematically in FIG. 2b.
- n + and / or p + boxes of a substrate (10) according to the invention may extend in the substrate over a thickness ranging from 100 nm to 2 ⁇ , preferably around 600 nm.
- the electrical insulation zones (3) interposed between two successive caissons and extending over the entire thickness (e) of the substrate preferably have a resistivity greater than or equal to 2 k ⁇ cm, in particular greater than or equal to 10 k ⁇ .cm.
- the resistivity can be measured by any conventional method, such as, for example, by the so-called 4-point measurement method, or by measuring the effect of eddy currents induced by an alternating magnetic field.
- each of the electrical isolation zones (3) advantageously have, in the vertical section plane, a width (Li) ranging from 50 ⁇ to 5 mm, preferably from 200 ⁇ to 1 mm.
- a zone of electrical insulation too long in the final device is likely to lead to an active loss and therefore a drop in performance at the module that will be formed from these devices.
- a zone of electrical insulation that is too short may be insufficient to ensure good isolation between the sub-cells, which can also lead to a drop in efficiency at the level of the resulting module.
- the electrical insulation zones (3) have a concentration of thermal donors based on interstitial oxygen (DT) distinct from that of the base (1) of the substrate ( 10).
- the DTs can be formed, either at the level of the electrical insulation zones (3), either at the base (1) of the substrate (10).
- a global annealing of a final substrate according to the invention for example at a temperature greater than or equal to 600 ° C., in particular between 600 and 700 ° C., allows dissolution (also called annihilation). ") Of the set of DT and leads to finding a homogeneous conductivity substrate except for the caissons which they retain their overdoping. This feature can be advantageously used to distinguish a device according to the invention, devices that would not be obtained by a method according to the invention.
- FIGS. 3 to 6 represent schematically the various stages of transformation of a starting wafer to obtain a substrate according to the invention, according to the different process variants developed below. .
- the starting silicon wafer implemented to form the final substrate of a device according to the invention, can be of p type or high resistivity.
- high resistivity silicon wafer refers to a silicon wafer having a resistivity greater than or equal to 1 k ⁇ cm, in particular greater than or equal to 2 k ⁇ cm, and advantageously greater than or equal to 10 k ⁇ . .cm.
- the starting silicon wafer can not be n-type.
- the final substrate obtained at the end of the different stages of transformation of the starting wafer it may comprise a p-type or n-type base.
- a substrate (10) according to the invention can be produced from a p-doped silicon wafer, more particularly comprising a concentration of hole-type charge carriers (p 0 ) lying between
- the p-doped silicon starting wafer may have a concentration of hole-type charge carriers ranging from 5 ⁇ 10 14 to 10 16 , in particular from 5 ⁇ 10 14 to 5 ⁇ 10 6 cm 3 .
- the starting wafer has a p-doped silicon interstitial oxygen concentration [Oi] of from 5.10 17 to 1.5x10 18 cm "3.
- the relative variation of the interstitial oxygen concentration in the starting silicon wafer is less than 40%, in particular less than 20% and preferably less than 10%.
- Such a p-doped silicon wafer may be derived from a multicrystalline, monocrystalline or monolike ingot. It may for example be obtained by cutting a silicon ingot formed according to techniques known to those skilled in the art, by directed solidification of a molten bath, in particular by the technique of cooling under gradient (also known as term "freeze gradient” in English) or by liquid or gaseous epitaxy.
- the first variant described below makes it possible to obtain a substrate (10) according to the invention in which the base (1) is of n-type, while the second variant makes it possible to obtain a substrate (10) according to the invention in which the base (1) is of type p.
- the invention relates to a process for preparing a substrate (10) according to the invention and in which the base (1) is of type n, comprising at least the steps of:
- n + and / or p + formed in step (bl) are adjusted with respect to the desired architecture for the substrate, as mentioned above.
- n + and p + boxes are formed at the two faces of the wafer.
- the base (1) formed by a portion of the initial wafer, is then n-type, in particular with a content of electron-type charge carriers ranging from 10 to 14. 5.10 16, in particular from 10 14 to 10 16 cm “3, preferably from 5.10 14 to 5.10 15 cm" 3.
- the invention relates to a process for preparing a substrate (10) according to the invention and in which the base (1) is of the p type, comprising at least the steps consisting of:
- This variant embodiment is particularly advantageous in view of the fact that, insofar as the electrical insulation zones are made by activation of the thermal donors, the doping thus implemented does not introduce recombinant centers for the minority carriers.
- the arrangement, the number and the nature of the n + and / or p + boxes formed in step (b2) are adjusted with respect to the desired architecture for the substrate.
- n + and p + boxes are formed at the two faces of the wafer.
- a substrate (10) according to the invention can be produced from a high-resistivity silicon wafer, more particularly comprising a concentration of hole-type charge carriers, between 10 10 and 10 14 cm -3 , and an interstitial oxygen concentration [Oi] between 10 17 and 2.10 18 cm- 3 .
- the high-resistivity silicon wafer may have a concentration of charge carriers of the hole type ranging from 10 10 to 13 cm -3 .
- the starting wafer has an interstitial oxygen concentration [Oi] of from 5.10 17 to 1.5x10 18 cm "3.
- the relative variation of the interstitial oxygen concentration in the starting silicon wafer is advantageously less than 40%, in particular less than 20% and preferably less than 10%.
- Such a wafer can be obtained, for example, by drawing an ingot undoped intentionally.
- the selection of a high resistivity starting board has the advantage of facilitating the electrical isolation between the sub-cells that will be formed on the final device.
- the invention relates to a process for preparing a substrate (10) according to the invention and in which the base (1) is of type n, comprising at least minus the steps of:
- n + and / or p + boxes formed in step (b3) are adjusted in view of the desired architecture for the substrate.
- n + and p + boxes are formed at the two faces of the wafer.
- the base (1) formed by a portion of the initial wafer, is then of type n, with, in particular, a content of electron-type charge carriers ranging from 14 to 2.10 16 , especially 10 14 to 10 16 cm -3 .
- This variant has the advantage, particularly compared to the first embodiment variant described above, of allowing greater flexibility with respect to the heat treatment performed for the annihilation of the DTs, since it is, in the case of case of this third embodiment, completely dissociate in step (d3) DTs previously activated.
- the invention also relates to a method of producing a substrate (10) according to the invention and in which the base (1) is of type n, comprising at least the steps of:
- n + and / or p + formed in step (b4) are adjusted with respect to the desired architecture for the substrate.
- n + and p + boxes are formed at the two faces of the wafer.
- n + and p + overdopped boxes may be formed according to methods known to those skilled in the art. They are intended to ensure the collection of current and the electrical contacts between sub-cells.
- the n + boxes may be formed by localized doping of the wafer by one or more n-type doping elements, in particular phosphorus.
- the p + boxes may be formed for example by localized doping of the wafer by one or more p-type doping elements, in particular boron.
- the doping may for example be carried out by gas diffusion (POCI 3 , BCI 3 ) after localized opening of a dielectric diffusion barrier (SiO 2 , SiN), or ion implantation or localized plasma immersion of boron or phosphorus.
- gas diffusion POCI 3 , BCI 3
- SiO 2 , SiN dielectric diffusion barrier
- ion implantation or localized plasma immersion of boron or phosphorus.
- activation is meant the formation of these thermal donors based on interstitial oxygen. They are generally formed during an anneal allowing the diffusion of associating oxygen dimers to form a species with more complex stoichiometry that has an electron donor behavior in silicon.
- thermal donors thus formed are stable at room temperature, but annealing at a temperature above 600 ° C. allows their dissociation, which cancels out the effects of the thermal activation previously carried out. This is called “annihilation” or “dissolution” of DTs.
- annihilation or “dissolution” of DTs.
- those skilled in the art are able to adjust the conditions of the heat treatments with respect to the desired conductivity for the treated zones.
- Heat treatments for activation / annihilation of thermal donors can be operated under air or under an inert atmosphere.
- the thermal activation treatment of DTs can be carried out at a temperature greater than or equal to 300 ° C. and strictly less than 600 ° C., in particular ranging from 400 ° to 500 ° C., and more particularly from approximately 450 ° C.
- the duration of the heat treatment may be greater than or equal to 30 minutes, in particular between 1 hour and 20 hours.
- the annihilation heat treatment of the DTs may be carried out at a temperature greater than or equal to 600 ° C., in particular ranging from 600 to 1000 ° C., in particular for at least 10 seconds.
- An overall heat treatment of the entire wafer can be achieved by thermal annealing of the wafer, for example in an oven.
- the localized heat treatment may advantageously be operated by exposing the areas to be treated to a laser beam, preferably a wide-spot laser if it is desired to irradiate large areas, for example with a spot size of about cm.
- the laser can for example operate at a wavelength greater than 500 nm, in particular from 500 nm to 1100 nm, which allows the absorption of heat deep in the material.
- the laser treatment In the context of a heat treatment performed at the areas of the wafer dedicated to form electrical insulation zones (3), the laser treatment must be more localized to reach the width (Li) of the desired electrical insulation zones. , and thus achieve a good compromise between quality insulation and limitation of the size of the area of electrical insulation, inactive from a photovoltaic point of view.
- the heat treatment of the areas of the wafer between two successive boxes, dedicated to form electrical insulation zones can then be operated by exposing the zones to a laser of small spot size, for example from 20 to 100 ⁇ .
- the laser treatment for the formation of the electrical insulation zones can be associated with a partial pre-ablation of the area of the wafer between two successive caissons, in order to further improve the quality of insulation, as shown for example in Figure 7c.2.
- the substrate may be subjected, after the aforementioned steps, to a surface treatment, in particular by chemical etching, to remove any hardened surface regions resulting from the laser treatment.
- the etching can be carried out using a solution formed of a mixture of HF, HN0 3 and CH 3 COOH.
- Hydrogen doping may for example be carried out via a first step of implantation of hydrogen on the surface or sub-surface of the zones to be doped, followed by a step of diffusion of hydrogen over the entire thickness of the wafer.
- substrate hydrogen implantation is understood to mean implantation at depths ranging from a few nanometers to a few microns.
- the implantation of hydrogen can be carried out by conventional techniques, for example by plasma treatment, in particular by plasma-assisted chemical vapor deposition (PECVD) or by microwave-induced remote plasma (MIRHP). It can still be operated by an ion implantation technique, in particular by a SmartCut ® type technique.
- PECVD plasma-assisted chemical vapor deposition
- MIRHP microwave-induced remote plasma
- the plasma treatment is carried out on both sides of the wafer.
- the hydrogen implantation zones can be defined using a mask (for example, a metal grid), leaving only the surfaces of the areas to be doped accessible.
- a mask for example, a metal grid
- the diffusion of hydrogen into the zones to be doped may for example be promoted by exposing said zones to ultrasound, in particular using piezoelectric transducers.
- the diffusion of hydrogen can be effected by thermal annealing of the wafer, in particular in an oven, in particular at a temperature ranging from 400 ° C. to 1000 ° C., and for a duration ranging from 5 seconds to 5 hours. .
- PV photovoltaic cell
- a device (100) comprises, in addition to the substrate (10) as defined above, one or more metallizations, also called “conductive contacts", on the front face and / or back of the cell, and adjusted to allow the serialization of the sub-cells of the device.
- the substrate (10) At the end of the process for manufacturing the substrate (10) according to the invention, it is possible to use a low temperature technology of the heterojunction type (amorphous silicon on crystalline silicon), for the production of the photovoltaic cell.
- the heterojunction type amorphous silicon on crystalline silicon
- a first layer of intrinsic amorphous silicon typically of a thickness of the order of 5 nm
- caissons or overdoped p + and / or n + zones on each of the faces of the substrate
- transparent conductive oxide layers in particular based on ITO, on the surface of said amorphous silicon layers
- metallizations also called “conductive contacts”
- a layer of Si0 2 with a thickness of the order of 10 nm passes the doped surfaces p + (reduction of surface recombinations);
- a step of annealing the metallizations is then carried out in a passage oven at 800 ° C for a few seconds.
- the PV cells obtained according to the invention can then be assembled to produce a photovoltaic module of reasonable size, conventionally of dimension of the order of m 2 , and having an increased voltage compared to modules developed from conventional cells.
- the invention thus relates to a photovoltaic module formed of a set of photovoltaic cells according to the invention.
- the starting wafer is a p-type silicon wafer with a thickness of 200 ⁇ and a size of 156 ⁇ 156 mm, obtained by cutting an ingot produced by solidification directed by the gradient cooling technique.
- n + and p + boxes are formed on the front and rear face of the wafer, as shown in FIG. 7a.
- the p + and n + boxes are formed by localized doping, respectively by boron and phosphorus.
- Both sides of the wafer are then oxidized to form a thin layer of silicon oxide with a thickness of about 10 nm.
- An antireflection layer S13N4 is then deposited on both sides of the wafer.
- metallizations are deposited by screen printing Ag / Al front and rear face.
- a step of annealing the metallizations is carried out in a passage oven at 800 ° C. for a few seconds.
- the wafer obtained is represented in FIG. 7a.
- the wafer undergoes firstly an annealing at the end of this manufacture.
- the annealing time chosen which is a function of the hole content and that of oxygen, is 12 hours. This time allows conversion of the p-type wafer to n-type, with an electron content at ambient of about 10 15 cm -3 as shown in Fig. 7b.
- the realized structure has different elements of cells n + / n / p + and p + / n / n + connected in series but not electrically isolated from each other. This electrical insulation is then achieved by localized deactivation of the thermal donors by laser.
- the laser beam is directed on the face opposite to the metallization pad.
- the parameters of irradiation duration and laser power are adjusted in order to obtain localized zones where only a fraction of the thermal donors has been dissolved, making it possible to obtain a zone depleted of charge carriers, and thus very resistive.
- the laser power used is for example 15 W, the wavelength 1064 nm, and the irradiation time is 5 seconds.
- the width of the formed isolation zones is approximately 500 ⁇ , the aim being to reduce it as much as possible in order to maintain a large active surface area.
- the starting wafer is a high resistivity silicon wafer, with a content of hole carrier, similar to the content type of electron charge carriers, 10 12 cm “3 and an oxygen concentration of 7.1017 cm” 3. Creating p + and n + boxes
- n + and p + boxes are formed on the front and rear face of the wafer, as shown in FIG. 8a.
- the p + and n + boxes are formed by localized doping, respectively by boron and phosphorus.
- Both sides of the wafer are then oxidized to form a thin layer of silicon oxide, about 10 nm thick.
- An antireflection layer S13N4 is then deposited on both sides of the wafer.
- metallizations are deposited by screen printing Ag / Al front and rear face.
- a step of annealing the metallizations is carried out in a passage oven at 800 ° C. for a few seconds.
- the plate obtained is represented in FIG. 8a.
- the wafer first undergoes annealing at 450 ° C in order to activate thermal donors.
- the annealing time chosen which depends on the hole content and that in oxygen, is 6 hours. This time permits conversion of the high resistivity wafer to n-type with an electron content of about 10-15 cm- 3 (FIG. 8b).
- the realized structure has different elements of cells n + / n / p + and p + / n / n + connected in series but not electrically isolated from each other.
- This electrical insulation is then achieved by laser localized deactivation of the thermal donors.
- a 10 second treatment at a temperature of 800 ° C is sufficient to deactivate the DTs and allow the localized formation of highly resistive areas that electrically isolate the different cell elements (Figure 8c).
- the width of the insulation is 1 mm, the goal being to reduce it as much as possible to maintain a large active surface.
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Abstract
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FR1352097A FR3003085B1 (en) | 2013-03-08 | 2013-03-08 | MONOLITHIC SEMICONDUCTOR SUBSTRATE BASED ON SILICON, DIVIDED IN SUB-CELLS |
PCT/IB2014/059498 WO2014136083A1 (en) | 2013-03-08 | 2014-03-06 | Monolithic semi-conductor substrate based on silicon, divided into sub-cells |
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CN108963018A (en) * | 2018-07-23 | 2018-12-07 | 英利能源(中国)有限公司 | The preparation method and solar cell module of solar battery |
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