WO2016200882A1

WO2016200882A1 - Microled display without transfer

Info

Publication number: WO2016200882A1
Application number: PCT/US2016/036359
Authority: WO
Inventors: Timothy James Orsley
Original assignee: Corning Inc
Current assignee: Corning Inc
Priority date: 2015-06-08
Filing date: 2016-06-08
Publication date: 2016-12-15
Anticipated expiration: 2017-12-08
Also published as: KR20180018659A; CN107787527A; JP2018518843A; CN107787527B

Abstract

Described herein are light emitting diode-based displays and fabrication methods of such displays. In particular, the devices described herein incorporate micro-LED (190) direct emissive technologies and methods of making such devices directly on LED wafers. The improved devices incorporate GaN layers (110') on silicon substrates (120) into the device structure, allowing for backside contact through the silicon and individual µLED control while avoiding the use of sapphire or having to transfer the µLED to another substrate.

Description

MICROLED DISPLAY WITHOUT TRANSFER

[0001] This application claims the benefit of priority under 35 U.S.C. § 119 of U.S.

Provisional Application Serial No. 62/172,393 filed on June 8, 2015 the content of which is relied upon and incorporated herein by reference in its entirety.

Field

[0002] Described herein are light emitting diode-based displays and methods of such displays. In particular, the devices described herein incorporate micro- LED direct emissive technologies and methods of making such devices directly on LED wafers.

Technical Background

[0003] Light emitting diodes ("LEDs") are semiconductor light sources that emit light when a voltage of suitable potential is applied across the leads of the diode. Generally speaking, an LED incorporates a chip of semiconducting material doped with impurities to create a p-n junction. As in other diodes, current flows easily from the p-side, or anode, to the n-side, or cathode, but not in the reverse direction. Charge-carriers— electrons and holes— flow into the junction from electrodes with different voltages. When an electron meets a hole, they combine via radiative recombination and release energy in the form of a photon by a process called electroluminescence.

[0004] The wavelength of the light emitted, and thus its color, depends on the band gap energy of the materials forming the p-n junction. In silicon or germanium diodes, the electrons and holes usually recombine by a non-radiative transition, which produces no optical emission, because these are indirect band gap materials. The materials used for the LED have a direct band gap with energies corresponding to near-infrared, visible, or near-ultraviolet light.

[0005] LEDs have many advantages over incandescent light sources, including lower energy consumption, longer lifetime, improved physical robustness, smaller size, and faster switching. Light-emitting diodes are now used in applications diverse lighting applications. However, there continues to be a need to improve LED design and functionality. For example, LEDs powerful enough for room lighting are still relatively expensive, and require more precise current and heat management than compact fluorescent lamp sources of comparable output. To that end, LED technology has continued to expand in a number of different ways. As demand and performance increase with smaller sized LEDs, there will be a continued need for improvements in efficiency, speed of operation, spectral control, and scalability. With reduction in size, fabrication issues become increasingly greater, especially with regard device isolation and global planarization.

[0006] Aspects described herein look to address some of the issues described by providing novel μί,Εϋ device structures and methods for making ultra-high resolution structures that avoid the need to transfer mLEDs from the source wafer.

Summary

[0007] A first aspect comprises a device comprising a silicon substrate comprising at least one via having a conductor material therein; a structured GaN layer comprising at least one independent GaN element and a void space on the silicon substrate; an optional buffer layer between the silicon substrate and the GaN layer; an optional planarizing layer on the silicon substrate or optional buffer layer and filling the void space between the at least one independent GaN element; a transparent conductor on the GaN layer and the optional planarizing layer; at least one wall element forming a well on the transparent conductor; a quantum dot material located in the well; and a transparent substrate on the wall element and well; wherein the GaN layer or optional buffer layer is exposed to the conductor material through the via.

[0008] A second aspect comprises a method of making the device of claim 1, the method comprising a. beginning with a silicon substrate optionally coated with a buffer layer and coated with a GaN layer, removing at least part of the GaN to produce a structured GaN layer comprising at least one independent GaN element and a void space on the silicon substrate; b. removing at least part of the silicon substrate under the at least one independent GaN element to form a via that exposes the GaN or optional buffer layer; c. inserting a conductor material into the via; d. optionally inserting a planarizing layer into the void space on the silicon substrate; e. forming a transparent conductor on the GaN layer and the optional planarizing layer; f. forming at least one wall element on the transparent conductor to produce at least one well; g. placing a quantum dot material in the well; and h. placing or forming a transparent substrate on the wall element and well.

[0009] Additional features and advantages will be set forth in the detailed description which follows, and in part will be readily apparent to those skilled in the art from the description or recognized by practicing the embodiments as described in the written description and claims hereof, as well as in the appended drawings.

[0010] It is to be understood that both the foregoing general description and the following detailed description are merely exemplary, and are intended to provide an overview or framework for understanding.

Brief Description of the Drawings

[0011] The accompanying drawings are included to provide a further

understanding, and are incorporated in and constitute a part of this specification.

[0012] FIGS. 1A-1G pictorially show an embodied process for forming embodied μΙ_,Ε05. Fig. 1A shows, in cross section, a GaN layer 110 on a silicon substrate 120 with an optional buffer layer 115, to produce a GaN-on-Si wafer 100. Regions 110A and HOB are optional p-type and n-type regions of the GaN as discussed herein. Fig. IB pictorially shows a cross section of the GaN-on-Si wafer 100 where the GaN 110 has been preferentially etched to produce isolated sections of the GaN 110'. In the step shown in Fig. 1C, the silicon 120 is etched under the remaining GaN 110' regions to produce via 125 that allow access to the underside of the GaN 110'. As shown in Fig. ID, these via 125 are then metallized with a conducting material 130. In Fig. IE, a planarization layer 140 is added around each of the GaN regions 110' and then a transparent conductor 150 is coated along the entire top of the device. Fig. IF shows the fabrication of wall element 160 on the transparent conductor. Element 165 shows that the wall elements may have a vertical dimension much larger than the other components shown. Finally, Fig. 1G shows the formation of red, green and blue or blue scattering quantum dot wells 180 in the voids formed by wall elements 160, and then an encapsulation layer 170 is formed over the wall elements 160 and QD wells 180 to produce μί,Εϋ display 190.

Detailed Description

[0013] Before the present materials, articles, and/or methods are disclosed and described, it is to be understood that the aspects described below are not limited to specific compounds, synthetic methods, or uses as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting.

[0014] In this specification and in the claims that follow, reference will be made to a number of terms that shall be defined to have the following meanings:

[0015] Throughout this specification, unless the context requires otherwise, the word "comprise," or variations such as "comprises" or "comprising," will be understood to imply the inclusion of a stated integer or step or group of integers or steps but not the exclusion of any other integer or step or group of integers or steps. Where comprise, or variations thereof, appears the terms "consists essentially of or "consists of may be substituted.

[0016] As used in the specification and the appended claims, the singular forms "a," "an" and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a quantum dot" includes mixtures of two or more such quantum dots, and the like.

[0017] "Optional" or "optionally" means that the subsequently described event or circumstance can or cannot occur, and that the description includes instances where the event or circumstance occurs and instances where it does not.

[0018] Ranges may be expressed herein as from "about" one particular value, and/or to "about" another particular value. When such a range is expressed, another aspect includes from the one particular value and/or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent "about," it will be understood that the particular value forms another aspect. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint.

μΙ,,ΕΡ Devices and Displays [0019] Aspects comprise novel μί,Εϋ devices on GaN-on-silicon structures and methods of making such devices. The μί,Εϋ devices embodied herein are unique in that the silicon structure is retained and incorporated into the device and may provide both an insulative function and/or a support function for the μί,Εϋ device while at the same time providing a very high resolution surface of mLEDs on the substrate. In some traditional display applications, the designs described herein would be unacceptable because using such a large amount of LED material to create a single display would not be economically viable. But in the case of near- eye displays such as those that would be attractive in virtual reality application, the tremendous density of LED material provides for the high resolution necessary when display is so close to the eye because of the magnification needed in order for the human eye to resolve.

[0020] In one embodiment, exemplified in Fig. 1G, the μ]-.ΕΌ comprises a silicon substrate 120 comprising vias 125 having conductor materials 130 therein, a structured GaN layer on the silicon substrate, a transparent conductor on the GaN layer, wall elements forming wells on the transparent conductor, quantum dots in the wells, and a transparent substrate on top of the wall elements and wells.

[0021] The silicon substrate 120 comprises a mono- or polycrystalline silicon, such as a silicon wafer and can have any orientation or crystal structure that works with the GaN 110 or optional buffer layer. For example, the silicon substrate 120 may have a (100), (110), or (111) orientation or a combination of orientations (in the case of polycrystalline silicon. In some embodiments, the silicon substrate 120 is doped with small amounts of a dopant. The dopant may comprise any element in any amount that works with the LED device 190, but in particular may comprise boron, phosphorous, arsenic, oxygen, or antimony in amounts from about 10¹³ to about 10¹⁶ atoms/cm³.

[0022] The vias 125 in the silicon can be of any size or shape that allows the device 190 to work properly. Based on the device 190 design, as shown in Fig. 1C, the vias 125 are generally of a size such that the silicon substrate 120 adequately supports the GaN material 110 and do not allow contact of the conductor materials outside of the GaN layer 110, as this minimizes the chance of shorting and optimizes conductor material use. In some embodiments, the vias, are just slightly smaller than the footprint of the GaN microLED and can be optimized for light extraction. However, where the optional planarizing layer is present and it can act as an insulator, the size of the via 125 may exceed the size of the GaN 110 in some regions or dimensions. In order to optimize substrate 120 usage, the via may be, in some embodiments, from about 1 μιη to about 50 μιη along their shortest in-plane dimension (i.e., not thickness).

[0023] The via, once formed, are then filled with a conductor material 130.

The conductor material 130 can be a metal or metal oxide, and especially in the case of a metal, can act as a reflector to enhance light output from the device 190. Metals and metal oxides that can be used for the conductor material 130 can comprise Al, Au, Cu, Ag, Pt, etc. In some embodiments, a mirror layer can be coated on the underside of the GaN before filling the via with another conductor, such as a copper paste. This is due in part to the absorbance of silicon. Silicon itself is very absorbing so much so that those who make LEDs based upon GaN- on-Si transfer the GaN off the original wafer and bond another wafer to the top of the GaN after laying down a mirror.

[0024] In some embodiments, an optional buffer layer 115 is present between the silicon and GaN layers. Because of the lattice differences between GaN 110 and silicon 120, it can be difficult to grow GaN on silicon. The buffer layer 115 comprises a material that bridges the lattice difference between GaN 110 and silicon 120 by minimizing the lattice mismatch. The bridging can be done by using a material with a structure that is crystalline or amorphous, that has a structure that changes or varies structurally or compositionally when transitioning from the silicon-facing side to the GaN-facing side. Possible buffer layers 115 comprise, for example, InGaN, AlGaN, Gd₂03, Ga₂03, A1N and Si3N4. The buffer layer 115, when present, can be etched away at with the formation of the via, or if conducting, may be retained. Fig. 1C, for the sake of clarity, shows the optional buffer layer 115 having been etched away.

[0025] The GaN layer 110 comprises GaN and may further include dopants such as aluminum or indium. In fact, in some embodiments, the GaN layer changes compositionally moving away from the silicon layer or buffer layer. In some embodiments, the GaN layer is of an n-type near or adjacent to the silicon/buffer layer (Region HOB in Fig. 1A) and has a composition that is doped with silicon or oxygen or other material to make it n-type, while at the region near or at the other face, the GaN is p-type and is doped with Mg or other material to make it p-type (Region 110A in Fig. 1A). The GaN layer is etched starting from the face farthest away from the silicon - the exposed face - and then proceeds down toward the silicon face and silicon layer. The GaN layer 110 is generally on the order of from about 1 μιη to about 100 μιη thick and can be etched into any reasonable shape with spacing between the etched GaN elements 110 being sufficient to prevent cross-talk or shorting - in some embodiments, from about 500 nm to about 5 μιη or more.

[0026] The optional planarizing layer 140 acts as an insulator to insulate the side walls of the GaN and in some embodiments, can act as a reflector. The planarizing layer 140 can comprise any insulating material that can be easily coated onto the substrate and not cause issues with the operation of the device. In some embodiments, the planarizing layer 140 is an optionally photopolymerizable organic or inorganic polymer. In embodiments where the planarizing layer 140 also serves as a reflector, it may further comprise organic or inorganic particles, such as nano- or microparticles, that scatter or reflect light.

[0027] The transparent conductor 150 is an optically transparent thin film that is electrically conducting, and may comprise a transparent conductive oxide (e.g., ITO, FTO, doped ZnO), organic or inorganic conductive polymer (e.g., PEDOT, PEDOT:PSS,etc), conductive transfer film, metal grid, carbon nanotubes, nanowires, or graphene, or the like.

[0028] Quantum dot elements 180, as used herein, comprise nanocrystalline semiconductor materials that exhibit quantum mechanical properties. QD materials that can be used in the embodiments described herein generally comprise any known QD materials without limitation. The size, composition, and quantity of QD elements 180 used in each well is within the ability of the skilled artisan, and can be modified for the application. QDs that can be used, include, for example, core-type, core-shell, and alloyed QDs of CdSe, CdS, ZnS, CdS_xSei-_x/ZnS, InP/ZnS, PbS, etc. The QD elements 180 may further comprise polymers or other carriers or support materials that the QDs are in the wells with. Depending on the application, the QD elements may have the same or different emission colors and may be structured or ordered to emit such colors in a particular arrangement. The QD elements 180 shown in Fig. 1G have a repeating pattern of different colors, but could be arranged differently without impacting the embodiments described herein.

[0029] Similar to the optional planarizing layer, wall element 160 act to produce wells for the QD materials as well as acting to insulate the wells from each other, and in some embodiments, can act as a reflector. The wall element 160 can comprise any non-conductive material that can be developed into a well like structure, is coatable onto the transparent conductor, and not cause issues with the operation of the device. In some embodiments, the wall element 160 is an optionally photopolymerizable organic or inorganic polymer. In embodiments where the wall element 160 also serves as a reflector or scatterer, it may further comprise organic or inorganic particles, such as nano- or microparticles, that scatter or reflect light.

[0030] Referring back to Fig. 1G, transparent substrate 170 may comprise a transparent glass, glass ceramic, polymer, or crystalline material that acts to encapsulate the QD elements. The transparent substrate 170 can be a thin, ultrathin, and/or flexible material, such as a flexible glass substrate with a thickness of 300 um or less. In some embodiments, the transparent substrate 170 could be further coated with any number of films, such as anti-reflective, anti-fingerprint, anti-microbial or the like. Alternatively, one or both sides of the transparent substrate 170 could be designed to scatter light via scattering films or by the substrate having a roughened or non-planar surface.

Methods

[0031] Common competing approaches to microLED displays, microLED are transferred from the source wafer to a separate display backplane. Transferring μΙ_,Ε05 from a formation substrate can be a difficult process as well as being quite costly. The downside of not transferring the μ]-.ΕΌ is that one wafer is that the formation substrate can't be reused, whereas a transfer approach allows for potentially multiple displays from a single wafer. However, some applications, e.g., virtual reality head mounted displays, may find the expense of an entire wafer per display to be compelling because of the extremely high resolution requirements for VR. The current μ]-.ΕΌ design and processes allow for high resolution μΙ_,Ε05 to be formed directly on a wafer without a need for transfer or removal of the silicon.

[0032] Previous methods for using forming μΙ_,Ε05 on silicon involve removal of the silicon substrate by etching. The proposed invention selectively etches through a patterned photoresist rather than removing the entire substrate. Selective removal of the substrate provides the desired access to contact the bottom n-GaN layer. Such viability is critical to the proposed invention because the invention relies upon creating through-silicon vias to address each subpixel from behind (with a common transparent electrode in front). Unlike sapphire, which is traditionally used for LED formation, silicon can be easily etched.

[0033] An aspect of the process described herein is shown in Figs. 1A-1G.

Referring to Fig. 1A, an optional buffer layer 115 is grown or formed on the silicon wafer 120. The buffer layer 115 may be formed via known means including molecular beam epitaxy (MBE), chemical vapor deposition (CVD), etc., using known precursors, such as NH3 and Al or alternative components. The GaN layer 110 is then coated onto the buffer-coated silicon substrate 120 via known means including MBE, CVD, hydride vapor phase epitaxy, metalorganic vapor phase epitaxy, metal organic CVD, etc. to a desired thickness. In some embodiments, the GaN layer 110 is doped in such a way that the GaN layer goes from n-type to p-type moving away from the silicon 120 or optional buffer layer 115.

[0034] Now referring to Fig. IB, the GaN 110 and optionally, the optional buffer layer 115, are etched away using a mask and etching techniques known in the art, such wet or dry etching, and etchants such as silicon tetrachloride, bases, acids, peroxides, and laser-assisted etching, etc. to produce a GaN structure 110' comprising individual GaN elements of any desired shape, such as pillars, cubes, cylinders, pyramids, etc. The GaN layer is etched starting from the face farthest away from the silicon - the exposed GaN face - and then proceeds down toward the silicon face and silicon layer.

[0035] Referencing Fig. 1C, the silicon 120 and optionally, the optional buffer layer 115, can be etched away using a mask and etching techniques known in the art, such wet or dry etching, and etchants such nitric acid, hydrofluoric acid, peroxides, bases, ethylene diamine pyrocatechol, amine gallate, TMAH, hydrazine, etc. to form via 125. The silicon 120 is etched starting from the face farthest away from the GaN - the exposed silicon face - and then proceeds down toward the GaN face and GaN structure 110'. The via 125 can be of any desired shape and can mimic the shape of the GaN structures 110' they are under. This step exposes the underside of the GaN structures 110' to allow for the formation of a circuit through the silicon substrate.

[0036] Following the etching of the silicon, a conductor material 130 can be inserted into the via 125 by known processes as shown in Fig. ID, including vapor deposition processes optionally under vacuum, films, pastes, liquid coating, blading, or combinations thereof, etc. for example, a reflective metal layer may be deposited on the GaN layer through the via and then a copper paste used to fill the via and form the contact. As noted above, the conductor material 130 can comprise conducting metals and metal oxides such as Al, Au, Cu, Ag, Pt, etc.

[0037] Fig. IE shows the step where the optional planarizing layer 140 is coated onto the GaN-on-silicon substrate 100. The planarizing layer 140 is designed to fill the voids around the GaN structures 110' without coating the upper surface that is the contact point for the transparent conductor 150. The planarizing layer 140 may be placed on the device through mechanical or chemical means, including vapor deposition, chemical reaction, blading, etc.

[0038] Again looking at Fig. IE, a transparent conductor 150 is then placed on the GaN 110' and optional planarizing layer 140. Depending on the transparent conductor, it may be deposited as a film, liquid, or vapor, and then may be allowed to set or crosslink, or undergo other chemical or physical process to adhere and set to the GaN and/or planarizing layer. The transparent conductor might also be carried upon a transparent film.

[0039] With the formation of the transparent conductor 150, wall elements

160 as shown in Fig. IF can be formed on the transparent conductor from any non-conductive material that can be developed into a well-like structure, is coatable onto the transparent conductor, and will not cause issues with the operation of the device 190. In some embodiments, the wall element 160 is formed via polymerization, lithography, etc.

[0040] Referring to Fig. 1G, one the wall elements 160 have been formed, materials can be placed in the wells and then the wells and wall elements 160 are then encapsulated under a transparent substrate 170. The resulting device 190 is a μί,Εϋ that utilizes and integrates the formation substrate and takes advantage of both micro-scale formation techniques and LED technology as well as the properties of QDs.

41] Although the embodiments herein have been described with reference to particular aspects and features, it is to be understood that these embodiments are merely illustrative of desired principles and applications. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the appended claims.

Claims

What is claimed is:

1. A device comprising:

a silicon substrate comprising at least one via having a conductor material therein;

a structured GaN layer comprising at least one independent GaN element and a void space on the silicon substrate;

a transparent conductor on the GaN layer and the optional planarizing layer; at least one wall element forming a well on the transparent conductor;

a quantum dot material located in the well; and

a transparent substrate on the wall element and well;

wherein the GaN layer or optional buffer layer is exposed to the conductor material through the via.

2. The device of claim 1, wherein the structured GaN layer is adjacent the silicon substrate and compositionally changes as a function of distance from the silicon layer.

3. The device of claim 2, wherein the structured GaN layer is of an n-type on the side nearest the silicon layer and is of a p-type on the side away from the silicon layer.

4. The device of any of claims 1-3, wherein the structured GaN layer is doped with oxygen, silicon, magnesium, aluminum or indium.

5. The device of any of claims 1-4, wherein the structured GaN layer is from about 1 μιη to about 100 μιη in thickness.

6. The device of any of claims 1-5, wherein the device further comprises a planarizing layer on the silicon substrate.

7. The device of claim 6, wherein the planarizing layer comprises a photopolymerizable organic or inorganic polymer optionally comprising nano- or microparticles.

8. The device of any of claims 1-7, wherein the device further comprises a buffer layer.

9. The device of any of claims 1-8, wherein the device further comprises a buffer layer between the silicon substrate and the GaN layer.

10. The device of claim 8 or 9, wherein the buffer layer comprises InGaN, AlGaN, Gd₂0₃, Ga₂0₃, A1N or Si₃N₄.

11. The device of any of claims 1-10, wherein the quantum dot material comprises core-type, core-shell, or alloyed quantum dots of CdSe, CdS, ZnS, CdS_xSei-_x/ZnS, InP/ZnS, or PbS.

12. The device of any of claims 1-11, wherein the wall element comprises a photopolymerizable organic or inorganic polymer optionally comprising nano- or microparticles.

13. The device of any of claims 1-12, wherein the transparent substrate comprises glass, glass ceramic, polymer or a crystalline material.

14. The device of any of claims 1-13, wherein the device further comprises filling the void space on the silicon substrate and the at least one independent GaN element.

15. The device of any of claims 1-14, wherein the silicon substrate comprises mono- or poly crystalline silicon that is optionally substituted with 10¹³-10¹⁶ atoms/cm³ of boron, phosphorous, arsenic, oxygen or antimony.

16. The device of any of claims 1-15, wherein the vias are from about 1 μιη to about 50 μιη along their shortest in plane dimension.

17. The device of any of claims 1-16, wherein the via comprises a conductor material.

18. The device of claim 17, wherein the conductor material comprises gold, aluminum, silver, copper, or platinum.

19. The device of any of claims 1-18, wherein the device comprises a micro-light emitting diode.

20. A method of making the device of any of claims 1-19, the method comprising: a. removing from a silicon substrate optionally coated with a buffer layer and coated with a GaN layer, at least part of the GaN layer to produce a structured GaN layer comprising at least one independent GaN element and a void space on the silicon substrate;

b. removing at least part of the silicon substrate under the at least one independent GaN element to form a via that exposes the GaN or an optional buffer layer;

c. inserting a conductor material into the via;

d. forming a transparent conductor on the GaN layer;

f. forming at least one wall element on the transparent conductor to produce at least one well;

g. placing a quantum dot material in the well; and

h. placing or forming a transparent substrate on the wall element and well.

21. The method of claim 20, further comprising the step of optionally inserting a planarizing layer into the void space on the silicon substrate.

22. The method of claim 20 or 21, wherein the buffer layer is formed by molecular beam epitaxy or chemical vapor deposition.

23. The method of any of claims 20-22, wherein the removing at least part of the GaN layer comprises etching the GaN via silicon tetrachloride, bases, acids, peroxides, or laser-assisted etching.