WO2016199196A1 - 時刻同期装置及び時刻同期システム及び時刻同期方法 - Google Patents

時刻同期装置及び時刻同期システム及び時刻同期方法 Download PDF

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Publication number
WO2016199196A1
WO2016199196A1 PCT/JP2015/066503 JP2015066503W WO2016199196A1 WO 2016199196 A1 WO2016199196 A1 WO 2016199196A1 JP 2015066503 W JP2015066503 W JP 2015066503W WO 2016199196 A1 WO2016199196 A1 WO 2016199196A1
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Prior art keywords
data
time
unit
master device
synchronization
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PCT/JP2015/066503
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English (en)
French (fr)
Japanese (ja)
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暁楠 時
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to SG11201709362WA priority Critical patent/SG11201709362WA/en
Priority to PCT/JP2015/066503 priority patent/WO2016199196A1/ja
Priority to JP2017522769A priority patent/JP6261822B2/ja
Priority to DE112015006604.7T priority patent/DE112015006604B4/de
Priority to KR1020177031526A priority patent/KR101847366B1/ko
Priority to CN201580080812.4A priority patent/CN107636627B/zh
Priority to TW104123047A priority patent/TWI599863B/zh
Publication of WO2016199196A1 publication Critical patent/WO2016199196A1/ja

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/28Timers or timing mechanisms used in protocols

Definitions

  • the present invention relates to a time synchronization apparatus, a time synchronization system, and a time synchronization method.
  • Time synchronization accuracy is in microseconds.
  • the time synchronization method is mainly implemented on a hardware basis.
  • IEEE 1588 defines a method of synchronizing time by transmitting and receiving a synchronization frame in which time is recorded via a network.
  • the IEEE 1588 implementation is divided into two types: hardware-based implementation and software-based implementation.
  • the time is recorded using the PHY hardware time stamp function of the physical layer of the OSI (Open Systems Interconnection) reference model (see, for example, Patent Document 1). Therefore, the time transmission side records the time stamp when the PHY transmits the synchronization frame as the transmission time, and transmits the recorded transmission time. Similarly, the time reception side records the time stamp when the PHY receives the synchronization frame as the reception time, and uses the recorded reception time in the application program.
  • the time synchronization accuracy is theoretically 1 nanosecond, but is actually about 100 nanoseconds at the maximum.
  • the time is recorded using the software time stamp function of the application program that performs the processing of the application layer of the OSI reference model. Therefore, the time transmission side records the time stamp when the application program instructs the lower processing to transmit the synchronization frame as the transmission time, and transmits the recorded transmission time. Similarly, the time receiving side records the time stamp when the application program is notified of reception of the synchronization frame from the lower processing as the reception time, and uses the recorded reception time in the application program.
  • the time synchronization accuracy deteriorates to about 100 milliseconds in the worst case. Note that the time synchronization accuracy of the software base implementation varies greatly depending on the OS (Operating System) on which the application program operates and the hierarchical structure of the communication function.
  • the present invention aims to improve the time synchronization accuracy of the time synchronization method by software-based implementation.
  • a time synchronization apparatus includes: A receiver for receiving first data from a master device having a master clock; A transmitter that transmits second data to the master device after the first data is received by the receiver; Using a slave clock that is a software clock, a recording unit that records a reception time of the first data in the reception unit and a transmission time of the second data in the transmission unit; A correction unit that corrects the reception time of the first data and the transmission time of the second data recorded by the recording unit; At least the transmission time of the first data in the master device notified from the master device, the reception time of the first data corrected by the correction unit, and the transmission time of the second data corrected by the correction unit And a synchronization unit that calculates an offset, which is a time lag between the master clock and the slave clock, from the reception time of the second data at the master device notified from the master device.
  • the time synchronization accuracy of the time synchronization method based on the software base implementation is improved.
  • FIG. 3 shows a configuration example of a time synchronization system according to the first embodiment.
  • FIG. 2 is a block diagram illustrating configurations of a master device and a time synchronization device according to Embodiment 1.
  • 4 is a flowchart showing the operation of the time synchronization system according to the first embodiment.
  • 4 is a flowchart showing the operation of the time synchronization system according to the first embodiment.
  • 4 is a flowchart showing the operation of the time synchronization system according to the first embodiment.
  • FIG. 3 is a block diagram illustrating an implementation example of a master device and a time synchronization device according to the first embodiment.
  • FIG. 3 is a sequence diagram showing a communication procedure between the master device and the time synchronization device according to the first embodiment.
  • FIG. 4 is a diagram illustrating a configuration example of a time synchronization system according to a second embodiment.
  • FIG. 9 shows a configuration example of a time synchronization system according to a third embodiment. The figure which shows the hardware structural example of the time synchronizer which concerns on embodiment of this invention.
  • Embodiment 1 FIG.
  • the conventional time synchronization method based on software-based implementation has a problem of deterioration of time synchronization accuracy as described above.
  • the cause of this problem is the software processing time stamp fluctuation and the asymmetry of the internal processing delay of the terminal in which time synchronization is implemented.
  • at least a part of these factors is removed or suppressed by correcting the recorded value of time.
  • time synchronization in a distributed system having a plurality of devices is realized by software-based implementation.
  • the principle of IEEE 1588 is used.
  • This time synchronization method can be implemented in any terminal existing in the distributed system.
  • the OS installed in the terminal is a real-time OS.
  • the terminal on the time transmission side is a master.
  • the terminal on the time receiving side is a slave and a terminal that performs time synchronization.
  • the time synchronization system 100 is a distributed system.
  • the time synchronization system 100 includes one GM 110 (Grand Master), a plurality of PLCs 120 (Programmable Logic Controller), and a plurality of field devices 130.
  • a tree-type network topology is adopted.
  • the GM 110 is a root, and at least three PLCs 120 are connected to the GM 110 as lower nodes of the root. Further, as a lower node, at least one PLC 120 or at least three field devices 130 are connected to form a sub-network.
  • the GM110 provides a time reference.
  • the first time synchronization method 101 is applied to time synchronization between the GM 110 and the PLC 120 connected to the GM 110.
  • the first time synchronization method 101 is a time synchronization method based on software-based implementation according to the present embodiment, and uses the principle of IEEE 1588. The procedure of time synchronization by the first time synchronization method 101 will be described later.
  • the second time synchronization method 102 is applied to time synchronization within each subnetwork.
  • the second time synchronization method 102 is a time synchronization method unique to each subnetwork.
  • An arbitrary procedure can be applied to the time synchronization procedure by the second time synchronization method 102, and the description thereof will be omitted.
  • the PLC 120 connected to the GM 110 corresponds to the second time synchronization method 102 of each subnetwork and also corresponds to the first time synchronization method 101.
  • the number of PLCs 120 connected to the GM 110 and the configuration of each sub-network can be changed as appropriate.
  • the PLC 120 may be replaced with other types of devices such as NC (Numerical Controller).
  • the master device 200 has a master clock 201.
  • the master clock 201 is not a hardware clock but a software clock.
  • a hardware clock is a clock mounted on hardware.
  • the hardware clock is used for the hardware time stamp function.
  • the software clock is a clock managed by software.
  • the software clock is used for the software time stamp function.
  • the master device 200 includes a transmission unit 210, a reception unit 220, a recording unit 230, and a correction unit 240.
  • 1 is a terminal on the time transmission side in the first time synchronization method 101, and corresponds to the master device 200.
  • the time synchronizer 300 has a slave clock 301.
  • the slave clock 301 is not a hardware clock but a software clock.
  • the time synchronization apparatus 300 includes a reception unit 310, a transmission unit 320, a recording unit 330, a correction unit 340, and a synchronization unit 350.
  • the PLC 120 connected to the GM 110 shown in FIG. 1 is a terminal on the time reception side in the first time synchronization method 101, and corresponds to the time synchronization apparatus 300.
  • the master device 200 and the time synchronization device 300 transmit / receive data to / from each other via the network 400 in accordance with the communication procedure of the first time synchronization method 101 described below. Thereby, the time synchronizer 300 can adjust the time of the slave clock 301 to the time of the master clock 201.
  • the transmission unit 210 of the master device 200 transmits the first data 401 to the time synchronization device 300.
  • the receiving unit 310 of the time synchronization device 300 receives the first data 401 from the master device 200.
  • the transmission unit 320 of the time synchronization device 300 transmits the second data 402 to the master device 200 after the reception unit 310 receives the first data 401.
  • the receiving unit 220 of the master device 200 receives the second data 402 from the time synchronization device 300.
  • the recording unit 230 of the master device 200 records the transmission time of the first data 401 at the transmission unit 210 and the reception time of the second data 402 at the reception unit 220 using the master clock 201.
  • the correction unit 240 of the master device 200 corrects the transmission time of the first data 401 and the reception time of the second data 402 recorded by the recording unit 230.
  • the transmission unit 210 of the master device 200 has the third data 403 for notifying the time synchronization device 300 of the transmission time of the first data 401 corrected by at least the correction unit 240 and the second data corrected by at least the correction unit 240.
  • the fourth data 404 for notifying the reception time of the data 402 is transmitted. Thereby, the transmission unit 210 notifies the time synchronization apparatus 300 of the transmission time of the first data 401 and the reception time of the second data 402 corrected by at least the correction unit 240.
  • the receiving unit 310 of the time synchronization device 300 receives the third data 403 and the fourth data 404 from the master device 200.
  • the recording unit 330 of the time synchronization apparatus 300 records the reception time of the first data 401 at the reception unit 310 and the transmission time of the second data 402 at the transmission unit 320 using the slave clock 301.
  • the correction unit 340 of the time synchronization apparatus 300 corrects the reception time of the first data 401 and the transmission time of the second data 402 recorded by the recording unit 330.
  • the synchronization unit 350 of the time synchronization apparatus 300 includes at least the transmission time of the first data 401 notified from the master apparatus 200 and the reception time of the first data 401 corrected by the correction unit 340 and the correction unit 340.
  • An offset 405 is calculated from the corrected transmission time of the second data 402 and the reception time of the second data 402 at the master device 200 notified from the master device 200.
  • the offset 405 is a time lag between the master clock 201 and the slave clock 301.
  • the synchronization unit 350 refers to the third data 403 and the fourth data 404 received by the reception unit 310 when calculating the offset 405.
  • the synchronization unit 350 obtains the transmission time of the first data 401 in the master device 200 from the third data 403 received by the reception unit 310.
  • the synchronization unit 350 obtains the reception time of the second data 402 at the master device 200 from the fourth data 404 received by the reception unit 310.
  • the third data 403 includes not only the transmission time of the first data 401 corrected by the correction unit 240 of the master device 200 but also the first data 401 recorded by the recording unit 230 of the master device 200. This is data for notifying the transmission time.
  • the fourth data 404 is data for notifying the reception time of the second data 402 recorded by the recording unit 230 as well as the reception time of the second data 402 corrected by the correction unit 240. That is, in the present embodiment, the transmission unit 210 of the master device 200 further notifies the time synchronization device 300 of the transmission time of the first data 401 and the reception time of the second data 402 recorded by the recording unit 230. To do.
  • the synchronization unit 350 of the time synchronization apparatus 300 corrects the transmission time of the first data 401 recorded by the recording unit 230 of the master device 200 and the correction unit 240 of the master device 200 when calculating the offset 405. Both the transmission time of the first data 401 and the transmission time of the first data 401 in the master device 200 notified from the master device 200 are used. In addition, the synchronization unit 350 of the time synchronization apparatus 300 corrects the reception time of the second data 402 recorded by the recording unit 230 of the master device 200 and the correction unit 240 of the master device 200 when calculating the offset 405. Both the reception time of the second data 402 is used as the reception time of the second data 402 in the master device 200 notified from the master device 200.
  • the synchronization unit 350 receives not only the reception time of the first data 401 corrected by the correction unit 340 but also the reception of the first data 401 recorded by the recording unit 330 when calculating the offset 405. Time is also used. Further, when calculating the offset 405, the synchronization unit 350 uses not only the transmission time of the second data 402 corrected by the correction unit 340 but also the transmission time of the second data 402 recorded by the recording unit 330.
  • the synchronization unit 350 is recorded by the recording unit 330 and the transmission time of the first data 401 recorded by the master device 200 and the transmission time of the first data 401 corrected by the master device 200.
  • An offset 405 is calculated from the transmission time, the reception time of the second data 402 recorded by the master device 200, and the reception time of the second data 402 corrected by the master device 200.
  • the synchronization unit 350 records the sum of the transmission time of the first data 401 recorded by the master device 200 and the transmission time of the first data 401 corrected by the master device 200 and the recording unit 330.
  • the difference between the reception time of the first data 401 and the sum of the reception times of the first data 401 corrected by the correction unit 340 and the transmission time of the second data 402 recorded by the recording unit 330 and the correction unit 340 And the sum of the reception time of the second data 402 recorded by the master device 200 and the reception time of the second data 402 corrected by the master device 200.
  • An offset 405 is calculated from the difference.
  • the third data 403 may be data for notifying only the transmission time of the first data 401 recorded by the recording unit 230 of the master device 200.
  • the fourth data 404 may be data for notifying only the reception time of the second data 402 recorded by the recording unit 230. Therefore, the master device 200 may not include the correction unit 240.
  • the correction unit 340 of the time synchronization device 300 is the master device 200.
  • the transmission time of the first data 401 in the master device 200 notified from may be corrected.
  • the synchronization unit 350 of the time synchronization device 300 calculates the offset 405 and the correction time 340 corrected by the correction unit 340 together with the transmission time of the first data 401 in the master device 200 notified from the master device 200.
  • the transmission time of one data 401 can be used.
  • the correction unit 340 of the time synchronization device 300 is the master device 200.
  • the reception time of the second data 402 in the master device 200 notified from may be corrected.
  • the synchronization unit 350 of the time synchronization device 300 calculates the offset 405 and the correction time 340 corrected by the correction unit 340 together with the reception time of the second data 402 in the master device 200 notified from the master device 200.
  • the reception time of the two data 402 can be used.
  • the operation of the time synchronization system 100 will be described with reference to FIGS. 3, 4, and 5.
  • the operation of the time synchronization system 100 corresponds to the time synchronization method according to the present embodiment.
  • FIG. 3 shows operations related to transmission / reception of the first data 401.
  • transmission / reception of the first data 401 is repeated.
  • step S11 the transmission unit 210 of the master device 200 repeatedly transmits the first data 401 to the time synchronization device 300.
  • step S ⁇ b> 12 the reception unit 310 of the time synchronization device 300 repeatedly receives the first data 401 from the master device 200.
  • step S ⁇ b> 13 the recording unit 230 of the master device 200 records the transmission time of the first data 401 in the transmission unit 210 using the master clock 201 every time the first data 401 is transmitted by the transmission unit 210. .
  • step S14 the correction unit 240 of the master device 200 generates a random number each time the transmission time of the first data 401 is recorded by the recording unit 230, and the recording unit 230 records the generated random number. A correction value for the transmission time of the first data 401 is calculated.
  • step S ⁇ b> 15 the transmission unit 210 of the master device 200 transmits data for notifying the time synchronization device 300 of the correction value of the transmission time of the first data 401 calculated by the correction unit 240 as the third data 403. .
  • step S16 the reception unit 310 of the time synchronization apparatus 300 repeatedly receives the third data 403 from the master apparatus 200.
  • step S ⁇ b> 17 the recording unit 330 of the time synchronization apparatus 300 records the reception time of the first data 401 at the receiving unit 310 using the slave clock 301 every time the first data 401 is received by the receiving unit 310. To do.
  • step S18 the correction unit 340 of the time synchronization apparatus 300 generates a random number every time the reception time of the first data 401 is recorded by the recording unit 330, and is recorded by the recording unit 330 using the generated random number.
  • the correction value of the reception time of the first data 401 is calculated.
  • the synchronization unit 350 of the time synchronization apparatus 300 uses the correction value of the reception time of the first data 401 calculated by the correction unit 340 as the reception time of the first data 401 when calculating the offset 405. .
  • FIG. 4 shows operations related to transmission / reception of the second data 402.
  • transmission / reception of the second data 402 is also repeated.
  • step S ⁇ b> 21 the transmission unit 320 of the time synchronization device 300 transmits the second data 402 to the master device 200 every time the first data 401 is received by the reception unit 310.
  • step S22 the receiving unit 220 of the master device 200 repeatedly receives the second data 402 from the time synchronization device 300.
  • step S ⁇ b> 23 the recording unit 230 of the master device 200 records the reception time of the second data 402 at the receiving unit 220 using the master clock 201 every time the second data 402 is received by the receiving unit 220. .
  • step S24 the correction unit 240 of the master device 200 generates a random number each time the reception time of the second data 402 is recorded by the recording unit 230, and the recording unit 230 records the generated random number. A correction value for the reception time of the second data 402 is calculated.
  • step S ⁇ b> 25 the transmission unit 210 of the master device 200 transmits data for notifying the time synchronization device 300 of the correction value of the reception time of the second data 402 calculated by the correction unit 240 as the fourth data 404. .
  • step S ⁇ b> 26 the reception unit 310 of the time synchronization device 300 repeatedly receives the fourth data 404 from the master device 200.
  • step S ⁇ b> 27 the recording unit 330 of the time synchronization apparatus 300 records the transmission time of the second data 402 in the transmission unit 320 using the slave clock 301 every time the second data 402 is transmitted by the transmission unit 320. To do.
  • step S28 the correction unit 340 of the time synchronization apparatus 300 generates a random number each time the transmission time of the second data 402 is recorded by the recording unit 330, and is recorded by the recording unit 330 using the generated random number.
  • the correction value of the transmission time of the second data 402 is calculated.
  • the synchronization unit 350 of the time synchronization apparatus 300 uses the correction value of the transmission time of the second data 402 calculated by the correction unit 340 as the transmission time of the second data 402 when calculating the offset 405. .
  • the communication procedure for transmitting and receiving the first data 401, the second data 402, the third data 403, and the fourth data 404 one by one in order is repeated.
  • FIG. 5 shows an operation for calculating the offset 405.
  • step S31 the synchronization unit 350 of the time synchronization apparatus 300 calculates the offset 405 each time the first data 401 is received by the reception unit 220. That is, the synchronization unit 350 calculates one offset 405 for one communication procedure.
  • step S32 the synchronization unit 350 of the time synchronization apparatus 300 stores a plurality of calculated values of the offset 405. That is, the synchronization unit 350 accumulates two or more offsets 405 corresponding to two or more communication procedures.
  • step S33 the synchronization unit 350 of the time synchronization apparatus 300 performs statistical processing on the accumulated plurality of calculated values.
  • the synchronization unit 350 adjusts the time of the slave clock 301 according to the result of the statistical processing. Specifically, the synchronization unit 350 adjusts the time of the slave clock 301 using an average of a plurality of accumulated calculation values as a result of statistical processing. Thereby, the time of the master clock 201 and the time of the slave clock 301 are synchronized.
  • the principle of IEEE 1588 is used. That is, the first data 401, the second data 402, the third data 403, and the fourth data 404 are transmitted and received as a synchronization frame. Specifically, the first data 401 is transmitted / received as a Sync message, the second data 402 is transmitted / received as a Follow_Up message, the third data 403 is transmitted / received as a Delay_Req message, and the fourth data 404 is transmitted / received as a Delay_Resp message.
  • the reception time of the first data 401 recorded by the recording unit 330 and the correction unit 340 corrected the reception time.
  • the transmission time of the first data 401 recorded by the master device 200 is calculated from the sum of the reception time of the first data 401 recorded by the recording unit 330 and the reception time of the first data 401 corrected by the correction unit 340.
  • the value obtained by subtracting the sum of the transmission time of the first data 401 corrected by the master device 200 and the value obtained by dividing by 2, the reception time of the second data 402 recorded by the master device 200 and the correction by the master device 200 A value obtained by subtracting the sum of the transmission time of the second data 402 recorded by the recording unit 330 and the transmission time of the second data 402 corrected by the correction unit 340 from the total of the received time of the second data 402
  • the value obtained by subtracting the one-way delay from either one of the values obtained by dividing by 2 is the offset 405.
  • the offset 405 is T_offset
  • the transmission time of the first data 401 recorded by the recording unit 230 of the master device 200 is T_m1
  • the correction value of T_m1 is T_m1 ′
  • the first recorded by the recording unit 330 of the time synchronization device 300 is T_offset
  • the sum of the value obtained by subtracting the transmission time of the second data 402 corrected by the correction unit 340 from the reception time 402 may be regarded as a one-way delay.
  • a value obtained by subtracting a one-way delay from one of the value obtained by subtracting the transmission time of the second data 402 corrected by the correction unit 340 from the reception time of the data 402 is the offset 405.
  • the offset 405 may be obtained using a calculation formula of “ ⁇ T_s2”)) / 2.
  • the functions of the reception unit 310 and the transmission unit 320 of the time synchronization apparatus 300 are implemented in the PHY 302 and the MAC 303 (Media / Access / Control).
  • the PHY 302 and the MAC 303 are hardware built in the time synchronization apparatus 300.
  • the PHY 302 is a chip that performs processing of the physical layer of the OSI reference model
  • the MAC 303 is a chip that performs processing of the data link layer of the OSI reference model. Note that the PHY 302 and the MAC 303 may be integrated into the same chip.
  • the functions of the transmission unit 210 and the reception unit 220 of the master device 200 are also implemented in the PHY 202 and the MAC 203.
  • the PHY 202 is a chip that performs physical layer processing
  • the MAC 203 is a chip that performs data link layer processing.
  • the function of the recording unit 330 of the time synchronization apparatus 300 is implemented in the MAC driver 304.
  • the MAC driver 304 is software installed in the time synchronization apparatus 300. Specifically, the MAC driver 304 is middleware used by the OS 305 to control and operate the MAC 303.
  • the MAC driver 304 has a software time stamp function that generates a time stamp using the slave clock 301.
  • the function of the recording unit 230 of the master device 200 is also implemented in the MAC driver 204.
  • the MAC driver 204 is middleware used by the OS 205 to control and operate the MAC 203.
  • the MAC driver 204 has a software time stamp function that generates a time stamp using the master clock 201.
  • the functions of the correction unit 340 and the synchronization unit 350 of the time synchronization apparatus 300 are implemented in the time synchronization application 306.
  • the time synchronization application 306 is software installed in the time synchronization apparatus 300. Specifically, the time synchronization application 306 is an application program that runs on the OS 305 together with other applications 307.
  • the time synchronization application 306 manages a correction table 308 for correcting time stamp fluctuations generated by the MAC driver 304.
  • the function of the correction unit 240 of the master device 200 is also implemented in the time synchronization application 206.
  • the time synchronization application 206 is an application program that runs on the OS 205 together with other applications 207.
  • the time synchronization application 206 manages a correction table 208 for correcting time stamp fluctuations generated by the MAC driver 204.
  • the master device 200 that transmits time and the time synchronization device 300 that synchronizes time have the same hierarchical structure with respect to time synchronization.
  • This hierarchical structure is a three-layer structure including an application layer corresponding to the OSs 205 and 305 and time synchronization applications 206 and 306, a data link layer corresponding to the MAC drivers 204 and 304 and MACs 203 and 303, and a physical layer corresponding to the PHYs 202 and 302. is there.
  • the data link layer is directly accessed from the application layer without passing through the transport layer and network layer of the OSI reference model.
  • step S41 in which the master device 200 transmits a Sync message as a synchronization frame, the time synchronization application 206 generates a synchronization frame that is a Sync message.
  • the time synchronization application 206 does not store the time in this synchronization frame.
  • the OS 205 detects that a synchronization frame is generated by the time synchronization application 206, the OS 205 activates a priority interrupt and inputs the synchronization frame to the MAC driver 204 before other frames.
  • the MAC driver 204 records the transmission time T_m1 of the synchronization frame by generating a software time stamp when the synchronization frame is input. Thereafter, the MAC driver 204 inputs a synchronization frame to the MAC 203.
  • the MAC 203 transmits a synchronization frame from the PHY 202.
  • the MAC driver 204 feeds back the recorded transmission time T_m1 to the time synchronization application 206.
  • the time synchronization application 206 stores the transmission time T_m1 fed back from the MAC driver 204 in the first column in the first column of the correction table 208.
  • the time synchronization application 206 generates a random number according to the normal distribution, and stores the generated random number in the same column of the second row of the correction table 208.
  • the time synchronization application 206 corrects the fluctuation of the transmission time T_m1 by subtracting the random number stored in the second row of the correction table 208 from the transmission time T_m1 stored in the first row of the correction table 208.
  • the time synchronization application 206 stores the corrected transmission time T_m1 ′ in the same column of the third row of the correction table 208.
  • the transmission time T_m1 may be corrected by other methods such as adding a random number to the transmission time T_m1 instead of subtracting a random number from the transmission time T_m1. Further, in which row and in what column of the correction table 208 the transmission time T_m1, the random number, and the corrected transmission time T_m1 'can be appropriately changed.
  • step S51 in which the time synchronization apparatus 300 receives the Sync message as a synchronization frame, the PHY 302 receives the synchronization frame from the master apparatus 200.
  • the PHY 302 inputs the received synchronization frame to the MAC 303.
  • the MAC driver 304 records the reception time T_s1 of the synchronization frame by generating a software time stamp when detecting that the synchronization frame is input to the MAC 303. Thereafter, the MAC driver 304 immediately inputs the recorded reception time T_s1 to the time synchronization application 306.
  • the time synchronization application 306 stores the reception time T_s ⁇ b> 1 input from the MAC driver 304 in the first column of the first column in the correction table 308.
  • the time synchronization application 306 generates a random number according to the normal distribution, and stores the generated random number in the same column on the second row of the correction table 308.
  • the time synchronization application 306 corrects the fluctuation of the reception time T_s1 by subtracting the random number stored in the second row of the correction table 308 from the reception time T_s1 stored in the first row of the correction table 308.
  • the time synchronization application 306 stores the corrected reception time T_s1 ′ in the same column in the third row of the correction table 308.
  • the reception time T_s1 may be corrected by other methods such as adding a random number to the reception time T_s1 instead of subtracting a random number from the reception time T_s1.
  • the random number, and the corrected reception time T_s1 ' can be appropriately changed.
  • step S42 in which the master device 200 transmits a follow_Up message as a synchronization frame, the time synchronization application 206 generates a synchronization frame that is a Follow_Up message.
  • the time synchronization application 206 stores the pre-correction stored in the first row and the third row of the correction table 208 and the correction before the correction stored in the last column of the set of the transmission times T_m1 and T_m1 ′ corrected in this synchronization frame.
  • Stores a set of corrected transmission times T_m1 and T_m1 ′ that is, the corrected transmission times T_m1 and T_m1 ′ before correction of the immediately preceding Sync message.
  • the OS 205 When the OS 205 detects that a synchronization frame is generated by the time synchronization application 206, the OS 205 activates a priority interrupt and inputs the synchronization frame to the MAC driver 204 before other frames.
  • the MAC driver 204 generates a software time stamp when a synchronization frame is input. However, the MAC driver 204 detects that the synchronization frame is a Follow_Up message, and holds the generated time stamp in a buffer or the like for a certain period of time, and does not feed back to the time synchronization application 206. Thereafter, the MAC driver 204 inputs a synchronization frame to the MAC 203.
  • the MAC 203 transmits a synchronization frame from the PHY 202.
  • step S52 where the time synchronization apparatus 300 receives the Follow_Up message as a synchronization frame
  • the PHY 302 receives the synchronization frame from the master apparatus 200.
  • the PHY 302 inputs the received synchronization frame to the MAC 303.
  • the MAC driver 304 generates a software time stamp when it detects that a synchronization frame has been input to the MAC 303.
  • the MAC driver 304 detects that the synchronization frame is a Follow_Up message, and only holds the generated time stamp in a buffer or the like and does not input it to the time synchronization application 306.
  • the MAC driver 304 inputs the synchronization frame to the time synchronization application 306 via the OS 305.
  • the time synchronization application 306 detects that the synchronization frame input from the MAC driver 304 is a Follow_Up message, and extracts pre-correction and corrected transmission times T_m1 and T_m1 ′ stored in the synchronization frame.
  • step S53 in which the time synchronization apparatus 300 transmits the Delay_Req message as a synchronization frame, the time synchronization application 306 generates a synchronization frame that is a Delay_Req message.
  • the time synchronization application 306 does not store the time in this synchronization frame.
  • the OS 305 detects that the synchronization frame is generated by the time synchronization application 306, the OS 305 activates a priority interrupt and inputs the synchronization frame to the MAC driver 304 before other frames.
  • the MAC driver 304 records the transmission time T_s2 of the synchronization frame by generating a software time stamp when the synchronization frame is input. Thereafter, the MAC driver 304 inputs a synchronization frame to the MAC 303.
  • the MAC 303 transmits a synchronization frame from the PHY 302.
  • the MAC driver 304 feeds back the recorded transmission time T_s2 to the time synchronization application 306.
  • the time synchronization application 306 stores the transmission time T_s2 fed back from the MAC driver 304 in the first column among the free columns in the fourth row of the correction table 308.
  • the time synchronization application 306 generates a random number according to a normal distribution, and stores the generated random number in the same column of the fifth row of the correction table 308.
  • the time synchronization application 306 corrects the fluctuation of the transmission time T_s2 by subtracting the random number stored in the fifth row of the correction table 308 from the transmission time T_s2 stored in the fourth row of the correction table 308.
  • the time synchronization application 306 stores the corrected transmission time T_s2 ′ in the same column of the sixth row of the correction table 308.
  • the transmission time T_s2 may be corrected by other methods such as adding a random number to the transmission time T_s2 instead of subtracting a random number from the transmission time T_s2.
  • what row and what column of the correction table 308 stores the transmission time T_s2, the random number, and the corrected transmission time T_s2 'can be appropriately changed.
  • step S43 where the master device 200 receives the Delay_Req message as a synchronization frame, the PHY 202 receives the synchronization frame from the time synchronization device 300.
  • the PHY 202 inputs the received synchronization frame to the MAC 203.
  • the MAC driver 204 records the reception time T_m2 of the synchronization frame by generating a software time stamp when detecting that the synchronization frame is input to the MAC 203. Thereafter, the MAC driver 204 immediately inputs the recorded reception time T_m2 to the time synchronization application 206.
  • the time synchronization application 206 stores the reception time T_m2 input from the MAC driver 204 in the first column among the free columns in the fourth row of the correction table 208.
  • the time synchronization application 206 generates a random number according to the normal distribution, and stores the generated random number in the same column of the fifth row of the correction table 208.
  • the time synchronization application 206 corrects the fluctuation of the reception time T_m2 by subtracting the random number stored in the fifth row of the correction table 208 from the reception time T_m2 stored in the fourth row of the correction table 208.
  • the time synchronization application 206 stores the corrected reception time T_m2 ′ in the same column of the sixth row of the correction table 208.
  • the reception time T_m2 may be corrected by other methods such as adding a random number to the reception time T_m2 instead of subtracting a random number from the reception time T_m2.
  • step S44 in which the master device 200 transmits the Delay_Resp message as a synchronization frame, the time synchronization application 206 generates a synchronization frame that is a Delay_Resp message.
  • the time synchronization application 206 stores the pre-correction stored in the last column of the set of the reception time T_m1 and T_m2 ′ before and after the correction stored in the fourth and sixth rows of the correction table 208 in the synchronization frame.
  • Stores a set of corrected reception times T_m1 and T_m2 ′ that is, the corrected reception times T_m1 and T_m2 ′ before correction of the immediately preceding Delay_Req message.
  • the OS 205 When the OS 205 detects that a synchronization frame is generated by the time synchronization application 206, the OS 205 activates a priority interrupt and inputs the synchronization frame to the MAC driver 204 before other frames.
  • the MAC driver 204 generates a software time stamp when a synchronization frame is input. However, the MAC driver 204 detects that the synchronization frame is a Delay_Resp message, and only holds the generated time stamp in a buffer or the like, and does not feed back to the time synchronization application 206. Thereafter, the MAC driver 204 inputs a synchronization frame to the MAC 203.
  • the MAC 203 transmits a synchronization frame from the PHY 202.
  • step S54 in which the time synchronization apparatus 300 receives the Delay_Resp message as a synchronization frame, the PHY 302 receives the synchronization frame from the master apparatus 200.
  • the PHY 302 inputs the received synchronization frame to the MAC 303.
  • the MAC driver 304 generates a software time stamp when it detects that a synchronization frame has been input to the MAC 303.
  • the MAC driver 304 detects that the synchronization frame is a Delay_Resp message, and only holds the generated time stamp in a buffer or the like and does not input it to the time synchronization application 306. Thereafter, the MAC driver 304 inputs the synchronization frame to the time synchronization application 306 via the OS 305.
  • the time synchronization application 306 detects that the synchronization frame input from the MAC driver 304 is a Delay_Resp message, and extracts pre-correction and corrected reception times T_m1 and T_m2 'stored in the synchronization frame.
  • the time synchronization application 306 includes the pre-correction and corrected reception times T_s1 and T_s1 ′ stored in the first and third rows of the correction table 308 in step S51, and the pre-correction and The corrected transmission times T_m1, T_m1 ′, the pre-correction and corrected transmission times T_s2, T_s2 ′ stored in the fourth and sixth rows of the correction table 308 in step S53, and the pre-correction and extracted in step S54
  • An offset 405 is calculated using the corrected reception times T_m2 and T_m2 ′.
  • step S41 to step S44 and the procedure from step S51 to step S54 are repeatedly executed.
  • Embodiment 2 FIG. In the present embodiment, differences from the first embodiment will be mainly described.
  • the second time synchronization method 102 is applied to time synchronization within all sub-networks.
  • the first time synchronization method 101 is used for time synchronization within some sub-networks. Applied.
  • some of the PLCs 120 connected to the GM 110 are also terminals on the time transmission side in the first time synchronization method 101, and correspond to both the master device 200 and the time synchronization device 300.
  • the field device 130 connected to a part of the PLC 120 is a terminal on the time reception side in the first time synchronization method 101, and corresponds to the time synchronization apparatus 300.
  • the configurations and operations of the master device 200 and the time synchronization device 300 according to the present embodiment are the same as those of the first embodiment.
  • Embodiment 3 FIG. In the present embodiment, differences from the first embodiment will be mainly described.
  • a line-type network topology is partially adopted.
  • Three PLCs 120 are connected in series to the GM 110. Under these three PLCs 120, at least one PLC 120 or at least two field devices 130 are connected to form a tree-type sub-network.
  • the first time synchronization method 101 is applied to time synchronization between the GM 110 and the PLC 120 connected in series to the GM 110.
  • the first time synchronization method 101 is also applied to time synchronization between the PLCs 120 connected in series to the GM 110.
  • the middle two PLCs 120 are also terminals on the time transmission side in the first time synchronization method 101, and correspond to both the master device 200 and the time synchronization device 300.
  • the master function is distributed to the GM 110 and the two PLCs 120.
  • the middle two PLCs 120 are not transmitted and received between the GM 110 and the other PLCs 120, instead of being terminals on the time transmission side in the first time synchronization method 101.
  • the synchronization frame may be simply transferred.
  • the middle two PLCs 120 correspond to only the time synchronization apparatus 300.
  • the present embodiment can be changed to a form in which the master functions are integrated into the GM 110.
  • the configurations and operations of the master device 200 and the time synchronization device 300 according to the present embodiment are the same as those of the first embodiment.
  • the time synchronization apparatus 300 is a computer.
  • the time synchronization apparatus 300 includes hardware such as a processor 901, an auxiliary storage device 902, a memory 903, a communication device 904, an input interface 905, and a display interface 906.
  • the processor 901 is connected to other hardware via the signal line 910, and controls these other hardware.
  • the input interface 905 is connected to the input device 907.
  • the display interface 906 is connected to the display 908.
  • the processor 901 is an IC (Integrated Circuit) that performs processing.
  • the processor 901 is, for example, a CPU (Central Processing Unit), a DSP (Digital Signal Processor), or a GPU (Graphics Processing Unit).
  • the auxiliary storage device 902 is a recording medium such as a ROM (Read / Only / Memory), a flash memory, or an HDD (Hard / Disk / Drive).
  • ROM Read / Only / Memory
  • HDD Hard / Disk / Drive
  • the memory 903 is, for example, a RAM (Random Access Memory).
  • the communication device 904 includes a receiver 921 that receives data and a transmitter 922 that transmits data.
  • the communication device 904 is, for example, a communication chip or a NIC (Network, Interface, Card).
  • the input interface 905 is a port to which the cable 911 of the input device 907 is connected.
  • the input interface 905 is, for example, a USB (Universal / Serial / Bus) terminal.
  • the display interface 906 is a port to which the cable 912 of the display 908 is connected.
  • the display interface 906 is, for example, a USB terminal or an HDMI (registered trademark) (High Definition, Multimedia, Interface) terminal.
  • the input device 907 is, for example, a mouse, a touch pen, a keyboard, or a touch panel.
  • the display 908 is, for example, an LCD (Liquid / Crystal / Display).
  • the auxiliary storage device 902 stores programs that realize the functions of “units” such as the reception unit 310, the transmission unit 320, the recording unit 330, the correction unit 340, and the synchronization unit 350. This program is loaded into the memory 903, read into the processor 901, and executed by the processor 901.
  • the auxiliary storage device 902 also stores an OS. At least a part of the OS is loaded into the memory 903, and the processor 901 executes a program that realizes the function of “unit” while executing the OS.
  • the time synchronization apparatus 300 may include a plurality of processors 901.
  • a plurality of processors 901 may execute a program for realizing the function of “unit” in cooperation with each other.
  • auxiliary storage device 902 Information, data, signal values, and variable values indicating the processing results of “unit” are stored in the auxiliary storage device 902, the memory 903, or a register or cache memory in the processor 901.
  • Parts may be provided on “Circuits”. Further, “part” may be read as “circuit”, “process”, “procedure”, or “processing”. “Circuit” and “Circuitry” include not only the processor 901 but also other logic ICs, GA (Gate-Array), ASIC (Application-Specific-Integrated-Circuit), FPGA (Field-Programmable-Gate-Array), etc. It is a concept that includes various types of processing circuits.
  • 100 time synchronization system 101 first time synchronization method, 102 second time synchronization method, 110 GM, 120 PLC, 130 field device, 200 master device, 201 master clock, 202 PHY, 203 MAC, 204 MAC driver, 205 OS, 206 Time synchronization application, 207 Other application, 208 Correction table, 210 Transmission unit, 220 Reception unit, 230 Recording unit, 240 Correction unit, 300 Time synchronization device, 301 Slave clock, 302 PHY, 303 MAC, 304 MAC driver, 305 OS, 306 Time synchronization application, 307 Other application, 308 Correction table, 310 Receiver, 320 Transmitter, 330 Recorder, 340 Correction , 350 synchronization unit, 400 network, 401 first data, 402 second data, 403 third data, 404 fourth data, 405 offset, 901 processor, 902 auxiliary storage device, 903 memory, 904 communication device, 905 input interface, 906 Display interface, 907 input device, 908 display, 910 signal line,

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PCT/JP2015/066503 2015-06-08 2015-06-08 時刻同期装置及び時刻同期システム及び時刻同期方法 WO2016199196A1 (ja)

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SG11201709362WA SG11201709362WA (en) 2015-06-08 2015-06-08 Time synchronization device, time synchronization system, and time synchronization method
PCT/JP2015/066503 WO2016199196A1 (ja) 2015-06-08 2015-06-08 時刻同期装置及び時刻同期システム及び時刻同期方法
JP2017522769A JP6261822B2 (ja) 2015-06-08 2015-06-08 時刻同期装置及び時刻同期システム及び時刻同期方法
DE112015006604.7T DE112015006604B4 (de) 2015-06-08 2015-06-08 Zeitsynchronisationseinrichtung, Zeitsynchronisationssystem und Zeitsynchronisationsverfahren
KR1020177031526A KR101847366B1 (ko) 2015-06-08 2015-06-08 시각 동기 장치 및 시각 동기 시스템
CN201580080812.4A CN107636627B (zh) 2015-06-08 2015-06-08 时刻同步装置、时刻同步系统及时刻同步方法
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019027099A1 (ko) * 2017-07-31 2019-02-07 한국전기연구원 이더캣 네트워크의 마스터와 슬레이브들 간의 동기화 오차 보상을 위한 동기화 오차 보상시스템 및 그 동기화 오차 보상방법
JP2021527355A (ja) * 2018-06-14 2021-10-11 マイクロチップ テクノロジー インコーポレイテッドMicrochip Technology Incorporated コストが最適化された環境におけるphyレベルハードウェアタイムスタンプ及び時間同期の実行

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020059137A1 (ja) * 2018-09-21 2020-03-26 三菱電機株式会社 通信装置、通信システム、通信方法および通信プログラム
CN110244635A (zh) * 2019-06-24 2019-09-17 中国航空无线电电子研究所 具有计算转发时间功能的远程数据集中器

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010078529A (ja) * 2008-09-26 2010-04-08 Brother Ind Ltd 端末装置及びその時刻調整方法
JP2011525308A (ja) * 2008-05-02 2011-09-15 ノーテル・ネットワークス・リミテッド パケットネットワークを介した時間同期のためのタイミングシステム及び方法
WO2013051446A1 (ja) * 2011-10-06 2013-04-11 ソニー株式会社 時刻制御装置、時刻制御方法、およびプログラム
JP2013074527A (ja) * 2011-09-28 2013-04-22 Fujitsu Ltd 伝送装置、伝送システム及び通信制御方法
JP2015020351A (ja) * 2013-07-19 2015-02-02 京セラドキュメントソリューションズ株式会社 画像形成装置及び画像形成方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013152095A (ja) * 2012-01-24 2013-08-08 Sony Corp 時刻制御装置、時刻制御方法、およびプログラム
WO2012092892A2 (zh) * 2012-02-01 2012-07-12 华为技术有限公司 时间同步方法和设备及系统
US10197974B2 (en) 2012-09-11 2019-02-05 Mitsubishi Electric Corporation Correction parameter calculation system and method
JP2015035158A (ja) * 2013-08-09 2015-02-19 ルネサスエレクトロニクス株式会社 データ処理システム

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011525308A (ja) * 2008-05-02 2011-09-15 ノーテル・ネットワークス・リミテッド パケットネットワークを介した時間同期のためのタイミングシステム及び方法
JP2010078529A (ja) * 2008-09-26 2010-04-08 Brother Ind Ltd 端末装置及びその時刻調整方法
JP2013074527A (ja) * 2011-09-28 2013-04-22 Fujitsu Ltd 伝送装置、伝送システム及び通信制御方法
WO2013051446A1 (ja) * 2011-10-06 2013-04-11 ソニー株式会社 時刻制御装置、時刻制御方法、およびプログラム
JP2015020351A (ja) * 2013-07-19 2015-02-02 京セラドキュメントソリューションズ株式会社 画像形成装置及び画像形成方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019027099A1 (ko) * 2017-07-31 2019-02-07 한국전기연구원 이더캣 네트워크의 마스터와 슬레이브들 간의 동기화 오차 보상을 위한 동기화 오차 보상시스템 및 그 동기화 오차 보상방법
JP2021527355A (ja) * 2018-06-14 2021-10-11 マイクロチップ テクノロジー インコーポレイテッドMicrochip Technology Incorporated コストが最適化された環境におけるphyレベルハードウェアタイムスタンプ及び時間同期の実行

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