WO2016197406A1 - Tft基板结构的制作方法及tft基板结构 - Google Patents

Tft基板结构的制作方法及tft基板结构 Download PDF

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WO2016197406A1
WO2016197406A1 PCT/CN2015/082168 CN2015082168W WO2016197406A1 WO 2016197406 A1 WO2016197406 A1 WO 2016197406A1 CN 2015082168 W CN2015082168 W CN 2015082168W WO 2016197406 A1 WO2016197406 A1 WO 2016197406A1
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Prior art keywords
photoresist
layer
gate
segment
segments
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French (fr)
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郭文帅
明星
申智渊
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/778,607 priority Critical patent/US9859436B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT substrate structure and a TFT substrate structure.
  • Liquid crystal display has many advantages such as thin body, power saving, no radiation, etc., and is widely used, such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptops. Screen, etc.
  • a liquid crystal display device includes a housing, a liquid crystal panel disposed in the housing, and a backlight module disposed in the housing.
  • the structure of the liquid crystal panel is mainly composed of a Thin Film Transistor Array Substrate (TFT Array Substrate), a color filter substrate (Color Filter, CF), and a liquid crystal layer disposed between the two substrates (Liquid).
  • the crystal layer is constructed by controlling the rotation of the liquid crystal molecules of the liquid crystal layer by applying a driving voltage on the two glass substrates, and refracting the light of the backlight module to produce a picture.
  • hot carriers are injected into the oxide layer across the insulating layer, accumulating, changing the threshold voltage, affecting the life of the device;
  • the depletion region near the drain collides with the crystal lattice to generate a new electron-hole pair.
  • MOS metal oxide semiconductor
  • the electrons generated by the collision form an additional leakage current.
  • the holes are collected by the substrate to form a substrate current such that the total current becomes the sum of the saturated leakage current and the substrate current.
  • the hot carrier effect is one of the fundamental factors limiting the maximum operating voltage of the device.
  • FIG. 1 is a schematic diagram of a conventional TFT substrate structure including a substrate 100, a semiconductor layer 200 disposed on the substrate 100, and a source/drain 300 disposed on the semiconductor layer 200.
  • An insulating layer 400 disposed on the source/drain 300 and the semiconductor layer 200, and a gate 500 disposed on the insulating layer 400.
  • the The semiconductor layer 200 includes two N-type heavily doped regions 220 corresponding to the channel region 210 under the gate 500, on both sides of the channel region 210, and in contact with the source/drain 300, and The two offset regions 230 between the two N-type heavily doped regions 220 and the channel region 210, because the offset region 230 is not doped, has a high resistance value, and can disperse a strong electric field near the electrode, thereby reducing hot carriers.
  • the leakage current of the TFT substrate structure becomes smaller, the operating current thereof is correspondingly reduced, resulting in an increase in power consumption.
  • An object of the present invention is to provide a method for fabricating a TFT substrate structure, which can form an n-type heavily doped region while forming an undoped region between n-type heavily doped regions to increase resistance and dispersion.
  • a strong electric field near the electrode prevents the hot carrier effect caused by the presence of a local strong electric field from affecting the device characteristics and improving the operating current.
  • Another object of the present invention is to provide a TFT substrate structure in which an undoped region is formed between n-type heavily doped regions of a polysilicon layer, which can avoid local strong electric field generation and eliminate the influence of hot carrier effect on device characteristics. Increase the working current.
  • the present invention provides a method for fabricating a TFT substrate structure, including the following steps:
  • Step 1 providing a substrate, depositing a buffer layer on the substrate;
  • Step 2 depositing a polysilicon layer on the buffer layer
  • Step 3 depositing a gate insulating layer on the polysilicon layer, and depositing a metal layer on the gate insulating layer;
  • Step 4 coating a photoresist layer on the metal layer, exposing and developing the photoresist layer through a photomask to obtain a first photoresist segment located in the middle, and spaced apart from the first photoresist layer a plurality of second photoresist segments on both sides of the segment;
  • Step 5 using the first photoresist segment and the plurality of second photoresist segments as a barrier layer, etching the metal layer, and obtaining a gate corresponding to the first photoresist segment, respectively corresponding to the number Several metal segments are obtained under the second photoresist segment;
  • Step 6 Stripping the first photoresist segment and the plurality of second photoresist segments, and using the gate electrode and the plurality of metal segments as photomasks, performing ion implantation on the polysilicon layer, corresponding to the polysilicon layer An undoped channel region is formed under the gate, and a plurality of n-type heavily doped regions are formed on opposite sides of the channel region, and corresponding to the plurality of n-type weights formed under the plurality of metal segments A plurality of undoped regions between the doped regions.
  • the step 4 uses a single slit mask, a halftone mask, or a gray scale mask to obtain the first photoresist segment and the plurality of second photoresist segments.
  • the distance between the two second photoresist segments on both sides of the first photoresist segment and the first photoresist segment is less than 1 ⁇ m, and the width of the second photoresist segment is from 1 ⁇ m to 2 ⁇ m.
  • the step 5 is performed by dry etching or wet etching to obtain the gate electrode and a plurality of metal segments.
  • the distance between the two metal segments on both sides of the gate and the gate is less than 1 ⁇ m, and the width of the metal segment is 1 ⁇ m to 2 ⁇ m.
  • the material of the buffer layer and the gate insulating layer is silicon oxide, silicon nitride, or a combination of the two.
  • the material of the metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the invention also provides a method for fabricating a TFT substrate structure, comprising the following steps:
  • Step 1 providing a substrate, depositing a buffer layer on the substrate;
  • Step 2 depositing a polysilicon layer on the buffer layer
  • Step 3 depositing a gate insulating layer on the polysilicon layer, and depositing a metal layer on the gate insulating layer;
  • Step 4 coating a photoresist layer on the metal layer, exposing and developing the photoresist layer through a photomask to obtain a first photoresist segment located in the middle, and spaced apart from the first photoresist layer a plurality of second photoresist segments on both sides of the segment;
  • Step 5 using the first photoresist segment and the plurality of second photoresist segments as a barrier layer, etching the metal layer, and obtaining a gate corresponding to the first photoresist segment, respectively corresponding to the number Several metal segments are obtained under the second photoresist segment;
  • Step 6 Stripping the first photoresist segment and the plurality of second photoresist segments, and using the gate electrode and the plurality of metal segments as photomasks, performing ion implantation on the polysilicon layer, corresponding to the polysilicon layer
  • An undoped channel region is formed under the gate, and a plurality of n-type heavily doped regions are formed on opposite sides of the channel region, and corresponding to the plurality of n-type weights formed under the plurality of metal segments a plurality of undoped regions between the doped regions;
  • the step 4 uses a single slit mask, a halftone mask, or a gray scale mask to obtain the first photoresist segment and the plurality of second photoresist segments;
  • the distance between the two second photoresist segments on both sides of the first photoresist segment and the first photoresist segment is less than 1 ⁇ m, and the width of the second photoresist segment is from 1 ⁇ m to 2 ⁇ m;
  • step 5 the gate electrode and the plurality of metal segments are obtained by dry etching or wet etching.
  • the present invention also provides a TFT substrate structure, comprising a substrate, a buffer layer disposed on the substrate, a polysilicon layer disposed on the buffer layer, a gate insulating layer disposed on the polysilicon layer, and disposed at the a gate electrode on the gate insulating layer; and a plurality of metal segments disposed on the gate insulating layer and spaced apart from each other on the two sides of the gate;
  • the polysilicon layer includes a channel region corresponding to the underside of the gate, and is located in the channel region a plurality of n-type heavily doped regions on the side, and a plurality of undoped regions corresponding to the plurality of metal segments and located between the plurality of n-type heavily doped regions.
  • the distance between the two metal segments on both sides of the gate and the gate is less than 1 ⁇ m, and the width of the metal segment is 1 ⁇ m to 2 ⁇ m.
  • the material of the buffer layer and the gate insulating layer is silicon oxide, silicon nitride, or a combination of the two; the gate and the material of the plurality of metal segments are one of molybdenum, titanium, aluminum, and copper. Or a variety of stack combinations.
  • the TFT substrate structure of the present invention is formed by forming a plurality of metal segments spaced apart on both sides of the gate while forming the gate electrode, and using the gate electrode and the plurality of metal segments as the photomask. Ion implantation of the polysilicon layer, forming an n-type heavily doped region on the polysilicon layer, forming an undoped region between the n-type heavily doped regions, increasing the resistance value, dispersing a strong electric field near the electrode, and avoiding The effect of the hot carrier effect on the device characteristics due to the existence of a local strong electric field improves the operating current, simplifies the process, reduces the production cost, and reduces the size of the TFT substrate.
  • an undoped region is formed between the n-type heavily doped regions of the polysilicon layer, thereby avoiding the generation of a local strong electric field and eliminating the influence of the hot carrier effect on the device characteristics, and having a high Working current, simple structure and low production cost.
  • 1 is a schematic view showing a structure of a conventional TFT substrate
  • FIG. 2 is a flow chart showing a method of fabricating a TFT substrate structure of the present invention
  • FIG. 3 is a schematic view showing the first step of the method for fabricating the TFT substrate structure of the present invention.
  • FIG. 4 is a schematic view showing a step 2 of a method for fabricating a TFT substrate structure according to the present invention
  • step 3 is a schematic diagram of step 3 of a method for fabricating a TFT substrate structure according to the present invention.
  • 6-7 is a schematic view showing a step 4 of a method for fabricating a TFT substrate structure according to the present invention
  • step 5 is a schematic diagram of step 5 of a method for fabricating a TFT substrate structure according to the present invention.
  • FIGS. 9-10 are schematic diagrams showing the step 6 of the method for fabricating the TFT substrate structure of the present invention.
  • FIG. 11 is a schematic view showing another embodiment of a method for fabricating a TFT substrate structure according to the present invention.
  • FIG. 12 is a cross-sectional view showing a first embodiment of a TFT substrate structure of the present invention.
  • Figure 13 is a cross-sectional view showing a second embodiment of the TFT substrate structure of the present invention.
  • the present invention first provides a method for fabricating a TFT substrate structure, including the following steps:
  • Step 1 As shown in FIG. 3, a substrate 1 is provided on which a buffer layer 2 is deposited.
  • the substrate 1 may be a glass substrate or a plastic substrate.
  • the material of the buffer layer 2 may be silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.
  • Step 2 As shown in FIG. 4, a polysilicon (poly-Si) layer 3 is deposited on the buffer layer 2.
  • Step 3 As shown in FIG. 5, a gate insulating layer 4 is deposited on the polysilicon layer 3, and a metal layer 5 is deposited on the gate insulating layer 4.
  • the material of the gate insulating layer 4 may be silicon oxide, silicon nitride, or a combination of the two.
  • the material of the metal layer 5 may be a stacked combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).
  • Step 4 as shown in FIG. 6 and FIG. 7, the photoresist layer 6 is coated on the metal layer 5, and the photoresist layer 6 is exposed and developed through a photomask to obtain a first photoresist located in the middle.
  • the segment 61 and the two second photoresist segments 62 are spaced apart from each other on both sides of the first photoresist segment 61.
  • the first photoresist segment 61 can be obtained by using a Single Slit Mask (SSM), a Halftone Tone Mask (HTM), or a Gray Tone Mask (GTM). And two second photoresist segments 62.
  • SSM Single Slit Mask
  • HTM Halftone Tone Mask
  • GTM Gray Tone Mask
  • the distance between the first photoresist segment 61 and the two second photoresist segments 62 is less than 1 ⁇ m, and the width of the second photoresist segment 62 is 1 ⁇ m to 2 ⁇ m.
  • Step 5 as shown in FIG. 8, the first photoresist segment 61 and the two second photoresist segments 62 are used as a barrier layer, and the metal layer 5 is etched corresponding to the first photoresist segment 61.
  • a gate electrode 51 is obtained below, and two metal segments 52 are obtained corresponding to the two second photoresist segments 62 respectively.
  • the gate electrode 51 and the two metal segments 52 may be obtained by dry etching (Dry Etch) or wet etching (Wet Etch).
  • the gate electrode 51 and the two metal segments 52 are respectively formed corresponding to the first photoresist segment 61 and the two second photoresist segments 62, the two metal segments 52 and the gate are The distance between the poles 51 is less than 1 ⁇ m, and the width of the metal segments 52 is 1 ⁇ m to 2 ⁇ m.
  • the distance between the metal segment 52 and the gate electrode 51 is reduced to 1 ⁇ m or less, so that the size of the TFT substrate can be correspondingly reduced, which is advantageous for the manufacture of a small-sized device.
  • Step 6 stripping the first photoresist segment 61 and the two second photoresist segments 62 to the gate 51.
  • the two metal segments 52 are photomasks, and the polysilicon layer 3 is ion-implanted, and an undoped channel region 33 is formed on the polysilicon layer 3 corresponding to the gate electrode 51, corresponding to the trenches.
  • Four n-type heavily doped regions (n+) 31 are formed on both sides of the track region 33, and two undoped regions between the four n-type heavily doped regions 31 are formed under the two metal segments 52. District 32. Subsequent steps can be implemented using existing techniques.
  • the widths of the two n-type heavily doped regions 31 adjacent to the channel region 33 are less than 1 ⁇ m, and the width of the undoped regions 32 is 1 ⁇ m to 2 ⁇ m.
  • the n-type ion concentration in the n-type heavily doped region 31 ranges from 10 14 to 10 15 ions/cm 3 .
  • FIG. 11 is a schematic diagram of another embodiment of a method for fabricating a TFT substrate structure according to the present invention.
  • the difference is that after the photoresist layer is exposed and developed, the first photoresist segment located in the middle is respectively obtained. And four second photoresist segments spaced apart on both sides of the first photoresist segment.
  • a gate 51 is obtained under the first photoresist segment, and four metal segments 52 are respectively obtained under the four second photoresist segments, and the first photoresist segment is peeled off.
  • the gate electrode 51 and the four metal segments 52 are used as a mask, and the polysilicon layer 3 is ion-implanted, and the channel is corresponding to the channel on the polysilicon layer 3.
  • Six n-type heavily doped regions 31 are formed on both sides of the region 33, and four undoped regions 32 between the six n-type heavily doped regions 31 are formed under the four metal segments 52, and the rest are The steps are the same as those in the previous embodiment, and are not described here.
  • the number of the second photoresist segments spaced apart from each other on both sides of the first photoresist segment is not specifically limited by the embodiment of the present invention, and may be two or more;
  • the number of the plurality of n-type heavily doped regions formed on the polysilicon layer 3 on the two sides of the corresponding channel region 33 can also be adjusted according to actual needs, and is not limited by the specific number.
  • a plurality of metal segments spaced apart are formed on both sides of the gate, and the gate electrode and the plurality of metal segments are used as a mask to ion implant the polysilicon layer.
  • an n-type heavily doped region is formed on the polysilicon layer, an undoped region is formed between the n-type heavily doped regions, which increases the resistance value, disperses a strong electric field near the electrode, and avoids a local strong electric field.
  • the presence of the hot carrier effect on the device characteristics increases the operating current, simplifies the process, reduces the production cost, and reduces the size of the TFT substrate.
  • a cross-sectional view of a first embodiment of a TFT substrate structure according to the present invention includes a substrate 1 and a buffer layer 2 disposed on the substrate 1. a polysilicon layer 3 on the buffer layer 2, a gate insulating layer 4 disposed on the polysilicon layer 3, a gate electrode 51 disposed on the gate insulating layer 4, and a gate insulating layer 4 disposed on the gate insulating layer 4.
  • the two metal segments 52 are spaced apart on both sides of the gate 51.
  • the polysilicon layer 3 includes an undoped channel region 33 corresponding to the underside of the gate 51, and four n-type heavily doped regions 31 on both sides of the channel region 33, corresponding to the two Two undoped regions 32 below the metal segment 52 and between the four n-type heavily doped regions 31.
  • the distance between the two metal segments 52 and the gate 51 is less than 1 ⁇ m, and the width of the metal segments 52 is 1 ⁇ m to 2 ⁇ m.
  • the widths of the two n-type heavily doped regions 31 adjacent to the channel region 33 on the polysilicon layer 3 are less than 1 ⁇ m, and the width of the undoped regions 32 is 1 ⁇ m to 2 ⁇ m. .
  • the n-type ion concentration in the n-type heavily doped region 31 ranges from 10 14 to 10 15 ions/cm 3 .
  • the material of the buffer layer 2 and the gate insulating layer 4 is silicon oxide, silicon nitride, or a combination of the two; the material of the gate 51 and the two metal segments 52 is molybdenum, titanium, A stack combination of one or more of aluminum and copper.
  • a cross-sectional view of a second embodiment of a TFT substrate structure according to the present invention is different from the first embodiment in that four gates are formed on the gate insulating layer 4 on both sides of the gate electrode 51.
  • the four undoped regions 32 between the heavily doped regions 31 are the same as the first embodiment, and are not described herein again.
  • the number of the metal segments 52 formed on the gate insulating layer 4 on both sides of the gate 51 is not specifically limited by the embodiment of the present invention, and may be two or more;
  • the number of n-type heavily doped regions formed on the polysilicon layer 3 on both sides of the corresponding channel region 33 can also be adjusted according to actual needs, without being limited by a specific number.
  • an undoped region is formed between the n-type heavily doped regions of the polysilicon layer, thereby avoiding the generation of a local strong electric field, eliminating the influence of the hot carrier effect on the device characteristics, and having a high operating current.
  • the structure is simple and the production cost is low.
  • a plurality of metal segments spaced apart are formed on both sides of the gate electrode while the gate electrode is formed, and the gate electrode and the plurality of metal segments are used as the photomask.
  • the polysilicon layer is ion-implanted, and an n-type heavily doped region is formed in the polysilicon layer, and an undoped region is formed between the n-type heavily doped regions, which increases the resistance value and disperses a strong electric field near the electrode, thereby avoiding the cause.
  • the effect of the hot carrier effect on the device characteristics caused by the existence of a local strong electric field improves the operating current, simplifies the process, reduces the production cost, and reduces the size of the TFT substrate.
  • an undoped region is formed between the n-type heavily doped regions of the polysilicon layer, thereby avoiding the generation of a local strong electric field and eliminating the influence of the hot carrier effect on the device characteristics, and having a high Working current, simple structure and low production cost.

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  • Crystallography & Structural Chemistry (AREA)

Abstract

提供一种薄膜晶体管（TFT）基板结构的制作方法及TFT基板结构。该TFT基板结构的制作方法，在制作栅极（51）的同时，在栅极（51）两侧形成间隔分布的数个金属段（52），并以栅极（51）和数个金属段（52）作为光罩，对多晶硅层（3）进行离子注入，在多晶硅层（3）上形成n型重掺杂区（31）的同时，在n型重掺杂区（31）之间形成未掺杂区（32），增加了阻值，分散了电极附近的强电场，避免了因局部强电场的存在而发生的热载流子效应对器件特性的影响，提高了工作电流，简化了制程，降低了生产成本，减小了TFT基板的尺寸。该TFT基板结构，多晶硅层（3）的n型重掺杂区（31）之间形成有未掺杂区（32），避免了局部强电场的产生，消除了热载流子效应对器件特性的影响，具有较高的工作电流，结构简单，生产成本低。

Description

TFT基板结构的制作方法及TFT基板结构 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板结构的制作方法及TFT基板结构。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等。
通常液晶显示装置包括壳体、设于壳体内的液晶面板及设于壳体内的背光模组(Backlight module)。其中，液晶面板的结构主要是由一薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)、一彩色滤光片基板(Color Filter，CF)、以及配置于两基板间的液晶层(Liquid Crystal Layer)所构成，其工作原理是通过在两片玻璃基板上施加驱动电压来控制液晶层的液晶分子的旋转，将背光模组的光线折射出来产生画面。
随着移动显示技术在生活中的应用起到的作用越来越大，移动显示技术向更高画质、更高精细程度、更轻薄和更低功耗的方向发展，在器件上就要求尺寸越来越小，器件内部局部区域的电场强度也因此而增强，特别是在漏极附近存在强电场。载流子在强电场的作用下获得较高的能量成为热载流子。热载流子对器件性能的影响主要表现在以下两个方面：
(1)热载流子越过绝缘层注入到氧化层，不断积累，改变阈值电压，影响器件寿命；
(2)在漏极附近的耗尽区与晶格碰撞产生新的电子空穴对，以金属氧化物半导体(Metal Oxid Semiconductor，MOS)场效应晶体管为例，碰撞产生的电子形成附加的漏电流，空穴则被衬底收集，形成衬底电流，使总电流成为饱和漏电流与衬底电流之和。热载流子效应是限制器件最高工作电压的基本因素之一。
为了解决热载流子的出现对器件特性的影响，技术人员想出了各种办法来避免局部强电场的产生。请参阅图1，为一种现有的TFT基板结构的示意图，所述TFT基板结构包括基板100、设于基板100上的半导体层200、设于所述半导体层200上的源/漏极300、设于所述源/漏极300及半导体层200上的绝缘层400、及设于所述绝缘层400上的栅极500，具体的，所述 半导体层200包括对应于所述栅极500下方的沟道区210、位于所述沟道区210两侧且与所述源/漏极300相接触的两N型重掺杂区220、及位于两N型重掺杂区220与沟道区210之间的两偏移区230，由于偏移区230没有掺杂，阻值较高，可以分散电极附近的强电场，从而减少热载流子的产生，但是，该种TFT基板结构的漏电流虽然变小了，其工作电流也相应减小，导致功耗增大。
发明内容
本发明的目的在于提供一种TFT基板结构的制作方法，可以在多晶硅层形成n型重掺杂区的同时，在n型重掺杂区之间形成未掺杂区，以增加阻值，分散电极附近的强电场，避免因局部强电场的存在而发生的热载流子效应对器件特性造成影响，提高工作电流。
本发明的目的还在于提供一种TFT基板结构，多晶硅层的n型重掺杂区之间形成有未掺杂区，可避免局部强电场的产生，消除热载流子效应对器件特性的影响，提高工作电流。
为实现上述目的，本发明提供一种TFT基板结构的制作方法，包括如下步骤：
步骤1、提供基板，在所述基板上沉积缓冲层；
步骤2、在所述缓冲层上沉积多晶硅层；
步骤3、在所述多晶硅层上沉积栅极绝缘层，在所述栅极绝缘层上沉积金属层；
步骤4、在所述金属层上涂布光阻层，通过一道光罩对所述光阻层进行曝光、显影，得到位于中间的第一光阻段、及间隔分布于所述第一光阻段两侧的数个第二光阻段；
步骤5、以所述第一光阻段、及数个第二光阻段为阻挡层，对所述金属层进行蚀刻，对应所述第一光阻段下方得到栅极，分别对应所述数个第二光阻段下方得到数个金属段；
步骤6、剥离所述第一光阻段、及数个第二光阻段，以所述栅极、及数个金属段为光罩，对所述多晶硅层进行离子注入，在所述多晶硅层上对应所述栅极下方形成未掺杂的沟道区，对应所述沟道区的两侧形成数个n型重掺杂区，对应所述数个金属段下方形成位于所述数个n型重掺杂区之间的数个未掺杂区。
所述步骤4采用单缝光罩、半色调光罩、或灰阶光罩得到所述第一光阻段、及数个第二光阻段。
靠近所述第一光阻段两侧的两个第二光阻段与所述第一光阻段之间的距离均小于1μm，所述第二光阻段的宽度为1μm～2μm。
所述步骤5采用干法蚀刻或湿法蚀刻得到所述栅极、及数个金属段。
靠近所述栅极两侧的两个金属段与所述栅极之间的距离均小于1μm，所述金属段的宽度为1μm～2μm。
所述缓冲层、及栅极绝缘层的材料为氧化硅、氮化硅、或二者的组合。
所述金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
本发明还提供一种TFT基板结构的制作方法，包括如下步骤：
步骤1、提供基板，在所述基板上沉积缓冲层；
步骤2、在所述缓冲层上沉积多晶硅层；
步骤3、在所述多晶硅层上沉积栅极绝缘层，在所述栅极绝缘层上沉积金属层；
步骤4、在所述金属层上涂布光阻层，通过一道光罩对所述光阻层进行曝光、显影，得到位于中间的第一光阻段、及间隔分布于所述第一光阻段两侧的数个第二光阻段；
步骤5、以所述第一光阻段、及数个第二光阻段为阻挡层，对所述金属层进行蚀刻，对应所述第一光阻段下方得到栅极，分别对应所述数个第二光阻段下方得到数个金属段；
步骤6、剥离所述第一光阻段、及数个第二光阻段，以所述栅极、及数个金属段为光罩，对所述多晶硅层进行离子注入，在所述多晶硅层上对应所述栅极下方形成未掺杂的沟道区，对应所述沟道区的两侧形成数个n型重掺杂区，对应所述数个金属段下方形成位于所述数个n型重掺杂区之间的数个未掺杂区；
其中，所述步骤4采用单缝光罩、半色调光罩、或灰阶光罩得到所述第一光阻段、及数个第二光阻段；
其中，靠近所述第一光阻段两侧的两个第二光阻段与所述第一光阻段之间的距离均小于1μm，所述第二光阻段的宽度为1μm～2μm；
其中，所述步骤5采用干法蚀刻或湿法蚀刻得到所述栅极、及数个金属段。
本发明还提供一种TFT基板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的多晶硅层、设于所述多晶硅层上的栅极绝缘层、设于所述栅极绝缘层上的栅极、及设于所述栅极绝缘层上间隔分布于所述栅极两侧的数个金属段；
所述多晶硅层包括对应于所述栅极下方的沟道区，位于所述沟道区两 侧的数个n型重掺杂区，以及对应于所述数个金属段下方且位于所述数个n型重掺杂区之间的数个未掺杂区。
靠近所述栅极两侧的两个金属段与所述栅极之间的距离均小于1μm，所述金属段的宽度为1μm～2μm。
所述缓冲层、及栅极绝缘层的材料为氧化硅、氮化硅、或二者的组合；所述栅极、及数个金属段的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
本发明的有益效果：本发明的TFT基板结构的制作方法，在制作栅极的同时，在栅极两侧形成间隔分布的数个金属段，并以栅极和数个金属段作为光罩，对多晶硅层进行离子注入，在多晶硅层上形成n型重掺杂区的同时，在n型重掺杂区之间形成未掺杂区，增加了阻值，分散了电极附近的强电场，避免了因局部强电场的存在而发生的热载流子效应对器件特性造成的影响，提高了工作电流，简化了制程，降低了生产成本，减小了TFT基板的尺寸。本发明的TFT基板结构，多晶硅层的n型重掺杂区之间形成有未掺杂区，避免了局部强电场的产生，消除了热载流子效应对器件特性的影响，具有较高的工作电流，结构简单，生产成本低。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为一种现有的TFT基板结构的示意图；
图2为本发明的TFT基板结构的制作方法的流程图；
图3为本发明的TFT基板结构的制作方法的步骤1的示意图；
图4为本发明的TFT基板结构的制作方法的步骤2的示意图；
图5为本发明的TFT基板结构的制作方法的步骤3的示意图；
图6-7为本发明的TFT基板结构的制作方法的步骤4的示意图；
图8为本发明的TFT基板结构的制作方法的步骤5的示意图；
图9-10为本发明的TFT基板结构的制作方法的步骤6的示意图；
图11为本发明的TFT基板结构的制作方法另一种实施方式的示意图；
图12为本发明的TFT基板结构的第一实施例的剖面示意图；
图13为本发明的TFT基板结构的第二实施例的剖面示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明首先提供一种TFT基板结构的制作方法，包括如下步骤：
步骤1、如图3所示，提供基板1，在所述基板1上沉积缓冲层2。
具体地，所述基板1可以是玻璃基板或塑料基板。所述缓冲层2的材料可以是氧化硅(SiOx)、氮化硅(SiNx)、或二者的组合。
步骤2、如图4所示，在所述缓冲层2上沉积多晶硅(poly-Si)层3。
步骤3、如图5所示，在所述多晶硅层3上沉积栅极绝缘层4，在所述栅极绝缘层4上沉积金属层5。
具体地，所述栅极绝缘层4的材料可以是氧化硅、氮化硅、或二者的组合。所述金属层5的材料可以是钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
步骤4、如图6、图7所示，在所述金属层5上涂布光阻层6，通过一道光罩对所述光阻层6进行曝光、显影，得到位于中间的第一光阻段61、及间隔分布于所述第一光阻段61两侧的两个第二光阻段62。
具体地，可以采用单缝光罩(Single Slit Mask，SSM)、半色调光罩(Hakf Tone Mask，HTM)、或灰阶光罩(Gray Tone Mask，GTM)得到所述第一光阻段61、及两个第二光阻段62。
优选的，所述第一光阻段61与两个第二光阻段62之间的距离均小于1μm，所述第二光阻段62的宽度为1μm～2μm。
步骤5、如图8所示，以所述第一光阻段61、及两个第二光阻段62为阻挡层，对所述金属层5进行蚀刻，对应所述第一光阻段61下方得到栅极51，分别对应所述两个第二光阻段62下方得到两个金属段52。
具体地，可以采用干法蚀刻(Dry Etch)或湿法蚀刻(Wet Etch)得到所述栅极51、及两个金属段52。
具体的，由于所述栅极51与两个金属段52分别对应于所述第一光阻段61与两个第二光阻段62形成，因此，所述两个金属段52与所述栅极51之间的距离均小于1μm，所述金属段52的宽度为1μm～2μm。
本发明通过采用SSM/HTM/GTM光罩，将所述金属段52与栅极51之间的距离缩小为1μm以下，使得TFT基板的尺寸也能相应减小，有利于小尺寸器件的制造。
步骤6、剥离所述第一光阻段61、及两个第二光阻段62，以所述栅极 51、及两个金属段52为光罩，对所述多晶硅层3进行离子注入，在所述多晶硅层3上对应所述栅极51下方形成未掺杂的沟道区33，对应所述沟道区33的两侧形成四个n型重掺杂区(n+)31，对应所述两个金属段52下方形成位于所述四个n型重掺杂区31之间的两个未掺杂区32。后续步骤可以采用现有技术实现。
具体的，与所述沟道区33相邻的两个n型重掺杂区31的宽度均小于1μm，所述未掺杂区32的宽度为1μm～2μm。
具体的，所述n型重掺杂区31中的n型离子浓度范围为1014～1015ions/cm3。
请参阅图11，为本发明的TFT基板结构的制作方法的另一种实施方式的示意图，其不同之处在于：对光阻层进行曝光、显影后，分别得到位于中间的第一光阻段、及间隔分布于所述第一光阻段两侧的四个第二光阻段。对所述金属层进行蚀刻后，对应所述第一光阻段下方得到栅极51，分别对应所述四个第二光阻段下方得到四个金属段52，剥离所述第一光阻段、及四个第二光阻段后，以所述栅极51、及四个金属段52为光罩，对所述多晶硅层3进行离子注入，在所述多晶硅层3上对应所述沟道区33的两侧形成六个n型重掺杂区31，对应所述四个金属段52下方形成位于所述六个n型重掺杂区31之间的四个未掺杂区32，其余步骤均与上一实施方式相同，此处不再赘述。
因此，可以理解的是，所述间隔分布于第一光阻段两侧的第二光阻段的个数不受本发明实施例的具体限制，可以为两个或两个以上；从而对应的，在多晶硅层3上对应沟道区33的两侧形成的多个n型重掺杂区的数量也可以根据实际需要进行调整，不受具体数量限制。
本发明的TFT基板结构的制作方法，在制作栅极的同时，在栅极两侧形成间隔分布的数个金属段，并以栅极和数个金属段作为光罩，对多晶硅层进行离子注入，在多晶硅层上形成n型重掺杂区的同时，在n型重掺杂区之间形成未掺杂区，增加了阻值，分散了电极附近的强电场，避免了因局部强电场的存在而发生的热载流子效应对器件特性造成的影响，提高了工作电流，简化了制程，降低了生产成本，减小了TFT基板的尺寸。
本发明还提供一种TFT基板结构，请参阅图12，为本发明的TFT基板结构的第一实施例的剖面示意图，包括基板1、设于所述基板1上的缓冲层2、设于所述缓冲层2上的多晶硅层3、设于所述多晶硅层3上的栅极绝缘层4、设于所述栅极绝缘层4上的栅极51、及设于所述栅极绝缘层4上间隔分布于所述栅极51两侧的两个金属段52。
所述多晶硅层3包括对应于所述栅极51下方的未掺杂的沟道区33，位于所述沟道区33两侧的四个n型重掺杂区31，对应于所述两个金属段52下方且位于所述四个n型重掺杂区31之间的两个未掺杂区32。
优选的，所述两个金属段52与所述栅极51之间的距离均小于1μm，所述金属段52的宽度为1μm～2μm。与此相对应的，所述多晶硅层3上与所述沟道区33相邻的两个n型重掺杂区31的宽度均小于1μm，所述未掺杂区32的宽度为1μm～2μm。
具体的，所述n型重掺杂区31中的n型离子浓度范围为1014～1015ions/cm3。
具体地，所述缓冲层2、及栅极绝缘层4的材料为氧化硅、氮化硅、或二者的组合；所述栅极51、及两个金属段52的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
请参阅图13，为本发明的TFT基板结构的第二实施例的剖面示意图，与第一实施例的区别在于，所述栅极绝缘层4上于所述栅极51两侧形成有四个金属段52，所述多晶硅层3上对应所述沟道区33的两侧形成有六个n型重掺杂区31，对应所述四个金属段52下方形成有位于所述六个n型重掺杂区31之间的四个未掺杂区32，其余结构均与第一实施例相同，此处不再赘述。
因此，可以理解的是，所述栅极绝缘层4上于栅极51两侧形成的金属段52的个数不受本发明实施例的具体限制，可以为两个或两个以上；从而对应的，在多晶硅层3上对应沟道区33的两侧形成的n型重掺杂区的数量也可以根据实际需要进行调整，不受具体数量限制。
上述TFT基板结构，多晶硅层的n型重掺杂区之间形成有未掺杂区，避免了局部强电场的产生，消除了热载流子效应对器件特性的影响，具有较高的工作电流，结构简单，生产成本低。
综上所述，本发明的TFT基板结构的制作方法，在制作栅极的同时，在栅极两侧形成间隔分布的数个金属段，并以栅极和数个金属段作为光罩，对多晶硅层进行离子注入，在多晶硅层形成n型重掺杂区的同时，在n型重掺杂区之间形成未掺杂区，增加了阻值，分散了电极附近的强电场，避免了因局部强电场的存在而发生的热载流子效应对器件特性造成的影响，提高了工作电流，简化了制程，降低了生产成本，减小了TFT基板的尺寸。本发明的TFT基板结构，多晶硅层的n型重掺杂区之间形成有未掺杂区，避免了局部强电场的产生，消除了热载流子效应对器件特性的影响，具有较高的工作电流，结构简单，生产成本低。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (14)

  1. 一种TFT基板结构的制作方法，包括如下步骤：
    步骤1、提供基板，在所述基板上沉积缓冲层；
    步骤2、在所述缓冲层上沉积多晶硅层；
    步骤3、在所述多晶硅层上沉积栅极绝缘层，在所述栅极绝缘层上沉积金属层；
    步骤4、在所述金属层上涂布光阻层，通过一道光罩对所述光阻层进行曝光、显影，得到位于中间的第一光阻段、及间隔分布于所述第一光阻段两侧的数个第二光阻段；
    步骤5、以所述第一光阻段、及数个第二光阻段为阻挡层，对所述金属层进行蚀刻，对应所述第一光阻段下方得到栅极，分别对应所述数个第二光阻段下方得到数个金属段；
    步骤6、剥离所述第一光阻段、及数个第二光阻段，以所述栅极、及数个金属段为光罩，对所述多晶硅层进行离子注入，在所述多晶硅层上对应所述栅极下方形成未掺杂的沟道区，对应所述沟道区的两侧形成数个n型重掺杂区，对应所述数个金属段下方形成位于所述数个n型重掺杂区之间的数个未掺杂区。
  2. 如权利要求1所述的TFT基板结构的制作方法，其中，所述步骤4采用单缝光罩、半色调光罩、或灰阶光罩得到所述第一光阻段、及数个第二光阻段。
  3. 如权利要求1所述的TFT基板结构的制作方法，其中，靠近所述第一光阻段两侧的两个第二光阻段与所述第一光阻段之间的距离均小于1μm，所述第二光阻段的宽度为1μm～2μm。
  4. 如权利要求1所述的TFT基板结构的制作方法，其中，所述步骤5采用干法蚀刻或湿法蚀刻得到所述栅极、及数个金属段。
  5. 如权利要求1所述的TFT基板结构的制作方法，其中，靠近所述栅极两侧的两个金属段与所述栅极之间的距离均小于1μm，所述金属段的宽度为1μm～2μm。
  6. 如权利要求1所述的TFT基板结构的制作方法，其中，所述缓冲层、及栅极绝缘层的材料为氧化硅、氮化硅、或二者的组合。
  7. 如权利要求1所述的TFT基板结构的制作方法，其中，所述金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
  8. 一种TFT基板结构的制作方法，包括如下步骤：
    步骤1、提供基板，在所述基板上沉积缓冲层；
    步骤2、在所述缓冲层上沉积多晶硅层；
    步骤3、在所述多晶硅层上沉积栅极绝缘层，在所述栅极绝缘层上沉积金属层；
    步骤4、在所述金属层上涂布光阻层，通过一道光罩对所述光阻层进行曝光、显影，得到位于中间的第一光阻段、及间隔分布于所述第一光阻段两侧的数个第二光阻段；
    步骤5、以所述第一光阻段、及数个第二光阻段为阻挡层，对所述金属层进行蚀刻，对应所述第一光阻段下方得到栅极，分别对应所述数个第二光阻段下方得到数个金属段；
    步骤6、剥离所述第一光阻段、及数个第二光阻段，以所述栅极、及数个金属段为光罩，对所述多晶硅层进行离子注入，在所述多晶硅层上对应所述栅极下方形成未掺杂的沟道区，对应所述沟道区的两侧形成数个n型重掺杂区，对应所述数个金属段下方形成位于所述数个n型重掺杂区之间的数个未掺杂区；
    其中，所述步骤4采用单缝光罩、半色调光罩、或灰阶光罩得到所述第一光阻段、及数个第二光阻段；
    其中，靠近所述第一光阻段两侧的两个第二光阻段与所述第一光阻段之间的距离均小于1μm，所述第二光阻段的宽度为1μm～2μm；
    其中，所述步骤5采用干法蚀刻或湿法蚀刻得到所述栅极、及数个金属段。
  9. 如权利要求8所述的TFT基板结构的制作方法，其中，靠近所述栅极两侧的两个金属段与所述栅极之间的距离均小于1μm，所述金属段的宽度为1μm～2μm。
  10. 如权利要求8所述的TFT基板结构的制作方法，其中，所述缓冲层、及栅极绝缘层的材料为氧化硅、氮化硅、或二者的组合。
  11. 如权利要求8所述的TFT基板结构的制作方法，其中，所述金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
  12. 一种TFT基板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的多晶硅层、设于所述多晶硅层上的栅极绝缘层、设于所述栅极绝缘层上的栅极、及设于所述栅极绝缘层上且间隔分布于所述栅极两侧的数个金属段；
    所述多晶硅层包括对应于所述栅极下方的沟道区，位于所述沟道区两 侧的数个n型重掺杂区，以及对应于所述数个金属段下方且位于所述数个n型重掺杂区之间的数个未掺杂区。
  13. 如权利要求12所述的TFT基板结构，其中，靠近所述栅极两侧的两个金属段与所述栅极之间的距离均小于1μm，所述金属段的宽度为1μm～2μm。
  14. 如权利要求12所述的TFT基板结构，其中，所述缓冲层、及栅极绝缘层的材料为氧化硅、氮化硅、或二者的组合；所述栅极、及数个金属段的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
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