WO2016194591A1 - Ultrasonic transducer and ultrasonic inspection device - Google Patents

Abstract

In a capacitive-detection-type ultrasonic transducer, variation in the film thickness of a membrane of each cell in a cell array of the ultrasonic transducer causes the device characteristics of cells in the cell array to be nonuniform. Provided is an ultrasonic transducer provided with a CMUT chip 301 including a cell array region CAR in which a plurality of cells are formed and a peripheral region PER adjoining the cell array region CAR, wherein a beam structure 201 is disposed in the cell array region CAR, and a plurality of pattern structures 311 corresponding to the beam structure 201 are disposed in the peripheral region PER. This reduces the difference between the unit surface area of the cell array region CAR and the unit surface area of the peripheral region PER. As a result, it is possible to improve uniformity in the film thickness of an insulating film covering the beam structure 201 and the pattern structures 311.

Description

Ultrasonic transducer and ultrasonic inspection device

The present invention relates to an ultrasonic transducer, a manufacturing technique thereof, and an ultrasonic inspection apparatus, for example, an ultrasonic transducer manufactured by a MEMS (Micro Electro Mechanical Systems) technique and a technique effective when applied to the manufacturing technique.

Ultrasonic transducers are used for various purposes such as diagnosis of tumors in the human body and inspection of cracks in buildings by transmitting and receiving ultrasonic waves.

Up to now, ultrasonic transducers using the vibration of piezoelectric materials have been used, but due to the recent advancement of MEMS technology, a capacitive detection type ultrasonic transducer (CMUT: Capacitive) in which a vibration part is fabricated on a silicon substrate. Micromachined (Ultrasonic Transducer) has been actively developed for practical use.

This CMUT has advantages such as a wider frequency band of ultrasonic waves that can be used or higher sensitivity than conventional ultrasonic transducers using piezoelectric materials. In addition, since it can be manufactured using LSI processing technology, there is an advantage that fine processing is possible.

For example, Patent Document 1 and Patent Document 2 describe CMUTs in which dummy cells are arranged on the outer periphery of a CMUT cell array so as to equalize membrane distortion or device characteristics. Patent Document 3 describes a CMUT in which a beam structure (“embossed structure”, “beam structure”) is arranged on a CMUT membrane to adjust the resonance frequency of the membrane.

JP 2010-172181 A International Publication No. 2008/136198 US Pat. No. 8,483,014

Usually, a semiconductor chip on which a CMUT is formed has a cell array region in which a plurality of cells are formed, and a peripheral region that is in contact with the cell array region and formed outside the cell array region. At this time, since a plurality of cells are formed in the cell array region, the flatness may be low. On the other hand, normally, no cells are formed in the peripheral region and the flatness is high. For this reason, a large difference in surface area occurs between the cell array region and the peripheral region. Here, for example, a passivation film (surface protective film) is formed on the uppermost layer of the CMUT in order to suppress the intrusion of moisture and foreign matter into the cell. Depending on the nature, there may be a difference in film thickness. Therefore, there is a difference between the thickness of the passivation film in the cell array region and the thickness of the passivation film in the peripheral region. As a result, the thickness of the passivation film in the central portion of the cell array region and the edge of the cell array region are different. A difference occurs in the thickness of the passivation film. Thereby, in CMUT, the film thickness variation of each membrane of the plurality of cells formed in the cell array region occurs. For this reason, device characteristics (for example, sensitivity) between a plurality of cells formed in the cell array region become non-uniform.

An object of the present invention is to improve uniformity of device characteristics among a plurality of cells by suppressing variations in the film thickness of the membrane in the plurality of cells constituting the CMUT.

Other issues and novel features will become clear from the description of the present specification and the accompanying drawings.

An ultrasonic transducer according to an embodiment includes a semiconductor chip including a cell array region in which a plurality of cells are formed and a peripheral region in contact with the cell array region. Each of the plurality of cells is formed on the substrate, the first electrode formed on the substrate, the first insulating film formed on the first electrode, the first insulating film, and in the plan view. A cavity overlapping with the one electrode; and a second insulating film formed on the cavity. Furthermore, each of the plurality of cells is formed on the second insulating film and overlaps the cavity in plan view, a third insulating film formed on the second electrode, and a third insulating film A beam structure that is formed above and overlaps the cavity in plan view, and a fourth insulation that covers the beam structure (“embossed 構造 structure”, “beam structure”) and is formed on the third insulating film And a membrane. Here, in the peripheral region, there are a third insulating film, a plurality of pattern structures formed on the third insulating film and corresponding to a beam structure, and a fourth insulating film covering the plurality of pattern structures. Is formed.

In addition, an ultrasonic inspection apparatus according to an embodiment is configured to contact an object and transmit an ultrasonic wave from the ultrasonic probe that transmits and receives an ultrasonic wave to and from the object. In addition, a transmission unit that supplies a drive signal to the ultrasonic probe and a reception unit that receives a reflected echo signal output from the ultrasonic probe that has received the ultrasonic wave are provided. Then, the ultrasonic inspection apparatus electrically connects the image processing unit that generates an image based on the reflected echo signal and the ultrasonic probe and the transmission unit while transmitting the ultrasonic wave, while receiving the ultrasonic wave. In some cases, a transmission / reception separating unit that switches a connection path so as to electrically connect the ultrasonic probe and the receiving unit is provided. Here, the ultrasonic probe includes the ultrasonic transducer that is electrically connected to the transmission / reception separating unit and configured as described above.

According to one embodiment, it is possible to suppress membrane thickness variations in a plurality of cells constituting the CMUT. As a result, according to one embodiment, it is possible to improve the uniformity of device characteristics among a plurality of cells.

It is sectional drawing which shows the structural example of basic CMUT. It is sectional drawing which shows the structural example of CMUT by which the beam structure was provided in the membrane. 4 is a plan view showing a schematic layout configuration example of a CMUT chip in the first embodiment. FIG. It is an enlarged view which expands and shows the partial area | region shown in FIG. FIG. 5 is a cross-sectional view taken along line AA in FIG. 4. FIG. 4 is a cross-sectional view taken along line BB in FIG. 3. FIG. 4 is a cross-sectional view taken along the line CC in FIG. 3. FIG. 4 is a cross-sectional view taken along line DD in FIG. 3. FIG. 6 is a cross-sectional view showing a CMUT manufacturing process in the first embodiment. FIG. 10 is a cross-sectional view showing a manufacturing step of the CMUT following FIG. 9. FIG. 11 is a cross-sectional view showing a manufacturing step of the CMUT following FIG. 10. FIG. 12 is a cross-sectional view showing a manufacturing step of the CMUT following FIG. 11. FIG. 13 is a cross-sectional view showing a manufacturing step of the CMUT following FIG. FIG. 14 is a cross-sectional view showing a manufacturing step of the CMUT following FIG. 13. FIG. 15 is a cross-sectional view showing a manufacturing step of the CMUT following FIG. 14. FIG. 16 is a cross-sectional view showing a manufacturing step of the CMUT following FIG. 15. FIG. 17 is a cross-sectional view showing a manufacturing step of the CMUT following FIG. 16. FIG. 18 is a cross-sectional view showing a manufacturing step of the CMUT following FIG. 17. FIG. 19 is a cross-sectional view showing a manufacturing step of the CMUT following FIG. 18. FIG. 10 is a plan view illustrating a schematic layout configuration example of a CMUT chip in Modification 1; FIG. 11 is a plan view showing a schematic layout configuration example of a CMUT chip in Modification 2. FIG. 10 is a plan view showing a schematic layout configuration example of a CMUT chip in Modification 3. FIG. 6 is a plan view showing a main surface of a semiconductor wafer in a second embodiment. It is an enlarged view which expands and shows the partial area | region shown in FIG. It is an enlarged view which expands and shows the other partial area | region shown in FIG. It is a figure which expands and shows a partial area | region after cut | disconnecting the scribe area | region of a semiconductor wafer by a dicing process. It is a figure which expands and shows the other partial area | region after cut | disconnecting the scribe area | region of a semiconductor wafer by a dicing process. 6 is a block diagram illustrating an exemplary configuration of an ultrasonic inspection apparatus according to Embodiment 3. FIG.

In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

In all the drawings for explaining the embodiments, the same members are, in principle, given the same reference numerals, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
<Basic structure and operation of CMUT>
The basic structure and operation of the CMUT will be described with reference to FIG. FIG. 1 shows a cross-sectional structure of one basic CMUT cell. A lower electrode 102 is formed above the substrate 101 via an insulating film 104a, and a cavity 103 surrounded by an insulating film 104b is formed above the lower electrode 102. A membrane 106 is disposed by the upper insulating film 104 b and the upper electrode 105 in the cavity 103.

When a DC voltage and an AC voltage are superimposed between the upper electrode 105 and the lower electrode 102, an electrostatic force acts between the upper electrode 105 and the lower electrode 102, and the membrane 106 vibrates at the frequency of the AC voltage applied. Send ultrasonic waves. At this time, an ultrasonic wave can be transmitted efficiently by applying an alternating voltage having a frequency close to the resonance frequency of the membrane 106.

When receiving ultrasonic waves, the membrane 106 vibrates due to the pressure of the ultrasonic waves that reach the surface of the membrane 106. Then, since the distance between the upper electrode 105 and the lower electrode 102 changes, ultrasonic waves can be detected as a change in capacitance. Also at this time, ultrasonic waves having a frequency close to the resonance frequency of the membrane 106 can be received efficiently.

The ultrasonic transmission efficiency and the reception efficiency are also related to the DC voltage applied between the upper electrode 105 and the lower electrode 102. As the DC voltage applied between the upper electrode 105 and the lower electrode 102 is increased, the reaction force by the spring of the membrane 106 and the electrostatic force between the upper electrode 105 and the lower electrode 102 maintain an equilibrium state. A phenomenon that the hollow portion 103 is crushed occurs. The DC voltage when this phenomenon occurs is called a pull-in voltage. The closer the DC voltage applied between the upper electrode 105 and the lower electrode 102 is to the pull-in voltage, the higher the conversion efficiency between vibration energy and electric energy of the CMUT membrane 106. Therefore, it is important from the viewpoint of improving the transmission efficiency and reception efficiency of ultrasonic waves by the CMUT that the DC voltage applied when using the CMUT is as close as possible to the pull-in voltage. That is, the CMUT drive voltage is determined based on the pull-in voltage.

<Examination of improvement>
As is clear from the operation principle described above, the resonance frequency and the pull-in voltage of the CMUT membrane 106 are important parameters when designing and using the CMUT. Resonance frequency (F) and pull-in voltage (V) are both F∝t / w ² and V∝t ^1.5 / w between membrane width w (cavity width) and film thickness t. It is necessary to produce the width w and the film thickness t as designed as the equation holds. In particular, a MEMS device such as a CMUT has a great influence on device characteristics, and thus requires more control than when manufacturing an ordinary LSI.

When a large number of CMUT chips (semiconductor chips) are produced on a semiconductor wafer using a semiconductor wafer (silicon wafer) which is a semiconductor substrate, the width w and the thickness t of the membrane 106 of all the CMUT cells in the semiconductor wafer. It is important to suppress the variation in the cell as much as possible and to make the cell device characteristics such as the resonance frequency and the pull-in voltage of each CMUT cell uniform.

As described above, since the CMUT is manufactured using LSI processing technology, the width w of the membrane 106 is determined by the accuracy of the lithography process for forming the pattern of the sacrificial layer that becomes the mold of the cavity 103. According to LSI lithography technology, even if a large number of CMUT cells are formed on a semiconductor wafer, the width w of the membrane by the lithography process, that is, the variation width of the sacrificial layer is very small, and the width w of the membrane is uniform. Can be produced.

On the other hand, the thickness t of the membrane 106 is determined by the film formation process of each film constituting the membrane 106, in FIG. 1, the film formation process of the insulating film 104 b and the upper electrode 105 above the cavity 103. Therefore, in order to uniformly manufacture the device characteristics of a large number of CMUT cells on a cell array or a semiconductor wafer, the thickness of each film constituting the membrane 106 of each CMUT cell is controlled, It is important to make the thickness of the membrane 106 uniform in the cell array and the semiconductor wafer.

When the insulating film constituting the membrane 106 is formed by CVD (Chemical Vapor Deposition), the film thickness on the pattern varies depending on the pattern density (pattern unit surface area) on the semiconductor wafer on which the film is formed. There is. This is called a loading effect, and occurs when the film formation mechanism in the CVD method is rate-controlled by the supply of the reaction gas. In particular, in the plasma CVD method, deposition species are formed by collision of gas molecules and electrons in the plasma, and these are deposited on the surface of the pattern, so that a loading effect is likely to occur. Therefore, when the pattern density is different between the cell array and the outer area, the thickness of the film formed at the center and the outer periphery of the array is different. As a result, the device characteristics of each CMUT cell in the cell array are different. Can be non-uniform.

FIG. 2 is a cross-sectional view of a CMUT showing, for example, a simplified structure in which the beam structure 201 is disposed on the insulating film 104b. In FIG. 2, the membrane 106 is constituted by the insulating film 104 b, the upper electrode 105, and the beam structure 201. This beam structure 201 has a function of increasing the vibration of the membrane 106 in the thickness direction of the membrane 106, in other words, a function of causing the membrane 106 to perform piston-like vibration, compared to the case where the beam structure 201 does not exist. By providing this beam structure 201, the transmission / reception efficiency of ultrasonic waves in the CMUT can be improved. Moreover, since the thickness t of the membrane 106 can be adjusted by providing the beam structure 201, an advantage that the resonance frequency and the pull-in voltage of the membrane 106 can be adjusted can be obtained.

However, as shown in FIG. 2, the beam structure 201 has a convex shape, and when the beam structure 201 is provided on the insulating film 104b, a large convex step is generated on the insulating film 104b. Become. In the case where such a beam structure 201 in which a large step is generated in the membrane 106 exists, the surface area of the membrane 106 is increased as compared with the CMUT cell as shown in FIG. It will be.

Therefore, in particular, in the CMUT provided with the beam structure 201, there is a large difference in surface area between the inside of the cell array and the region where the CMUT cells in the outer region (peripheral region) of the cell array that is normally flat are not arranged. Occurs. For this reason, in the CMUT provided with the beam structure 201, a loading effect is likely to occur when an insulating film (passivation film, surface protective film) is formed so as to cover the beam structure 201. As a result, the thickness of the insulating film formed at the center of the cell array and the outer periphery of the array becomes particularly large, which increases the possibility that the device characteristics of each CMUT cell in the cell array become non-uniform. Become.

Therefore, in the first embodiment, a contrivance is made to suppress the film thickness variation of the membrane 106 in a plurality of CMUT cells (particularly, each CMUT cell in which the beam structure 201 is formed) constituting the CMUT. That is, in the first embodiment, a device for suppressing the film thickness variation of the membrane 106 and improving the uniformity of device characteristics among a plurality of CMUT cells is provided. Hereinafter, the technical idea of the first embodiment in which this device is applied will be described.

<Configuration of CMUT in Embodiment 1>
The basic idea of the first embodiment is to improve the uniformity of the device characteristics of the CMUT by suppressing variations in the membrane thickness in the cell array, and to configure the constituent elements that constitute the CMUT cell in the region excluding the cell array. This is realized by arranging and making the membrane thickness of each CMUT cell in the cell array uniform.

Specifically, in the first embodiment, in the semiconductor chip in which the cell array is formed, a plurality of pattern structures corresponding to the beam structure constituting the CMUT cell are in contact with the cell array region in which the plurality of CMUT cells are formed. By disposing in the region, variation in the film thickness of the membrane of each CMUT cell in the cell array is suppressed, thereby realizing uniform device characteristics of each CMUT cell.

FIG. 3 is a top view showing a semiconductor chip (hereinafter referred to as a CMUT chip 301) on which the cell array according to the first embodiment is formed. FIG. 3 shows an example of a CMUT cell in which the cavity 103 has a hexagonal shape when viewed from the upper surface of the CMUT chip 301. Ninety-seven CMUT cells constitute a cell array 310 indicated by a one-dot chain line. Further, CMUT cells are connected in parallel by wiring 304 connecting the upper electrode 105 in units of 15 and are connected to a plug 306 for supplying power to the upper electrode 105 via a lead wiring 305 from the upper electrode 105. One CMUT cell channel is configured. In FIG. 3, a total of six rows of CMUT cell channels are arranged on the lower electrode 102. The lower electrode 102 is connected to a plug 303 for supplying power to the lower electrode 102 via an extraction wiring 302 of the lower electrode 102. The pattern structure 311 is a structure corresponding to the beam structure 201 of the CMUT cell, and is arranged in a peripheral region outside the cell array region. Each CMUT cell includes a cavity portion 103 disposed on the lower electrode 102, an upper electrode 105 disposed on the cavity portion 103, a beam structure 201 constituting a part of the membrane, and the like.

FIG. 4 is an enlarged top view of the area AR in FIG. As shown in FIG. 4, the CMUT cell is provided with an etching hole 401 for forming the cavity 103. That is, the etching hole 401 is connected to the cavity 103. An insulating film made of a silicon oxide film is formed so as to cover the lower electrode 102 between the lower electrode 102 and the cavity 103, and a silicon oxide film is also formed between the upper electrode 105 and the cavity 103. Although an insulating film is formed, FIG. 4 is not shown to show the cavity 103 and the lower electrode 102.

FIG. 5 shows a cross-sectional view taken along line AA in FIG. As shown in FIG. 5, the lower electrode 102 of the CMUT cell is disposed on an insulating film 502 made of a silicon oxide film formed on a semiconductor substrate 501. A cavity 103 is disposed on the lower electrode 102 via an insulating film 503 made of a silicon oxide film. An insulating film 504 made of a silicon oxide film is disposed so as to surround the cavity 103, and the upper electrode 105 and a lead wiring 305 from the upper electrode 105 are disposed on the insulating film 504. An insulating film 505 made of a silicon nitride film and an insulating film 506 made of a silicon oxide film are disposed on the upper electrode 105 and the lead-out wiring 305 from the upper electrode 105. The insulating film 504 and the insulating film 505 are formed with etching holes 401 penetrating these films, and the etching holes 401 are filled with the insulating film 506. The etching hole 401 is formed to form the cavity 103. On the upper layer of the insulating film 506, the beam structure 201 is arranged at a position included in the cavity 103 as viewed from the upper surface of the main surface of the semiconductor substrate 501, and overlaps with the lead wiring 305 from the upper electrode 105. A pattern structure 311 is disposed in a peripheral region outside the cell array region. Further, an insulating film 507 made of a silicon nitride film is disposed on the insulating film 506 so as to cover the beam structure 201 and the pattern structure 311. The insulating film 504, the insulating film 505, the insulating film 506, the insulating film 507, the upper electrode 105, and the beam structure 201 arranged in the upper layer of the cavity 103 constitute the membrane 106 of the CMUT cell.

FIG. 6 shows a cross-sectional view taken along line BB in FIG. In FIG. 6, the pattern structure 311 arranged in the peripheral region outside the cell array region is arranged in an upper layer of the extraction wiring 302 from the lower electrode 102, and the extraction wiring 305 and the cavity 103 from the upper electrode 105 and the upper electrode 105. However, the structure is such that there is no interposition between the lead wiring 302 from the lower electrode 102 and the pattern structure 311.

FIG. 7 shows a cross-sectional view taken along the line CC of FIG. Reference numeral 701 denotes an end face of the CMUT chip 301. In FIG. 7, in the lower layer of the pattern structure 311 arranged in the peripheral region outside the cell array region, a lower electrode 102, a lead wiring 302 from the lower electrode 102, a lead wiring 305 from the upper electrode 105 or the upper electrode 105, a cavity The part 103 does not exist. That is, only the insulating film (insulating films 502 to 506) is interposed between the semiconductor substrate 501 and the pattern structure 311.

FIG. 8 shows a cross-sectional view taken along the line DD in FIG. In FIG. 8, the pattern structure 311 arranged in the peripheral region outside the cell array region is arranged between the plug 306 and the end surface 701 of the CMUT chip.

As described above, the CMUT according to the first embodiment includes, for example, a CMUT chip including a cell array region CAR in which a plurality of CMUT cells are formed and a peripheral region PER in contact with the cell array region CAR, as shown in FIG. 301 (semiconductor chip).

Each of the plurality of CMUT cells is formed on the lower electrode 102 and the lower electrode 102 formed on the semiconductor substrate 501 with the semiconductor substrate 501 and the insulating film 502 interposed therebetween as shown in FIG. The insulating film 503 is formed, and the cavity 103 is formed on the insulating film 503 and overlaps the lower electrode 102 in plan view. Further, as shown in FIG. 5, each of the plurality of CMUT cells includes an insulating film 504 formed on the cavity 103 and an upper electrode formed on the insulating film 504 and overlapping the cavity 103 in plan view. 105, and an insulating film 505 and an insulating film 506 formed over the upper electrode 105. Each of the plurality of CMUT cells is formed on the insulating film 506 and overlaps the cavity 103 in plan view, and covers the beam structure 201 and is formed on the insulating film 506. And an insulating film 507. Here, in the CMUT cell according to the first embodiment, as shown in FIG. 5, the membrane 106 is formed by the insulating films 504 to 507, the upper electrode 105, and the beam structure 201 arranged on the cavity 103. Will be. In particular, in the first embodiment, the thickness of the beam structure 201 is configured to be approximately equal to or greater than the combined thickness of the insulating films 504 to 506 and the upper electrode 105, for example. The beam structure 201 has the largest aspect ratio indicated by the thickness / width among the components constituting the CMUT cell.

On the other hand, as shown in FIG. 5, insulating films 502 to 506 are stacked on the semiconductor substrate 501 in the peripheral region, and the insulating film 506 corresponds to the beam structure 201 that is a component of the CMUT cell. A pattern structure 311 is formed, and an insulating film 507 is formed so as to cover the pattern structure 311. That is, as shown in FIG. 5, the beam structure 201 is formed in the CMUT cell, and the pattern structure 311 corresponding to the beam structure 201 is formed in the peripheral region. That is, in the CMUT cell, the pattern structure 311 is formed so as to protrude from the insulating film 506 in the peripheral region as the beam structure 201 protruding from the insulating film 506 is formed. Has been. That is, a convex shape is formed on the insulating film 506 by each of the beam structure 201 and the pattern structure 311.

In particular, in the first embodiment, the pattern structure 311 and the beam structure 201 are formed, for example, by processing a silicon nitride film, whereby the pattern structure 311 and the beam structure 201 are: It is formed from the same material. Further, although not limited thereto, for example, the pattern structure 311 has substantially the same structure as the beam structure 201.

Next, as shown in FIG. 3, a beam structure 201 is formed in each of the plurality of CMUT cells formed in the cell array region CAR, and the plurality of CMUT cells themselves are regularly arranged. Therefore, the beam structure 201 which is a constituent element of the CMUT cell is also arranged in a regular arrangement pattern. In the first embodiment, as shown in FIG. 3, a plurality of pattern structures 311 corresponding to the beam structures 201 are arranged almost regularly in the peripheral region PER. Specifically, in the peripheral region PER, a plurality of pattern structures 311 are arranged in an arrangement pattern substantially equal to the arrangement pattern of the beam structures 201. In other words, at least a part of the arrangement pattern of the plurality of pattern structures 311 is equal to the arrangement pattern of the plurality of beam structures 201.

That is, as shown in FIG. 3, in the peripheral region PER, the lead wiring 302 electrically connected to the lower electrode 102, the plug 303 electrically connected to the lead wiring 302, and the upper electrode 105 are electrically connected. A lead wire 305 connected to the lead wire 305 and a plug 306 electrically connected to the lead wire 305 are formed. Therefore, since the plurality of pattern structures 311 need to be arranged at positions that do not overlap the plug 303 and the plug 306 in plan view, the plurality of pattern structures 311 are completely equal to the arrangement pattern of the beam structure 201. It cannot be arranged.

However, as shown in FIG. 3, a part of the plurality of pattern structures 311 can be arranged at a position overlapping the lead-out wiring 302 in plan view, and a part of the plurality of pattern structures 311 is a plane. In view, it can be arranged at a position overlapping the lead wiring 305. This is because, as shown in FIGS. 5 and 6, in the thickness direction of the semiconductor substrate 501, the extraction wiring 305 is disposed below the pattern structure 311, and the extraction wiring 302 is disposed below the pattern structure 311. Because it is.

Further, in FIG. 3, the peripheral region PER is divided into a first lead region in which the lead wiring 302 and the plug 303 are formed, a second lead region in which the lead wiring 305 and the plug 306 are formed, and an outer region of the first lead region. The first outer edge region is divided into the second outer edge region which is the outer region of the second lead-out region. In this case, as shown in FIG. 3, the pattern structure 311 is formed not only in the first extraction region and the second extraction region, but also in the first outer edge region and the second outer edge region. As described above, the CMUT in the first embodiment is configured.

<Characteristics in Embodiment 1>
Next, feature points in the first embodiment will be described. For example, as shown in FIG. 3, a feature point in the first embodiment is that a pattern structure 311 corresponding to a beam structure 201 which is a component constituting a CMUT cell is formed in a peripheral region PER outside the cell array region CAR. Are arranged at a pitch substantially equal to the cell pitch of the cell array. That is, in the first embodiment, the CMUT excluding the region where the plug 306 for supplying power to the upper electrode 105 is formed and the region where the plug 303 for supplying power to the lower electrode 102 is formed. A pattern structure 311 is arranged in the peripheral region PER of the chip 301. In other words, the feature point of the first embodiment is that the peripheral structure PER provided outside the cell array region CAR is provided with the pattern structure 311 corresponding to the beam structure 201 of the CMUT cell, and at least a plurality of pattern structures 311 are provided. This is because a part of the arrangement pattern of the pattern structure 311 is arranged to be equal to the arrangement pattern of the plurality of beam structures 201. By adopting such a configuration, it is possible to suppress variations in the thickness of the membrane between the CMUT cells in the cell array, thereby making it possible to make the device characteristics of all the CMUT cells in the cell array uniform. .

That is, when the pattern structure 311 corresponding to the beam structure 201 constituting the CMUT cell is not disposed in the peripheral region PER outside the cell array region CAR, the convex beam structure 201 is formed on the surface of the cell array region CAR. Is disposed, the surface of the peripheral region PER is relatively flat. As a result, a large difference in surface area occurs between the cell array region CAR and the peripheral region PER. When such a large difference in surface area occurs, when the film formation process is performed by the CVD method after forming the convex beam structure 201 (in FIG. 5, the insulating film 507), due to the loading effect based on the difference in surface area, Depending on the difference in surface area, the thickness of the insulating film that is gradually deposited increases from the center of the cell array region CAR toward the end of the peripheral region PER. As a result, the device characteristics of the CMUT cell arranged at the center of the cell array region CAR and the CMUT cell arranged at the outer periphery of the cell array region CAR become non-uniform. That is, the resonance frequency and the pull-in voltage are higher in the CMUT cell disposed in the outer peripheral portion of the cell array region CAR having a larger film thickness than in the CMUT cell disposed in the center portion of the cell array region CAR having a small film thickness. In this state, it is not possible to efficiently transmit and receive ultrasonic waves at a desired frequency designed by all CMUT cells, and the sensitivity differs within and among the channels of each CMUT cell. This means that the sensitivity of the CMUT chip 301 is lowered.

As described above, making the DC voltage applied to the CMUT cell as equal as possible to the CMUT cell pull-in voltage leads to an improvement in sensitivity. However, if the pull-in voltage of each CMUT cell in the cell array is different, the DC voltage to be applied is different. Needs to be determined based on the CMUT cell having the lowest pull-in voltage among the plurality of CMUT cells in the cell array. This is because when a CMUT cell having a relatively high pull-in voltage in the cell array is used as a reference and a DC voltage close to the pull-in voltage is applied to all CMUT cells in the cell array, the CMUT cell having a low pull-in voltage is pulled in. This is because it may not contribute to the transmission and reception of ultrasonic waves. Conversely, even when the DC voltage to be applied is determined based on the CMUT cell having the lowest pull-in voltage among the plurality of CMUT cells in the cell array, the CMUT cell having a relatively high pull-in voltage in the cell array Since the applied DC voltage is a low voltage as seen from the pull-in voltage of the CMUT cell, the sensitivity is lowered.

On the other hand, in the first embodiment, the pattern structure 311 having a relatively large step (convex shape) corresponding to the beam structure 201 constituting the CMUT cell in the peripheral region PER outside the cell array region CAR. Arrangement pitches are approximately equal to the arrangement pitch of the plurality of CMUT cells. Thus, according to the first embodiment, the difference between the surface area in the peripheral region PER in which the plurality of pattern structures 311 is formed and the surface area in the cell array region CAR in which the plurality of beam structures 201 are formed is When the plurality of pattern structures 311 are not formed in the PER, the difference is smaller than the difference between the surface area in the peripheral region PER and the surface area in the cell array region CAR in which the plurality of beam structures 201 are formed. As a result, it is possible to prevent a large difference in surface area between the central portion of the cell array region CAR and the outer periphery of the cell array region CAR. Therefore, the CVD method is performed after the beam structure 201 and the pattern structure 311 are formed. Even if the film formation is performed, the insulating film deposited on the central portion of the cell array region CAR and the outer peripheral portion of the cell array region CAR can be made uniform. Therefore, the device characteristics such as the resonance frequency and the pull-in voltage become uniform between the CMUT cell arranged at the center of the cell array region CAR and the CMUT cell arranged at the outer periphery of the cell array region CAR. It is possible to transmit and receive good ultrasonic waves.

In particular, in the first embodiment, a structure corresponding to the beam structure 201 that is a component of the CMUT cell is adopted as the pattern structure 311 arranged in the peripheral region PER. This is due to the following reason. That is, the beam structure 201 is a structure having the largest aspect ratio (thickness / width) among the components constituting the CMUT cell. That is, a structure having a large aspect ratio is a structure in which the convex shape protrudes most, and contributes most to an increase in surface area. In other words, since the surface area of the cell array region CAR is increased by the beam structure 201 having the largest aspect ratio, the pattern structure 311 corresponding to the beam structure 201 having the largest aspect ratio is provided in the peripheral region PER. Otherwise, the difference between the surface area of the cell array region CAR and the surface area of the peripheral region PER cannot be minimized. In other words, also in the peripheral region PER, by providing the pattern structure 311 corresponding to the beam structure 201 having the largest aspect ratio, the difference between the surface area of the cell array region CAR and the surface area of the peripheral region PER is minimized. Can do it. The fact that the difference between the surface area of the cell array region CAR and the surface area of the peripheral region PER can be minimized means that the loading effect at the time of film formation can be suppressed, and thereby the surface of the cell array region CAR ( This means that the film thickness of the film covering the uneven shape and the film thickness covering the surface of the peripheral region PER (uneven shape) can be improved. As a result, it is possible to improve the uniformity of device characteristics such as the resonance frequency and the pull-in voltage between the CMUT cell arranged at the center of the cell array region CAR and the CMUT cell arranged at the outer periphery of the cell array region CAR. Thus, efficient transmission / reception of ultrasonic waves can be performed. For the above reasons, it is desirable that the pattern structure 311 disposed in the peripheral region PER is composed of a structure corresponding to the structure having the highest aspect ratio among the structures disposed in the cell array region CAR. It is. Specifically, in the first embodiment, since the structure having the highest aspect ratio among the structures arranged in the cell array region CAR is the beam structure 201, the pattern structure arranged in the peripheral region PER. As 311, a structure corresponding to the beam structure 201 which is a component of the CMUT cell is employed.

<Manufacturing Method of CMUT in Embodiment 1>
Next, a CMUT manufacturing method according to the first embodiment will be described with reference to the drawings. 9 to 19 correspond to cross-sectional views taken along line AA in FIG.

First, a semiconductor wafer having a plurality of chip regions, a scribe region that partitions the plurality of chip regions, and an off-chip region formed outside the plurality of chip regions is prepared. Then, as shown in FIG. 9, an insulating film 502 made of a silicon oxide film is deposited on the semiconductor substrate (semiconductor wafer) 501 by a plasma CVD method (Chemical Vapor Deposition) by 1000 nm. Next, a titanium nitride film, an aluminum alloy film, and a titanium nitride film are stacked to a thickness of 100 nm, 600 nm, and 100 nm on the insulating film 502 by using a sputtering method, respectively. Thereafter, patterning is performed using a photolithography technique and a dry etching technique to form the lower electrode 102 and the lead-out wiring 302 drawn from the lower electrode 102 shown in FIG. 3 in each of the plurality of chip regions.

Subsequently, as shown in FIG. 10, an insulating film 503 made of a silicon oxide film is deposited on the main surface including the lower electrode 102 by 3000 nm by using a plasma CVD method. Then, as shown in FIG. 11, planarization is performed by using a CMP technique (Chemical ま で Mechanical Polishing) until the thickness of the insulating film 503 on the lower electrode 102 becomes 200 nm.

Thereafter, as shown in FIG. 12, a polycrystalline silicon film (polysilicon film) is deposited on the upper surface of the insulating film 503 by a plasma CVD method to a thickness of 300 nm, and a polycrystalline silicon film is used by using a photolithography technique and a dry etching technique. A sacrificial layer 1203 made of a polycrystalline silicon film is formed on the insulating film 503 by patterning the film. That is, a sacrificial layer 1203 that overlaps the lower electrode 102 in plan view is formed on the insulating film 503 in each of the plurality of chip regions. This sacrificial layer 1203 becomes a cavity in a subsequent process.

Next, as shown in FIG. 13, an insulating film 504 made of a silicon oxide film is deposited to a thickness of 200 nm by plasma CVD so as to cover the sacrificial layer 1203 and the insulating film 503. That is, the insulating film 504 is formed over the insulating film 503 that covers the sacrificial layer 1203 and is formed on the main surface.

Subsequently, as shown in FIG. 14, in order to form the upper electrode 105 of the CMUT cell, a laminated film of a titanium nitride film, an aluminum alloy film, and a titanium nitride film is deposited by sputtering to a thickness of 50 nm, 100 nm, and 50 nm, respectively. Then, the upper electrode 105 is formed by using a photolithography technique and a dry etching technique. At this time, a lead wire 305 drawn from the upper electrode and a wire 304 connecting the plurality of upper electrodes 105 shown in FIG. As described above, in the process shown in FIG. 14, the upper electrode 105 that overlaps the sacrificial layer 1203 in plan view is formed on the insulating film 504 in each of the plurality of chip regions.

Then, as shown in FIG. 15, by using a plasma CVD method, an insulating film 505 made of a silicon nitride film is 200 nm so as to cover the insulating film 504, the upper electrode 105, and the extraction wiring 305 extracted from the upper electrode. accumulate.

Next, as shown in FIG. 16, an etching hole 401 reaching the sacrifice layer 1203 is formed in the insulating film 505 and the insulating film 504 by using a photolithography technique and a dry etching technique. That is, in each of the plurality of chip regions, the etching hole 401 that penetrates the insulating film 504 and the insulating film 505 and reaches the sacrifice layer 1203 is formed.

Thereafter, as shown in FIG. 17, in each of the plurality of chip regions, the sacrificial layer 1203 is isotropically etched with xenon fluoride (XeF ₂ ) gas through the etching hole 401, thereby forming the cavity 103. To do.

Subsequently, as shown in FIG. 18, an insulating film 506 made of a silicon oxide film is deposited to a thickness of 200 nm by using a plasma CVD method to fill the etching hole 401. Thus, the etching hole 401 is closed by the insulating film 506 in each of the plurality of chip regions.

Thereafter, as shown in FIG. 19, by using a plasma CVD method, an insulating film made of a silicon nitride film is deposited by 800 nm, and by using a photolithography technique and a dry etching technique, Overlapping beam structures 201 of CMUT cells and a pattern structure 311 corresponding to the beam structure 201 are formed in the peripheral region outside the cell array region. Thereby, a convex shape is formed on the insulating film 506 by the beam structure 201 and the pattern structure 311. At this time, all pattern structures 311 arranged in the peripheral region outside the cell array region shown in FIG. 3 are also formed.

Then, as shown in FIG. 5, an insulating film 507 made of a silicon nitride film is deposited by 400 nm by using the plasma CVD method. At this time, according to the first embodiment, the pattern structure 311 having a relatively large step (convex shape) corresponding to the beam structure 201 constituting the CMUT cell is formed in the peripheral region outside the cell array region. ing. Thus, according to the first embodiment, the surface area on the insulating film 506 in the peripheral region where the plurality of pattern structures 311 are formed and the insulating film 506 in the cell array region where the plurality of beam structures 201 are formed. The difference from the surface area can be reduced. As a result, it is possible to suppress the occurrence of a loading effect when forming the insulating film 507 by the plasma CVD method. Thus, according to the first embodiment, it is possible to prevent a large difference in surface area between the central portion of the cell array region and the outer peripheral portion of the cell array region. The film thickness of the insulating film deposited on the outer peripheral portion can be made substantially uniform.

Finally, a plug 303 (see FIG. 3) for performing electrical connection to the lower electrode 102 and a plug 306 (see FIG. 3) for performing electrical connection to the upper electrode 105 are formed. . As described above, the CMUT according to the first embodiment can be manufactured.

<Modification 1>
In FIG. 3, the arrangement of the pattern structures 311 formed in the peripheral region PER outside the cell array region CAR is arranged at a pitch equal to the arrangement pitch of CMUT cells in the cell array. However, as shown in FIG. 3, the region overlaps with the end portions of the plug 303, the plug 306, and the CMUT chip 301, and an area where the pattern structure 311 cannot be arranged at the same pitch occurs in the peripheral area PER. In that case, the arrangement pitch and the pattern shape of the pattern structure 311 may be changed as in the structure 2001 and the structure 2002 shown in FIG. Making the arrangement pitch of the pattern structures 311 arranged in the peripheral area PER equal to the arrangement pitch of the plurality of CMUT cells in the cell array means that the surface area (unit surface area) of the cell array area CAR and the surface area (unit) of the peripheral area in the CMUT chip Although it is desirable from the viewpoint of equalizing the surface area), by disposing the structure 2002 having a different shape in the region where the pattern structure 311 disposed in the peripheral region PER cannot be disposed, the unit surface area and the cell array region CAR of the peripheral region PER are arranged. The unit surface area can be made substantially equal. As a result, device characteristics can be made more uniform in the plurality of CMUT cells constituting the cell array.

<Modification 2>
FIG. 21 is a diagram in which dummy cells 2003 are arranged on the outer periphery of the cell array 310, and a pattern structure 311 is further arranged outside the region 2004 in which the dummy cells 2003 and the cell array 310 are arranged. As used herein, a dummy cell is a cell that includes at least an electrode (upper electrode and lower electrode) and either a cavity or a filling part filled with a cavity, and does not perform an ultrasonic wave transmission / reception function. Means. The dummy cell 2003 is arranged to make the distortion of the membrane uniform or to make the device characteristics uniform. However, as shown in FIG. The pattern structure 311 may be arranged outside the area where the 310 and the dummy cell 2003 are arranged. It is possible to dispose the dummy cell 2003 in a region outside the cell array 310 to the extent that the influence of the loading effect does not reach the cell array 310. However, when the dummy cell 2003 is provided, since the dummy cell 2003 includes electrodes (upper electrode and lower electrode), a large number of unnecessary floating electrodes are formed on the CMUT chip 301, and an increase in parasitic capacitance via the floating electrodes, etc. May cause the sensitivity of the cell array 310 to decrease. In addition, since the dummy cell 2003 includes a cavity, when the dummy cell 2003 is disposed in the entire peripheral region outside the cell array 310, the cavity of the dummy cell 2003 near the end of the CMUT chip 301 is obtained by cutting the CMUT chip 301 from the substrate. The upper membrane may peel off. The peeled membrane may be reattached on the CMUT chip 301 and may damage the CMUT cells in the cell array 310.

On the other hand, as in Modification 2 shown in FIG. 21, a pattern structure that does not include electrodes or cavities outside the region where the dummy cells 2003 for uniformizing membrane distortion are arranged in order to suppress the loading effect. When only 311 is disposed, an increase in parasitic capacitance and peeling of the membrane can be suppressed. That is, according to the second modification, the dummy cells 2003 are arranged on the outer periphery of the cell array 310, and the pattern structures 311 (the structures 2001 and 2002) are arranged in the outer region of the dummy cells 2003. Thereby, according to the second modification, the membrane distortion can be made uniform by the dummy cell 2003, and the parasitic capacitance caused by the dummy cell 2003 is increased by the pattern structure 311 (the structure 2001 and the structure 2002). In addition, it is possible to obtain an advantage that the loading effect can be suppressed while preventing peeling of the membrane.

<Modification 3>
3, 4, 20, and 21, each cavity 103 of the plurality of CMUT cells has a hexagonal shape when viewed from the top surface of the substrate (in plan view). The shape of each cavity 103 of the CMUT cell is not limited to this, and may be, for example, a circular shape or a rectangular shape.

FIG. 22 is a diagram showing the CMUT chip 301 when the CMUT cell has a rectangular cavity shape and a large number of rectangular pattern structures 311 are arranged on the cavity portion. Also in the third modification shown in FIG. 22, a pattern structure that generates a relatively large step is arranged outside the cell array 310. Also in the third modification, the pattern structures 311 are arranged at substantially the same pitch as the cell pitch of the cell array 310, so that the central portion of the cell array 310 and the cell array are arranged as in the case of the hexagonal cell. The difference in surface area can be reduced with respect to the outer periphery of the. As a result, according to the third modification as well, the film thickness deposited on the central portion of the cell array 310 and the outer peripheral portion of the cell array 310 can be made uniform even when the film forming process by the CVD method is performed. Therefore, according to the third modification as well, the device characteristics such as the resonance frequency and the pull-in voltage between the CMUT cell arranged at the center of the cell array 310 and the CMUT cell arranged at the outer periphery of the cell array 310 become uniform, and the efficiency is improved. Good ultrasound transmission and reception is possible.

Furthermore, in the first embodiment, among the constituent elements constituting the CMUT cell, the pattern structure 311 corresponding to the beam structure 201 is arranged in the peripheral region. For example, the beam structure is included in the constituent elements of the CMUT cell. When a structure with a high aspect ratio is included like the body 201, a pattern structure 311 corresponding to this structure may be arranged in the peripheral region.

The constituent material of the CMUT described in the first embodiment is one example of the combination. For example, as the material of the upper electrode 105 and the lower electrode 102, tungsten or other conductive material May be used. Further, as the material of the sacrificial layer 1203, a material that can ensure wet etching selectivity with respect to the material surrounding the sacrificial layer 1203 can be used. Therefore, as the material of the sacrificial layer 1203, SOG (Spin-on-Glass) or a metal film can be used in addition to the polycrystalline silicon film.

(Embodiment 2)
In the second embodiment, on the semiconductor substrate on which the CMUT chip is formed, the pattern structure corresponding to the beam structure constituting the CMUT cell also in the scribe region and the off-chip region other than the chip region where the CMUT chip is formed. Is disposed on the insulating film. Thereby, also in the second embodiment, it is possible to suppress the variation in the film thickness of the membrane of each CMUT cell formed in the cell array, thereby realizing uniform device characteristics of each CMUT cell. Can do.

FIG. 23 is a top view showing a semiconductor wafer 2101 in which CMUT chips 301 (chip regions 2102) are arranged. In the second embodiment, a plurality of CMUT chips 301 (a plurality of chip regions 2102) are formed on a semiconductor wafer 2101 in a matrix arrangement of 8 rows and 2 columns. An off-chip region 2103 is formed in a region other than the plurality of chip regions 2102 in which the plurality of CMUT chips 301 are arranged. That is, the off-chip region 2103 is formed in the outer region of the plurality of chip regions 2102 on the main surface of the semiconductor wafer 2101.

FIG. 24 is a top view showing the region BR of FIG. 23 in an enlarged manner. This region BR is a region where the corners of the four CMUT chips 301 face each other, and a scribe region 2201 is formed between the CMUT chips 301. The scribe area 2201 is an area where the semiconductor wafer is cut by dicing or the like in order to cut out the CMUT chip 301.

FIG. 25 is a top view showing the region CR of FIG. 23 in an enlarged manner. In this region CR, a boundary region between the chip region 2102 and the off-chip region 2103 is shown.

FIG. 26 is a diagram showing a state of the region BR after the scribe region 2201 of the semiconductor wafer 2101 shown in FIG. 23 is cut by a dicing process. Similarly, FIG. 27 is a diagram illustrating a state of the region CR after the scribe region 2201 of the semiconductor wafer 2101 illustrated in FIG. 23 is cut by a dicing process. Reference numeral 2202 denotes a surface cut by a dicing process. In the dicing of the semiconductor wafer 2101, since the semiconductor wafer 2101 is generally cut with a dicing blade having a certain width, an area substantially equal to the width of the dicing blade in the scribe area 2201 is cut. At this time, the pattern structure 311 arranged in the scribe region 2201 and the off-chip region 2103 outside the CMUT chip 301 is also cut.

For example, as shown in FIG. 24 and FIG. 25, the feature point of the second embodiment is that the beam constituting the CMUT cell also in the scribe region 2201 and the off-chip region 2103 other than the plurality of chip regions 2102 of the semiconductor wafer 2101. The pattern structure 311 corresponding to the structure 201 is arranged on the insulating film (insulating film 506 shown in FIG. 5). As described above, by disposing the pattern structure 311 also in the scribe region 2201 and the off-chip region 2103, the unit surface area on the entire main surface of the semiconductor wafer 2101 can be made substantially uniform. As a result, according to the second embodiment, it is possible to suppress variation in the thickness of the membrane of each CMUT cell in the cell array formed on the CMUT chip 301, and thereby, all CMUT cells in the cell array can be suppressed. The device characteristics can be made uniform.

For example, the loading effect generated when a film is formed by the CVD method depends on the film forming conditions of the film constituting the membrane, but it may affect the boundary area between the areas having different unit surface areas to several millimeters. . Therefore, even if the pattern structure 311 is disposed in the peripheral region PER that is the outer region of the cell array region CAR, these regions must be disposed unless the pattern structure 311 is disposed up to the scribe region 2201 and the off-chip region 2103 other than the chip region 2102 There is a possibility that the effect of the loading effect due to the difference in unit surface area may reach the cell array region CAR. As a result, there is a possibility that the device characteristics of the CMUT cell arranged in the central part of the cell array region CAR and the CMUT cell arranged in the outer peripheral part become non-uniform.

Here, in order to suppress this influence, it is conceivable to arrange a cell array in the chip area 2102 while securing a distance of several mm from the boundary between the scribe area 2201 or the off-chip area 2103 and the chip area 2102. However, in this case, the size of the chip region 2102 needs to be increased in order to maintain the size (size) of the cell array having the function of transmitting and receiving ultrasonic waves. As a result, the number of CMUT chips 301 that can be obtained from the semiconductor wafer 2101 decreases, leading to a decrease in yield and an increase in chip price (cost).

On the other hand, in the second embodiment, for example, as shown in FIGS. 24 and 25, a pattern structure 311 corresponding to the beam structure 201 is arranged also in the scribe area 2201 and the off-chip area 2103 other than the chip area 2102. is doing. For this reason, according to the second embodiment, the unit surface area of the entire main surface of the semiconductor wafer 2101 can be made substantially uniform. Therefore, according to the second embodiment, it is necessary to dispose the cell array at a distance from the scribe region 2201 and the off-chip region 2103 in order to suppress the loading effect caused by the scribe region 2201 and the off-chip region 2103. There is no. Therefore, it is not necessary to increase the chip size in order to make the device characteristics uniform between the CMUT cell arranged at the center of the cell array and the CMUT cell arranged at the outer periphery. That is, according to the second embodiment, the device characteristics of the CMUT cells in the cell array formed in all the chip regions 2102 are made uniform, and the number of CMUT chips 301 that can be acquired from the semiconductor wafer 2101 is reduced. Both yield reduction and chip price increase can be suppressed.

The CMUT manufacturing method according to the second embodiment is the same as the CMUT manufacturing method according to the first embodiment. In order to arrange the pattern structure 311 in the scribe region 2201, a pattern of the pattern structure 311 may be laid out in advance in the scribe region 2201 in a photomask for forming the beam structure 201 in the chip region 2102. Further, the off-chip region 2103 only needs to be patterned not only in the chip region 2102 but also in the off-chip region 2103 using a photomask for forming the beam structure 201. Alternatively, the pattern structure 311 may be patterned in the off-chip region 2103 using a photomask dedicated to the pattern in the off-chip region 2103.

Further, as described in the first embodiment, even if the arrangement pitch and pattern shape of the pattern structures 311 arranged in the scribe region 2201 and the off-chip region 2103 are changed, the unit on the entire main surface of the semiconductor wafer 2101 is changed. If the surface areas are substantially equal, the same effect can be obtained regardless of the arrangement pitch and pattern shape.

Furthermore, in the second embodiment, for example, the example in which the pattern structure 311 is arranged in both the scribe region 2201 and the off-chip region 2103 has been described. However, the present invention is not limited to this, and depends on the degree of effect. The pattern structure 311 may be disposed only in one of the scribe region 2201 and the off-chip region 2103.

(Embodiment 3)
Next, one configuration example and role of an ultrasonic inspection apparatus including the CMUT in the first embodiment or the second embodiment will be described with reference to the drawings.

FIG. 28 is a block diagram showing a schematic configuration of the ultrasonic inspection apparatus 2401 according to the third embodiment. In FIG. 28, the ultrasonic inspection apparatus 2401 according to the first embodiment includes a main body and an ultrasonic probe 2402. The main body includes a transmission / reception separation unit 2403, a transmission unit 2404, a bias unit 2405, a reception unit 2406, A phasing addition unit 2407, an image processing unit 2408, a display unit 2409, a control unit 2410, and an operation unit 2411 are included.

The ultrasonic probe 2402 is a device that transmits and receives ultrasonic waves to and from a subject by making contact with the subject, and is manufactured using the CMUT in the first embodiment or the second embodiment. . An ultrasonic wave is transmitted from the ultrasonic probe 2402 to the subject, and a reflected echo signal from the subject is received by the ultrasonic probe 2402. The ultrasonic probe 2402 is electrically connected to a transmission / reception separating unit 2403 described later.

The transmission unit 2404 and the bias unit 2405 have a function of supplying a drive signal to the ultrasonic probe 2402 in order to transmit an ultrasonic wave from the ultrasonic probe 2402.

The receiving unit 2406 has a function of receiving a reflected echo signal output from the ultrasonic probe 2402. The receiving unit 2406 further performs signal processing such as analog-digital conversion (AD conversion) on the received reflected echo signal.

The transmission / reception separating unit 2403 electrically connects the ultrasonic probe 2402 and the transmission unit 2404 when transmitting ultrasonic waves, while electrically connecting the ultrasonic probe 2402 and the reception unit 2406 when receiving ultrasonic waves. Has a function of switching the connection path so as to be connected. That is, the transmission / reception separating unit 2403 switches between transmission and reception so as to pass a drive signal from the transmission unit 2404 to the ultrasonic probe 2402 during transmission and to pass a reception signal from the ultrasonic probe 2402 to the reception unit 2406 during reception. Have the function of separating.

The phasing addition unit 2407 has a function of adding a reflection echo signal output from the focus point in consideration of a time difference received by each CMUT cell. That is, the phasing addition unit 2407 has a function of adding (phasing addition) in consideration of the phase difference of the reflected echo signal.

The image processing unit 2408 has a function of forming an inspection image based on the phasing-added reflected echo signal, and the display unit 2409 is a display device that displays the image-processed inspection image.

The control unit 2410 has a function of controlling each component constituting the main body, and the control unit 2410 controls transmission / reception of ultrasonic waves of the ultrasonic probe 2402.

The operation unit 2411 is a device that gives an instruction to the control unit 2410. The operation unit 2411 includes, for example, an input device such as a trackball, a keyboard, or a mouse.

As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say. That is, the present invention is not limited to the above-described embodiment, and includes various modifications. For example, the embodiments described above are described in detail for better understanding of the present invention, and are not necessarily limited to those provided with all the configurations described above. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

The embodiment includes the following forms.

(Appendix 1)
A cell array region in which a plurality of cells are formed;
A peripheral region in contact with the cell array region;
Including
Each of the plurality of cells is
A substrate,
A first electrode formed on the substrate;
A first insulating film formed on the first electrode;
A cavity formed on the first insulating film and overlapping the first electrode in plan view;
A second insulating film formed on the cavity,
A second electrode formed on the second insulating film and overlapping the cavity in plan view;
A third insulating film formed on the second electrode;
A beam structure protruding from the third insulating film and overlapping the cavity in plan view;
A fourth insulating film covering the beam structure and formed on the third insulating film;
Have
In the peripheral area,
The third insulating film;
A plurality of pattern structures protruding in a convex shape from the third insulating film;
The fourth insulating film covering the plurality of pattern structures;
An ultrasonic transducer is formed.

(Appendix 2)
In the ultrasonic transducer according to attachment 1,
Each of the plurality of pattern structures is an ultrasonic transducer formed of the same material as the beam structure.

(Appendix 3)
In the ultrasonic transducer according to attachment 1,
Each of the plurality of pattern structures is an ultrasonic transducer having the same structure as the beam structure.

(Appendix 4)
In the ultrasonic transducer according to attachment 1,
The difference between the surface area on the third insulating film in the peripheral region where the plurality of pattern structures are formed and the surface area on the third insulating film in the cell array region where the plurality of beam structures are formed is: The surface area on the third insulating film in the peripheral region and the surface area on the third insulating film in the cell array region in which the plurality of beam structures are formed when the plurality of pattern structures are not formed in the peripheral region Ultrasonic transducer, smaller than the difference.

(Appendix 5)
In the ultrasonic transducer according to attachment 1,
A membrane is configured by the second insulating film, the second electrode, the third insulating film, the beam structure, and the fourth insulating film,
The ultrasonic transducer has a function of increasing the vibration of the membrane in the thickness direction of the membrane as compared with the case where the beam structure does not exist.

(Appendix 6)
In the ultrasonic transducer according to attachment 1,
The thickness of the said beam structure is an ultrasonic transducer which is more than the thickness which combined the said 2nd insulating film, the said 2nd electrode, and the said 3rd insulating film.

(Appendix 7)
(A) preparing a semiconductor wafer having a plurality of chip regions, a scribe region that partitions the plurality of chip regions, and an off-chip region formed outside the plurality of chip regions on a main surface;
(B) forming a first electrode in each of the plurality of chip regions;
(C) forming a first insulating film on the main surface including on the first electrode;
(D) forming a sacrificial layer overlapping the first electrode in plan view on the first insulating film in each of the plurality of chip regions;
(E) forming a second insulating film on the first insulating film covering the sacrificial layer and formed on the main surface;
(F) forming a second electrode that overlaps the sacrificial layer in plan view on the second insulating film in each of the plurality of chip regions;
(G) forming a third insulating film on the main surface including the second electrode;
(H) forming an etching hole that penetrates the third insulating film and the second insulating film and reaches the sacrificial layer in each of the plurality of chip regions;
(I) forming a cavity by removing the sacrificial layer through the etching hole in each of the plurality of chip regions;
(J) After the step (i), a step of closing the etching hole in each of the plurality of chip regions;
(K) After the step (j), a beam structure is formed on the third insulating film in the plurality of chip regions so as to overlap the cavity in plan view, and the third insulating film in the scribe region A step of forming a plurality of pattern structures corresponding to the beam structure;
(L) After the step (k), a step of covering the beam structure and the plurality of pattern structures and forming a fourth insulating film on the third insulating film formed on the main surface;
A method for manufacturing an ultrasonic transducer.

(Appendix 8)
In the method of manufacturing an ultrasonic transducer according to appendix 7,
In the method (k), the plurality of pattern structures are formed on the third insulating film in the off-chip region.

(Appendix 9)
In the method of manufacturing an ultrasonic transducer according to appendix 7,
Each of the plurality of chip regions is
A cell array region in which a plurality of cells are formed;
A peripheral region in contact with the cell array region;
Including
In the step (k), the plurality of pattern structures are also formed on the third insulating film in the peripheral region of each of the plurality of chip regions.

(Appendix 10)
In the method of manufacturing an ultrasonic transducer according to appendix 7,
A method of manufacturing an ultrasonic transducer, wherein a convex shape is formed on the third insulating film by each of the beam structure and the plurality of pattern structures formed in the step (k).

(Appendix 11)
In the method of manufacturing an ultrasonic transducer according to appendix 7,
In the step (l), the fourth insulating film is formed using a plasma CVD method.

DESCRIPTION OF SYMBOLS 101 Substrate 102 Lower electrode 103 Cavity portion 104a Insulating film 104b Insulating film 105 Upper electrode 106 Membrane 201 Beam structure 301 CMUT chip 302 Lead wire 303 Plug 304 Wire 305 Lead wire 306 Plug 310 Cell array 311 Pattern structure 401 Etching hole 501 Semiconductor substrate 502 Insulating Film 503 Insulating Film 504 Insulating Film 505 Insulating Film 506 Insulating Film 507 Insulating Film 701 End Face 1203 Sacrificial Layer 2001 Structure 2002 Structure 2003 Dummy Cell 2004 Area 2101 Semiconductor Wafer 2102 Chip Area 2103 Off-Chip Area 2202 Surface Scribe 1 2202 Ultrasonic inspection apparatus 2402 Ultrasonic probe 2403 Transmission / reception separation unit 2404 Transmission unit 2405 Bias unit 240 Receiving unit 2407 phasing addition unit 2408 image processing unit 2409 display unit 2410 control unit 2411 operation unit CAR cell array region PER peripheral region

Claims (15)

1. A cell array region in which a plurality of cells are formed;
   A peripheral region in contact with the cell array region;
   Including
   Each of the plurality of cells is
   A substrate,
   A first electrode formed on the substrate;
   A first insulating film formed on the first electrode;
   A cavity formed on the first insulating film and overlapping the first electrode in plan view;
   A second insulating film formed on the cavity,
   A second electrode formed on the second insulating film and overlapping the cavity in plan view;
   A third insulating film formed on the second electrode;
   A beam structure formed on the third insulating film and overlapping the cavity in plan view;
   A fourth insulating film covering the beam structure and formed on the third insulating film;
   Have
   In the peripheral area,
   The third insulating film;
   A plurality of pattern structures formed on the third insulating film and corresponding to the beam structures;
   The fourth insulating film covering the plurality of pattern structures;
   An ultrasonic transducer is formed.
2. The ultrasonic transducer according to claim 1.
   An ultrasonic transducer in which a convex shape is formed on the third insulating film by each of the beam structure and the plurality of pattern structures.
3. The ultrasonic transducer according to claim 1.
   The ultrasonic transducer, wherein the beam structure has the largest aspect ratio indicated by thickness / width among the components constituting each of the plurality of cells.
4. The ultrasonic transducer according to claim 1.
   The ultrasonic transducer in which at least a part of the arrangement pattern of the plurality of pattern structures is equal to the arrangement pattern of the plurality of beam structures.
5. The ultrasonic transducer according to claim 1.
   In the peripheral area,
   A first wiring electrically connected to the first electrode;
   A first plug electrically connected to the first wiring;
   A second wiring electrically connected to the second electrode;
   A second plug electrically connected to the second wiring;
   An ultrasonic transducer is formed.
6. The ultrasonic transducer according to claim 5, wherein
   The ultrasonic transducer, wherein the plurality of pattern structures are arranged at positions that do not overlap the first plug and the second plug in plan view.
7. The ultrasonic transducer according to claim 5, wherein
   The ultrasonic transducer, wherein a part of the plurality of pattern structures is arranged at a position overlapping the first wiring in a plan view.
8. The ultrasonic transducer according to claim 5, wherein
   The ultrasonic transducer, wherein a part of the plurality of pattern structures is arranged at a position overlapping the second wiring in a plan view.
9. The ultrasonic transducer according to claim 5, wherein
   The peripheral area is
   A first lead region in which the first wiring and the first plug are formed;
   A second lead region in which the second wiring and the second plug are formed;
   A first outer edge region that is an outer region of the first lead region;
   A second outer edge region that is an outer region of the second lead region;
   Including an ultrasonic transducer.
10. The ultrasonic transducer according to claim 9, wherein
    The plurality of pattern structures are ultrasonic transducers arranged in the first outer edge region.
11. The ultrasonic transducer according to claim 9, wherein
    The plurality of pattern structures are ultrasonic transducers arranged in the second outer edge region.
12. The ultrasonic transducer according to claim 9, wherein
    The plurality of pattern structures are ultrasonic transducers arranged in the first outer edge region and the second outer edge region.
13. The ultrasonic transducer according to claim 1.
    An ultrasonic transducer in which only an insulating film is interposed between a part of the plurality of pattern structures and the substrate in the thickness direction of the substrate.
14. The ultrasonic transducer according to claim 1.
    In the peripheral area,
    At least the dummy cell including either the cavity part or the filling part filled with the cavity part, and the dummy cell that does not perform the function of transmitting and receiving ultrasonic waves, and
    The plurality of pattern structures;
    Formed,
    The ultrasonic transducer, wherein the dummy cell is disposed closer to the cell array region than the plurality of pattern structures.
15. An ultrasonic probe that is brought into contact with the subject and transmits / receives ultrasonic waves to / from the subject;
    A transmitter for supplying a drive signal to the ultrasonic probe to transmit ultrasonic waves from the ultrasonic probe;
    A receiving unit that receives a reflected echo signal output from the ultrasonic probe that has received the ultrasonic wave; and
    An image processing unit for generating an image based on the reflected echo signal;
    When transmitting an ultrasonic wave, the ultrasonic probe and the transmitting unit are electrically connected, while when receiving an ultrasonic wave, the ultrasonic probe and the receiving unit are electrically connected. A transmission / reception separation unit for switching connection paths;
    An ultrasonic inspection apparatus comprising:
    The ultrasonic probe is electrically connected to the transmission / reception separating unit, and includes an ultrasonic transducer;
    The ultrasonic transducer is
    A cell array region in which a plurality of cells are formed;
    A peripheral region in contact with the cell array region;
    A semiconductor chip including
    Each of the plurality of cells is
    A substrate,
    A first electrode formed on the substrate;
    A first insulating film formed on the first electrode;
    A cavity formed on the first insulating film and overlapping the first electrode in plan view;
    A second insulating film formed on the cavity,
    A second electrode formed on the second insulating film and overlapping the cavity in plan view;
    A third insulating film formed on the second electrode;
    A beam structure formed on the third insulating film and overlapping the cavity in plan view;
    A fourth insulating film covering the beam structure and formed on the third insulating film;
    Have
    In the peripheral area,
    The third insulating film;
    A plurality of pattern structures formed on the third insulating film and corresponding to the beam structures;
    The fourth insulating film covering the plurality of pattern structures;
    An ultrasonic inspection apparatus is formed.

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