JP2013219303A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability in a semiconductor device including a capacitive detection type ultrasonic sensor which has a cavity between electrodes to oscillate a membrane.SOLUTION: In a semiconductor device manufacturing method, silicon (Si) is used for a material of a sacrificial pattern 6 which is a pattern formed for forming a cavity in a region sandwiched by an upper electrode M1E and a lower electrode M0E and removed in a subsequent process. Further, silicon oxide films having selectivity to the material of the sacrificial pattern 6 is used as etching stopper films 5, 7 which are formed so as to surround an upper part and a lower part of the sacrificial pattern 6.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to an ultrasonic sensor manufactured by a MEMS (Micro Electro Mechanical System) technology and a technology effective when applied to a manufacturing method thereof.

  Ultrasonic sensors have been put to practical use in various devices such as a medical ultrasonic echo diagnostic apparatus or a nondestructive ultrasonic flaw detector.

  Up to now, ultrasonic sensors using the vibration of a piezoelectric body have been the mainstream. However, due to recent advances in MEMS technology, development of capacitive detection type ultrasonic sensors using MEMS technology has been promoted.

  The capacitive detection type ultrasonic sensor is a vibrator having a configuration with a hollow portion between electrodes facing each other formed on a semiconductor substrate, and by applying DC and AC voltages to each electrode in a superimposed manner, The membrane vibrates near the resonance frequency and generates ultrasonic waves.

  A technique related to such an ultrasonic sensor is described in, for example, Patent Document 1 (Japanese Patent Laid-Open No. 2008-85246), and an ultrasonic transmission / reception sensor manufactured using the MEMS technique is disclosed.

  Patent Document 2 (International Patent Publication WO 2005/015637 pamphlet) describes that an electronic device is provided with a gettering thin film in contact with a decompressed cavity to maintain the degree of vacuum in a micro vacuum package. ing. Here, a silicon oxide film, which is a sacrificial film formed on a silicon substrate, is covered with a polysilicon film, and then the silicon oxide film is removed by injecting hydrofluoric acid from an etching hole that penetrates the polysilicon film. Forming the cavity. However, in Patent Document 2, there is no description that the silicon film covering the cavity is amorphous for the purpose of improving the flatness of the surface of the film formed on the cavity via the silicon film.

  Patent Document 3 (Japanese Patent Publication No. 2009-531884) discloses that the silicon layer is made porous and the lower and upper surfaces thereof are covered with a conductive layer (high concentration semiconductor film) and a silicon oxide layer, respectively. It is described that the silicon layer is exposed by opening a conductive layer, and a cavity is formed by partially removing the porous silicon layer using a solution containing KOH (potassium hydroxide). .

JP 2008-85246 A International Patent Publication WO 2005/015637 Pamphlet Special table 2009-531884 gazette

  As a method for forming the cavity, a sacrificial film containing tungsten (W) or titanium nitride (TiN) is formed on the lower electrode through a silicon oxide film, and the upper portion is formed on the silicon oxide film covering the sacrificial film. A method of removing the sacrificial film by injecting sulfuric acid or the like from a hole exposing a part of the sacrificial film after forming the electrode can be considered.

  As described above, when tungsten or titanium nitride is used as the sacrificial film material and silicon oxide is used as the material of the etching stopper film covering the sacrificial film, the characteristics of the ultrasonic sensor are sufficient to ensure the rigidity of the vibrator. Problems such as deterioration, a problem in which the life of the ultrasonic sensor is deteriorated due to a small vertical distance of the cavity, and a problem in that the life of the ultrasonic sensor is deteriorated due to the formation of irregularities on the upper surface of the cavity.

  An object of the present invention is to improve the reliability of a semiconductor device.

  The above object and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  Of the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to an embodiment includes a first conductor film, for example, a first etching stopper film including a silicon film, a second etching stopper film including a silicon film, and a second conductor film, which are sequentially formed on a substrate. And a cavity formed between the first conductor film and the second conductor film and between the first etching stopper film and the second etching stopper film.

  In another embodiment, a method of manufacturing a semiconductor device includes a first conductive film, for example, a first etching stopper film including a silicon film, a sacrificial film including a silicon oxide film, such as a silicon film, on a substrate. After the second etching stopper film and the second conductor film are formed in order, the second etching stopper film is opened to remove the sacrificial film.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, the reliability of a semiconductor device can be improved.

It is a top view which shows the semiconductor device which is one embodiment of this invention. FIG. 2 is a plan view of main parts of the semiconductor chip shown in FIG. 1. FIG. 3 is a main part cross-sectional view taken along line X1-X1 in FIG. 2. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; FIG. 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7; FIG. 9 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8; FIG. 10 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9; FIG. 11 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; FIG. 14 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 13; FIG. 15 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 14; 1 is a schematic diagram of an ultrasonic echo diagnostic apparatus to which a semiconductor device according to an embodiment of the present invention is applied. It is principal part sectional drawing of the semiconductor device shown as a comparative example.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. Also, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  The semiconductor substrate in this application refers to silicon and other semiconductor single crystal substrates, quartz substrates, sapphire substrates, glass substrates, other insulating substrates, semiconductor substrates, etc. used in the manufacture of semiconductor integrated circuits, and composite substrates thereof. And

  The semiconductor device according to the present embodiment is an ultrasonic transmission / reception sensor such as an ultrasonic probe (CMUT: Capacitive Micro-machined Ultrasonic Transducer) manufactured using, for example, MEMS (Micro Electro Mechanical System) technology.

  FIG. 1 is an overall plan view of a semiconductor chip 1 constituting the semiconductor device of the present embodiment. The semiconductor chip 1 has a first main surface (upper surface, front surface) and a second main surface (lower surface, back surface) located on opposite sides along the thickness direction. FIG. 1 is a plan view (that is, a top view) of the first main surface side of the semiconductor chip 1.

  As shown in FIG. 1, the planar shape of the semiconductor chip 1 is, for example, a rectangular shape, that is, a rectangular shape. The length of the semiconductor chip 1 in the longitudinal direction (second direction Y) is, for example, about 4 cm, and the length of the semiconductor chip 1 in the short direction (first direction X) is, for example, about 1 cm. However, the planar dimensions of the semiconductor chip 1 are not limited to this and can be variously changed. For example, the length in the longitudinal direction (second direction Y) is about 8 cm, and the length in the short direction (first direction X). The size can be various sizes such as about 1.5 cm.

  On the first main surface of the semiconductor chip 1, a sensor region (sensor cell array, vibrator array) SA and a plurality of bonding pads (hereinafter referred to as pads) BP1 and BP2 are arranged.

  In the sensor area SA, a plurality of lower electrode wirings M0, a plurality of upper electrode wirings M1 orthogonal thereto, and a plurality of vibrators (sensor cells, corresponding to vibrators 20 described later) are arranged.

  Each of the plurality of lower electrode wirings M0 is formed so as to extend along the longitudinal direction (second direction Y) of the semiconductor chip 1, and is, for example, 16 in the short direction (first direction X) of the semiconductor chip 1. Channels (channel: hereinafter also referred to as “ch”) are arranged side by side.

  Each of the lower electrode wirings M0 is electrically connected to the pad BP1. A plurality of pads BP1 are provided along the short side of the semiconductor chip 1 so as to correspond to the lower electrode wiring M0 in the vicinity of both ends in the longitudinal direction (second direction Y) of the semiconductor chip 1 on the outer periphery of the sensor region SA. They are arranged side by side.

  Each of the plurality of upper electrode wirings M1 is formed so as to extend along the short direction (first direction X) of the semiconductor chip 1, and for example, 192ch in the longitudinal direction (second direction Y) of the semiconductor chip 1 They are arranged side by side.

  Each upper electrode wiring M1 is electrically connected to the pad BP2. A plurality of pads BP2 are provided along the long side of the semiconductor chip 1 so as to correspond to the upper electrode wiring M1 in the vicinity of both ends in the short direction (first direction X) of the semiconductor chip 1 on the outer periphery of the sensor region SA. They are arranged side by side.

  The vibrator (corresponding to a vibrator 20 to be described later) constitutes, for example, an electrostatic variable capacitor, and is disposed at the intersection of the lower electrode wiring M0 and the upper electrode wiring M1. That is, a plurality of transducers (corresponding to transducers 20 described later) are regularly arranged in a matrix (matrix, array) in the sensor area SA. In the sensor area SA, for example, 50 vibrators are arranged in parallel at the intersection of the lower electrode wiring M0 and the upper electrode wiring M1.

  Therefore, the sensor area SA is a sensor area in which a plurality of sensor cells (corresponding to a vibrator 20 described later) is formed, and the semiconductor chip 1 is a sensor in which a plurality of sensor cells (corresponding to a vibrator 20 described later) is formed. This is a semiconductor device having a region SA on the main surface (first main surface).

  Next, FIG. 2 is a main part plan view (main part enlarged plan view) of the semiconductor chip 1 (see FIG. 1). 2 and 3 are a plan view and a cross-sectional view of a main part of a main body region (a region where the sensor region SA and the pads BP1 and BP2 are formed) of the semiconductor chip 1 are combined. 3 substantially corresponds to the cross-sectional view taken along line X1-X1 of FIG. FIG. 2 is a plan view in the case where one vibrator is arranged at the intersection of the lower electrode wiring M0 and the upper electrode wiring M1. For simplicity, in FIG. 2 (main body region), the lower electrode wiring M0 is 2ch, the upper electrode wiring M1 is 3ch, and the vibrator 20 located at each intersection of each lower electrode wiring M0 and each upper electrode wiring M1 is shown. A plan view of one case is shown.

As shown in FIGS. 2 and 3, the semiconductor substrate 1S constituting the semiconductor chip 1 (see FIG. 1) is made of, for example, a silicon (Si) single crystal, and is located on opposite sides along the thickness direction. It has a main surface (upper surface, front surface) 1Sa and a second main surface (lower surface, back surface) 1Sb. On the first main surface 1Sa of the semiconductor substrate 1S, the plurality of vibrators 20 are arranged (formed) via an insulating film 2 made of, for example, silicon oxide (SiO ₂ or the like). Here, the insulating film 2 is a TEOS (Tetra Ethyl Ortho Silicate, tetraethoxysilane) film, and the insulating film 2 is mainly composed of SiO or SiO ₂ .

  As shown in FIG. 2, each of the plurality of vibrators 20 is formed in a planar hexagonal shape, for example, and is disposed in a honeycomb shape, for example. Thereby, since the several vibrator | oscillator 20 can be arrange | positioned with high density, sensor performance can be improved. Note that the shape of the vibrator 20 in plan view is not limited to a hexagon, and may be, for example, a rectangle.

  As shown in FIG. 3, each vibrator 20 includes a lower electrode M0E, an upper electrode M1E provided so as to face the lower electrode M0E, and a cavity (first cavity) VR1 interposed between these electrodes. And have. The height of the cavity VR1, that is, the distance between the upper surface of the etching stopper film 5 that is the bottom surface of the cavity portion VR1 and the lower surface of the etching stopper film 7 that is the upper surface of the cavity portion VR1 is greater than 200 nm. 230 nm. That is, the height of the cavity portion VR1 here refers to the length from the bottom surface to the top surface of the cavity portion VR1 in the direction perpendicular to the first main surface of the semiconductor substrate 1S.

  The lower electrode M0E is formed in a portion of the lower electrode wiring M0 where the upper electrode wiring M1 overlaps in a plane. That is, the lower electrode M0E of each vibrator 20 is formed by a part of the lower electrode wiring M0, and a portion of the lower electrode wiring M0 that overlaps the upper electrode wiring M1 in a plan view (that is, below the upper electrode wiring M1). The portion located at () is the lower electrode M0E. The lower electrode M0E and the lower electrode wiring M0 are made of the conductor film 3, for example, a tungsten (W) film. The conductor film 3 may be a film made of a titanium nitride (TiN) film instead of the tungsten (W) film. The conductor film 3 may have a laminated structure composed of a plurality of conductor films including a tungsten film or a titanium nitride film.

  On the side surfaces of the lower electrode M0E and the lower electrode wiring M0, from the viewpoint of reducing a step due to the thickness of the lower electrode M0E and the lower electrode wiring M0, for example, sidewalls (sidewall insulating film, Sidewall spacers (SW) are formed. The surfaces of the lower electrode M0E, the lower electrode wiring M0, the insulating film 2 and the sidewall SW are covered with an etching stopper film 5 made of, for example, amorphous (amorphous) silicon.

  An etching stopper film 7 made of, for example, amorphous silicon is deposited on the etching stopper film 5. An insulating film 8a is formed on the etching stopper film 7, and the upper electrode M1E is provided on the insulating film 8a so as to face the lower electrode M0E. The thickness of each of the etching stopper films 5 and 7 is, for example, 100 nm.

The etching stopper films 5 and 7 mainly contain an intrinsic semiconductor into which no impurity is introduced. For example, the etching stopper films 5 and 7 are made of non-doped silicon (Si). The reason why impurities are not introduced into the etching stopper films 5 and 7 in this way is to prevent the etching stopper films 5 and 7 from being electrically connected to the lower electrode M0E or the upper electrode M1E and the vibrator 20 from operating. . That is, the insulating properties of the etching stopper films 5 and 7 are enhanced by using the etching stopper films 5 and 7 as intrinsic semiconductor films and increasing the resistance value. Further, by preventing charge traps from being formed in the etching stopper films 5 and 7, charges are prevented from being accumulated in the etching stopper films 5 and 7. Although the case where the material of the etching stopper films 5 and 7 is silicon (Si) will be described here, the materials constituting the etching stopper films 5 and 7 are silicon nitride (Si ₃ N ₄ or the like), silicon carbide (SiC). ) Or silicon carbonitride (SiCN).

The insulating film 8a is made of, for example, a silicon oxide film, and is provided to maintain a withstand voltage between the lower electrode M0E and the upper electrode M1E, and has a role of insulating the upper electrode M1E and the etching stopper film 7. . That is, the insulating film 8a is provided to prevent leakage current from flowing between the lower electrode M0E and the upper electrode M1E, and the film thickness thereof is, for example, 100 to 200 nm. Here, the insulating film 8a is TEOS film, is SiO or SiO ₂ for mainly constituting the insulating film 8a. The distance between the lower electrode M0E and the upper electrode M1E is, for example, about 500 nm. When the vibrator 20 is operated to generate ultrasonic waves, a potential difference of, for example, about 300 V at the maximum between the lower electrode M0E and the upper electrode M1E. The membrane is vibrated by generating

  The membrane here refers to a region that bends (vibrates) when the vibrator 20 operates, and in FIG. 2, the etching stopper film 7, the insulating film 8a, the upper electrode M1E, the insulating film directly above the cavity VR1. It refers to the film 9 and the insulating film (passivation film) 11.

  The upper electrode M1E is formed in a portion where the lower electrode wiring M0 overlaps in a plane in the upper electrode wiring M1. That is, the upper electrode M1E of each vibrator 20 is formed by a part of the upper electrode wiring M1, and a portion of the upper electrode wiring M1 that overlaps the lower electrode wiring M0 in a plane (that is, above the lower electrode wiring M0). The portion located at () is the upper electrode M1E. The planar shape of the upper electrode M1E is substantially hexagonal or rectangular, and the upper electrode wiring M1 extends in the first direction X and is wider than the connecting portion M1C that connects the upper electrodes M1E. It is formed with. As described above, the upper electrode wiring M1 includes a plurality of upper electrodes M1E and a connecting portion M1C that connects the upper electrodes M1E adjacent in the first direction X to each other.

  The upper electrode wiring M1 including the upper electrode M1E and the connecting portion M1C is made of a conductor film (second conductor film) 8, for example, a tungsten (W) film. The conductor film 8 may be a film made of a titanium nitride (TiN) film instead of the tungsten (W) film. Further, the conductor film 8 may have a laminated structure composed of a plurality of conductor films including a tungsten film or a titanium nitride film.

  The cavity VR1 is formed between the lower electrode M0E and the upper electrode M1E (between the etching stopper film 5 and the etching stopper film 7). The planar shape of the hollow portion VR1 is formed in, for example, a hexagonal shape or a rectangle. The surface of the etching stopper film 5 is exposed on the bottom surface of the cavity VR1, and the surface of the etching stopper film 7 is exposed on the side surface and the top surface of the cavity VR1. That is, the shape of the cavity VR1 is mainly defined by the etching stopper films 5 and 7, and the etching stopper films 5 and 7 are exposed in the cavity VR1.

On the etching stopper film 7, an insulating film 9 made of, for example, a silicon oxide (SiO ₂ or the like) film is deposited so as to cover the upper electrode wiring M1 including the upper electrode M1E and the connecting portion M1C. Here, the insulating film 9 is a TEOS film, and the insulating film 9 is mainly composed of SiO or SiO ₂ . In the etching stopper film 7, the insulating film 8a, and the insulating film 9, a hole (opening, contact hole, through hole) 10 reaching the cavity VR1 is formed in the vicinity of the hexagonal portion of the cavity VR1. As will be described later, the hole 10 is a hole for forming a cavity VR1 by etching a sacrificial pattern (sacrificial pattern 6 described later) between the etching stopper films 5 and 7 (hole for forming the cavity VR1). . Since the cavity VR1 is a space formed by removing the sacrificial pattern surrounded by the etching stopper films 5 and 7 using a solution that hardly dissolves the etching stopper films 5 and 7, the cavity VR1 is formed in the cavity VR1. Then, the surfaces of the etching stopper films 5 and 7 are exposed.

On the insulating film 9, an insulating film (passivation film) 11 made of, for example, a silicon nitride (Si ₃ N ₄ or the like) film is deposited. A part of the insulating film 11 enters the hole 10, thereby closing the hole 10. The insulating film 11 is not a film provided to supplement the strength of a region (membrane) that bends when the vibrator 20 is operated, but is merely a film formed for passivation. Since the insulating film 11 has a role of protecting the semiconductor device from moisture and the like, silicon nitride having a higher density than silicon oxide or the like is used here as a material thereof.

  Further, the bottom surfaces of the etching stopper film 7, the insulating film 8a, and the upper electrode M1E in the region immediately above the cavity VR1 are all flat and have no unevenness. As described later, this is caused by forming a sacrificial pattern (not shown) for forming the cavity VR1 with a silicon oxide film.

  In the etching stopper films 5 and 7 and the insulating films 8a, 9 and 11, an opening 12a reaching a part of the lower electrode wiring M0 is formed. A part of the lower electrode wiring M0 exposed from the opening 12a is the pad BP1. The insulating films 9 and 11 are formed with an opening 12b reaching a part of the upper electrode wiring M1. A part of the upper electrode wiring M1 exposed from the opening 12b is the pad BP2.

  On the insulating film 11, an insulating film (protective film) 13 made of, for example, a negative photosensitive polyimide film is deposited.

  Openings 14 a and 14 b are formed in the insulating film 13. Among these, the opening 14a is formed in a position and a plane dimension that includes the opening 12a in a plane, and a part of the lower electrode wiring M0 exposed from the opening 14a is the pad BP1. Further, the opening 14b is formed in a position and a plane dimension that includes the opening 12b in a plane, and a part of the upper electrode wiring M1 exposed from the opening 14b is the pad BP2. The pads BP1 and BP2 are input / output terminals of the semiconductor chip 1, and bonding wires and the like are electrically connected to the pads BP1 and BP2.

  The insulating film 13 has a function as a protective film that protects the plurality of vibrators 20 on the first main surface of the semiconductor chip 1 in a dicing process for cutting out the semiconductor chip 1 from the semiconductor wafer. If unnecessary, the formation of the insulating film 13 can be omitted, and the insulating film 11 can be used as the uppermost layer film (protective film). In the semiconductor chip 1 (see FIG. 1), the vibrator 20 as described above is formed in the sensor region SA.

  As described above, the semiconductor chip (semiconductor device) 1 of the present embodiment shown in FIGS. 1 to 3 is a semiconductor device having a sensor region SA in which a plurality of sensor cells (vibrator 20) are formed on the main surface, Semiconductor substrate 1S, and lower electrode (conductor film) M0E, etching stopper film 5, etching stopper film 7, and upper electrode (conductor film) formed on semiconductor substrate 1S in this order from the main surface (1Sa) side of semiconductor substrate 1S I have M1E. An insulating film 2 is formed between the semiconductor substrate 1S and the lower electrode M0E, an insulating film 8a is formed between the etching stopper film 7 and the upper electrode M1E, and an insulating film 9 is formed on the etching stopper film 7. An insulating film (passivation film) 11 is formed on the insulating film 9 so as to cover the upper electrode M1E.

  Each of the plurality of sensor cells (vibrator 20) of the semiconductor chip 1 includes a cavity VR1 formed between the etching stopper film 5 and the etching stopper film 7, an upper electrode M1E, and a lower electrode in the sensor region SA. M0E. Each of the plurality of sensor cells (vibrator 20) of the semiconductor chip 1 includes a lower electrode M0E (first electrode), an upper electrode M1E (second electrode), and an insulating film 8a between the lower electrode M0E and the upper electrode M1E. The variable capacitance sensor includes the etching stopper film 5, the cavity VR1 and the etching stopper film 7.

  In the ultrasonic transmission / reception sensor having such a configuration, an electrostatic force is applied by applying DC and AC voltages to the lower electrode wiring M0 (lower electrode M0E) and the upper electrode wiring M1 (upper electrode M1E), thereby causing each vibration. A direction in which the membrane of the child 20 (the film positioned above the cavity VR1) intersects (orthogonally) the first main surface 1Sa of the semiconductor substrate 1S near the resonance frequency due to the balance with the force of the spring of the membrane (see FIG. 3). At this time, the maximum potential difference between the upper electrode M1E and the lower electrode M0E is, for example, 300V. Thereby, an ultrasonic wave (ultrasonic pulse) of several MHz is generated.

  In the case of reception, the membrane is vibrated by the pressure of the ultrasonic waves reaching the membrane of each transducer 20, and the ultrasonic wave is detected by changing the capacitance between the lower electrode M0E and the upper electrode M1E. can do. That is, the displacement of the interval between the lower electrode M0E and the upper electrode M1E due to the reflected wave is detected as a change in electrostatic capacity (the electrostatic capacity of each vibrator 20). By performing such transmission / reception, for example, a tomographic image of a living tissue can be taken.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 4 to 15 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the present embodiment. Note that the cross-sectional views of FIGS. 4 to 15 show only the portion corresponding to the left region of the cross-sectional view of FIG.

  To manufacture the semiconductor chip 1, first, as shown in FIG. 4, a semiconductor substrate (planar substantially circular semiconductor thin plate called a semiconductor wafer at this stage) 1 </ b> S is prepared. The semiconductor substrate 1S is made of, for example, silicon single crystal, and has a first main surface (upper surface, front surface) 1Sa and a second main surface (lower surface, back surface) 1Sb located on opposite sides along the thickness direction. .

Next, an insulating film 2 made of, for example, a silicon oxide (SiO ₂ etc.) film is formed (deposited) on the entire surface of the first main surface 1Sa of the semiconductor substrate 1S. The film thickness of the insulating film 2 can be about 400 nm, for example. The insulating film 2 is composed of a TEOS film formed at a relatively low temperature (for example, about 200 ° C.) using, for example, a plasma CVD method. That is, the TEOS film constituting the insulating film 2 is a silicon oxide film formed at a film forming temperature of about 200 ° C. or lower by a plasma CVD method using tetraethoxysilane (TEOS) as a source gas. The TEOS film is an insulating film mainly containing SiO or SiO ₂ .

  Next, a conductor film (first conductor film) 3 including a tungsten (W) film is formed on the insulating film 2. The conductor film (first conductor film) 3 can be formed using, for example, a sputtering method or a CVD (Chemical Vapor Deposition) method. The conductor film 3 may be formed of a titanium nitride (TiN) film instead of the tungsten film. Further, the conductor film 3 may be a laminated film made of a plurality of metal films including a tungsten film or a titanium nitride film, which is sequentially formed on the entire surface of the first main surface 1Sa of the semiconductor substrate 1S.

  Next, as shown in FIG. 5, the conductor film 3 is patterned (processed and selectively removed) using a lithography method, a dry etching method, or the like. A lower electrode wiring M0 (lower electrode M0E) is formed by the patterned conductor film 3. In this way, the lower electrode wiring M0 is formed on the semiconductor substrate 1S (that is, on the insulating film 2). Note that the lithography method (photolithography method) is a method of patterning a resist film into a desired pattern (resist pattern) by a series of steps of coating a resist film (photoresist film), exposure, and development.

  Next, as shown in FIG. 6, for example, silicon oxide is applied to the entire surface of the first main surface 1Sa of the semiconductor substrate 1S (semiconductor wafer) (that is, on the insulating film 2) so as to cover the surface of the lower electrode wiring M0. An insulating film mainly containing is deposited, and this insulating film is etched back (entire etching) by anisotropic dry etching. Thus, the insulating film is left on the side surface (side wall) of the lower electrode wiring M0 (lower electrode M0E) to form the side wall (side wall insulating film) SW in a self-aligning manner, and the upper surface of the lower electrode wiring M0 is exposed. .

  Next, as shown in FIG. 7, the entire surface of the first main surface 1Sa of the semiconductor substrate 1S (ie, on the insulating film 2) is covered with the surface of the lower electrode wiring M0 (lower electrode M0E) and the sidewall SW. Then, an etching stopper film 5 is formed (deposited). The etching stopper film 5 is made of an amorphous (amorphous) silicon film, for example, and can be formed using a relatively low temperature plasma CVD method or the like. The thickness (film thickness) of the etching stopper film 5 is, for example, about 100 nm.

  Subsequently, a sacrificial film 6b made of, for example, a silicon oxide film is formed (deposited) on the entire surface of the first main surface 1Sa of the semiconductor substrate 1S on the etching stopper film 5. The sacrificial film 6b can be formed, for example, by a plasma CVD method, and the thickness (deposition thickness, film thickness) is greater than 200 nm, for example, about 230 nm. The sacrificial film 6b is made of, for example, a TEOS film.

  Here, the reason why the plasma CVD method at a low temperature is used as a method for forming the sacrificial film 6b is that a creep phenomenon occurs in the tungsten (W) film used for the lower electrode M0E due to excessively high heat. This is to prevent a change in composition, deformation or fracture of the tungsten film. Therefore, a thermal CVD method or the like is not suitable as a method for forming the sacrificial film 6b, but other methods may be used as long as the temperature is about 200 ° C. or lower.

  Next, as shown in FIG. 8, the sacrificial film 6b is patterned by a lithography method and a dry etching method to form a sacrificial pattern (sacrificial pattern for forming a cavity) 6 made of the patterned sacrificial film 6b. The sacrificial pattern 6 is a pattern for forming the cavity VR1 and is formed in the sensor region SA. For this reason, the planar shape of the sacrificial pattern 6 is formed in the same planar shape as the cavity VR1. That is, the sacrificial pattern 6 is formed in the region where the cavity VR1 is to be formed in the sensor region SA of the main body region.

  Since the sacrificial pattern 6 is composed of an insulating film such as a silicon oxide film, the sacrificial pattern 6 is compared with the case where the sacrificial film 6b is formed using a conductive film such as a crystalline tungsten film or a titanium nitride film. The upper surface of 6 can be formed flat. Since a conductor film such as a tungsten film or a titanium nitride film is composed of a plurality of grains (crystals), its surface is likely to be uneven, whereas an insulating film such as a silicon oxide film is an amorphous film. Therefore, it is easy to form the upper surface flat. That is, the surface morphology of the conductor film is likely to deteriorate, but an insulating film such as a silicon oxide film has a good surface morphology. By forming the sacrificial pattern 6 using the insulating film, the surface of the sacrificial pattern 6 and The surface of the film formed thereon can be formed in a flat shape.

  Next, as shown in FIG. 9, an etching stopper film 7 is formed (deposited) so as to cover the surface of the sacrificial pattern 6 on the entire surface of the first main surface 1Sa of the semiconductor substrate 1S (that is, on the etching stopper film 5). ) The etching stopper film 7 is made of, for example, an amorphous (amorphous) silicon film or the like, and can be formed using a relatively low temperature plasma CVD method or the like. The thickness (film thickness) of the etching stopper film 7 is, for example, about 100 nm. As described above, since the upper surface of the sacrificial pattern 6 is formed flat, the bottom surface of the etching stopper film 7 in contact with the upper surface of the sacrificial pattern 6 has high flatness.

  Since the lower electrode M0E may include an aluminum (Al) film, the etching stopper films 5 and 7 and the sacrificial film 6b must be formed at a temperature lower than the melting point of aluminum (Al). The etching stopper films 5 and 7 are stopper films for preventing structures other than the sacrificial pattern 6 from being removed by wet etching or the like performed when the sacrificial pattern 6 is removed in a later process.

Next, an insulating film 8 a and a tungsten (W) film are sequentially formed on the etching stopper film 7. Thus, a conductor film (second conductor film) 8 made of a tungsten film is formed on the etching stopper film 7 via the insulating film 8a. The insulating film 8a can be formed by, for example, a plasma CVD method, and the thickness (deposition thickness, film thickness) is, for example, about 100 to 200 nm. Insulating film 8a is, for example, a silicon oxide film formed by TEOS film mainly contains SiO or SiO _2. The insulating film 8a is an insulating film for securing a withstand voltage between an upper electrode M1E (conductor film 8) and a lower electrode M0E (conductor film 3), which will be described later, and the thickness of the insulating film 8a is appropriately set. By determining, the withstand voltage can be adjusted.

  Here, the reason why the plasma CVD method at a low temperature is used as a method of forming the insulating film 8a is to prevent a creep phenomenon from occurring in the tungsten film used for the upper electrode M1E and the lower electrode M0E. Therefore, the method used to form the insulating film 8a is not limited to the plasma CVD method, and other methods may be used as long as the temperature is about 200 ° C. or lower.

  The tungsten film can be formed using, for example, a sputtering method or a CVD method. The conductor film 8 may be formed of a titanium nitride (TiN) film instead of the tungsten film. The conductor film 8 may be a laminated film made of a plurality of metal films including a tungsten film or a titanium nitride film.

  Next, as shown in FIG. 10, the conductor film 8 is patterned (processed and selectively removed) by using a lithography method, a dry etching method, or the like. An upper electrode wiring M1 is formed by the patterned conductor film (second conductor film) 8. The upper electrode wiring M1 includes an upper electrode M1E and a connecting portion M1C (see FIG. 3). Here, a part of the upper electrode wiring M1 in a region immediately above the lower electrode M0E is referred to as an upper electrode M1E. Thereby, the upper electrode wiring M1 is formed on the etching stopper film 7 via the insulating film 8a. The upper electrode wiring M1 is formed on the etching stopper film 7 and includes a patterned conductor film 8.

  As the above-described upper electrode M1E and lower electrode M0E, it is also conceivable to use an aluminum (Al) film or the like in addition to the tungsten (W) film. However, the creep of the aluminum film is likely to occur at a lower temperature than that of the tungsten film, and if the aluminum film undergoes metal fatigue due to high heat, the electrode does not return to its original shape when the membrane is bent, and the vibrator May not vibrate. Therefore, it is desirable that the upper electrode M1E and the lower electrode M0E are composed of a film mainly containing tungsten (W).

Next, as shown in FIG. 11, the upper electrode wiring M1 (upper electrode M1E, patterned conductor film 8) is formed on the entire surface of the first main surface 1Sa of the semiconductor substrate 1S (that is, on the etching stopper film 7). An insulating film 9 is formed (deposited) so as to cover the surface. The insulating film 9 can be formed by, for example, a plasma CVD method, and the thickness (deposition thickness, film thickness) is, for example, about 1500 nm. The insulating film 9 is a silicon oxide film made of, for example, a TEOS film, and mainly contains SiO or SiO ₂ . Since the insulating film 9 is provided for the purpose of increasing the distance between the upper electrode M1E and the lower electrode M0E and an insulating film (passivation film) 11 described later, the insulating film 9 is formed with a relatively thick film thickness. The method used for forming the insulating film 9 is not limited to the plasma CVD method, and other methods may be used as long as the temperature is about 200 ° C. or lower.

  Next, as shown in FIG. 12, the insulating film 9, 8a and the etching stopper film 7 are reached to the sacrificial pattern 6 and a part of the sacrificial pattern 6 is exposed by lithography and dry etching. A simple hole (opening) 10 is formed. The hole 10 is formed at a position overlapping the sacrificial pattern 6 in a plan view, and a part of the sacrificial pattern 6 is exposed at the bottom of the hole 10.

  Next, the sacrifice pattern 6 is selectively removed through the hole 10 using, for example, an aqueous solution of hydrofluoric acid (hydrogen fluoride). Thereby, as shown in FIG. 13, the sacrificial pattern 6 is removed, and a cavity VR <b> 1 is formed between the etching stopper film 5 and the etching stopper film 7. The region where the sacrificial pattern 6 was present becomes the cavity VR1.

  That is, in the sensor region SA of the main body region, the cavity portion VR1 is formed between the opposing surfaces (the removal region of the sacrificial pattern 6) between the lower electrode wiring M0 (lower electrode M0E) and the upper electrode wiring M1 (upper electrode M1E). . In this way, by selectively etching the sacrificial pattern 6 through the hole 10, the cavity portion VR1 can be formed. At this time, since the etching stopper films 5 and 7 made of silicon (Si) cover the sacrifice pattern 6 and hardly dissolve in hydrofluoric acid, the sacrifice pattern 6 made of silicon oxide is selectively removed. can do.

  In the lower electrode wiring M0, the portion facing the upper electrode wiring M1 via the cavity VR1 is the lower electrode M0E, and the portion facing the lower electrode wiring M0 via the cavity VR1 in the upper electrode wiring M1. This is the upper electrode M1E.

Next, as shown in FIG. 14, an insulating film (passivation film) 11 is formed (deposited) on the entire surface (that is, on the insulating film 9) on the first main surface 1Sa of the semiconductor substrate 1S. Thereby, a part of the insulating film 11 can be embedded in the hole 10 and the hole 10 can be closed. The insulating film 11 is made of, for example, a silicon nitride (Si ₃ N ₄ ) film, and can be formed using a plasma CVD method or the like. Moreover, the thickness (film thickness) of the insulating film 11 can be about 400 nm, for example.

  Here, the hole 10 is filled with the insulating film 11. However, after the formation of the hole 10 and before the formation of the insulating film 11, for example, a silicon oxide film is formed on the insulating film 9, and the hole is formed by the silicon oxide film. 10 may be embedded. In this case, the insulating film 11 is formed on the silicon oxide film.

  Next, as shown in FIG. 15, the insulating film 11, 9, 8a and the etching stopper film 7, 5 have an opening 12a where a part of the lower electrode wiring M0 is exposed, and the insulating film 11, 9 has an upper electrode. An opening 12b (not shown in FIG. 15) from which a part of the wiring M1 is exposed is formed by a lithography method and a dry etching method. In this way, the vibrator 20 having an electrostatic variable capacitance configuration is formed.

  Next, as shown in FIG. 3, an insulating film 13 made of, for example, a negative photosensitive polyimide film is formed on the entire surface of the first main surface 1Sa of the semiconductor substrate 1S (that is, on the insulating film 11). Thereafter, openings 14 a and 14 b are formed in the insulating film 13 by exposing and developing the exposed portions of the lower electrode wiring M 0 and the upper electrode wiring M 1. Part of the lower electrode wiring M0 and the upper electrode wiring M1 exposed from the openings 14a and 14b becomes the pads BP1 and BP2.

  Thereafter, the semiconductor chip 1 can be manufactured by cutting individual chip regions from the semiconductor substrate 1S (semiconductor wafer) by dicing. Thereby, the semiconductor device of the present embodiment including the semiconductor chip 1 is completed.

  Next, effects of the semiconductor device and the manufacturing method thereof according to the present embodiment will be described.

In the present embodiment, silicon oxide such as TEOS is used as the material of the sacrifice pattern 6 for forming the cavity VR1 shown in FIG. 3, and amorphous silicon is used as the material of the etching stopper films 5 and 7 covering the sacrifice pattern 6. ing. On the other hand, it is conceivable to use tungsten (W) or titanium nitride (TiN) as the material of the sacrificial pattern 6 and silicon oxide (SiO ₂ or the like) as the material of the etching stopper film. If so, problems as described below arise.

A silicon oxide (SiO ₂ or the like) film has a property of having a lower Young's modulus than a silicon nitride (TiN) film or a silicon (Si) film. For this reason, when the etching stopper film constituting the vibrating portion (membrane) of the vibrator is formed of a silicon oxide film, the Young's modulus of the membrane is lowered, and the membrane is easily bent by vibration. When the Young's modulus of the membrane decreases, the margin of the cavity VR1 (see FIG. 3) during vibration, that is, the distance between the etching stopper film 5 and the etching stopper film 7 provided across the cavity VR1 decreases. There is a high risk that a leak current flows between the upper electrode and the lower electrode via the etching stopper film. At this time, the electrons move in the etching stopper film made of the silicon oxide film, so that the film quality of the etching stopper film is deteriorated.

  When film quality deterioration occurs in the etching stopper film, the etching stopper films do not move when they are in contact with each other or close to each other, and the membrane does not vibrate even when a voltage is applied to the upper and lower electrodes, that is, the upper and lower electrodes. To do. Further, when the quality of the etching stopper film is deteriorated, the withstand voltage of the etching stopper film is lowered, and there is a problem that leakage current is more noticeable.

  For this reason, when silicon oxide having a low Young's modulus is used as the material of the etching stopper film surrounding the cavity, as shown in FIG. 17, in order to increase the rigidity of the membrane including the etching stopper film 7a, For example, it is conceivable to form the insulating film 8b made of a silicon nitride film on the upper electrode M1E. Since the silicon nitride film has a higher Young's modulus than the silicon oxide film, the rigidity of the membrane can be maintained by forming the insulating film 8b with a thickness of about 800 nm. As a result, it is conceivable to prevent the membrane from vibrating excessively and to prevent the occurrence of a leak current that causes electrons in the etching stopper film to move.

  FIG. 17 is a cross-sectional view of a main part of a semiconductor device including a vibrator 20a shown as a comparative example, and shows a structure similar to the cross-sectional view shown in FIG. That is, the upper electrode M1E and the lower electrode M0E are provided to face each other with the cavity VR1 interposed therebetween, and the etching stopper films 5a and 7a are provided between the upper electrode M1E and the lower electrode M0E and the cavity VR1. Are formed respectively. However, unlike the structure shown in FIG. 15, the vibrator 20a shown in FIG. 17 has etching stopper films 5a and 7a made of a TEOS film (silicon oxide film), and an insulating film 8a is provided on the upper electrode M1E. In addition, an insulating film 8b for ensuring rigidity is formed on the upper electrode M1E. On the insulating film 8b, an insulating film 21 made of a silicon oxide film and an insulating film 11a which is a passivation film made of a silicon nitride film are sequentially formed.

  In the cavity VR1 shown in FIG. 17, the sacrificial pattern 6 formed in the process described with reference to FIGS. 7 and 8 is not a silicon oxide film but a tungsten (W) film or a titanium nitride (TiN) film or their It is formed by a laminated film, and then a sacrificial pattern is removed by injecting a solution containing sulfuric acid or potassium hydroxide from the hole 10 shown in FIG.

  As shown in FIG. 17, by providing the insulating film 8b, it is considered that the rigidity of the membrane can be supplemented and the vibration width can be reduced to suppress the deterioration of the etching stopper films 5a and 7a. There is a problem that when the voltage is applied to the upper electrode M1E and the lower electrode M0E, electrons are trapped in the insulating film 8b and the drive voltage changes. The insulating film 8b formed in order to maintain the rigidity of the membrane is thicker than the insulating film 11a and the like, and the amount of accumulated charge is very large. For this reason, when charges are accumulated in the insulating film 8b, the voltage (threshold voltage) at which the vibrator 20a vibrates decreases, and a higher potential difference is not caused between the upper electrode M1E and the lower electrode M0E. The vibrator 20a cannot be operated. However, if the voltage applied to the upper electrode M1E and the lower electrode M0E increases, the charge accumulated in the insulating film 8b also increases, and the etching stopper films 5a and 7a are interposed between the upper electrode M1E and the lower electrode M0E. Through this, a leakage current flows, and the etching stopper films 5a and 7a are significantly deteriorated.

  As described above, when the etching stopper films 5a and 7a are formed of a silicon oxide film and the insulating film 8b made of a silicon nitride film is provided in the membrane in order to compensate for the rigidity, the driving voltage of the vibrator 20a is increased due to charge accumulation. As a result of the shift, the life of the vibrator 20a is reduced, which causes a problem that the reliability of the semiconductor device is lowered. This problem occurs even if an insulating film made of a silicon oxide film or the like is provided between the upper electrode M1E and the insulating film 8b for the purpose of separating the upper electrode M1E and the insulating film 8b.

  In addition, a silicon oxide film such as a TEOS film may contain impurities such as carbon (C) inside due to a manufacturing method. Thus, the silicon oxide film containing impurities has a property of easily trapping charges. As shown in FIG. 17, when a silicon oxide film such as a TEOS film is used as the etching stopper films 5a and 7a surrounding the cavity VR1 of the vibrator 20a, carbon (C) as an impurity exists in the TEOS film. Thus, when a voltage is applied to the upper electrode M1E and the lower electrode M0E, charges are accumulated in the etching stopper films 5a and 7a, and the insulating properties of the etching stopper films 5a and 7a are lowered. For this reason, when the upper electrode M1E and the lower electrode M0E approach when the membrane vibrates, a leakage path is generated in the etching stopper films 5a and 7a in which charges are accumulated, and the etching stopper films 5a and 7a deteriorate due to leakage current flowing. Occurs.

  In response to these problems, the semiconductor device of this embodiment secures the rigidity of the membrane by using silicon (Si) having a Young's modulus higher than that of silicon oxide as the material of the etching stopper films 5 and 7 shown in FIG. doing. This eliminates the need to provide the insulating film 8b shown in the comparative example of FIG. 17 to supplement the rigidity of the membrane. Therefore, even if the insulating film 8b is not provided in the vicinity of the upper electrode, the rigidity of the etching stopper films 5 and 7 made of a silicon film can prevent leakage current from flowing between the upper electrode M1E and the lower electrode M0E. it can. That is, it is possible to prevent the electrons from moving through the etching stopper films 5 and 7 to deteriorate the film quality of the etching stopper films 5 and 7, and the vibrator 20 from operating.

  The insulating film 11 shown in FIG. 3 is made of a silicon nitride film, similar to the insulating film 8b shown in FIG. 17, but the insulating film 11 is sufficiently thinner than the insulating film 8b. By interposing the insulating film 9 shown in FIG. 3, the insulating film 11 can be separated from the upper electrode M1E and the lower electrode M0E, so that charges are accumulated in the silicon nitride film as described with reference to FIG. Can be prevented.

  In addition, by using silicon (Si) having a higher Young's modulus than silicon oxide, it is not necessary to provide a silicon nitride film having a large film thickness such as the insulating film 8b. Therefore, vibration caused by charge accumulation in the silicon nitride film Variations in the threshold voltage of the child can be prevented.

  Further, since a silicon oxide film such as a TEOS film that has a high possibility of containing impurities (for example, C (carbon)) is not used in the etching stopper films 5 and 7, it is possible to suppress charge accumulation in the etching stopper films 5 and 7. And fluctuations in the threshold voltage of the vibrator can be suppressed. Further, the insulating properties are improved by making the etching stopper films 5 and 7 amorphous amorphous semiconductors that do not contain impurities. As described above, the reliability of the semiconductor device can be improved.

  Further, when a conductive film such as a tungsten film or a titanium nitride film is used as a sacrificial pattern for forming the cavity VR1 shown in FIG. 17, the distance between the upper electrode M1E and the lower electrode M0E can be sufficiently increased. There is a problem that leakage current easily flows between the upper electrode M1E and the lower electrode M0E. When the leak current is generated, the change in the capacitance between the lower electrode M0E and the upper electrode M1E cannot be read, and in addition to the problem that the vibrator 20a does not operate normally, the etching stopper film as described above. When the electrons move inside, the film quality of the etching stopper film deteriorates, and there arises a problem that the vibrator 20a does not operate.

  One of the reasons why the distance between the upper and lower electrodes cannot be sufficiently separated when a conductive film such as a tungsten film or a titanium nitride film is used for the sacrificial pattern is that the conductive film such as the tungsten film or the titanium nitride film is thick. It is difficult to form a film. This is because when a conductor film such as a tungsten film or a titanium nitride film is formed with a thickness greater than a certain thickness, the stress generated in the conductor film increases, and the conductor film peels off or the conductor film breaks. This is because problems arise. Therefore, there is a limit to the film thickness of the conductor film.

  The height of the cavity VR1, that is, the distance from the upper surface of the etching stopper film immediately below the cavity VR1 to the lower surface of the etching stopper film immediately above the cavity VR1, is a leakage current between the upper electrode M1E and the lower electrode M0E. In order to prevent flowing, it is necessary to be 230 nm or more. That is, the thickness of the film formed as the sacrificial pattern needs to be 230 nm or more. However, for example, the maximum thickness of a tungsten film formed by using the CVD method is about 200 nm. When the cavity VR1 is formed using the tungsten film as a sacrificial pattern, a margin between the upper and lower electrodes is ensured. This is not possible and the risk of leakage current is increased.

  When a conductor film made of a tungsten film is formed by a sputtering method, or when a laminated film in which a titanium nitride film and a tungsten film are sequentially stacked from the semiconductor substrate side is formed by a sputtering method, the film thickness of the conductor film is 60 to 200 nm. However, the height of the cavity cannot be sufficiently increased even when the cavity is formed using these conductor films as a sacrificial pattern. Titanium nitride has a property that is difficult to dissolve in sulfuric acid hydrate. However, when a tungsten film in contact with the titanium nitride film is dissolved by sulfuric acid hydration, the titanium nitride film is also easily dissolved. Therefore, when a titanium nitride film is used as a sacrificial pattern, it can be considered that a laminated film in which a tungsten film is stacked on the titanium nitride film is used as a sacrificial pattern.

  In contrast, in the present embodiment, as described with reference to FIGS. 7 and 8, a silicon oxide film that is an insulating film is used for the sacrifice pattern 6. Since the silicon oxide film has a smaller stress generated in the film even when formed with a larger film thickness than the above-described conductor film such as a tungsten film or a titanium nitride film, for example, the CVD method is used to increase the thickness to about 1 μm. It is possible to

  In the present embodiment, by using silicon oxide as the material of the sacrificial pattern 6, the sacrificial pattern 6 is thickened to 230 nm or more, and the sacrificial pattern 6 is removed in the process described with reference to FIG. Makes it possible to form a cavity VR1 of 230 nm or more. Thus, it becomes possible to form the cavity VR1 having a large distance (height) from the bottom surface to the top surface, and when the membrane vibrates, the etching stopper film 5 in contact with each of the lower electrode M0E and the upper electrode M1E. , 7 can be prevented from approaching each other. For this reason, it is possible to prevent leakage current from flowing between the lower electrode M0E and the upper electrode M1E via the etching stopper films 5 and 7, and to prevent deterioration of the film quality of the etching stopper films 5 and 7.

  In addition, when a conductive film such as a tungsten film or a titanium nitride film is used for the sacrificial pattern, another reason why the distance between the upper and lower electrodes cannot be sufficiently separated is that the conductive film such as a tungsten film or a titanium nitride film It is difficult to form the bottom surfaces of the etching stopper film 7a and the upper electrode M1E shown in FIG. The top surface of the conductor film is likely to be uneven. A tungsten film, a titanium nitride film, or the like is a conductor film having crystallinity, and each of the plurality of grains (crystal grains) constituting the conductor film has a height. This is because they are not uniform and the top surfaces of the plurality of grains are not flat. Note that FIG. 17 does not show the concavo-convex shapes of the surfaces of the etching stopper film 7a and the upper film.

  When the upper surface of the sacrificial pattern is not flat but has irregularities (poor surface morphology), the bottom surfaces of the etching stopper film 7a and the upper electrode M1E formed thereon are also formed with irregularities. In this case, the lower surface of the etching stopper film 7a in contact with the upper electrode M1E and the surface exposed in the cavity VR1 is entirely at a uniform distance from the etching stopper film 5a in contact with the lower electrode M0E and the lower electrode M0E. It is not formed, and the distance to the lower electrode M0E varies depending on the location.

  When a voltage is applied to the upper electrode M1E and the lower electrode M0E of the vibrator 20a, an electric field concentrates on a part of the lower surface of the concavo-convex etching stopper film 7a and locally passes through the etching stopper films 5a and 7a. Leak current easily flows. When the leak current is generated, the change in the capacitance between the lower electrode M0E and the upper electrode M1E cannot be read, and in addition to the problem that the vibrator 20a does not operate normally, the etching stopper film as described above. When the electrons move inside, the film quality of the etching stopper film deteriorates, and there arises a problem that the vibrator 20a does not operate.

  Even if the surface of the etching stopper film 7a and the upper electrode M1E on the cavity VR1 is uneven due to the unevenness on the upper surface of the sacrificial pattern, the height of the cavity VR1 is sufficiently increased, As described above, leakage current can be prevented from being generated due to electric field concentration. However, as described above, when the sacrificial pattern is formed of a conductor film such as a tungsten film or a titanium nitride film, it is difficult to increase the thickness of the sacrificial pattern. Therefore, the height of the cavity VR1 is sufficiently increased. It is not possible.

  That is, if the sacrificial pattern 6 that can be thickened as described above is used even if the top surface or the bottom surface of the cavity VR1, that is, the top surface of the etching stopper film 5 or the bottom surface of the etching stopper film 7, is uneven, The cavity VR1 having a large distance (height) from the top surface to the top surface can be formed, and the vibration margin of the membrane is increased. For this reason, it is possible to prevent the occurrence of a leakage current due to the concentration of the electric field on a part of the region where the unevenness is formed on the lower surface of the etching stopper film 7. Therefore, by forming the etching stopper films 5 and 7 from a polysilicon film or the like, even if irregularities occur on the surfaces of these films, it is possible to prevent the occurrence of leakage current if the vibration margin is large. Reliability can be improved.

  In contrast, in this embodiment, as described with reference to FIGS. 7 and 8, a silicon oxide film that is an insulating film is used as the sacrificial pattern 6. Since the silicon oxide film is an amorphous insulating film having no crystallinity and is not a film composed of grains, the upper surface thereof can be formed in a flat shape. Therefore, since the lower surface of the etching stopper film 7 (see FIG. 3) formed on the sacrificial pattern 6 and the lower surface of the upper electrode M1E (see FIG. 3) can be formed flat, the bottom surfaces of the etching stopper film and the upper electrode can be formed. Generation of leakage current due to electric field concentration due to the uneven shape can be prevented. Thereby, since the deterioration of the etching stopper films 5 and 7 can be prevented, the reliability of the semiconductor device can be improved.

  As described above, in the present embodiment, the sacrificial pattern 6 (see FIG. 12) for forming the cavity is made of a silicon oxide film, and the etching stopper films 5 and 7 (see FIG. 12) are made of a silicon film. However, the combination of the sacrificial pattern 6 and the etching stopper films 5 and 7 is not limited to this, and other materials can be used as long as the etching stopper films 5 and 7 and the sacrificial pattern 6 have a high etching selectivity. May be used. That is, when removing the sacrificial pattern 6 using a wet etching method or the like, it is only necessary that the members of the etching stopper films 5 and 7 have a property that is difficult to dissolve in the solution used for the wet etching. As described above, the etching stopper films 5 and 7 and the sacrificial pattern 6 may be formed using other materials as long as the materials are selective with respect to etching.

For example, the sacrificial pattern 6 can be a silicon nitride (Si ₃ N ₄ or the like) film, and the etching stopper films 5 and 7 can be silicon germanium (SiGe) films. In this case, in the step described with reference to FIG. 13, the sacrificial pattern 6 is removed using a solution of hot phosphoric acid.

When the sacrificial pattern 6 is a silicon oxide film, the types of films constituting the etching stopper films 5 and 7 are silicon nitride (Si ₃ N ₄ etc.) film, silicon germanium (SiGe) film, silicon carbide ( An SiC) film, a silicon carbonitride (SiCN) film, or the like can be used. Even when the sacrificial pattern 6 and the etching stopper films 5 and 7 are formed using the above materials, in order to prevent the conductor films (electrodes and the like) from being deteriorated, each film is formed at a low temperature (plasma CVD). Method).

Silicon (Si) film, silicon nitride (Si ₃ N ₄ etc.) film, silicon germanium (SiGe) film, silicon carbide (SiC) film or silicon carbonitride (which can be used as a film constituting the etching stopper films 5 and 7 Among the SiCN) films, the silicon film and the silicon germanium film have the advantage that there are fewer charge traps in the inside than the silicon nitride film, silicon carbide film, or silicon carbonitride film, and it is difficult to accumulate charges. Therefore, when a silicon film or a silicon germanium film is used for the etching stopper films 5 and 7, the etching stopper film is compared with a case where a silicon nitride film, a silicon carbide film or a silicon carbonitride film is used for the etching stopper films 5 and 7. It is possible to prevent the occurrence of a leak current through the electrodes 5 and 7, and to prevent the characteristics of the vibrator 20 from being deteriorated due to the accumulation of electric charges in the etching stopper films 5 and 7.

  Next, a case where the semiconductor device (semiconductor chip 1) of the present embodiment is applied to, for example, an ultrasonic echo diagnostic apparatus will be described with reference to FIG. FIG. 16 is a schematic diagram of an ultrasonic echo diagnostic apparatus including the semiconductor device (semiconductor chip 1) of the present embodiment.

  Ultrasonic echo diagnostic equipment is a medical diagnostic equipment that uses the permeability of sound waves and visualizes the inside of a living body that cannot be seen from the outside by using ultrasonic waves that exceed the audible sound range in real time. is there. A probe (probe) 30 of this ultrasonic echo diagnostic apparatus is shown in FIG.

  The probe 30 is an ultrasonic transmission / reception unit. As shown in FIG. 16, the semiconductor chip 1 is attached to the distal end surface of a probe case 30a forming the probe 30 with the first main surface (formation surface of the plurality of vibrators 20) facing outside. Yes. Further, an acoustic lens 30 b is attached to the first main surface side of the semiconductor chip 1.

  In ultrasonic diagnosis, the tip of the probe 30 (acoustic lens 30b side) is applied to the surface of the living body, and then scanning is performed while gradually shifting the position by a minute position. At this time, an ultrasonic pulse of several MHz is transmitted from the probe 30 applied to the body surface into the living body, and a reflected wave (echo or echo) from a tissue boundary having different acoustic impedance is received. Thereby, it is possible to obtain a tomographic image of a living tissue and know information related to a diagnosis target. The distance information of the reflector can be obtained by the time interval from transmitting the ultrasonic wave to receiving it. In addition, information on the presence or quality of the reflector can be obtained from the level or contour of the reflected wave.

  By using the semiconductor chip 1 of this embodiment for the probe 30 of such an ultrasonic echo diagnostic apparatus, the reliability of the probe 30 can be improved.

  Although the invention made by the present inventors has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is effective when applied to a manufacturing technique of a semiconductor device including a vibrator having a cavity between electrodes.

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 1S Semiconductor substrate 1Sa 1st main surface 1Sb 2nd main surface 2 Insulating film 3 Conductive film 5, 5a Etching stopper film 6 Sacrificial pattern 6b Sacrificial film 7, 7a Etching stopper film 8 Conductor films 8a, 8b, 9 Insulating film 10 Holes 11 and 13 Insulating films 12a and 12b Openings 14a and 14b Openings 20 and 20a Vibrator 21 Insulating film 30 Probe 30a Probe case 30b Acoustic lens BP1 and BP2 Pad M0 Lower electrode wiring M0E Lower electrode M1 Upper electrode wiring M1C Connection Part M1E Upper electrode SA Sensor region SW Side wall VR1 Cavity part

Claims (15)

A first conductor film formed on the substrate;
A first film formed on the first conductor film and made of a silicon film or a silicon germanium film;
A second film formed on the first film and made of a silicon film or a silicon germanium film;
A second conductor film formed on the second film;
A cavity formed between the first conductor film and the second conductor film and between the first film and the second film;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the first film and the second film are amorphous films.   The semiconductor device according to claim 1, wherein the first film and the second film are intrinsic semiconductor films.   The semiconductor device according to claim 1, wherein the first film and the second film are exposed in the cavity.   2. The semiconductor device according to claim 1, wherein the first film and the second film have a higher Young's modulus than the silicon oxide film. (A) preparing a substrate;
(B) forming a first conductor film on the substrate;
(C) forming a first film on the first conductor film;
(D) forming a sacrificial film on the first film;
(E) forming a second film on the sacrificial film;
(F) forming a second conductor film on the second film;
(G) opening the second film and forming a hole exposing the sacrificial film;
(H) removing the sacrificial film to form a cavity between the first conductor film and the second conductor film;
Have
The first film and the second film are made of a silicon film or a silicon germanium film,
The method of manufacturing a semiconductor device, wherein the sacrificial film includes a silicon oxide film or a silicon nitride film.   7. The method of manufacturing a semiconductor device according to claim 6, wherein the sacrificial film is an amorphous film.   The method of manufacturing a semiconductor device according to claim 6, wherein the first film and the second film are amorphous films.   The method of manufacturing a semiconductor device according to claim 6, wherein the first film and the second film are intrinsic semiconductor films.   7. The method of manufacturing a semiconductor device according to claim 6, wherein the first film and the second film have a higher Young's modulus than the silicon oxide film.   7. The method of manufacturing a semiconductor device according to claim 6, wherein the first conductor film and the second conductor film contain tungsten. (E1) The method further includes a step of forming a first insulating film on the second film before the step (f),
7. The method of manufacturing a semiconductor device according to claim 6, wherein, in the step (f), the second conductor film is formed on the first insulating film. (F1) Before the step (g), further includes a step of forming a second insulating film on the second conductor film,
7. The method of manufacturing a semiconductor device according to claim 6, wherein in the step (g), the second insulating film and the second film are opened to expose the sacrificial film. 14. The method of claim 13, further comprising: (h1) after the step (h), forming a third insulating film on the second conductive film and filling the hole with the third insulating film. Semiconductor device manufacturing method.   7. The method of manufacturing a semiconductor device according to claim 6, wherein in the step (h), the sacrificial film is removed by using the first film and the second film as an etching stopper film.

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