JP6577653B2 - Ultrasonic probe and manufacturing method thereof - Google Patents

Description

  The present invention relates to an ultrasonic probe and a manufacturing method thereof, and more particularly, to a technique effective when applied to an ultrasonic transducer used therein and a manufacturing method thereof.

  An ultrasonic probe using an ultrasonic transducer is used in various applications such as diagnosis of a tumor in a human body and inspection of a crack generated in a building by transmitting and receiving ultrasonic waves.

  Up to now, ultrasonic probes using the vibration of piezoelectric materials have been used, but due to the recent advancement of MEMS (Micro Electro Mechanical Systems) technology, a capacitive detection type super- A sound transducer (CMUT: Capacitive Micromachined Ultrasonic Transducer) has been developed.

  This CMUT has advantages such as a wider frequency band of ultrasonic waves that can be used or higher sensitivity than conventional ultrasonic transducers using piezoelectric materials. In addition, since it can be manufactured using LSI processing technology, there is an advantage that fine processing is possible.

  For example, FIG. 29 of Patent Document 1 describes a CMUT cell. The CMUT cell includes a lower electrode 103, a lower insulating film 104 on the lower electrode 103, an upper insulating film 106 on the lower insulating film 104, and a lower insulating layer. A cavity 105 between the film 104 and the upper insulating film 106 and an upper electrode 107 on the upper insulating film 106 are provided.

  FIG. 18 of Patent Document 2 describes a CMUT cell. The CMUT cell includes a lower electrode 1008, an insulating film 1010 on the lower electrode 1008, a cavity 1009 between the lower electrode 1008 and the insulating film 1010, In addition, an upper electrode 1011 over the insulating film 1010 is provided.

International Publication No. 2009/154091 Japanese Patent Laid-Open No. 2006-211185

  The CMUT cell studied by the present inventor also has the same structure as that of Patent Document 1, but the following facts have been clarified by the study of the present inventor.

  In the CMUT cell, a bias voltage and a driving voltage signal are applied between the upper electrode and the lower electrode to vibrate the membrane of the CMUT cell and transmit ultrasonic waves. On the other hand, at the time of reception, the membrane is vibrated by the ultrasonic wave that reaches the CMUT, so that the capacitance between the upper electrode and the lower electrode changes. The received ultrasonic wave is detected by the change in capacitance.

  In recent years, as the bias voltage increases, the maximum electric field applied between the upper electrode and the lower electrode reaches an electric field in which an FN (Fowler Nordheim) tunnel current flows in the insulating film between the electrodes. As will be described later, due to this electric field, for example, electrons move in the lower insulating film toward the upper insulating film, and some electrons are captured by the upper insulating film, thereby accumulating the lower insulating film and the upper insulating film. An imbalance occurs in the charge amount. For this reason, it has been found that the detection accuracy of ultrasonic waves at the time of medical examination is lowered, and current signals corresponding to the ultrasonic waves cannot be detected normally.

  The present invention provides an ultrasonic probe with improved ultrasonic detection accuracy.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  An ultrasonic probe according to an embodiment is formed on a substrate, a first electrode formed on the substrate, a first insulating film formed on the first electrode, a first insulating film, A second insulating film that forms a cavity with the first insulating film; and a second electrode that is formed on the second insulating film. The cavity overlaps with the first electrode, the second electrode overlaps with the cavity and the first electrode, and the second insulating film is an insulating film having a higher leakage current than the first insulating film.

  According to one embodiment, in an ultrasonic probe having a CMUT, ultrasonic detection accuracy can be improved.

It is sectional drawing which shows the structural example of basic CMUT. It is a figure which shows the electrostatic capacitance between the upper and lower electrodes of CMUT, and the relationship of a voltage. It is principal part sectional drawing of the ultrasonic probe of this Embodiment. It is a graph which shows the leakage current characteristic of the silicon rich oxide film of this Embodiment. It is a graph which shows the refractive index of the silicon rich oxide film of this Embodiment. It is principal part sectional drawing of the ultrasonic probe of a modification. It is principal part sectional drawing in the manufacturing process of the ultrasonic probe of this Embodiment. FIG. 8 is an essential part cross-sectional view of the ultrasonic probe during a manufacturing step following that of FIG. 7; FIG. 9 is an essential part cross-sectional view of the ultrasonic probe during a manufacturing step following that of FIG. 8; FIG. 10 is an essential part cross-sectional view of the ultrasonic probe during a manufacturing step following that of FIG. 9; FIG. 11 is a fragmentary cross-sectional view of the ultrasonic probe during a manufacturing step following that of FIG. 10; FIG. 12 is an essential part cross-sectional view of the ultrasonic probe during a manufacturing step following that of FIG. 11; It is principal part sectional drawing in the manufacturing process of the ultrasonic probe following FIG. FIG. 14 is an essential part cross-sectional view of the ultrasonic probe during a manufacturing step following that of FIG. 13; FIG. 15 is an essential part cross-sectional view of the ultrasonic probe during a manufacturing step following that of FIG. 14; FIG. 16 is an essential part cross-sectional view of the ultrasonic probe during a manufacturing step following that of FIG. 15; It is drawing which shows the effect of this Embodiment.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.
(Embodiment)
<Basic structure and operation of CMUT>

  The ultrasonic probe according to the present embodiment has a structure called CMUT, and a plurality of CMUT cells are provided on the substrate.

  The basic structure and operation of the CMUT will be described with reference to FIG. FIG. 1 shows a cross-sectional structure of a basic CMUT cell. A lower electrode 102 is formed on an upper layer of the substrate 101 via an insulating film 104a, and a cavity 103 surrounded by a lower insulating film 104b and an upper insulating film 104c is formed on the lower electrode 102. An upper electrode 105 is formed on the upper portion of the cavity 103 via an upper insulating film 104 c, an insulating film 104 d is formed so as to cover the upper electrode 105, and an upper insulating film 104 c on the upper layer of the cavity 103 is formed. The membrane 106 is composed of the upper electrode 105 and the insulating film 104d. In addition, the upper electrode 105, the lower electrode 102, and the dielectric layer composed of the lower insulating film 104b, the cavity 103, and the upper insulating film 104c constitute a variable capacitance element.

  A bias voltage source 108, a drive voltage signal source 109, and a switch 111 are connected in series between the upper electrode 105 and the lower electrode 102. In addition, a bias voltage source 108, a current detection unit 110, and a switch 112 are connected in series between the upper electrode 105 and the lower electrode 102. At the time of transmission, the switch 112 is turned off and the switch 111 is turned on. Then, a bias voltage (DC voltage) and a drive voltage signal (AC voltage) are applied between the upper electrode 105 and the lower electrode 102. Then, an electrostatic force acts between the upper electrode 105 (positive electrode) and the lower electrode 102 (negative electrode), and the membrane 106 vibrates at the frequency of the applied drive voltage signal, thereby transmitting ultrasonic waves.

  When receiving ultrasonic waves, the switch 111 is turned off and the switch 112 is turned on. When the membrane 106 vibrates due to the pressure of the ultrasonic waves that reach the surface of the membrane 106, the capacitance value of the variable capacitance element changes due to the change in the width (thickness) of the cavity 103. That is, a change in the capacitance between the upper electrode 105 and the lower electrode 102 generates a current signal corresponding to the ultrasonic wave. The received ultrasonic wave is detected by detecting this current signal by the current detection means 110.

The transmission efficiency and reception efficiency of ultrasonic waves are also related to the bias voltage applied between the upper electrode 105 and the lower electrode 102. By increasing the bias voltage, the conversion efficiency between vibration energy and electric energy of the CMUT membrane 106 is increased, so that the bias voltage tends to increase.
<Examination of improvement>

  By increasing the bias voltage applied between the upper electrode 105 and the lower electrode 102, the maximum electric field applied to the upper insulating film 104c and the lower insulating film 104b is 5 MV / cm or more, and the insulating film between the upper and lower electrodes is applied to the insulating film. An electric field through which an FN (Fowler Nordheim) tunnel current flows is reached. When the upper electrode 105 is a positive electrode and the lower electrode 102 is a negative electrode, electrons move in the lower insulating film 104b toward the upper insulating film 104c, and some electrons are captured in the lower insulating film 104b and trapped electrons 107a. It becomes. Some electrons are injected into the upper insulating film 104c by the discharge of the cavity 103, and are captured in the upper insulating film 104c to become trapped electrons 107b.

  Normally, the number of trapped electrons 107b in the upper insulating film 104c on the upper electrode (positive electrode) 105 side on which electrons accelerated by high energy collide is equal to the number of trapped electrons 107a in the lower insulating film 104b on the lower electrode (negative electrode) 103 side. More than the number. That is, the number of electrons trapped in each of the upper insulating film 104c and the lower insulating film 104b is unbalanced, and the amount of accumulated charge in the upper insulating film 104c is larger than the amount of accumulated charge in the lower insulating film 104b. The main cause is as follows. That is, since the cavity 103 is discharged, electrons accelerated with high energy collide with the upper insulating film 104c. This is because new defect levels are generated in the surface portion of the upper insulating film 104c (surface portion on the cavity 103 side), and electrons are successively captured in the new levels. The trapped electrons 107b trapped in the deep level are not easily detrapped (disappeared) by the upper electrode 105, which is the positive electrode, and the amount of trapped electrons 107b in the upper insulating film 104c continues to increase. That is, the accumulated charge amount of the upper insulating film 104c is increased as compared with the lower insulating film 104b.

  As described above, an imbalance occurs in the number of electrons (charges) accumulated in each of the upper insulating film 104c and the lower insulating film 104b, so that the voltage that minimizes the capacitance between the electrodes shifts, and the ultrasonic wave It has been confirmed that the problem that the detection accuracy is lowered occurs.

FIG. 2 is a diagram illustrating the relationship between the capacitance between the upper and lower electrodes of the CMUT and the voltage (Vdc). Graph (a) shows an initial state before charges are accumulated in upper insulating film 104c and lower insulating film 104b, and graph (b) shows a case where a large amount of charges are accumulated on upper insulating film 104c. c) is a case where the charge accumulated on the lower insulating film 104b side is large. In the graph (b), the minimum voltage between the electrodes is shifted to the positive side compared to the initial state, and in the graph (c), the minimum voltage is shifted to the negative side. Even if the number of trapped electrons increases, voltage shift does not occur if the number of electrons accumulated in each of the upper insulating film 104c and the lower insulating film 104b is the same.

  The following facts have also been clarified by the study of the present inventor. When the membrane vibrates, the portion with the largest upper and lower operating range is the central portion of the cavity 103. In other words, the central portion has a moment when the cavity height is maximized and a moment when the cavity height is minimized compared to the other portions. When the cavity height is minimized, the electric field applied to this region is maximized, so that the electrons accelerated by the high energy are intensively trapped in a part of the upper insulating film 104c. Further, since the trapped electrons 107b cannot move in the lateral direction in the upper insulating film 104c, the trapped electrons 107b are intensively distributed in the central portion of the upper insulating film 104c. Due to the self-electric field of the trapped electrons 107b, the central portion of the cavity is likely to have a shape like the recess 103a as compared to before the operation.

  The technical idea in the present embodiment will be described below.

The ultrasonic probe of the present embodiment has a plurality of CMUT cells.
<Configuration of CMUT Cell in Embodiment>

  The basic idea in this embodiment is that the number of electrons (charge amount) accumulated in the upper insulating film 104c on the positive electrode side is reduced in the CMUT cell, and the number of electrons (charge) accumulated in the lower insulating film 104b on the negative electrode side is reduced. The difference in the accumulated charge amount is reduced within an allowable range. Specifically, the upper insulating film 104c is a film having a larger leakage current than the lower insulating film 104b. In order to make the leakage currents different, the upper insulating film 104c and the lower insulating film 104b are configured with different film thicknesses, different film qualities, or both.

FIG. 3 is a cross-sectional view of a main part of the ultrasonic probe according to the present embodiment. Specifically, it is a cross-sectional view of the main part of the CMUT cell. As shown in FIG. 3, a lower electrode 102 of a CMUT cell is disposed on an insulating film 302 made of a silicon oxide film formed on a semiconductor substrate (substrate) 301. A cavity 103 is disposed above the lower electrode 102 with a lower insulating film 303 made of a silicon oxide film interposed therebetween. The cavity 103 is disposed so as to overlap the lower electrode 102. An upper insulating film 305 made of a silicon oxide film is disposed so as to surround the cavity 103, and an upper electrode 105 and insulating films 306, 308, and 309 covering the upper electrode 105 are disposed on the upper insulating film 305. ing. The upper electrode 105 overlaps the cavity 103 and the lower electrode 102. The CMUT cell shown in FIG. 3 also operates with the upper electrode 103 as a positive electrode and the lower electrode 102 as a negative electrode, as in FIG. Although not shown, a recess 103 a similar to that shown in FIG. 1 is formed in the center of the cavity 103. The upper electrode 105, the lower electrode 102, and the dielectric layer formed between the lower insulating film 303, the cavity 103, and the upper insulating film 305 located therebetween constitute a variable capacitance element. The membrane 106 includes an upper insulating film 305, an upper electrode 105 , and insulating films 306, 308, and 309.

  The upper electrode 105 and the lower electrode 102 are formed of a metal conductor layer, for example, an aluminum film or an aluminum alloy film or the like as a main conductor film, and a barrier made of, for example, a titanium nitride film or a tungsten nitride film above and below the main conductor film. It consists of the laminated structure which arrange | positioned the film | membrane.

  The silicon oxide film constituting the lower insulating film 303 is a PTEOS film formed by a plasma CVD (Chemical Vapor Deposition) method using TEOS (tetraethoxysilane) as an organic source gas, and has a film thickness of 400 nm, for example. The lower insulating film 303 may be a PSiO film formed by a plasma CVD method using monosilane gas and oxidizing gas.

  The silicon oxide film constituting the upper insulating film 305 is preferably a silicon-rich oxide film having a large leakage current, and the thickness thereof is 100 nm, which is thinner than that of the lower insulating film 303. Here, the silicon-rich oxide film means, for example, a silicon oxide film having a larger silicon composition ratio in the film than the PTEOS film. The silicon-rich oxide film can be expressed as SiOX (X <1.8), and the PTEOS film used as the lower insulating film 303 can be expressed as SiOX (1.9 ≦ X ≦ 2.0). Here, the silicon composition ratio means [Si] / [O].

FIG. 4 is a graph showing the leakage current characteristics of the silicon-rich oxide film of the present embodiment. Here, the optical film thickness is the same. FIG. 5 is a graph showing the refractive index of the silicon-rich oxide film of the present embodiment. Here, the silicon-rich oxide film was formed by a plasma CVD method using SiH 4 gas and N 2 O gas. 4 and 5 show leakage current characteristics and refractive indexes of various silicon-rich oxide films produced by changing the SiH ₄ gas flow rate while keeping the N ₂ O gas flow rate constant. As shown in FIG. 5, since the silicon content in the film increases as the monosilane gas flow rate increases, the refractive index of the silicon-rich oxide film also increases. In FIG. 5, a silicon oxide film having a refractive index higher than that of the PTEOS film is a silicon-rich oxide film. The refractive index was measured by ellipsometry using a He—Ne laser (wavelength λ = 633 nm) light source.

As shown in FIG. 4, for example, when compared at a position of an electric field of 5.3 MV / cm, the leakage current of the silicon-rich oxide film having a monosilane (SiH ₄ ) gas flow rate of 600 cc or more is larger than the leakage current of the PTEOS film. ing. The refractive index of the silicon-rich oxide film having a monosilane gas flow rate of 600 cc is slightly smaller than 1.6 but larger than the refractive index of the PTEOS film. That is, it can be seen from FIGS. 4 and 5 that the leakage current of the silicon-rich oxide film having a refractive index of 1.6 or more is larger than the leakage current of the PTEOS film. A silicon oxide film having a refractive index of 1.5 or less can be said to be a film having a small leakage current. The PTEOS film is classified as a film having a small leakage current. Note that the silicon-rich oxide film has a feature that the wet etching rate for dilute hydrofluoric acid is lower than that of the PTEOS film.

  Therefore, in order to increase the leakage current, it is preferable to use a silicon-rich oxide film having a refractive index of 1.6 or more for the upper insulating film 305. In other words, the upper insulating film 305 is preferably a silicon oxide film having a refractive index of 1.6 or more.

  The thickness of the upper insulating film 305 is preferably smaller than that of the lower insulating film 303. By reducing the thickness of the upper insulating film 305, a film with higher leakage current can be obtained. Further, by increasing the thickness of the lower insulating film 303, the withstand voltage of the variable capacitance element can be improved even if the upper insulating film 305 is thinned.

Although the example in which the upper electrode 105 is a positive electrode and the lower electrode 102 is a negative electrode has been described, the upper electrode 105 may be a negative electrode and the lower electrode 102 may be a positive electrode. In that case, the upper insulating film 305 and the lower insulating film 303 need to be interchanged.
<Features in Embodiment>

  The upper insulating film 305 located on the upper electrode 105 side serving as the positive electrode with respect to the cavity 103 is a film having a larger leakage current than the lower insulating film 303 located on the lower electrode 102 side serving as the negative electrode. That is, the upper insulating film 305 is relatively an insulating film with a large leakage current, and the lower insulating film 303 is an insulating film with a small leakage current. Thereby, the electrons captured by the upper insulating film 305 can be easily detrapped to the upper electrode 105 which is a positive electrode. In other words, since the amount of accumulated charge in the upper insulating film 305 is reduced, the imbalance between the amount of accumulated charges in the upper insulating film 305 and the lower insulating film 303 can be reduced, so that the ultrasonic detection accuracy can be improved.

  FIG. 17 is a graph showing a stress test result of the CMUT cell according to the present embodiment.

  The stress conditions are set as follows. The switch 111 shown in FIG. 1 is turned on, and only the bias voltage (DC voltage) 108 is applied to check the DC voltage (collapse voltage) at which the upper and lower sides of the membrane are in contact. The stress voltage condition is selected and applied so that a value obtained by dividing the maximum voltage of the bias voltage (DC voltage) and the drive voltage signal (AC voltage) by the collapse voltage is 1.1 to 1.2.

As shown in FIG. 17D, in the CMUT cell of the present embodiment, the minimum voltage shift amount (ΔVdc) between the electrodes increases rapidly at the beginning, but then remains constant after that. The upper insulating film 305 is a film having a high trap level density and a shallow trap level trap depth. Initially, the amount of stored charge trapped in the upper insulating film 305 on the positive electrode side increases, but immediately, the charge stored in the upper insulating film 305 is detrapped, so that it does not increase beyond a certain level. Therefore, the upper layer insulating film 305 and the lower layer insulating film 303 are saturated in a state where the accumulated charge amount is balanced.

  FIG. 17E relates to a CMUT cell in which an upper insulating film and a lower insulating film are composed of PTEOS films having the same film thickness. As shown in FIG. 17E, charges (electrons) accumulated in the upper insulating film on the positive electrode side are not easily detrapped because they are trapped in deep trap levels. For this reason, the accumulated charge of the upper insulating film continues to increase, and the minimum voltage shift amount (ΔVdc) between the electrodes also continues to increase.

  By making the thickness of the upper insulating film 305 thinner than the thickness of the lower insulating film 303, the leakage current of the upper insulating film 305 can be made larger than that of the lower insulating film 303. In addition, since the upper insulating film 305 is a film having a large leakage current and is a thin film, the trapped electrons captured in the new defect order described above are easily detrapped by the upper electrode 105, and the upper insulating film 305 The accumulated charge can be reduced.

  By making the thickness of the lower insulating film 303 larger than that of the upper insulating film 305, the breakdown voltage of the variable capacitance element can be improved and the leakage current of the upper insulating film 305 can be increased.

  By making the upper insulating film 305 a silicon oxide film having a silicon composition ratio larger than that of the lower insulating film 303, the leakage current of the upper insulating film 305 can be made larger than that of the lower insulating film 303.

The upper insulating film 305 is a silicon oxide film having a refractive index of 1.6 or more, and the lower insulating film 303 is a silicon oxide film having a refractive index of 1.5 or less, so that the leakage current of the upper insulating film 305 can be reduced. It can be larger than the film 303.
<Modification>

  The modification is characterized in that a conductor layer 601 is added between the upper insulating film 305 and the cavity 103 in FIG. 3 of the above embodiment. Other parts are the same as those in the above embodiment.

  FIG. 6 is a cross-sectional view of a main part of an ultrasonic probe according to a modification. Specifically, it is a sectional view of a CMUT cell of a modification. As shown in FIG. 6, a conductor layer 601 having an outer shape substantially equal to the cavity 103 is disposed on the cavity 103 and below the upper insulating film 305. The conductor layer 601 is made of an amorphous silicon film or a metal film such as a tungsten film or a molybdenum film. The conductor layer 601 is electrically floating.

  The conductor layer 601 has a function of receiving electrons accelerated by high energy by the discharge of the cavity 103 and a function of diffusing the received electrons in the planar direction. Since the accelerated electrons are received by the conductor layer 601, the accelerated electrons do not collide with the upper insulating film 305. Accordingly, a new defect order is not generated on the surface of the upper insulating film 305, and the accumulated charge of the upper insulating film 305 can be reduced. Further, since the electrons received by the conductor layer 601 are diffused in the plane direction, a phenomenon in which charges are accumulated only in the central portion of the cavity 103 can be suppressed as shown in FIG. Therefore, the conductor layer 601 is preferably disposed on the cavity 103 side of the upper insulating film 305.

An amorphous silicon film is precisely a semiconductor, and the mobility of electrons in the film is considerably lower than that of a silicon single crystal or the like. However, in this modification, the conductor layer 601 is used because electrons can move.
<Method for Manufacturing CMUT Cell in the Present Embodiment>

  Next, a method for manufacturing a CMUT cell of an ultrasonic probe in the present embodiment will be described with reference to the drawings. 7-16 is principal part sectional drawing in the manufacturing process of the ultrasonic probe of this Embodiment. Here, a manufacturing method of a CMUT cell having a conductor layer 601 of a modification which is a part of the present embodiment will be described.

  First, as shown in FIG. 7, an insulating film 302 made of a silicon oxide film is deposited on the main surface of a semiconductor substrate (semiconductor wafer) 301 by a plasma CVD method (Chemical Vapor Deposition) to a thickness of 1000 nm. Next, a titanium nitride film, an aluminum alloy film, and a titanium nitride film are stacked over the insulating film 302 by a sputtering method to a thickness of 100 nm, 600 nm, and 100 nm, respectively. Thereafter, the lower electrode 102 is formed by patterning using a photolithography technique and a dry etching technique. The aluminum alloy film is a film obtained by adding a small amount of silicon and copper to aluminum.

  Subsequently, as shown in FIG. 8, a PTEOS film, which is a silicon oxide film serving as the lower insulating film 303, is deposited by 3000 nm on the main surface of the semiconductor substrate 301 including the lower electrode 102 by plasma CVD. Then, as shown in FIG. 9, the lower insulating film 303 on the lower electrode 102 is formed by polishing the PTEOS film using a CMP technique (Chemical Mechanical Polishing). The film thickness of the lower insulating film 303 is 400 nm, for example.

  After that, as shown in FIG. 10, a 300 nm metal film such as aluminum is deposited on the upper surface of the lower insulating film 303 by, for example, sputtering, and then an amorphous silicon film is deposited on the metal film by, for example, plasma CVD. To deposit. Next, the sacrificial layer 1003 made of a metal film and the conductor layer 601 made of an amorphous silicon film are formed on the lower insulating film 303 by patterning the amorphous silicon film and the metal film using a photolithography technique and a dry etching technique. To do. That is, the sacrificial layer 1003 and the conductor layer 601 that overlap with the lower electrode 102 in plan view are formed. The conductor layer 601 and the sacrificial layer 1003 have the same planar pattern. This sacrificial layer 1003 becomes a cavity in a subsequent process.

  Next, as shown in FIG. 11, a silicon-rich oxide film is deposited to a thickness of 100 nm by plasma CVD so as to cover the conductor layer 601, the sacrificial film 1003, and the lower insulating film 303. That is, the upper insulating film 305 made of a silicon-rich oxide film is formed on the lower insulating film 303 so as to cover the conductor layer 601 and the sacrificial layer 1003. Since the upper insulating film 305 has a larger leakage current than the lower insulating film 303, it is important to make the film thickness thinner than the lower insulating film 303.

  Subsequently, as shown in FIG. 12, in order to form the upper electrode 105 of the CMUT cell, a laminated film of a titanium nitride film, an aluminum alloy film, and a titanium nitride film is deposited by sputtering to a thickness of 50 nm, 100 nm, and 50 nm, respectively. Then, the upper electrode 105 is formed by patterning the laminated film using a photolithography technique and a dry etching technique.

  Then, as shown in FIG. 13, an insulating film 306 made of a silicon nitride film is deposited to a thickness of 200 nm so as to cover the upper insulating film 305 and the upper electrode 105 by plasma CVD.

  Next, as illustrated in FIG. 14, an opening 307 reaching the sacrificial layer 1003 is formed in the insulating film 306, the upper insulating film 305, and the conductor layer 601 by using a photolithography technique and a dry etching technique.

  After that, as shown in FIG. 15, the sacrificial layer 1003 is removed with hydrochloric acid through the opening 307, thereby forming the cavity 103.

  Note that the sacrificial layer 1003 may be a film that can be selectively removed with respect to the insulating film covering the sacrificial layer 1003. For example, any metal film that can be removed with hydrochloric acid, sulfuric acid, nitric acid, hydrogen peroxide, or a mixed solution thereof that does not etch a silicon nitride insulating film, a silicon oxide film, or a silicon film may be used. Alternatively, an organic film such as a photoresist can be used as the sacrificial layer 1003, and the sacrificial layer 1003 in that case can be removed by an ashing method using ozone gas or oxygen plasma. Further, when the sacrificial layer 1003 is an organic film, a metal film such as a tungsten film or a molybdenum film can be used as the conductor layer 601. When the sacrificial layer 1003 and the conductor layer 601 are combined as described above, it is possible to prevent the conductor layer 601 from being removed when the sacrificial layer 1003 is removed, so that the manufacturing yield can be improved.

  Subsequently, as shown in FIG. 16, in order to fill the opening 307, an insulating film 308 made of a silicon oxide film is deposited by 400 nm using a plasma CVD method. In this way, the cavity 103 which is a closed space is formed as shown in FIG. The cavity 103 is a space surrounded by the lower insulating film 303, the upper insulating film 305, the conductor layer 601, and the insulating film 308.

  Thereafter, as shown in FIG. 6, an insulating film 309 made of a silicon nitride film is deposited by 400 nm using a plasma CVD method. The insulating film 309 is a protective film for protecting the CMUT from the external atmosphere or stress.

  As described above, the CMUT according to the modification of the present embodiment can be manufactured. In the case of the CMUT cell of this embodiment that does not have the conductor layer 601, the step of forming the conductor layer 601 is omitted. The cavity 103 is a space closed by the lower insulating film 303, the upper insulating film 305, and the insulating film 308.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say. That is, the present invention is not limited to the above-described embodiment, and includes various modifications.

DESCRIPTION OF SYMBOLS 101 Substrate 102 Lower electrode 103 Cavity 103a Recess 104a Insulating film 104b Lower insulating film 104c Upper insulating film 104d Insulating film 105 Upper electrode 106 Membrane 107a, 107b Captured electrons 108 Bias voltage source 109 Driving voltage signal source 110 Current detecting means 111 Switch 112 Switch 301 Semiconductor substrate (substrate)
302 Insulating film 303 Lower insulating film 305 Upper insulating film 306 Insulating film 307 Opening 308 Insulating film 309 Insulating film 601 Conductor layer
1003 sacrificial layer

Claims (14)

A substrate,
A first electrode serving as a negative electrode formed on the substrate;
A first insulating film formed on the first electrode;
A second insulating film formed on the first insulating film and forming a cavity with the first insulating film;
A second electrode serving as a positive electrode formed on the second insulating film;
Have
The cavity overlaps the first electrode, the second electrode overlaps the cavity and the first electrode,
The ultrasonic probe, wherein the second insulating film is a film having a leakage current larger than that of the first insulating film. The ultrasonic probe according to claim 1,
The ultrasonic probe, wherein the first insulating film is made of a first silicon oxide film, and the second insulating film is made of a second silicon oxide film. The ultrasonic probe according to claim 2,
The ultrasonic probe in which a silicon composition ratio of the second silicon oxide film is larger than a silicon composition ratio of the first silicon oxide film. The ultrasonic probe according to claim 2,
The ultrasonic probe, wherein a refractive index of the second silicon oxide film is larger than a refractive index of the first silicon oxide film. The ultrasonic probe according to claim 1, further comprising:
An ultrasonic probe having a bias voltage source connected between the first electrode and the second electrode so that the second electrode is a positive electrode and the first electrode is a negative electrode. The ultrasonic probe according to claim 1, further comprising:
An ultrasonic probe having a conductor layer formed between the cavity and the second insulating film so as to be in contact with the second insulating film. The ultrasonic probe according to claim 6 ,
Before Kishirube layer, an amorphous silicon film, the ultrasonic probe. The ultrasonic probe according to claim 6 ,
Before Kishirube layer, a metal film, the ultrasonic probe. A substrate,
A first electrode serving as a negative electrode formed on the substrate;
A first silicon oxide film formed on the first electrode;
A second silicon oxide film formed on the first silicon oxide film and forming a cavity with the first silicon oxide film;
A second electrode serving as a positive electrode formed on the second silicon oxide film;
Have
The cavity overlaps the first electrode, the second electrode overlaps the cavity and the first electrode,
The ultrasonic probe in which the second silicon oxide film has a larger leakage current than the first silicon oxide film , and the film thickness thereof is smaller than the film thickness of the first silicon oxide film. The ultrasonic probe according to claim 9 , further comprising:
An ultrasonic probe having a bias voltage source connected between the first electrode and the second electrode so that the second electrode is a positive electrode and the first electrode is a negative electrode. The ultrasonic probe according to claim 9 ,
The ultrasonic probe in which a leakage current of the second silicon oxide film is larger than a leakage current of the first silicon oxide film. (A) a step of preparing a substrate;
(B) Ri Do from the first metal film on the substrate, forming a first electrode serving as a negative electrode,
(C) forming a first silicon oxide film on the first electrode;
(D) forming a sacrificial layer on the first silicon oxide film;
(E) forming a second silicon oxide film on the first silicon oxide film so as to cover the sacrificial layer;
(F) forming a second electrode serving as a positive electrode on the second silicon oxide film so as to overlap the sacrificial layer;
(G) forming a first insulating film on the second silicon oxide film so as to cover the second electrode;
(H) forming an opening that reaches the sacrificial layer through the first insulating film and the second silicon oxide film;
(I) forming the cavity by removing the sacrificial layer through the opening;
(J) After the step (i), a step of forming a second insulating film so as to close the opening;
Have
The method of manufacturing an ultrasonic probe, wherein the second silicon oxide film is thinner than the first silicon oxide film. In the manufacturing method of the ultrasonic probe according to claim 12 ,
The ultrasonic probe manufacturing method, wherein a silicon composition ratio of the second silicon oxide film is larger than a silicon composition ratio of the first silicon oxide film. In the manufacturing method of the ultrasonic probe according to claim 12 ,
Between the step (d) and the step (e),
(K) forming an amorphous silicon film on the sacrificial layer;
A method for manufacturing an ultrasonic probe.

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