WO2016189781A1

WO2016189781A1 - Dynamic characteristics test device and dynamic characteristics test method

Info

Publication number: WO2016189781A1
Application number: PCT/JP2016/001414
Authority: WO
Inventors: Yoichi Sakamoto; Nobuyuki Takita
Original assignee: Sintokogio, Ltd.
Priority date: 2015-05-28
Filing date: 2016-03-14
Publication date: 2016-12-01
Also published as: CN107209223A; JP6398873B2; TWI676037B; JP2016223832A; TW201641946A; CN107209223B

Abstract

A dynamic characteristics test device comprises a power source, a reactor, a selection circuit including a first switch unit and a second switch unit connected electrically in series, and an overcurrent preventing circuit configured to consume an energy stored in the reactor. A first connection part electrically connecting the first semiconductor and the second semiconductor, and a second connection part electrically connecting the first switch unit and the second switch unit are electrically connected via the reactor. The overcurrent preventing circuit includes a third switch unit and a first diode connected electrically in series, and a fourth switch unit and a second diode connected electrically in series. A forward direction of the first diode is a direction from the first connection part toward the second connection part, and a forward direction of the second diode is a direction from the second connection part toward the first connection part.

Description

DYNAMIC CHARACTERISTICS TEST DEVICE AND DYNAMIC CHARACTERISTICS TEST METHOD

The present disclosure relates to a dynamic characteristics test device and a dynamic characteristics test method.

In the past, a dynamic characteristics (AC: Alternating Current) test has been conducted as inspection of a power semiconductor module such as an insulated gate bipolar transistor (IGBT: Insulated Gate Bipolar Transistor) (e.g., see PTL 1).

In the dynamic characteristics test, when a device under test (DUT: Device Under Test) is broken or the like, a current continues to flow through the DUT so that an overcurrent may occur. In order to prevent the overcurrent like this, a test device described in PTL 2 comprises a discharge circuit which discharges an energy stored in a coil (reactor). This test device forcibly discharges the energy stored in the reactor by the discharge circuit if the overcurrent is detected.

Japanese Unexamined Patent Publication No. 2013-160572 Japanese Unexamined Patent Publication No. 2007-33042

In a case where a test device described in PTL 1 is used to conduct a dynamic characteristics test on, for example, a power semiconductor module of so-called a 2in1 (also referred to as "2 pack" or the like) type which includes two semiconductors, a current flows bidirectionally through a reactor. Even if a discharge circuit described in PTL 2 is applied to this test device, an overcurrent in one direction flowing through the reactor can be prevented, but an overcurrent in the other direction cannot be prevented.

In the dynamic characteristics test of a device under test including two semiconductors, it is desired to suppress the overcurrent flowing through the device under test in a case where a current may flow bidirectionally through the reactor.

A dynamic characteristics test device according to one aspect of the present disclosure is a dynamic characteristics test device for conducting a dynamic characteristics test on a device under test including a first semiconductor and a second semiconductor connected electrically in series. This dynamic characteristics test device comprises a power source configured to supply a current for the dynamic characteristics test, a reactor that is a load on the first semiconductor and the second semiconductor, a selection circuit including a first switch unit and a second switch unit connected electrically in series and configured to select any of the first semiconductor and the second semiconductor as an object of switching measurement, and an overcurrent preventing circuit connected electrically in parallel with the reactor and configured to consume an energy stored in the reactor. A first connection part and a second connection part are electrically connected via the reactor, the first connection part electrically connecting the first semiconductor and the second semiconductor, and the second connection part electrically connecting the first switch unit and the second switch unit. A positive terminal of the power source is electrically connected with the first switch unit and the first semiconductor, and a negative terminal of the power source is electrically connected with the second switch unit and the second semiconductor. The overcurrent preventing circuit includes a third switch unit and a first diode which are connected electrically in series, and a fourth switch unit and a second diode which are connected electrically in series. The first diode is arranged in a manner such that a forward direction of the first diode is a direction from the first connection part toward the second connection part, and the second diode is arranged in a manner such that a forward direction of the second diode is a direction from the second connection part toward the first connection part.

According to this dynamic characteristics test device, the second switch unit is set to the ON-state so that the first semiconductor is selected as an object of switching measurement, and a current flows through the reactor from the first connection part toward the second connection part in the switching measurement of the first semiconductor. Moreover, the first switch unit is set to the ON-state so that the second semiconductor is selected as an object of switching measurement, and a current flows through the reactor from the second connection part toward the first connection part in the switching measurement of the second semiconductor. In other words, a current may flow bidirectionally through the reactor. Then, in the switching measurement of the first semiconductor, in a case where an overcurrent is detected in the dynamic characteristics test device, the fourth switch unit is set to the ON-state such that a current path is formed which goes round through, for example, the reactor, the fourth switch unit, and the second diode. Then, the energy stored in the reactor is consumed by way of being flowed as the current through this current path. On the other hand, in the switching measurement of the second semiconductor, in a case where an overcurrent is detected in the dynamic characteristics test device, the third switch unit is set to the ON-state such that a current path is formed which goes round through, for example, the reactor, the third switch unit, and the first diode. Then, the energy stored in the reactor is consumed by way of being flowed as the current through this current path. In this way, in the dynamic characteristics test device for the device under test including the first semiconductor and the second semiconductor connected electrically in series, a current flows bidirectionally through the reactor but a further overcurrent can be prevented from flowing through the device under test in both direction. Note that the phrase "electrically connected" as used herein refers to not only a case where two components to be connected are directly connected with each other but also a case where another component which is electrically conductible is connected between two components to be connected. Examples of another component may include a switch unit such as a relay and a transistor.

The overcurrent preventing circuit may include a third diode connected electrically in parallel with the third switch unit, and a fourth diode connected electrically in parallel with the fourth switch unit. The third diode may be arranged in a manner such that a forward direction of the third diode is opposite to the forward direction of the first diode, and the fourth diode may be arranged in a manner such that a forward direction of the fourth diode is opposite to the forward direction of the second diode. In this case, any of the third switch unit and the fourth switch unit is set to the ON-state so that only a current flows unidirectionally through the overcurrent preventing circuit. For this reason, in the switching measurement of the first semiconductor, in a case where an overcurrent is detected in the dynamic characteristics test device, even if the fourth switch unit is set to the ON-state before the second switch unit is set to the OFF-state, a short-circuit current does not flow through the first semiconductor. Moreover, in the switching measurement of the second semiconductor, in a case where an overcurrent is detected in the dynamic characteristics test device, even if the third switch unit is set to the ON-state before the first switch unit is set to the OFF-state, a short-circuit current does not flow through the second semiconductor. Therefore, a restriction on a timing to cause the overcurrent preventing circuit to operate can be reduced, allowing simplification of control.

The first diode and the fourth diode may be the same diode, and the second diode and the third diode may be the same diode. In this case, the third switch unit and the fourth switch unit are switch units different from each other, and are connected electrically in series. Moreover, the first diode is connected electrically in parallel with the fourth switch unit, and the second diode is connected electrically in parallel with the third switch unit, where the forward direction of the first diode and the forward direction of the second diode are opposite to each other. For this reason, any of the third switch unit and the fourth switch unit is set to the ON-state so that only a current flows unidirectionally through the overcurrent preventing circuit. For this reason, in the switching measurement of the first semiconductor, in a case where an overcurrent is detected in the dynamic characteristics test device, even if the fourth switch unit is set to the ON-state before the second switch unit is set to the OFF-state, a short-circuit current does not flow through the first semiconductor. Moreover, in the switching measurement of the second semiconductor, in a case where an overcurrent is detected in the dynamic characteristics test device, even if the third switch unit is set to the ON-state before the first switch unit is set to the OFF-state, a short-circuit current does not flow through the second semiconductor. Therefore, a restriction on a timing to cause the overcurrent preventing circuit to operate can be reduced, allowing simplification of control.

The overcurrent preventing circuit may further include a fifth diode and a sixth diode. The third switch unit and the fourth switch unit may be the same switch unit. An anode of the second diode and a cathode of the first diode may be electrically connected with one end of the reactor, and an anode of the fifth diode and a cathode of the sixth diode may be electrically connected with the other end of the reactor, A cathode of the second diode and a cathode of the fifth diode may be electrically connected via the third switch unit with an anode of the first diode and an anode of the sixth diode. In this case, in the switching measurement of the first semiconductor, in a case where an overcurrent is detected in the dynamic characteristics test device, the third switch unit (fourth switch unit) is set to the ON-state so that a current path is formed which goes round through the reactor, the second diode, the third switch unit (fourth switch unit) and the sixth diode, and thus, an energy stored in the reactor is consumed by way of being flowed as the current through this current path. On the other hand, in the switching measurement of the second semiconductor, in a case where an overcurrent is detected in the dynamic characteristics test device, the third switch unit (fourth switch unit) is set to the ON-state so that a current path is formed which goes round through the reactor, the fifth diode, the third switch unit (fourth switch unit) and the first diode, and thus, an energy stored in the reactor is consumed by way of being flowed as the current through this current path. In this way, a further overcurrent can be prevented from flowing bidirectionally through the device under test.

A dynamic characteristics test device according to another aspect of the present disclosure may further comprises a high-speed breaking circuit configured to cause the overcurrent preventing circuit to consume an energy stored in the reactor. The high-speed breaking circuit may include a fifth switch unit connected electrically in series with the reactor. According to this configuration, in a case where an overcurrent is detected, the fifth switch unit is set to the OFF-state so that a current path different from the overcurrent preventing circuit can be broken. For this reason, an energy stored in the reactor can be flowed as the current through the overcurrent preventing circuit, allowing the energy stored in the reactor to be consumed at a high speed.

A dynamic characteristics test device according to a still another aspect of the present disclosure may further comprise a control device configured to perform switching control between an ON-state and an OFF-state of each of the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit. The control device may set the second switch unit to the ON-state so as to set the first semiconductor to an object of switching measurement, and may set the first switch unit to the ON-state so as to set the second semiconductor to an object of switching measurement. The control device may set the second switch unit to the OFF-state and set the fourth switch unit to the ON-state in response to a current having an electric current amount exceeding a predetermined threshold being detected in making a switching measurement of the first semiconductor. In this case, in response to an overcurrent being detected in the switching measurement of the first semiconductor, an energy stored in the reactor can be consumed by way of being flowed as the current through a current path which goes round through, for example, the reactor, the fourth switch unit, and the second diode.

The control device may set the first switch unit to the OFF-state and set the third switch unit to the ON-state in response to a current having an electric current amount exceeding a predetermined threshold being detected in making a switching measurement of the second semiconductor. In this case, in response to an overcurrent being detected in the switching measurement of the second semiconductor, an energy stored in the reactor can be consumed by way of being flowed as the current through a current path which goes round through, for example, the reactor, the third switch unit, and the first diode.

A dynamic characteristics test method according to a still another aspect of the present disclosure is a dynamic characteristics test method for conducting a dynamic characteristics test on a device under test including a first semiconductor and a second semiconductor connected electrically in series. This dynamic characteristics test method comprises a step of making a switching measurement of the first semiconductor by selecting the first semiconductor as an object of switching measurement, and flowing a current in one direction through a reactor that is a load on the first semiconductor and the second semiconductor, a step of causing an overcurrent preventing circuit to consume an energy stored in the reactor in response to a current having an electric current amount exceeding a predetermined threshold being detected in the step of making the switching measurement of the first semiconductor, a step of making a switching measurement of the second semiconductor by selecting the second semiconductor as an object of switching measurement, and flowing a current in the other direction through the reactor, and a step of causing the overcurrent preventing circuit to consume an energy stored in the reactor in response to a current having an electric current amount exceeding a predetermined threshold being detected in the step of making the switching measurement of the second semiconductor.

According to this dynamic characteristics test method, a current flows through the reactor differently between the switching measurement of the first semiconductor and the switching measurement of the second semiconductor in the directions opposite to each other. In other words, a current may flow bidirectionally through the reactor. Then, in a case where an overcurrent having an electric current amount exceeding a predetermined threshold is detected in the dynamic characteristics test device in the switching measurement of the first semiconductor, the energy stored in the reactor is consumed by the overcurrent preventing circuit, and in a case where an overcurrent exceeding a predetermined threshold is detected in the dynamic characteristics test device in the switching measurement of the second semiconductor, the energy stored in the reactor is consumed by the overcurrent preventing circuit. In this way, in the dynamic characteristics test device for the device under test including the first semiconductor and the second semiconductor connected electrically in series, a current flows bidirectionally through the reactor but a further overcurrent can be prevented from flowing through the device under test in both direction.

According to the present disclosure, it is possible to suppress the overcurrent flowing through the device under test in a case where a current may flow bidirectionally through the reactor.

Fig. 1 is a circuit diagram schematically illustrating a dynamic characteristics test device according to an embodiment. Fig. 2 is a timing chart for N-side switching measurement in the dynamic characteristics test device in Fig. 1. Fig. 3 is a diagram illustrating a current path at switch-on in the N-side switching measurement in Fig. 2. Fig. 4 is a diagram illustrating a current path at switch-off in the N-side switching measurement in Fig. 2. Fig. 5 is a diagram illustrating a current path at regenerating energy in the N-side switching measurement in Fig. 2. Fig. 6 is a timing chart for P-side switching measurement in the dynamic characteristics test device in Fig. 1. Fig. 7 is a diagram illustrating a current path at switch-on in the P-side switching measurement in Fig. 6. Fig. 8 is a diagram illustrating a current path at switch-off in the P-side switching measurement in Fig. 6. Fig. 9 is a diagram illustrating a current path at regenerating energy in the P-side switching measurement in Fig. 6. Fig. 10 is a timing chart for the N-side switching measurement in a comparative example. Fig. 11 is a timing chart for the P-side switching measurement in a comparative example. Fig. 12 is a timing chart for the N-side switching measurement including an overcurrent preventing process in the dynamic characteristics test device in Fig. 1. Fig. 13 is a diagram illustrating a current path at the overcurrent preventing process in the N-side switching measurement in Fig. 12. Fig. 14 is a timing chart for the P-side switching measurement including the overcurrent preventing process in the dynamic characteristics test device in Fig. 1. Fig. 15 is a diagram illustrating a current path at the overcurrent preventing process in the P-side switching measurement in Fig. 14. Fig. 16 is a timing chart for the N-side switching measurement including the overcurrent preventing process using a high-speed breaking circuit in the dynamic characteristics test device in Fig. 1. Fig. 17 is a diagram illustrating a current path at the overcurrent preventing process using the high-speed breaking circuit in the N-side switching measurement in Fig. 16. Fig. 18 is a timing chart for the P-side switching measurement including the overcurrent preventing process using the high-speed breaking circuit in the dynamic characteristics test device in Fig. 1. Fig. 19 is a diagram illustrating a current path at the overcurrent preventing process using the high-speed breaking circuit in the P-side switching measurement in Fig. 18. Fig. 20 is a timing chart for N-side short circuit capability measurement in the dynamic characteristics test device in Fig. 1. Fig. 21 is a timing chart for P-side short circuit capability measurement in the dynamic characteristics test device in Fig. 1. Fig. 22 is a circuit diagram showing a modification example of the dynamic characteristics test device in Fig. 1. Fig. 23 is a diagram illustrating a current path at the overcurrent preventing process in the N-side switching measurement in the dynamic characteristics test device in Fig. 22. Fig. 24 is a diagram illustrating a current path at the overcurrent preventing process in the P-side switching measurement in the dynamic characteristics test device in Fig. 22. Fig. 25 is a diagram for comparing the overcurrent preventing process in the dynamic characteristics test device in Fig. 1 with the overcurrent preventing process in the dynamic characteristics test device in Fig. 22. Fig. 26 is a circuit diagram showing another modification example of the dynamic characteristics test device in Fig. 1.

Hereinafter, a description is given of an embodiment according to the present disclosure with reference to the drawings. Note that in description of the drawings the same components are designated by the same reference signs, and the duplicated description is omitted.

Fig. 1 is a circuit diagram schematically illustrating a dynamic characteristics test device according to an embodiment. As shown in Fig. 1, a dynamic characteristics test device 1 is a device for conducting a dynamic characteristics test on a DUT 50, and includes a testing circuit 10, an overcurrent detecting circuit 20, and a control device 30. The dynamic characteristics test device 1 makes, as a dynamic characteristics test, a switching measurement, a short circuit capability measurement (SC measurement) and the like. In the switching measurement, IGBT characteristics and diode characteristics may be measured. Examples of the IGBT characteristics include rise time, fall time, on-delay time, off-delay time, off-surge voltage, gate charge, on-loss, and off-loss. Examples of the diode characteristics include reverse recovery time, reverse recovery current, and reverse recovery energy.

The DUT 50, which is a device under test for the dynamic characteristics test device 1, is a power semiconductor module of a 2in1 type including two semiconductors connected electrically in series. Specifically, the DUT 50 includes transistors Qdp and Qdn (first semiconductor and second semiconductor), and diodes Ddp and Ddn. The transistors Qdp and Qdn each are an IGBT. An emitter of the transistor Qdp and a collector of the transistor Qdn are electrically connected with each other. Cathodes of the diodes Ddp and Ddn are electrically connected with the collectors of the transistors Qdp and Qdn, respectively, and anodes of the diodes Ddp and Ddn are electrically connected with the emitters of the transistors Qdp and Qdn, respectively. In other words, the transistors Qdp and Qdn are connected electrically in series and in the same direction, the diode Ddp is a free wheel diode connected electrically in parallel with transistor Qdp, and the diode Ddn is a free wheel diode connected electrically in parallel with the transistor Qdn. The DUT 50 has a P terminal, an O terminal, and an N terminal. The P terminal is electrically connected with the collector of the transistor Qdp and the cathode of the diode Ddp, the N terminal is electrically connected with the emitter of the transistor Qdn and the anode of the diode Ddn, and the O terminal is electrically connected with the emitter of the transistor Qdp, the collector of the transistor Qdn, the anode of the diode Ddp and the cathode of the diode Ddn. In other words, the O terminal is electrically connected with a connection part Cd (first connection part) electrically connecting the transistors Qdp and Qdn. For example, the DUT 50 may be used for a one-phase inverter circuit, the transistor Qdp may be used for an upper arm, and the transistor Qdn may be used for a lower arm.

A testing circuit 10 is a circuit for conducting the dynamic characteristics test on the DUT 50. The testing circuit 10 includes a power source capacitor 11, a main switch unit 12, a selection circuit 13, an overcurrent preventing circuit 14, a high-speed breaking circuit 15, a selection circuit 16, and a reactor L. The power source capacitor 11 is a power source supplying current for the dynamic characteristics test to the testing circuit 10. As the power source capacitor 11, a film capacitor excellent in frequency characteristics is used, for example. If energy (electric charge) stored in the power source capacitor 11 is reduced, the power source capacitor 11 is connected to a high-voltage power supply not shown so as to be charged by the high-voltage power supply.

The main switch unit 12 is a circuit for switching between breaking and supplying of the current from the power source capacitor 11 to the DUT 50 (transistor Qdp or transistor Qdn). The main switch unit 12 includes a transistor Qp and a diode Dp. The transistor Qp is an IGBT. A cathode of the diode Dp is electrically connected with a collector of the transistor Qp, and an anode of the diode Dp is electrically connected with an emitter of the transistor Qp. In other words, the diode Dp is a free wheel diode connected electrically in parallel with the transistor Qp. The collector of the transistor Qp is electrically connected with a plus terminal (positive terminal) of the power source capacitor 11, and the emitter of the transistor Qp is electrically connected with a collector of a transistor Qhp, a cathode of a diode Dhp, and one end of a switch SWp which are described later, and the P terminal of DUT 50.

The selection circuit 13 is a circuit for selecting any one of the transistors Qdp and Qdn included in the DUT 50 as an object of switching measurement. The selection circuit 13 includes transistors Qhp and Qhn (first switch unit and second switch unit), and diodes Dhp and Dhn. The transistors Qhp and Qhn each are an IGBT. Cathodes of the diodes Dhp and Dhn are electrically connected with collectors of the transistors Qhp and Qhn, respectively, and anodes of the diodes Dhp and Dhn are electrically connected with emitters of the transistors Qhp and Qhn, respectively. In other words, the diode Dhp is a free wheel diode connected electrically in parallel with the transistor Qhp, and the diode Dhn is a free wheel diode connected electrically in parallel with the transistor Qhn. The emitter of the transistor Qhp and the collector of the transistor Qhn are electrically connected with each other, and are electrically connected with a collector of a transistor Qcf and a cathode of a diode Dcf which are described later. In other words, the transistors Qhp and Qhn are connected electrically in series and in the same direction, and a connection part Cs (second connection part) electrically connecting the transistors Qhp and Qhn is electrically connected with the high-speed breaking circuit 15 and the O terminal of the DUT 50 via the reactor L. The collector of the transistor Qhp is electrically connected with the emitter of the transistor Qp, the anode of the diode Dp, one end of the switch SWp, and the P terminal of the DUT 50. The emitter of the transistor Qhn is electrically connected with a minus terminal (negative terminal) of the power source capacitor 11, the other end of a switch SWn, and the N terminal of the DUT 50.

The overcurrent preventing circuit 14 is a circuit for consuming the energy stored in the reactor L. The overcurrent preventing circuit 14 is provided electrically in parallel with the reactor L. The overcurrent preventing circuit 14 includes transistors Qif and Qir (fourth switch unit and third switch unit), and diodes Dif and Dir. The transistors Qif and Qir each are an IGBT. Cathodes of the diodes Dif and Dir are electrically connected with collectors of the transistors Qif and Qir, respectively, and anodes of the diodes Dif and Dir are electrically connected with emitters of the transistors Qif and Qir, respectively. In other words, the diode Dif (first diode, fourth diode) is a free wheel diode connected electrically in parallel with the transistor Qif, and the diode Dir (second diode, third diode) is a free wheel diode connected electrically in parallel with the transistor Qir. The emitter of the transistor Qif and the emitter of the transistor Qir are electrically connected with each other. In other words, the transistors Qif and Qir are connected electrically in series with each other and in directions opposite to each other. The collector of the transistor Qif is electrically connected with a collector of a transistor Qcr, and a cathode of a diode Dcr which are described later, and one end of the reactor L. The collector of the transistor Qir is electrically connected with the other end of the reactor L, the other end of the switch SWp, one end of the switch SWn, and the O terminal of the DUT 50.

The high-speed breaking circuit 15 is a circuit for consuming the energy stored in the reactor L at high speed by the overcurrent preventing circuit 14. The high-speed breaking circuit 15 is provided electrically in series to the reactor L. The high-speed breaking circuit 15 includes the transistors Qcf and Qcr (fifth switch unit) and the diodes Dcf and Dcr. The transistors Qcf and Qcr each are an IGBT. The cathodes of the diodes Dcf and Dcr are electrically connected with the collectors of the transistors Qcf and Qcr, respectively, and anodes of the diodes Dcf and Dcr are electrically connected with emitters of the transistors Qcf and Qcr, respectively. In other words, the diode Dcf is a free wheel diode connected electrically in parallel with the transistor Qcf, and the diode Dcr is a free wheel diode connected electrically in parallel with the transistor Qcr. The emitter of the transistor Qcf and the emitter of the transistor Qcr are electrically connected with each other. In other words, the transistors Qcf and Qcr are connected electrically in series with each other and in directions opposite to each other. The collector of the transistor Qcf is electrically connected with the emitter of the transistor Qhp, the collector of the transistor Qhn, the anode of the diode Dhp, and the cathode of the diode Dhn. The collector of the transistor Qcr is electrically connected with the collector of the transistor Qif, the cathode of the diode Dif, and one end of the reactor L.

The selection circuit 16 is a circuit for selecting any one of the transistors Qdp and Qdn included in the DUT 50 as an object of short circuit capability measurement. The selection circuit 16 includes the switches SWp and SWn. The switches SWp and SWn each are a relay. One end of the switch SWp is electrically connected with the emitter of the transistor Qp, the anode of the diode Dp, the collector of the transistor Qhp, the cathode of the diode Dhp, and the P terminal of the DUT 50. The other end of the switch SWp and one end of the switch SWn are electrically connected with each other, and are electrically connected with the other end of the reactor L, the collector of the transistor Qir, the cathode of the diode Dir, and the O terminal of the DUT 50. The other end of the switch SWn is electrically connected with the minus terminal of the power source capacitor 11, the emitter of the transistor Qhn, the anode of the diode Dhn, and the N terminal of the DUT 50.

The reactor L is a load for the dynamic characteristics test. In other words, the reactor L is a load on the transistors Qdp and Qdn. One end of the reactor L is electrically connected with the collector of the transistor Qcr and the cathode of the diode Dcr, and the other end of the reactor L is electrically connected with the O terminal of the DUT 50.

The overcurrent detecting circuit 20 is a circuit for detecting an overcurrent flowing through the testing circuit 10 and the DUT 50. The overcurrent detecting circuit 20 includes a current sensor 21, a current sensor 22, a comparator 23 and a comparator 24.

The current sensor 21 is a sensor for detecting a current value of a current flowing through the testing circuit 10 and the DUT 50 at N-side switching measurement. The current sensor 21 is provided in the vicinity of an N terminal of a wiring connecting the N terminal of the DUT 50 with the minus terminal of the power source capacitor 11. The current sensor 21 outputs the detected current value to the comparator 23. The current sensor 22 is a sensor for detecting a current value of a current flowing through the testing circuit 10 and DUT 50 at P-side switching measurement. The current sensor 22 is provided in the vicinity of a P terminal of a wiring connecting the P terminal of the DUT 50 with the emitter of the transistor Qp. The current sensor 22 outputs the detected current value to the comparator 24.

The comparator 23 compares the current value detected by the current sensor 21 with an N-side overcurrent threshold Ref_N to output a comparative result to the control device 30. The overcurrent threshold Ref_N is a value predefined for detecting an overcurrent. The comparator 23 receives the N-side overcurrent threshold Ref_N input to a plus terminal thereof and the current value detected by the current sensor 21 input to a minus terminal thereof. In this case, the comparator 23 outputs a high level output signal to the control device 30 if the current value detected by the current sensor 21 is equal to or less than the overcurrent threshold Ref_N, and outputs a low level output signal to the control device 30 if the current value detected by the current sensor 21 is more than the overcurrent threshold Ref_N.

The comparator 24 compares the current value detected by the current sensor 22 with a P-side overcurrent threshold Ref_P to output a comparative result to the control device 30. The overcurrent threshold Ref_P is a value predefined for detecting an overcurrent. The comparator 24 receives the P-side overcurrent threshold Ref_P input to a plus terminal thereof and the current value detected by the current sensor 22 input to a minus terminal thereof. In this case, the comparator 24 outputs a high level output signal to the control device 30 if the current value detected by the current sensor 22 is equal to or less than the overcurrent threshold Ref_P, and outputs a low level output signal to the control device 30 if the current value detected by the current sensor 22 is more than the overcurrent threshold Ref_P.

The control device 30 is a controller performing switching control for switching between an ON-state (conduction state) and an OFF-state (cutoff state) of the transistors Qp, Qhp, Qhn, Qif, Qir, Qcf, Qcr, Qdp, and Qdn, and the switches SWp and SWn. The control device 30 outputs gate signals Sqp, Sqhp, Sqhn, Sqif, Sqir, Sqcf, Sqcr, Sqdp, and Sqdn to the transistors Qp, Qhp, Qhn, Qif, Qir, Qcf, Qcr, Qdp, and Qdn, respectively to switch between ON-state and the OFF-state of each transistor. The control device 30 outputs relay signals Sswp and Sswn to the switches SWp and SWn, respectively to switch between the ON-state and the OFF-state of each switch. The switching control by the control device 30 is described in detail in each measurement below. Note that the ON-state of the transistor means that a state between the collector and the emitter is electrically in the conduction state, and the OFF-state of the transistor means that a state between the collector and the emitter is electrically in the cutoff state. Moreover, if the transistor is an IGBT, the ON-state and the OFF-state are switched by a voltage between the gate and the emitter. In the following description, for convenience sake, assume that the transistor is brought into the ON-state in a case where a high level gate signal is supplied to the transistor, and the transistor is brought into the OFF-state in a case where a low level gate signal is supplied to the transistor.

(Switching measurement)
Next, a description is given of switching measurement using the dynamic characteristics test device 1. First, a description is given of switching measurement of the transistor Qdn (also referred to as "N-side switching measurement" in some cases). Fig. 2 is a timing chart for the N-side switching measurement in the dynamic characteristics test device 1. Fig. 3 is a diagram illustrating a current path at switch-on in the N-side switching measurement. Fig. 4 is a diagram illustrating a current path at switch-off in the N-side switching measurement. Fig. 5 is a diagram illustrating a current path at regenerating energy in the N-side switching measurement.

Note that in the switching measurement, since the relay signals Sswp and Sswn are always set at the low level, and the switches SWp and SWn are always in the OFF-state, the description of the relay signal and the switch is omitted at each step. Moreover, in the following description, a description is given with an assumption that a current supplied from the power source capacitor 11 is designated by Ic, currents flowing through the transistors Qp, Qhp, Qhn, Qif, Qir, Qcf, Qcr, Qdp, and Qdn are currents Iqp, Iqhp, Iqhn, Iqif, Iqir, Iqcf, Iqcr, Iqdp, and Iqdn, respectively, and a current flowing through the reactor L is a current IL. Additionally, assume that a current flowing through each transistor has a positive value if the current flows from the collector to the emitter, and has a negative value if flowing from the emitter to the collector or from the anode of the free wheel diode to the cathode (forward direction). Assume that the current flowing through the reactor L has a positive value if the current flowing toward the O terminal of the DUT 50, and a negative value if flowing toward the opposite direction. The respective steps are illustrated to have the same length, but times taken for the respective steps are not necessarily the same and may be adjusted as needed. At each step, timings for the switching control of the respective transistors may be the same or different.

As shown in Fig. 2, at step ST11, the control device 30 sets all of the gate signals Sqp, Sqhp, Sqhn, Sqif, Sqir, Sqcf, Sqcr, Sqdp, and Sqdn to the low level and outputs them. For this reason, all of the transistors Qp, Qhp, Qhn, Qif, Qir, Qcf, Qcr, Qdp, and Qdn are in the OFF-state such that a current does not flow through any transistor. Moreover, an energy Ec (electric charge) of the power source capacitor 11 is in a full charge state, for example.

Subsequently, at step ST12, the control device 30 sets the gate signals Sqp, Sqhp, Sqcf, Sqcr, and Sqdn to the high level and other gate signals than these to the low level, and outputs them. This makes the transistors Qp, Qhp, Qcf, Qcr, and Qdn be in the ON-state and other transistors than these be in the OFF-state. At this time, as shown in Fig. 3, a current path Pn1 is formed which passes from the plus terminal of the power source capacitor 11 through the transistor Qp, transistor Qhp, transistor Qcf, transistor Qcr, reactor L, and transistor Qdn in this order and returns to the minus terminal of the power source capacitor 11 such that a current supplied from the power source capacitor 11 flows through the current path Pn1. In this state, electric current amounts of the currents Ic, Iqp, Iqhp, Iqcf, -Iqcr, IL, and Iqdn increase with time while the energy Ec of the power source capacitor 11 decreases with time. Additionally, the currents Iqhn, Iqif, Iqir, and Iqdp do not flow through the transistors Qhn, Qif, Qir, and Qdp. In other words, at step ST12, the control device 30 sets the transistor Qhp to the ON-state so as to set the transistor Qdn to an object of switching measurement, and sets the transistors Qp, Qcf, and Qcr to the ON-state to supply a current from the power source capacitor 11 to the transistor Qdn.

Subsequently, at step ST13, the control device 30 sets the gate signals Sqp, Sqhp, Sqcf, and Sqcr to the high level and other gate signals than these to the low level, and outputs them. In other words, only the gate signal Sqdn is changed from the high level to the low level differently from step ST12, and other gate signals than this are not changed. This makes the transistors Qp, Qhp, Qcf, and Qcr be in the ON-state and other transistors than these be in the OFF-state. At this time, as shown in Fig. 4, a current path Pn2 is formed which goes round through the transistor Qhp, transistor Qcf, transistor Qcr, reactor L, and diode Ddp in this order, and the current having been flowing through the current path Pn1 immediately before step ST13 flows through the current path Pn2. For this reason, since the electric current amounts of the currents Ic, Iqp, and Iqdn become 0 and a current is not supplied from the power source capacitor 11, the energy Ec does not change. At this time, since the energy is consumed by resistance components or the like of the transistor Qhp, transistor Qcf, transistor Qcr, reactor L, and diode Ddp, the electric current amounts of the currents Iqhp, Iqcf, -Iqcr, and IL, and the current -Iqdp flowing through the diode Ddp gradually decrease with time from the electric current amount of the current having been flowing through the current path Pn1 immediately before step ST13. Moreover, the electric current amounts of the Iqhn, Iqif, and Iqir remain 0.

Subsequently, at step ST14 as is at step ST12, the control device 30 sets the gate signals Sqp, Sqhp, Sqcf, Sqcr, and Sqdn to the high level and other gate signals than these to the low level, and outputs them. In other words, only the gate signal Sqdn is changed from the low level to the high level differently from step ST13, and other gate signals than this are not changed. This forms the current path Pn1 so that the current having been flowing through the current path Pn2 immediately before step ST14 and the current supplied from the power source capacitor 11 flow through the current path Pn1. At this time, the electric current amounts of the currents Ic, Iqp, Iqhp, Iqcf, -Iqcr, IL, and Iqdn further increase with time from the electric current amount of the current having been flowing through the current path Pn2 immediately before step ST14 while the energy Ec of the power source capacitor 11 further decreases with time. Additionally, the currents Iqhn, Iqif, Iqir, and Iqdp do not flow through the transistors Qhn, Qif, Qir, and Qdp.

Subsequently, at step ST15 as is at step ST13, the control device 30 sets the gate signals Sqp, Sqhp, Sqcf, and Sqcr to the high level and other gate signals than these to the low level, and outputs them. In other words, only the gate signal Sqdn is changed from the high level to the low level differently from step ST14, and other gate signals than this are not changed. This forms the current path Pn2 so that the current having been flowing through the current path Pn1 immediately before step ST15 flows through the current path Pn2. At this time, as is at step ST13, the electric current amounts of the currents Ic, Iqp, and Iqdn become 0 and the electric current amounts of the currents Iqhp, Iqcf, -Iqcr, IL, and -Iqdp gradually decrease with time. Moreover, the electric current amounts of the currents Iqhn, Iqif, and Iqir remain 0. In addition, since current is not supplied from the power source capacitor 11, the energy Ec does not change. At this point of time, a waveform required for the N-side switching measurement is obtained. In other words, by the process from step ST12 to the transistor Qdn is set to the OFF-state at step ST15, a waveform required for the switching measurement of the transistor Qdn is obtained. In this sense, the process from step ST12 to the transistor Qdn is set to the OFF-state at step ST15 can be said to be narrow-sense switching measurement of the transistor Qdn.

After that, the control device 30 changes the gate signal Sqhp from the high level to the low level. This makes the transistors Qp, Qcf, and Qcr be in the ON-state and other transistors than these be in the OFF-state. At this time, as shown in Fig. 5, a current path Pn3 is formed which passes from the minus terminal of the power source capacitor 11 through the diode Dhn, transistor Qcf, transistor Qcr, reactor L, diode Ddp, and transistor Qp in this order and returns to the plus terminal of the power source capacitor 11, and the current having been flowing through the current path Pn2 immediately before switching the gate signal Sqhp to the low level flows through the current path Pn3. For this reason, the electric current amount of the current Iqhp becomes 0. Then, since the current path Pn3 travels from the minus terminal to plus terminal of the power source capacitor 11, the power source capacitor 11 is charged and the energy Ec increases with time while the electric current amounts of the currents -Iqhn (current flowing through the diode Dhn), Iqcf, -Iqcr, IL, -Iqdp, -Iqp, and -Ic (current flowing from the minus terminal of the power source capacitor 11 to the plus terminal) decrease with time. Moreover, the electric current amounts of the currents Iqdn, Iqif, and Iqir remain 0.

Subsequently, at step ST16, a state the same as at step ST15 is continued so that the electric current amount of the current flowing through the current path Pn3 becomes 0 and the energy Ec of the power source capacitor 11 recovers to an almost full charge state.

Subsequently, at step ST17, the control device 30 sets all of the gate signals Sqp, Sqhp, Sqhn, Sqif, Sqir, Sqcf, Sqcr, Sqdp, and Sqdn to the low level and outputs them. For this reason, all of the transistors Qp, Qhp, Qhn, Qif, Qir, Qcf, Qcr, Qdp, and Qdn are in the OFF-state such that a current does not flow through any transistor. In this way, the N-side switching measurement ends. Note that the electric current amount of the current flowing through the current path Pn3 may be detected to be a predetermined threshold or less by a detecting circuit or the like not shown, and the control device 30 may detect by use of an output signal from the detecting circuit that the electric current amount of the current flowing through the current path Pn3 becomes almost 0 (energy regeneration process completion). A predetermined threshold is set to 0 or a value slightly larger than 0, for example. Then, the control device 30 may perform a process at step ST17 in response to detecting the energy regeneration process completion.

As described above, the control device 30, at the start of the N-side switching measurement, sets the transistors Qp, Qhp, Qcf, and Qcr to the ON-state and sets the transistor Qhp to the OFF-state in response to completion of taking in the waveform in the N-side switching measurement to regenerate the energy having been used for the N-side switching measurement. Then, the control device 30, after regenerating the energy having been used for the N-side switching measurement, sets the transistor Qp, Qcf, and Qcr to the OFF-state. Therefore, at the end of the N-side switching measurement, the energy Ec is in the almost full charge state so that the power source capacitor 11 does not need to be charged by the high-voltage power supply for the next measurement.

Next, a description is given of switching measurement of the transistor Qdp (also referred to as "P-side switching measurement" in some cases). Fig. 6 is a timing chart for the P-side switching measurement in the dynamic characteristics test device 1. Fig. 7 is a diagram illustrating a current path at switch-on in the P-side switching measurement. Fig. 8 is a diagram illustrating a current path at switch-off in the P-side switching measurement. Fig. 9 is a diagram illustrating a current path at regenerating energy in the P-side switching measurement.

As shown in Fig. 6, step ST21 is the same as step ST11 in Fig. 2, and thus, the description thereof is omitted. Subsequently, at step ST22, the control device 30 sets the gate signals Sqp, Sqhn, Sqcf, Sqcr, and Sqdp to the high level and other gate signals than these to the low level, and outputs them. This makes the transistors Qp, Qhn, Qcf, Qcr, and Qdp be in the ON-state and other transistors than these be in the OFF-state. At this time, as shown in Fig. 7, a current path Pp1 is formed which passes from the plus terminal of the power source capacitor 11 through the transistor Qp, transistor Qdp, reactor L, transistor Qcr, transistor Qcf and transistor Qhn in this order and returns to the minus terminal of the power source capacitor 11 such that a current supplied from the power source capacitor 11 flows through the current path Pp1. In this state, electric current amounts of the currents Ic, Iqp, Iqdp, -IL, Iqcr, -Iqcf, and Iqhn increase with time while the energy Ec of the power source capacitor 11 decreases with time. Additionally, the currents Iqhp, Iqif, Iqir, and Iqdn do not flow through the transistors Qhp, Qif, Qir, and Qdn. In other words, at step ST22, the control device 30 sets the transistor Qhn to the ON-state so as to set the transistor Qdp to an object of switching measurement, and sets the transistors Qp, Qcf, and Qcr to the ON-state to supply a current from the power source capacitor 11 to the transistor Qdp.

Subsequently, at step ST23, the control device 30 sets the gate signals Sqp, Sqhn, Sqcf, and Sqcr to the high level and other gate signals than these to the low level, and outputs them. In other words, only the gate signal Sqdp is changed from the high level to the low level differently from step ST22, and other gate signals than this are not changed. This makes the transistors Qp, Qhn, Qcf, and Qcr be in the ON-state and other transistors than these be in the OFF-state. At this time, as shown in Fig. 8, a current path Pp2 is formed which goes round through the transistor Qhn, diode Ddn, reactor L, transistor Qcr, and transistor Qcf in this order, and the current having been flowing through the current path Pp1 immediately before step ST23 flows through the current path Pp2. For this reason, since the electric current amounts of the currents Ic, Iqp, and Iqdp become 0 and a current is not supplied from the power source capacitor 11, the energy Ec does not change. At this time, since the energy is consumed by resistance components or the like of the transistor Qhn, diode Ddn, reactor L, transistor Qcr, and transistor Qcf, the electric current amounts of the currents Iqhn, -Iqdn (current flowing through the diode Ddn), -IL, Iqcr, and -Iqcf gradually decrease with time from the electric current amount of the current having been flowing through the current path Pp1 immediately before step ST23. Moreover, the electric current amounts of the currents Iqhp, Iqif, and Iqir remain 0.

Subsequently, at step ST24 as is at step ST22, the control device 30 sets the gate signals Sqp, Sqhn, Sqcf, Sqcr, and Sqdp to the high level and other gate signals than these to the low level, and outputs them. In other words, only the gate signal Sqdp is changed from the low level to the high level differently from step ST23, and other gate signals than this are not changed. This forms the current path Pp1 so that the current having been flowing through the current path Pp2 immediately before step ST24 and the current supplied from the power source capacitor 11 flow through the current path Pp1. At this time, the electric current amounts of the currents Ic, Iqp, Iqdp, -IL, Iqcr, -Iqcf, and Iqhn further increase with time from the electric current amount of the current having been flowing through the current path Pp2 immediately before step ST24 while the energy Ec of the power source capacitor 11 further decreases with time. Additionally, the currents Iqhp, Iqif, Iqir, and Iqdn do not flow through the transistors Qhp, Qif, Qir, and Qdn.

Subsequently, at step ST25 as is at step ST23, the control device 30 sets the gate signals Sqp, Sqhn, Sqcf, and Sqcr to the high level and other gate signals than these to the low level, and outputs them. In other words, only the gate signal Sqdp is changed from the high level to the low level differently from step ST24, and other gate signals than this are not changed. This forms the current path Pp2 so that the current having been flowing through the current path Pp1 immediately before step ST25 flows through the current path Pp2. At this time, as is at step ST23, the electric current amounts of the currents Ic, Iqp, and Iqdp become 0 and the electric current amounts of the currents Iqhn, -Iqdn, -IL, Iqcr, and -Iqcf gradually decrease with time. Moreover, the electric current amounts of the currents Iqhp, Iqif, and Iqir remain 0. In addition, since current is not supplied from the power source capacitor 11, the energy Ec does not change. At this point of time, a waveform required for the P-side switching measurement is obtained. In other words, by the process from step ST22 to the transistor Qdp is set to the OFF-state at step ST25, a waveform required for the switching measurement of the transistor Qdp is obtained. In this sense, the process from step ST22 to the transistor Qdp is set to the OFF-state at step ST25 can be said to be narrow-sense switching measurement of the transistor Qdp.

After that, the control device 30 changes the gate signal Sqhn from the high level to the low level. This makes the transistors Qp, Qcf, and Qcr be in the ON-state and other transistors than these be in the OFF-state. At this time, as shown in Fig. 9, a current path Pp3 is formed which passes from the minus terminal of the power source capacitor 11 through the diode Ddn, reactor L, transistor Qcr, transistor Qcf, diode Dhp, and transistor Qp in this order and returns to the plus terminal of the power source capacitor 11, and the current having been flowing through the current path Pp2 immediately before switching the gate signal Sqhn to the low level flows through the current path Pp3. For this reason, the electric current amount of the current Iqhn becomes 0. Then, since the current path Pp3 travels from the minus terminal of the power source capacitor 11 to the plus terminal, the power source capacitor 11 is charged and the energy Ec increases with time while the electric current amounts of the currents -Iqdn, -IL, Iqcr, -Iqcf, -Iqhp (current flowing through the diode Dhp), -Iqp, and -Ic decrease with time. Moreover, the electric current amounts of the currents Iqdp, Iqif, and Iqir remain 0.

Subsequently, at step ST26, a state the same as at step ST25 is continued so that the electric current amount of the current flowing through the current path Pp3 becomes 0 and the energy Ec of the power source capacitor 11 recovers to an almost full charge state.

Subsequently, at step ST27, the control device 30 sets all of the gate signals Sqp, Sqhp, Sqhn, Sqif, Sqir, Sqcf, Sqcr, Sqdp, and Sqdn to the low level and outputs them. For this reason, all of the transistors Qp, Qhp, Qhn, Qif, Qir, Qcf, Qcr, Qdp, and Qdn are in the OFF-state such that a current does not flow through any transistor. In this way, the P-side switching measurement ends. Note that the electric current amount of the current flowing through the current path Pp3 may be detected to be a predetermined threshold or less by a detecting circuit or the like not shown, and the control device 30 may detect by use of an output signal from the detecting circuit that the electric current amount of the current flowing through the current path Pp3 becomes almost 0 (energy regeneration process completion). A predetermined threshold is set to 0 or a value slightly larger than 0, for example. Then, the control device 30 may perform a process at step ST27 in response to detecting the energy regeneration process completion.

As described above, the control device 30, at the start of the P-side switching measurement, sets the transistors Qp, Qhn, Qcf, and Qcr to the ON-state and sets the transistor Qhn to the OFF-state in response to completion of taking in the waveform in the P-side switching measurement to regenerate the energy having been used for the P-side switching measurement. Then, the control device 30, after regenerating the energy having been used for the P-side switching measurement, sets the transistor Qp, Qcf, and Qcr to the OFF-state. Therefore, at the end of the P-side switching measurement, the energy Ec is in the almost full charge state so that the power source capacitor 11 does not need to be charged by the high-voltage power supply for the next measurement.

Next, a description is given of a comparative example of the switching measurement using the dynamic characteristics test device 1. Fig. 10 is a timing chart for the N-side switching measurement in the comparative example. Fig. 11 is a timing chart for the P-side switching measurement in the comparative example. As shown in Fig. 10, the N-side switching measurement in the comparative example differs in a timing when the gate signal Sqhp is switched from the high level to the low level as compared with the N-side switching measurement in Fig. 2. Specifically, in the N-side switching measurement in the comparative example, at step ST115 and step ST116, the control device 30 maintains the gate signal Sqhp remained at the high level. For this reason, the electric current amounts of the currents (currents Iqhp, Iqcf, -Iqcr, IL, and -Iqdp) flowing through the current path Pn2 gradually decrease with time and result in 0 in time, but the power source capacitor 11 is not charged. Therefore, the power source capacitor 11 needs to be charged by the high-voltage power supply before making the next measurement.

Similarly, as shown in Fig. 11, the P-side switching measurement in the comparative example differs in a timing when the gate signal Sqhn is switched from the high level to the low level as compared with the P-side switching measurement in Fig. 6. Specifically, in the P-side switching measurement in the comparative example, at step ST125 and step ST126, the control device 30 maintains the gate signal Sqhn remained at the high level. For this reason, the electric current amounts of the currents (currents Iqhn, -Iqdn, -IL, Iqcr, and -Iqcf) flowing through the current path Pp2 gradually decrease with time and result in 0 in time, but the power source capacitor 11 is not charged. Therefore, the power source capacitor 11 needs to be charged by the high-voltage power supply before making the next measurement.

Next, a description is given of overcurrent prevention of the dynamic characteristics test device 1. First, a description is given of overcurrent prevention in the N-side switching measurement. Fig. 12 is a timing chart for the N-side switching measurement including an overcurrent preventing process in the dynamic characteristics test device 1. Fig. 13 is a diagram illustrating a current path at the overcurrent preventing process in the N-side switching measurement.

As shown in Fig. 12, the gate signals at step ST31 to step ST33 are the same as at step ST11 to step ST13 in Fig. 2, and thus, the description thereof is omitted. In this example, a case is assumed where at step ST33 the transistor Qdn is not set to the OFF-state because the DUT 50 is defective. In this case, at step ST32 and subsequent steps, the currents (currents Ic, Iqp, Iqhp, Iqcf, -Iqcr, IL, and Iqdn) continue to flow through the current path Pn1, and the electric current amounts thereof continue to increase with time.

Then, at step ST34, the electric current amount of the current flowing through the current path Pn1 increases larger than the N-side overcurrent threshold Ref_N and the comparator 23 outputs a low level output signal to the control device 30. Then, the control device 30 detects an overcurrent in response to receiving the low level output signal from the comparator 23, and changes the gate signals Sqp, and Sqhp from the high level to the low level and changes the gate signal Sqir from the low level to the high level. This makes the transistors Qcf, Qcr, Qir, and Qdn be in the ON-state and other transistors than these be in the OFF-state. At this time, as shown in Fig. 13, a current path Pn41 is formed which goes round through the transistor Qcf, transistor Qcr, reactor L, transistor Qdn, and diode Dhn in this order, and a current path Pn42 is formed which goes round through the reactor L, transistor Qir, and diode Dif in this order. Then, the overcurrent having been flowing through the current path Pn1 is divided into and flows through the current path Pn41 and the current path Pn42. This prevents the overcurrent from continuously flowing through the testing circuit 10 and the DUT 50.

Subsequently, at step ST35 as in at step ST15, the control device 30 changes only the gate signal Sqdn from the high level to the low level differently from the state of the gate signal at step ST34 and does not change other gate signals than this. However, the transistor Qdn is not set to the OFF-state because the DUT 50 is defective, and each transistor maintains the state the same as at step ST34. Then, since the current flowing through the current path Pn41 goes round the current path Pn41 so that the energy is consumed by the resistance components or the like of the transistor Qcf, transistor Qcr, reactor L, transistor Qdn, and diode Dhn, the electric current amount thereof decreases with time. Similarly, since the current flowing through the current path Pn42 goes round the current path Pn42 so that the energy is consumed by the resistance components or the like of the reactor L, transistor Qir, and diode Dif, the electric current amount thereof decreases with time.

Subsequently, at step ST36, the state of the gate signal at step ST35 is continued, and the electric current amounts of the currents flowing through the current path Pn41 and the current path Pn42 further decrease and become 0.

Subsequently, at step ST37, the control device 30 sets all of the gate signals Sqp, Sqhp, Sqhn, Sqif, Sqir, Sqcf, Sqcr, Sqdp, and Sqdn to the low level and outputs them. For this reason, all of the transistors Qp, Qhp, Qhn, Qif, Qir, Qcf, Qcr, Qdp, and Qdn are in the OFF-state such that a current does not flow through any transistor. Note that the electric current amounts of the currents flowing through the current path Pn41 and the current path Pn42 may be detected to be a predetermined threshold or less by a detecting circuit or the like not shown, and the control device 30 may detect by use of an output signal from the detecting circuit that the electric current amounts of the currents flowing through the current path Pn41 and the current path Pn42 become almost 0 (energy consumption process completion). A predetermined threshold is set to 0 or a value slightly larger than 0, for example. Then, the control device 30 may perform a process at step ST37 in response to detecting the energy consumption process completion.

As described above, the control device 30 sets the transistors Qp and Qhp to the OFF-state in response to detecting the overcurrent in the N-side switching measurement and sets the transistor Qir to the ON-state to cause the overcurrent preventing circuit 14 to operate. This allows that the energy stored in the reactor L when an overcurrent occurs is consumed by the overcurrent preventing circuit 14 and a further overcurrent is prevented from flowing through the DUT 50 in the N-side switching measurement.

Next, a description is given of overcurrent prevention in the P-side switching measurement. Fig. 14 is a timing chart for the P-side switching measurement including the overcurrent preventing process in the dynamic characteristics test device 1. Fig. 15 is a diagram illustrating a current path at the overcurrent preventing process in the P-side switching measurement.

As shown in Fig. 14, the gate signals at step ST41 to step ST43 are the same as at step ST21 to step ST23 in Fig. 6, and thus, the description thereof is omitted. In this example, a case is assumed where at step ST43 the transistor Qdp is not set to the OFF-state because the DUT 50 is defective. In this case, at step ST42 and subsequent steps, the currents (currents Ic, Iqp, Iqdp, -IL, Iqcr, -Iqcf, and Iqhn) continue to flow through the current path Pp1, and the electric current amounts thereof continue to increase with time.

Then, at step ST44, the electric current amount of the current flowing through the current path Pp1 increases larger than the P-side overcurrent threshold Ref_P and the comparator 24 outputs a low level output signal to the control device 30. Then, the control device 30 detects an overcurrent in response to receiving the low level output signal from the comparator 24, and changes the gate signals Sqp and Sqhn from the high level to the low level and changes the gate signal Sqif from the low level to the high level. This makes the transistors Qcf, Qcr, Qif, and Qdp be in the ON-state and other transistors than these be in the OFF-state. At this time, as shown in Fig. 15, a current path Pp41 is formed which goes round through the reactor L, transistor Qcr, transistor Qcf, diode Dhp, and transistor Qdp in this order, and a current path Pp42 is formed which goes round through the reactor L, transistor Qif, and diode Dir in this order. Then, the overcurrent having been flowing through the current path Pp1 is divided into and flows through the current path Pp41 and the current path Pp42. This prevents the overcurrent from continuously flowing through the testing circuit 10 and the DUT 50.

Subsequently, at step ST45 as in at step ST25, the control device 30 changes only the gate signal Sqdp from the high level to the low level differently from the state of the gate signal at step ST44 and does not change other gate signals than this. However, the transistor Qdp is not set to the OFF-state because the DUT 50 is defective, and each transistor maintains the state the same as at step ST44. Then, since the current flowing through the current path Pp41 goes round the current path Pp41 so that the energy is consumed by the resistance components or the like of the reactor L, transistor Qcr, transistor Qcf, diode Dhp, and transistor Qdp, the electric current amount thereof decreases with time. Similarly, since the current flowing through the current path Pp42 goes round the current path Pp42 so that the energy is consumed by the resistance components or the like of the reactor L, transistor Qif, and diode Dir, the electric current amount thereof decreases with time.

Subsequently, at step ST46, the state of the gate signal at step ST45 is continued, and the electric current amounts of the currents flowing through the current path Pp41 and the current path Pp42 further decrease and become 0.

Subsequently, at step ST47, the control device 30 sets all of the gate signals Sqp, Sqhp, Sqhn, Sqif, Sqir, Sqcf, Sqcr, Sqdp, and Sqdn to the low level and outputs them. For this reason, all of the transistors Qp, Qhp, Qhn, Qif, Qir, Qcf, Qcr, Qdp, and Qdn are in the OFF-state such that a current does not flow through any transistor. Note that the electric current amounts of the currents flowing through the current path Pp41 and the current path Pp42 may be detected to be a predetermined threshold or less by a detecting circuit or the like not shown, and the control device 30 may detect by use of an output signal from the detecting circuit that the electric current amounts of the currents flowing through the current path Pp41 and the current path Pp42 become almost 0 (energy consumption process completion). A predetermined threshold is set to 0 or a value slightly larger than 0, for example. Then, the control device 30 may perform a process at step ST47 in response to detecting the energy consumption process completion.

As described above, the control device 30 sets the transistors Qp and Qhn to the OFF-state in response to detecting the overcurrent in the P-side switching measurement and sets the transistor Qif to the ON-state to cause the overcurrent preventing circuit 14 to operate. This allows that the energy stored in the reactor L when an overcurrent occurs is consumed by the overcurrent preventing circuit 14 and a further overcurrent is prevented from flowing through the DUT 50 in the P-side switching measurement.

Further, a description is given of overcurrent prevention using the high-speed breaking circuit 15. First, a description is given of overcurrent prevention in the N-side switching measurement using the high-speed breaking circuit 15. Fig. 16 is a timing chart for the N-side switching measurement including the overcurrent preventing process using a high-speed breaking circuit in the dynamic characteristics test device 1. Fig. 17 is a diagram illustrating a current path at the overcurrent preventing process using the high-speed breaking circuit in the N-side switching measurement.

The timing chart of the gate signals shown Fig. 16 differs in that at step ST54 the control device 30 further changes the gate signals Sqcf and Sqcr from the high level to the low level in response to detecting the overcurrent as compared with the timing chart of the gate signals shown in Fig. 12. For this reason, when the overcurrent is detected, the transistors Qir and Qdn are set to the ON-state, and other transistors than these are set to the OFF-state. At this time, as shown in Fig. 17, since the current path Pn41 is not formed but only the current path Pn42 is formed, the overcurrent having been flowing through the current path Pn1 flows through the current path Pn42. Then, since the current flowing through the current path Pn42 goes round the current path Pn42 so as to consume the energy, the electric current amount thereof decreases with time.

As described above, the control device 30 sets the transistors Qp and Qhp to the OFF-state in response to detecting the overcurrent in the N-side switching measurement and sets the transistor Qir to the ON-state to cause the overcurrent preventing circuit 14 to operate, and further sets the transistors Qcf and Qcr to the OFF-state to cause the high-speed breaking circuit 15 to operate. This allows that the energy stored in the reactor L when the overcurrent occurs flows as the current through the overcurrent preventing circuit 14 to be consumed by the overcurrent preventing circuit 14. In a case where the high-speed breaking circuit 15 is not caused to operate, the overcurrent having been flowing through the current path Pn1 is divided into and flows through the current path Pn41 and the current path Pn42. At this time, a resistance value contributing to consumption of the overcurrent is a combined resistance value of a resistance value of the resistance component in the current path Pn41 and a resistance value of the resistance component in the current path Pn42, which is smaller than the resistance value of the resistance component in the current path Pn42. For this reason, since the resistance value contributing to consumption of the overcurrent is larger in a case where the high-speed breaking circuit 15 is caused to operate as compared with the case where the high-speed breaking circuit 15 is not caused to operate, the energy stored in the reactor L is consumed in a short time and a further overcurrent is ensured to be prevented from flowing through the DUT 50 in the N-side switching measurement.

Next, a description is given of overcurrent prevention in the P-side switching measurement using the high-speed breaking circuit 15. Fig. 18 is a timing chart for the P-side switching measurement including the overcurrent preventing process using the high-speed breaking circuit in the dynamic characteristics test device 1. Fig. 19 is a diagram illustrating a current path at the overcurrent preventing process using the high-speed breaking circuit in the P-side switching measurement.

The timing chart of the gate signals shown Fig. 18 differs in that at step ST64 the control device 30 further changes the gate signals Sqcf and Sqcr from the high level to the low level in response to detecting the overcurrent as compared with the timing chart of the gate signals shown in Fig. 14. For this reason, when the overcurrent is detected, the transistors Qif and Qdp are set to the ON-state, and other transistors than these are set to the OFF-state. At this time, as shown in Fig. 19, since the current path Pp41 is not formed but only the current path Pp42 is formed, the overcurrent having been flowing through the current path Pp1 flows through the current path Pp42. Then, since the current flowing through the current path Pp42 goes round the current path Pp42 so as to consume the energy, the electric current amount thereof decreases with time.

As described above, the control device 30 sets the transistors Qp and Qhn to the OFF-state in response to detecting the overcurrent in the P-side switching measurement and sets the transistor Qif to the ON-state to cause the overcurrent preventing circuit 14 to operate, and further sets the transistors Qcf and Qcr to the OFF-state to cause the high-speed breaking circuit 15 to operate. This allows that the energy stored in the reactor L when the overcurrent occurs flows as the current through the overcurrent preventing circuit 14 to be consumed by the overcurrent preventing circuit 14. In a case where the high-speed breaking circuit 15 is not caused to operate, the overcurrent having been flowing through the current path Pp1 is divided into and flows through the current path Pp41 and the current path Pp42. At this time, a resistance value contributing to consumption of the overcurrent is a combined resistance value of a resistance value of the resistance component in the current path Pp41 and a resistance value of the resistance component in the current path Pp42, which is smaller than the resistance value of the resistance component in the current path Pp42. For this reason, since the resistance value contributing to consumption of the overcurrent is larger in a case where the high-speed breaking circuit 15 is caused to operate as compared with the case where the high-speed breaking circuit 15 is not caused to operate, the energy stored in the reactor L is consumed in a short time and a further overcurrent is ensured to be prevented from flowing through the DUT 50 in the P-side switching measurement.

(Short circuit capability measurement)
Next, a description is given of short circuit capability measurement using the dynamic characteristics test device 1. First, a description is given of short circuit capability measurement of the transistor Qdn (also referred to as "N-side short circuit capability measurement" in some cases). Fig. 20 is a timing chart for N-side short circuit capability measurement in the dynamic characteristics test device 1. As shown in Fig. 20, at step ST71, the control device 30 sets all of the relay signals Sswp and Sswn and all of the gate signals Sqp, Sqhp, Sqhn, Sqif, Sqir, Sqcf, Sqcr, Sqdp, and Sqdn to the low level, and outputs them. For this reason, all of the switches SWp and SWn and all of the transistors Qp, Qhp, Qhn, Qif, Qir, Qcf, Qcr, Qdp, and Qdn are in the OFF-state such that a current does not flow through any transistor and switch.

Subsequently, at step ST72, the control device 30 sets the relay signal Sswp and the gate signals Sqp and Sqdn to the high level, sets the relay signal Sswn and the gate signals Sqhp, Sqhn, Sqif, Sqir, Sqcf, Sqcr, and Sqdp to the low level, and outputs them. This makes the switch SWp and the transistors Qp and Qdn be in the ON-state and other switches and transistors than these be in the OFF-state. At this time, a current path is formed which passes from the plus terminal of the power source capacitor 11 through the transistor Qp, switch SWp and transistor Qdn in this order and returns to the minus terminal of the power source capacitor 11 such that a current flows through the current path. In this way, a short-circuit current flows through the transistor Qdn without via the reactor L.

Subsequently, at step ST73, the control device 30, as is at step ST71, sets all of the relay signals Sswp and Sswn and all of the gate signals Sqp, Sqhp, Sqhn, Sqif, Sqir, Sqcf, Sqcr, Sqdp, and Sqdn to the low level, and outputs them. This makes all the switches and transistors be in the OFF-state and a current does not flow through any transistor and switch. The N-side short circuit capability measurement is made by a series of the processes described above.

Next, a description is given of short circuit capability measurement of the transistor Qdp (also referred to as "P-side short circuit capability measurement" in some cases). Fig. 21 is a timing chart for P-side short circuit capability measurement in the dynamic characteristics test device 1. As shown in Fig. 21, at step ST81, the control device 30 sets all of the relay signals Sswp and Sswn and all of the gate signals Sqp, Sqhp, Sqhn, Sqif, Sqir, Sqcf, Sqcr, Sqdp, and Sqdn to the low level, and outputs them. For this reason, all of the switches SWp and SWn and all of the transistors Qp, Qhp, Qhn, Qif, Qir, Qcf, Qcr, Qdp, and Qdn are in the OFF-state such that a current does not flow through any transistor or switch.

Subsequently, at step ST82, the control device 30 sets the relay signal Sswn and the gate signals Sqp and Sqdp to the high level, sets the relay signal Sswp and the gate signals Sqhp, Sqhn, Sqif, Sqir, Sqcf, Sqcr, and Sqdn to the low level, and outputs them. This makes the switch SWn and the transistors Qp and Qdp be in the ON-state and other switches and transistors than these be in the OFF-state. At this time, a current path is formed which passes from the plus terminal of the power source capacitor 11 through the transistor Qp, transistor Qdp and switch SWn in this order and returns to the minus terminal of the power source capacitor 11 such that a current flows through the current path. In this way, a short-circuit current flows through the transistor Qdp without via the reactor L.

Subsequently, at step ST83, the control device 30, as is at step ST81, sets all of the relay signals Sswp and Sswn and all of the gate signals Sqp, Sqhp, Sqhn, Sqif, Sqir, Sqcf, Sqcr, Sqdp, and Sqdn to the low level, and outputs them. This makes all the switches and transistors be in the OFF-state and a current does not flow through any transistor or switch. The P-side short circuit capability measurement is made by a series of the processes described above.

In the dynamic characteristics test device 1 described above, the transistors Qp, Qhp, Qcf, and Qcr are set to the ON-state at the start of the switching measurement of the transistor Qdn, and the transistors Qp, Qcf, and Qcr are set to the OFF-state after the transistor Qhp is set to the OFF-state in response to completion of the switching measurement (taking in the waveform for the switching measurement) of the transistor Qdn. The current supplied from the power source capacitor 11 to the transistor Qdn flows through the reactor L from the connection part Cs toward the connection part Cd at the switching measurement of the transistor Qdn, and the energy has been stored in the reactor L at a point of time when the switching measurement (taking in the waveform for the switching measurement) of the transistor Qdn completes. For this reason, the transistor Qhp is set to the OFF-state in response to completion of the switching measurement (taking in the waveform for the switching measurement) of the transistor Qdn so that a current path Pn3 is formed which passes from the minus terminal of the power source capacitor 11 through the diode Dhn, transistor Qcf, transistor Qcr, reactor L, diode Ddp, and transistor Qp in this order and returns to the plus terminal of the power source capacitor 11, and the energy stored in the reactor L flows as the current through the plus terminal of the power source capacitor 11. This makes it possible to regenerate a part of the energy (electricity) of the power source capacitor 11 used for the switching measurement of the transistor Qdn. As a result, electricity usage can be reduced in the dynamic characteristics test. Moreover, time required to charge the power source capacitor 11 for the next measurement can be shortened, allowing a machine cycle to be shortened (improved).

Moreover, in the dynamic characteristics test device 1, the transistors Qp, Qhn, Qcf, and Qcr are set to the ON-state at the start of the switching measurement of the transistor Qdp, and the transistors Qp, Qcf, and Qcr are set to the OFF-state after the transistor Qhn is set to the OFF-state in response to completion of the switching measurement (taking in the waveform for the switching measurement) of the transistor Qdp. The current supplied from the power source capacitor 11 to the transistor Qdp flows through reactor L from the connection part Cd toward the connection part Cs at the switching measurement of the transistor Qdp, and the energy has been stored in the reactor L at a point of time when the switching measurement (taking in the waveform for the switching measurement) of the transistor Qdp completes. For this reason, the transistor Qhn is set to the OFF-state in response to completion of the switching measurement (taking in the waveform for the switching measurement) of the transistor Qdp so that a current path Pp3 is formed which passes from the minus terminal of the power source capacitor 11 through the diode Ddn, reactor L, transistor Qcr, transistor Qcf, diode Dhp, and transistor Qp in this order and returns to the plus terminal of the power source capacitor 11, and the energy stored in the reactor L flows as the current through the plus terminal of the power source capacitor 11. This makes it possible to regenerate a part of the energy (electricity) of the power source capacitor 11 used for the switching measurement of the transistor Qdp. As a result, electricity usage can be further reduced in the dynamic characteristics test. Moreover, time required to charge the power source capacitor 11 for the next measurement can be shortened, allowing a machine cycle to be further shortened (improved).

Additionally, in the dynamic characteristics test device 1, the transistor Qhp is set to the ON-state so that the transistor Qdn is selected as an object of switching measurement, and a current flows through the reactor L from the connection part Cs toward connection part Cd in the switching measurement of the transistor Qdn. Moreover, the transistor Qhn is set to the ON-state so that the transistor Qdp is selected as an object of switching measurement, and a current flows through the reactor L from the connection part Cd toward the connection part Cs in the switching measurement of the transistor Qdp. In other words, a current may flow bidirectionally through the reactor L. In the switching measurement of the transistor Qdn, in a case where an overcurrent having an electric current amount exceeding the overcurrent threshold Ref_N is detected in the dynamic characteristics test device 1, the transistor Qir is set to the ON-state such that the current path Pn42 is formed which goes round through the reactor L, transistor Qir and diode Dif. Then, the energy stored in the reactor L is consumed by way of being flowed as the current through this current path Pn42. On the other hand, in the switching measurement of the transistor Qdp, in a case where an overcurrent having an electric current amount exceeding the overcurrent threshold Ref_P is detected in the dynamic characteristics test device 1, the transistor Qif is set to the ON-state such that the current path Pp42 is formed which goes round through the reactor L, transistor Qif, and diode Dir. Then, the energy stored in the reactor L is consumed by way of being flowed as the current through this current path Pp42. In this way, in the dynamic characteristics test device 1 for the DUT 50 including the transistor Qdp and the transistor Qdn which are connected electrically in series, a current flows bidirectionally through the reactor L, but a further overcurrent can be prevented from flowing through the DUT 50 in both directions. This can prevent failure or the like of the dynamic characteristics test device 1, and as a result, a frequency of maintenance such as part replacement can be reduced, even contributing to cost reduction.

The diode Dif is a free wheel diode of the transistor Qif, and the diode Dir is a free wheel diode of the transistor Qir. The diode Dif is arranged in a manner such that a forward direction thereof is a direction from the connection part Cd toward the connection part Cs, and the diode Dir is arranged in a manner such that a forward direction thereof is a direction from the connection part Cs toward the connection part Cd. In this way, since the current paths Pn42 and Pp42 described above are formed by use of the free wheel diodes for protecting the transistors Qif and Qir, a further overcurrent can be prevented from flowing bidirectionally through the DUT 50 while suppressing the rise in the number of parts.

Moreover, in the switching measurement of the transistor Qdn, in a case where an overcurrent is detected, the transistor Qir is set to the ON-state and further the transistors Qcf and Qcr are set to the OFF-state so that the current path Pn41 different from the current path Pn42 can be broken. For this reason, the energy stored in the reactor L can be flowed as the current through the overcurrent preventing circuit 14 (current path Pn42), allowing the energy stored in the reactor L to be consumed at a high speed. Similarly, in the switching measurement of the transistor Qdp, in a case where an overcurrent is detected, the transistor Qif is set to the ON-state and further the transistors Qcf and Qcr are set to the OFF-state so that the current path Pp41 different from the current path Pp42 can be broken. For this reason, the energy stored in the reactor L can be flowed as the current through the overcurrent preventing circuit 14 (current path Pp42), allowing the energy stored in the reactor L to be consumed at a high speed.

Note that the dynamic characteristics test device and the dynamic characteristics test method according to the invention are not limited to the above embodiments. For example, the transistors Qp, Qhp, Qhn, Qif, Qir, Qcf, and Qcr are not limited to an IGBT, but may be a switch unit so long as it can switch between the ON-state and the OFF-state. For example, as the transistors Qp, Qhp, Qhn, Qif, Qir, Qcf, and Qcr, another transistor such as an FET (Field Effect Transistor) and a bipolar transistor, and a relay or the like capable of high-speed operation may be used. Use of the transistor makes it possible to switch between the ON-state and the OFF-state at a high speed and improve accuracy of the dynamic characteristics test including the switching measurement.

Additionally, another rechargeable power source may be used in place of the power source capacitor 11. Moreover, in a case where it is not aimed to conduct the energy regeneration in the switching measurement, a non-rechargeable power source may be used and the main switch unit 12 may not be arranged. In this case, the plus terminal of the power source capacitor 11 is electrically connected with the collector of the transistor Qhp, the cathode of the diode Dhp, one end of the switch SWp, the collector of the transistor Qdp, and the cathode of the diode Ddp, and the minus terminal of the power source capacitor 11 is electrically connected with the emitter of the transistor Qhn, the anode of the diode Dhn, the other end of the switch SWn, the emitter of the transistor Qdn, and the anode of the diode Ddn.

Additionally, in a case where it is aimed to conduct the energy regeneration in the switching measurement, the overcurrent preventing circuit 14 and the high-speed breaking circuit 15 may not be arranged. In this case, the emitter of the transistor Qhp, the collector of the transistor Qhn, and the one end of the reactor L are electrically connected.

The high-speed breaking circuit 15 is sufficient so long as it may set at least the transistor Qcf to the OFF-state in a case of breaking the overcurrent in the N-side switching measurement at a high speed, and so long as it may set at least the transistor Qcr to the OFF-state in a case of breaking the overcurrent in the P-side switching measurement at a high speed. Moreover, the high-speed breaking circuit 15 is sufficient so long as it may be arranged in series to the reactor L at a portion in the current path Pn41 not overlapping the current path Pn42 in the case of breaking the overcurrent in the N-side switching measurement at a high speed. Moreover, the high-speed breaking circuit 15 is sufficient so long as it may be arranged in series to the reactor L at a portion in the current path Pp41 not overlapping the current path Pp42 in the case of breaking the overcurrent in the P-side switching measurement at a high speed. The high-speed breaking circuit 15 may be arranged between the DUT 50 and the reactor L, for example. Further, the high-speed breaking circuit 15 is sufficient so long as it may include a switch unit capable of switching between the conduction state and the cutoff state, and may be one relay or the like, for example.

Moreover, the overcurrent preventing circuit 14 is sufficient so long as it has a configuration capable of preventing the bidirectional overcurrent. The overcurrent preventing circuit 14 may be a reverse blocking IGBT, for example. More specifically, the overcurrent preventing circuit 14 is sufficient so long as it may include a switch unit and a diode connected electrically in series in one direction from the connection part Cd toward the connection part Cs, and a switch unit and a diode connected electrically in series in the other direction from the connection part Cs toward the connection part Cd. It is sufficient that the diode in one direction may be arranged in a manner such that the forward direction thereof is the relevant one direction, and the diode in the other direction may be arranged in a manner such that the forward direction thereof is the relevant other direction.

As shown in Fig. 22, the overcurrent preventing circuit 14 may be configured as a diode bridge, for example. To put it specifically, the overcurrent preventing circuit 14 in a modification example includes a transistor Qi (third switch unit, fourth switch unit), a diode Di, and diodes D1 to D4 (second diode, first diode, fifth diode, sixth diode). The transistor Qi is an IGBT. A cathode of the diode Di is electrically connected with a collector of the transistor Qi, and an anode of the diode Di is electrically connected with an emitter of the transistor Qi. In other words, the diode Di is a free wheel diode connected electrically in parallel with the transistor Qi. The collector of the transistor Qi is electrically connected with a cathode of the diode D1 and a cathode of the diode D3, and the emitter of the transistor Qi is electrically connected with an anode of the diode D2 and an anode of the diode D4. An anode of the diode D1 and a cathode of the diode D2 are electrically connected with each other, and are electrically connected with the collector of the transistor Qcr, the cathode of the diode Dcr, and the one end of the reactor L. An anode of the diode D3 and a cathode of the diode D4 are electrically connected with each other, and electrically connected with the other end of the reactor L, the other end of the switch SWp, one end of the switch SWn, and the O terminal of the DUT 50.

For example, in a case where at step ST34 in Fig. 12, the electric current amounts of the currents (currents Ic, Iqp, Iqhp, Iqcf, -Iqcr, IL, and Iqdn) flowing through the current path Pn1 increase to be larger than the N-side overcurrent threshold Ref_N, and the comparator 23 outputs a low level output signal to the control device 30, the control device 30 detects an overcurrent in response to receiving the low level output signal from the comparator 23, and changes the gate signals Sqp and Sqhp from the high level to the low level. This makes the transistors Qcf, Qcr, and Qdn be in the ON-state and other transistors than these be in the OFF-state. At this time, as shown in Fig. 23, the current path Pn41 is formed, and the overcurrent having been flowing through the current path Pn1 flows through the current path Pn41.

Subsequently, the control device 30 changes the gate signal Sqi from the low level to the high level. This makes the transistor Qi further be in the ON-state, and as shown in Fig. 23, a current path Pn43 is formed which goes round through the reactor L, diode D3, transistor Qi, and diode D2 in this order so that a part of the current flowing through the current path Pn41 flows through the current path Pn43. Then, since the current flowing through the current path Pn41 goes round the current path Pn41 so that the energy is consumed by the resistance component or the like of the transistor Qcf, transistor Qcr, reactor L, transistor Qdn, and diode Dhn, the electric current amount thereof decreases with time. Similarly, since the current flowing through the current path Pn43 goes round the current path Pn43 so that the energy is consumed by the resistance component or the like of the reactor L, diode D3, transistor Qi, and diode D2, the electric current amount thereof decreases with time.

Moreover, in a case where at step ST44 in Fig. 14, the electric current amounts of the currents (currents Ic, Iqp, Iqdp, -IL, Iqcr, -Iqcf, and Iqhn) flowing through the current path Pp1 increase to be larger than the P-side overcurrent threshold Ref_P, and the comparator 24 outputs a low level output signal to the control device 30, the control device 30 detects an overcurrent in response to receiving the low level output signal from the comparator 24, and changes the gate signals Sqp and Sqhn from the high level to the low level. This makes the transistors Qcf, Qcr, and Qdp be in the ON-state and other transistors than these be in the OFF-state. At this time, as shown in Fig. 24, the current path Pp41 is formed, and the overcurrent having been flowing through the current path Pp1 flows through the current path Pp41.

Subsequently, the control device 30 changes the gate signal Sqi from the low level to the high level. This makes the transistor Qi further be in the ON-state, and as shown in Fig. 24, a current path Pp43 is formed which goes round through the reactor L, diode D1, transistor Qi, and diode D4 in this order so that a part of the current flowing through the current path Pp41 flows through the current path Pp43. Then, since the current flowing through the current path Pp41 goes round the current path Pp41 so that the energy is consumed by the resistance components or the like of the reactor L, transistor Qcr, transistor Qcf, diode Dhp, and transistor Qdp, the electric current amount thereof decreases with time. Similarly, since the current flowing through the current path Pp43 goes round the current path Pp43 so that the energy is consumed by the resistance component or the like of the reactor L, diode D1, transistor Qi, and diode D4, the electric current amount thereof decreases with time. Even in the overcurrent preventing circuit 14 configured like this, the bidirectional overcurrent can be prevented in the dynamic characteristics test device 1.

Note that as shown in (a) in Fig. 25, in a case where the overcurrent preventing circuit 14 includes the transistors Qif and Qir, and the diodes Dif and Dir, even if the transistor Qir is set to the ON-state before the transistors Qp and Qhp are set to the OFF-state in the N-side switching measurement, a short-circuit current without via the reactor L does not flow. In this way, in the case where the overcurrent preventing circuit 14 includes the transistors Qif and Qir, and the diodes Dif and Dir, the order of a timing when the transistors Qp and Qhp are set to the OFF-state and a timing when the transistor Qir is set to the ON-state may be arbitrary. The same goes for the P-side switching measurement.

On the other hand, as shown in (b) in Fig. 25, in a case where the overcurrent preventing circuit 14 includes the diode bridge, if the transistor Qi is set to the ON-state before the transistors Qp and Qhp are set to the OFF-state in the N-side switching measurement, a current path Pn5 is formed which passes from the plus terminal of the power source capacitor 11 through the transistor Qp, transistor Qhp, transistor Qcf, transistor Qcr, diode D1, transistor Qi, diode D4 and transistor Qdn, and returns to the minus terminal of the power source capacitor 11. Since the current path Pn5 is a current path without via the reactor L, a short-circuit current flows through the dynamic characteristics test device 1. For this reason, in the case where the overcurrent preventing circuit 14 includes the diode bridge, the transistor Qi needs to be set to the ON-state after the transistors Qp and Qhp are set to the OFF-state in operating the overcurrent preventing circuit 14. The same goes for the P-side switching measurement.

In this way, in the case where the overcurrent preventing circuit 14 includes the transistors Qif and Qir, and the diodes Dif and Dir, the transistors Qif and Qir are connected electrically in series so that if any of the transistors Qif and Qir is set to the ON-state, only a current flows unidirectionally through the overcurrent preventing circuit 14. For this reason, even if the transistor Qir is set to the ON-state before the transistors Qp and Qhp are set to the OFF-state in the N-side switching measurement, a short-circuit current does not flow through the transistor Qdn, and even if the transistor Qif is set the ON-state before the transistors Qp and Qhn are set to the OFF-state in the P-side switching measurement, a short-circuit current does not flow through the transistor Qdp. Therefore, a restriction on a timing to cause the overcurrent preventing circuit 14 to operate can be reduced, allowing simplification of control.

Moreover, the DUT 50 is not limited to a 2in1 type power semiconductor module, but may be a device including the transistor Qdp and the transistor Qdn. For example, the DUT 50 may be a power semiconductor module of 4in1 type, 6in1 type, 8in1 type or the like.

Fig. 26 is a circuit diagram showing another modification example of the dynamic characteristics test device. A dynamic characteristics test device 1A shown in Fig. 26 is a dynamic characteristics test device in a case of using a 6in1 type power semiconductor module as a DUT. The dynamic characteristics test device 1A differs, as compare with the dynamic characteristics test device 1, in that a DUT 50A is a device under test in place of the DUT 50, and that a testing circuit 10A is included in place of the testing circuit 10. The testing circuit 10A differs, as compared with the testing circuit 10, in further including a selection circuit 17. Note that the overcurrent detecting circuit 20 is omitted to be shown in Fig. 26.

The DUT 50A is a 6in1 type power semiconductor module including six transistors. Specifically, the DUT 50A has three phases (U, V, W phases) in parallel each of which includes a set of the transistors Qdp and Qdn and the diodes Ddp and Ddn in the DUT 50. That is, the DUT 50A has transistors Qdpu and Qdnu, and diodes Ddpu and Ddnu for the U phase, has transistors Qdpv and Qdnv, and diodes Ddpv and Ddnv for the V phase, and has transistors Qdpw and Qdnw, and diodes Ddpw and Ddnw for the W phase. The DUT 50A has a P terminal, a U terminal, a V terminal, a W terminal and an N terminal. The P terminal is electrically connected with collectors of the transistors Qdpu, Qdpv, and Qdpw, and the N terminal is electrically connected with emitters of the transistors Qdnu, Qdnv, and Qdnw. The U terminal is electrically connected with an emitter of the transistor Qdpu and a collector of the transistor Qdnu, the V terminal is electrically connected with an emitter of the transistor Qdpv and a collector of the transistor Qdnv, and the W terminal is electrically connected with an emitter of the transistor Qdpw and a collector of the transistor Qdnw. For example, the DUT 50A may be used for a three-phase inverter circuit, and the transistor Qdpu may be used for an upper arm of the U phase, the transistor Qdnu for a lower arm of the U phase, the transistor Qdpv for an upper arm of the V phase, the transistor Qdnv for a lower arm of the V phase, the transistor Qdpw for an upper arm of the W phase, and the transistor Qdnw for a lower arm of the W phase.

The selection circuit 17 is a circuit for selecting the transistors Qdp and Qdn of the phase which is to make the switching measurement from the transistors Qdp and Qdn in three phases (U, V, W phases) included in the DUT 50A. The selection circuit 17 includes switches SWu, SWv, and SWw. The switches SWu, SWv, and SWw each are a relay. One ends of the switches SWu, SWv, and SWw are electrically connected with each other, and are electrically connected with the other end of the reactor L, the collector of the transistor Qir, the cathode of the diode Dir, the other end of the switch SWp, and one end of the switch SWn. The other ends of the switches SWu, SWv, and SWw are electrically connected with the U, V, and W terminals of the DUT 50A, respectively.

In the dynamic characteristics test device 1A configured like this, the control device 30 further outputs gate signals Sqdpu, Sqdnu, Sqdpv, Sqdnv, Sqdpw, and Sqdnw to the transistors Qdpu, Qdnu, Qdpv, Qdnv, Qdpw, and Qdnw, respectively to switch between the ON-state and the OFF-state of each transistor. Moreover, the control device 30 outputs relay signals Sswu, Sswv, and Ssww to the switches SWu, SWv, and SWw, respectively to switch between the ON-state and the OFF-state of each switch. In also a case where the DUT is another type power semiconductor module, a configuration similar to the dynamic characteristics test device 1A may be employed.

1, 1A ... dynamic characteristics test device, 11 ... power source capacitor (power source), 13 ... selection circuit, 14 ... overcurrent preventing circuit, 15 ... high-speed breaking circuit, 30 ... control device, 50, 50A ... DUT (device under test), Cd ... connection part (first connection part), Cs ... connection part (second connection part), D1 ... diode (second diode), D2 ... diode (first diode), D3 ... diode (fifth diode), D4 ... diode (sixth diode), Dif ... diode (first diode, fourth diode), Dir ... diode (second diode, third diode), L ... reactor, Qdn, Qdnu, Qdnv, Qdnw ... transistor (second semiconductor), Qdp, Qdpu, Qdpv, Qdpw ... transistor (first semiconductor), Qcf ... transistor (fifth switch unit), Qcr ... transistor (fifth switch unit), Qhn ... transistor (second switch unit), Qhp ... transistor (first switch unit), Qi ... transistor (third switch unit, fourth switch unit), Qif ... transistor (fourth switch unit), Qir ... transistor (third switch unit)

Claims

A dynamic characteristics test device for conducting a dynamic characteristics test on a device under test including a first semiconductor and a second semiconductor connected electrically in series, the device comprising:
a power source configured to supply a current for the dynamic characteristics test;
a reactor that is a load on the first semiconductor and the second semiconductor;
a selection circuit including a first switch unit and a second switch unit connected electrically in series and configured to select any of the first semiconductor and the second semiconductor as an object of switching measurement; and
an overcurrent preventing circuit connected electrically in parallel with the reactor and configured to consume an energy stored in the reactor,
wherein
a first connection part and a second connection part are electrically connected to each other via the reactor, the first connection part electrically connecting the first semiconductor and the second semiconductor, and the second connection part electrically connecting the first switch unit and the second switch unit,
a positive terminal of the power source is electrically connected with the first switch unit and the first semiconductor,
a negative terminal of the power source is electrically connected with the second switch unit and the second semiconductor,
the overcurrent preventing circuit includes a third switch unit and a first diode which are connected electrically in series, and a fourth switch unit and a second diode which are connected electrically in series,
the first diode is arranged in a manner such that a forward direction of the first diode is a direction from the first connection part toward the second connection part, and
the second diode is arranged in a manner such that a forward direction of the second diode is a direction from the second connection part toward the first connection part.
The dynamic characteristics test device according to claim 1, wherein
the overcurrent preventing circuit includes a third diode connected electrically in parallel with the third switch unit, and a fourth diode connected electrically in parallel with the fourth switch unit,
the third diode is arranged in a manner such that a forward direction of the third diode is opposite to the forward direction of the first diode, and
the fourth diode is arranged in a manner such that a forward direction of the fourth diode is opposite to the forward direction of the second diode.
The dynamic characteristics test device according to claim 2, wherein
the first diode and the fourth diode are the same diode, and
the second diode and the third diode are the same diode.
The dynamic characteristics test device according to claim 1, wherein
the overcurrent preventing circuit further includes a fifth diode and a sixth diode,
the third switch unit and the fourth switch unit are the same switch unit,
an anode of the second diode and a cathode of the first diode are electrically connected with one end of the reactor,
an anode of the fifth diode and a cathode of the sixth diode are electrically connected with the other end of the reactor, and
a cathode of the second diode and a cathode of the fifth diode are electrically connected via the third switch unit with an anode of the first diode and an anode of the sixth diode.
The dynamic characteristics test device according to any one of claims 1 to 4, further comprising:
a high-speed breaking circuit configured to cause the overcurrent preventing circuit to consume an energy stored in the reactor,
wherein
the high-speed breaking circuit includes a fifth switch unit connected electrically in series with the reactor.
The dynamic characteristics test device according to any one of claims 1 to 5, further comprising:
a control device configured to perform switching control between an ON-state and an OFF-state of each of the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit,
wherein
the control device sets the second switch unit to the ON-state so as to set the first semiconductor to an object of switching measurement, and sets the first switch unit to the ON-state so as to set the second semiconductor to an object of switching measurement, and
the control device sets the second switch unit to the OFF-state and sets the fourth switch unit to the ON-state in response to a current having an electric current amount exceeding a predetermined threshold being detected in making a switching measurement of the first semiconductor.
The dynamic characteristics test device according to claim 6, wherein the control device sets the first switch unit to the OFF-state and sets the third switch unit to the ON-state in response to a current having an electric current amount exceeding a predetermined threshold being detected in making a switching measurement of the second semiconductor.
A dynamic characteristics test method for conducting a dynamic characteristics test on a device under test including a first semiconductor and a second semiconductor connected electrically in series, comprising:
a step of making a switching measurement of the first semiconductor by selecting the first semiconductor as an object of switching measurement, and flowing a current in one direction through a reactor that is a load on the first semiconductor and the second semiconductor;
a step of causing an overcurrent preventing circuit to consume an energy stored in the reactor in response to a current having an electric current amount exceeding a predetermined threshold being detected in the step of making the switching measurement of the first semiconductor;
a step of making a switching measurement of the second semiconductor by selecting the second semiconductor as an object of switching measurement, and flowing a current in the other direction through the reactor; and
a step of causing the overcurrent preventing circuit to consume an energy stored in the reactor in response to a current having an electric current amount exceeding a predetermined threshold being detected in the step of making the switching measurement of the second semiconductor.