WO2016188026A1 - Procédé et dispositif de synchronisation temporelle entre une carte mère primaire et une carte mère de secours - Google Patents

Procédé et dispositif de synchronisation temporelle entre une carte mère primaire et une carte mère de secours Download PDF

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Publication number
WO2016188026A1
WO2016188026A1 PCT/CN2015/092571 CN2015092571W WO2016188026A1 WO 2016188026 A1 WO2016188026 A1 WO 2016188026A1 CN 2015092571 W CN2015092571 W CN 2015092571W WO 2016188026 A1 WO2016188026 A1 WO 2016188026A1
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Prior art keywords
control board
main control
packet
time
standby
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PCT/CN2015/092571
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English (en)
Chinese (zh)
Inventor
唐明理
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中兴通讯股份有限公司
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Publication of WO2016188026A1 publication Critical patent/WO2016188026A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter

Definitions

  • the present invention relates to the field of communications, and in particular, to a method and apparatus for time synchronization between an active main control board and a standby main control board.
  • the traditional time synchronization scheme configures a Global Positioning System (GPS) or a BeiDou Navigation Satellite System (BD) device for each base station, so each base station needs to be configured with a time source, which is costly. From the perspective of cost, the use of bearer network to transmit high-precision time synchronization information has become a future development trend. With the continuous evolution of bearer technology, the need for time synchronization networks to provide time synchronization information to telecommunication network operators is becoming more and more urgent.
  • GPS Global Positioning System
  • BD BeiDou Navigation Satellite System
  • the main purpose of the embodiments of the present invention is to provide a method and apparatus for time synchronization between an active main control board and a standby main control board, so as to at least solve the problem of high cost in implementing the time synchronization scheme in the related art.
  • a method for time synchronization between an active main control board and a standby main control board including: an active main control board and a standby main control determined in a state of the main control board
  • the multiple timestamps are sent and received when the PTP packet is sent, and the preset rule is used to calculate the preset time according to the multiple timestamps. Determining a time compensation value between the main control board and the standby main control board; and correcting a time deviation of the standby main control board relative to the main main control board according to the time compensation value.
  • the acquiring, by using the first preset time, the multiple timestamps when sending and receiving the PTP packet includes: receiving, by the standby main control board, the PTP packet sent by the active main control board The first timestamp T1 when the first message is sent and the second timestamp T2 when the first message is received is carried in the first message;
  • the standby main control board sends the second packet in the PTP packet to the main control board, obtain a third timestamp T3 when the second packet is sent, and the standby main control board
  • the fourth timestamp T4 when the third packet is sent in the third packet is obtained.
  • the method further includes: acquiring the state of the main control board every second preset time, where the main control board is the main control board and the main control board is successfully performing the switching. And switching the state of the main control board to the state of the standby main control board; when the main control board is the standby main control board, and the standby main control board successfully performs the switching, the standby main The status of the control board is switched to the status of the active main control board.
  • the state of switching the state of the active main control board to the standby main control board includes: latching a current time stamp of the main control board, and closing the PTP report of the main main control board And sending the second packet to the standby main control board, and triggering the sending of the second packet.
  • the switching the state of the standby main control board to the state of the active main control board includes: latching the current time stamp of the main control board, and closing the PTP report of the standby main control board Sending the text, and stopping the calculation of the compensation value and the trimming of the time offset and modifying the state of the main control board to the standby main control board state; the first message and the third message are Writing to the active main control board, and triggering the sending of the first message and the third message.
  • the second preset time is less than the first preset time.
  • an apparatus for time synchronization between an active main control board and a standby main control board including: an obtaining module, configured as an active main control board determined in a state of the main control board Obtaining a plurality of timestamps when transmitting and receiving the PTP packet every first preset time, and performing a precise time synchronization protocol PTP packet forwarding with the standby main control board;
  • the time stamp uses a preset rule to calculate a time compensation value between the main control board and the standby main control board; and the correction module is configured to correct the standby main control board according to the time compensation value The time deviation of the main control board.
  • the acquiring module includes: a first acquiring unit, configured to acquire, when the standby main control board receives the first packet in the PTP packet sent by the active main control board a first timestamp T1 when the first message is sent and a second timestamp T2 when the first message is received, and a second acquiring unit, configured to be in the standby
  • the main control board sends the second packet in the PTP packet to the main control board, obtains a third timestamp T3 when the second packet is sent
  • the third acquiring unit is configured to be in the standby
  • the main control board acquires a fourth timestamp when the third packet is sent in the third packet. T4.
  • the PTP report is adopted for the main control board and the standby main control board in the main control board. Forwarding the file, and obtaining a plurality of timestamps when the PTP message is sent and received at a preset time, and calculating between the main control board and the standby main control board according to the multiple timestamps and preset rules
  • the time compensation value is used to correct the time deviation of the standby main control board relative to the main control board.
  • the embodiment of the present invention adopts a software method to realize time synchronization, and solves the time synchronization in the related art. The cost of the program is high.
  • FIG. 1 is a flowchart of a method for time synchronization between an active main control board and a standby main control board according to an embodiment of the present invention
  • FIG. 2 is a block diagram showing the structure of a device for time synchronization between an active main control board and an alternate main control board according to an embodiment of the present invention
  • FIG. 3 is a structural block diagram of an apparatus for implementing time synchronization of a standby main control board by using a PTP message according to an optional embodiment of the present invention
  • FIG. 4 is a schematic diagram of a T1, T2, T3, T4 timestamp generation mechanism according to an alternative embodiment of the present invention
  • FIG. 5 is a flow chart of an initial state control method in accordance with an alternative embodiment of the present invention.
  • FIG. 6 is a flow chart of a 1-second timer control in accordance with an alternative embodiment of the present invention.
  • FIG. 7 is a flow diagram of a 100 millisecond timer control in accordance with an alternate embodiment of the present invention.
  • FIG. 1 is a method for time synchronization between the main main control board and the standby main control board according to an embodiment of the invention.
  • Flowchart, as shown in Figure 1, the steps of the method include:
  • Step S102 When the precision time synchronization protocol (PTP) packet is forwarded between the active main control board and the standby main control board, the first preset time is obtained. Multiple timestamps when sending and receiving PTP messages;
  • PTP precision time synchronization protocol
  • Step S104 Calculate a time compensation value between the active main control board and the standby main control board by using a preset rule according to the multiple timestamps;
  • Step S106 Correct the time deviation of the standby main control board relative to the main main control board according to the time compensation value.
  • the PTP packet is forwarded to the main control board and the standby main control board in the main control board, and then the transmission and reception are obtained every first preset time.
  • the multiple timestamps of the PTP packet are calculated according to the multiple timestamps and preset rules, and the time compensation value between the main control board and the standby main control board is calculated, and the compensation value is used to correct the relative main control board.
  • the software uses the software to implement time synchronization, and solves the problem of high cost in implementing the time synchronization scheme in the related art.
  • the method may be implemented as follows:
  • Step S11 When the standby main control board receives the first packet in the PTP packet sent by the active main control board, the first timestamp T1 when the first packet is sent in the first packet is obtained. Receiving a second timestamp T2 when the first message is received;
  • Step S12 When the standby main control board sends the second packet in the PTP packet to the main control board, the third timestamp T3 when the second packet is sent is obtained;
  • Step S13 When the standby main control board receives the third packet in the PTP packet sent by the active main control board, the fourth timestamp T4 when the third packet is sent in the third packet is obtained.
  • the time compensation value can be obtained by:
  • Time delay value [(T2 + T4) - (T1 + T3)] / 2;
  • Time compensation value (T2-T1) - time delay value.
  • the method in this embodiment may further include:
  • Step S22 Acquire the state of the main control board every second preset time.
  • the main control board is the main control board and the main control board successfully performs the switching, the state of the main control board is switched to the standby state. The status of the main control board;
  • Step S23 When the main control board is the standby main control board and the standby main control board successfully performs the switching, the state of the standby main control board is switched to the state of the active main control board.
  • the manner in which the state of the active main control board in the step S22 is switched to the state of the standby main control board can be implemented by: latching the current time stamp of the main control board, and closing the main control board.
  • the PTP packet is sent, and the status of the main control board is changed to the status of the standby main control board.
  • the second packet is written to the standby main control board, and the second packet is sent.
  • the manner of switching the state of the standby main control board to the state of the active main control board in step S23 can be implemented in the following manner: latching the current time stamp of the main control board, and turning off the standby
  • the PTP packet of the main control board is sent, and the calculation of the compensation value and the modification of the time offset are performed, and the state of the main control board is changed to the state of the standby main control board; the first message and the third message are written to the main use.
  • the main control board triggers the sending of the first packet and the third packet.
  • the current time stamp may be latched during the main conversion process of the main control board, and the PTP message of the PTP port is closed by the software, and the PTP is simultaneously The port state modification is switched to the slave state.
  • the delay_req message format is written into the FPGA register by the CPU in advance, and the delay_req message is sent.
  • the current time stamp is latched, and the PTP packet transmission of the PTP port is closed by the software, and the time offset calculation and the offset correction are stopped.
  • the PTP port status is changed to master.
  • the sync and delay_resp message formats are written into the FPGA register by the CPU in advance, and the sync and delay_resp messages are sent.
  • the second preset time involved in the embodiment is less than the first preset time.
  • the second preset time may be 100 milliseconds, and the first preset time is 1 second.
  • the first preset and the second preset value here is merely an example, and may be corresponding according to actual conditions. The value.
  • a device for time synchronization between the main control board and the standby main control board is provided.
  • the device is used to implement the foregoing embodiments and preferred embodiments, and details are not described herein.
  • the term “module” "unit” may implement a combination of software and/or hardware of a predetermined function.
  • the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • the apparatus includes: an obtaining module 22, which is set in a state of the main control board.
  • the timestamps are sent and received at the first preset time.
  • the correction module 26 is coupled to the calculation module 24 and configured to correct the time deviation of the standby main control board relative to the main control board according to the time compensation value.
  • the obtaining module 22 includes: a first acquiring unit, configured to: when the standby main control board receives the first packet in the PTP packet sent by the active main control board, obtain the sending in the first packet The first timestamp T1 of the first packet and the second timestamp T2 when the first packet is received; the second obtaining unit is configured to send the second of the PTP packets to the main control board on the standby main control board The third timestamp T3 is sent when the second packet is sent, and the third acquiring unit is configured to obtain the third packet in the PTP packet sent by the active main control board when the standby main control board receives the third packet. The fourth timestamp T4 when the third message is sent carried in the third packet.
  • the device may further include: a first switching module, configured to acquire the state of the main control board every second preset time, where the main control board is the main control board and the main control board is performing the switching When the switch is successful, the state of the main control board is switched to the state of the standby main control board.
  • the second switch module is set to be the standby main control board when the main control board is the standby main control board. The status of the control board is switched to the status of the active main control board.
  • the first switching module is configured to latch the current timestamp of the main control board, and disable the sending of the PTP message of the main control board, and modify the state of the main control board to the standby main control board.
  • the second packet is written to the standby main control board, and the second packet is sent.
  • the second switching module is configured to latch the current timestamp of the main control board, and close the sending of the PTP message of the standby main control board, and stop the calculation of the compensation value, the time deviation trimming, and the state of the main control board. Change to the status of the standby main control board; write the first packet and the third packet to the active main control board, and trigger the sending of the first packet and the third packet.
  • the optional embodiment provides a method for realizing time synchronization of the main control board by using a precise time protocol (Precision Time ProTocol PTP) message.
  • a precise time protocol Precision Time ProTocol PTP
  • the standby main control board in order to implement the standby main control board to track the main control clock, ensure that the system reference clocks of the primary and backup boards are the same, and the primary and backup main control boards are respectively virtualized as two PTP ports interacted by the PTP protocol.
  • the physical line can be seen as completely symmetrical, in accordance with the conditions of use of the PTP protocol. Therefore, the active main control board is virtualized into a master port, and the standby main control board is virtualized into a slave port.
  • the Ethernet switching processing chip on the main control board is used to transmit PTP protocol packets.
  • the software calculates the slave side relative to the PTP protocol algorithm. The deviation at the master end is adjusted accordingly.
  • the optional embodiment does not need to support the BMC algorithm, and only needs to configure the master/slave state of the port according to the state of the main control board. Therefore, it is not necessary to construct an announce message to negotiate the master/slave state of the port.
  • FIG. 3 is a structural block diagram of a device for implementing time synchronization of a standby main control board by using a PTP packet according to an optional embodiment of the present invention.
  • the main control board and the standby main control board include: a network switching processing unit, a CPU processing unit, and a Field-Programmed GaTe Array (FPGA) processing unit;
  • FPGA Field-Programmed GaTe Array
  • the function of the Ethernet switching processing unit is performed by a dedicated Ethernet switching processing chip or a CPU to perform PTP packet forwarding processing, and the packet type is identified, and the PTP packet forwarding between the primary and backup boards is completed.
  • the packet congestion time is negligible, so it can be regarded as the packet receiving and sending processing between the main and standby FPGAs on the main control board, and the delay is small, and the obtained synchronization precision is high.
  • the CPU processing unit is configured to create a virtual PTP port after the main control board competes for decision making the primary and backup states, and complete basic parameter configuration.
  • a synchronous packet Synchronous PackeT
  • a delay_resp packet Delay RequesT PackeT, delay request packet
  • a delay_req packet to be sent Delay RequesT PackeT, delay response message
  • the CPU processing is further configured to acquire T1, T2, T3, and T4 timestamps from the FPGA processing unit register on the slave side, calculate a time offset from the main control board according to the algorithm, and write the logic counter of the FPGA processing unit, thereby implementing Track the requirements for the time stamp of the main control board.
  • FIG. 4 is a schematic diagram of a T1, T2, T3, T4 time stamp generation mechanism according to an alternative embodiment of the present invention.
  • a 1 second timer timing reads T1, T2, T3, and T4 time stamps from an FPGA. And complete the OffseT calculation and write the FPGA to complete the time synchronization.
  • the timing time is up, and the FPGA processing unit sends a Sync message by applying a T1 timestamp in the message.
  • the Sync message is received by the FPGA, the message receives the time stamp T2, and the time stamp T1 is extracted in the message.
  • the FPGA immediately sends a delay_req message and puts a T3 timestamp.
  • the delay_req message is received by the FPGA, and the time stamp T4 is recorded; the T4 timestamp is inserted into the delay_resp message and transmitted to the slave; at the slave receiving end, the delay_resp message is received by the FPGA, and the time stamp T4 is extracted; therefore, the slave is
  • the end FPGA processing unit can extract the T1, T2, T3, and T4 time stamps for the CPU processing unit to calculate the time offset.
  • the optional embodiment further relates to another timer, a 100 millisecond timer, which is configured to poll the main board and the standby state of the main control board in real time, and switch the PTP port status and configuration according to the status of the primary and backup states.
  • a 100 millisecond timer configured to poll the main board and the standby state of the main control board in real time, and switch the PTP port status and configuration according to the status of the primary and backup states.
  • the CPU processing unit adopts a 100ms timer and is set to poll the main board and the standby status of the main control board in real time. If the board is currently the main board, the main board is switched. If the switch is not completed, continue to judge whether the switchover occurs; otherwise, the switchover is completed, switch to the standby board state, and obtain the time compensation value. If the board is currently a spare board, spare The master detects that a switchover has occurred, and the switchover is not completed, and continues to determine whether a switchover occurs; otherwise, the switchover is completed, and the time compensation value is obtained.
  • the PTP packet is sent by the software to disable the PTP packet transmission, and the PTP port state is changed to the slave state.
  • the delay_req message format is written into the FPGA register by the CPU in advance, and the delay_req message is sent.
  • the current time stamp is latched, and the PTP packet transmission of the PTP port is closed by the software, and the time offset calculation and the offset correction are stopped.
  • the PTP port status is changed to master.
  • the sync and delay_resp message formats are written into the FPGA register by the CPU in advance, and the sync and delay_resp messages are sent.
  • the physical position of the active and standby main control boards is completely bidirectional. Therefore, the PTP protocol can be applied to the primary and backup boards for time synchronization.
  • the PTP packet is forwarded through the Ethernet switch processing chip to perform PTP packet negotiation, and the time tracking function of the main board and the standby board of the main control board is set.
  • FIG. 5 is a flowchart of an initial state control method according to an alternative embodiment of the present invention. As shown in FIG. 5, the steps of the method include:
  • Step S502 The main control board is powered on
  • Step S504 determining whether the main control board is used, when the determination result is yes, executing step S506, and if the determination result is no, executing step S508;
  • Step S506 The main control board configures a PTP master port (main port) with an agreed port number;
  • Step S508 The standby main control board configures a PTP slave port (secondary port) of the agreed port number.
  • one port state is configured as a master PTP port by default.
  • the one-step method is used in the Ethernet packet encapsulation format.
  • the default interval of the PTP protocol is used to set the interval for the packet to be sent and the delay_resp packet format.
  • the basic parameters of the PTP port are configured as follows:
  • Delay measurement method one-step method
  • Sync message sending interval 0, send one sync packet per second
  • Source port ID pre-assigned port ID
  • the CPU saves the configuration data and status of the PTP port, and sets the time stamp of the PTP port to be polled by the timer. Construct the sync message and delay_resp message format to be sent, and write the FPGA register in advance.
  • the standby main control board is configured with a PTP port and the port status is slave.
  • the basic parameters of the basic PTP port are configured.
  • the Ethernet packet encapsulation format is used in one-step mode.
  • the packet transmission interval is set with the default parameters defined by the PTP protocol.
  • the delay_req message format is pre-written by the CPU into the FPGA registers.
  • the basic parameters of the PTP port are configured as follows:
  • Delay measurement method one-step method
  • Delay_req message sending interval 1, sending 2 packets per second;
  • Source port ID pre-assigned port ID
  • the CPU processing unit saves the configuration data and status of the PTP port, and is used by the timer to poll the time stamp of the PTP port. Constructs the delay_req message format that needs to be sent, which is pre-written into the FPGA register by the CPU.
  • control includes:
  • Step S602 1 second timer time is up;
  • Step S604 determining whether to reserve the main control board; when the determination result is yes, executing step S606, and when the determination result is no, ending;
  • Step S606 Read T1, T2, T3, T4 timestamps from the PFGA processing unit;
  • Step S608 Calculate the time offset compensation value and write it to the FPGA.
  • the slave end may obtain the T1, T2, T3, and T4 time stamps from the FPGA processing unit register, calculate the time deviation from the active main control board according to the algorithm, and write the time to the FPGA processing unit.
  • a logic counter that enables tracking of the time stamp of the active main control board.
  • the FPGA processing unit implements a 1MS timer, and periodically sends PTP packets according to the PTP packet sending frequency configured by the CPU processing unit. In order to achieve fast measurement, the delay and delay mechanism messages are sent and received by the FPGA of the main and standby main control boards.
  • the FPGA processing unit implements a 1MS timer.
  • the FPGA periodically sends PTP packets according to the PTP packet sending frequency configured by the CPU processing unit, and performs a corresponding time stamp.
  • the FPGA filters and resolves the PTP packet of the port and extracts the corresponding time stamp.
  • the CPU processing unit maintains a 1S timer. If the board is the main board and does nothing, the board is a standby board and is not in a swapping state.
  • the pre-agreed PTP slave port is polled, and the timestamp T1 is read from the FPGA.
  • the software calculates OffseT, writes the calculated OffseT to the FPGA processing unit, and the FPGA corrects the slave main control board from time to time synchronization.
  • FIG. 7 is a flowchart of 100 millisecond timer control according to an alternative embodiment of the present invention. As shown in FIG. 7, the control flow includes:
  • Step S702 The 100ms timer expires
  • Step S704 determining whether it is currently used; when the determination is yes, step S706 is performed; if the determination is no, step S714 is performed;
  • Step S706 determining whether the primary transfer is performed, when the determination result is yes, executing step S708; and when the determination result is negative, ending;
  • Step S708 Turn off the PTP packet.
  • Step S710 determining whether the main conversion is completed, when the determination result is yes, executing step S712; if the determination result is no, executing step S704;
  • Step S712 The PTP slave port (secondary port) of the port number of the standby configuration is agreed, and then ends;
  • Step S714 determining whether to prepare the master, if the determination result is yes, executing step S716, and when the determination result is no, ending;
  • Step S716 Turn off the PTP packet.
  • Step S718 determining whether the backup transfer is completed; when the determination is yes, executing step S720, and if the determination result is no, executing step S714;
  • Step S720 The standby configuration appoints the PTP slave port (secondary port) of the port, and then ends.
  • the clock software needs to adopt a 100ms timer, and is set to poll the main board and the standby state of the main control board in real time, and the software completes the switching of the PTP port status according to the primary and backup states and the corresponding configuration. deal with. If the board is currently the main board, the main board is switched. If the switch is not completed, continue to judge whether to switch; otherwise, the switch is completed, switch to the standby board state, and obtain the time compensation value.
  • the standby master detects that a switchover has occurred, and the switchover is not completed, and continues to determine whether to switch; otherwise, the switchover is completed, and the time compensation value is obtained; wherein the main control board is in the active state, the software needs to close the switch.
  • PTP packets are sent on the PTP port. If the primary transition is completed, the PTP port state modification is switched to the slave state. Delay_req by the CPU in advance The message format is written to the FPGA register and the delay_req message is sent. The main control board is switched to the master state. The software first disables the sending of PTP packets on the PTP port. And stop calculating the calculation of time deviation and deviation correction. If the backup master is completed, the status of the PTP port is changed to master. The sync and delay_resp message formats are written into the FPGA register by the CPU in advance, and the sync and delay_resp messages are sent.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
  • the PTP packet is forwarded to the main control board and the standby main control board in the main control board, and the PTP message is sent and received every other preset time.
  • a timestamp according to the multiple timestamps and a preset rule, calculating a time compensation value between the main control board and the standby main control board, The compensation value is used to correct the time deviation of the standby main control board with respect to the main control board.
  • the embodiment of the present invention adopts a software method to realize time synchronization, and solves the problem that the implementation of the time synchronization scheme in the related art is costly.

Abstract

L'invention concerne un procédé et un dispositif de synchronisation temporelle entre une carte mère primaire et une carte mère de secours. Le procédé consiste : lors du transfert d'un message PTP de protocole de synchronisation temporelle précise entre une carte mère active, ayant un état de carte mère, et une carte mère de secours, à acquérir une pluralité d'estampilles temporelles lors de l'envoi et de la réception d'un message PTP à chaque premier moment prédéfini ; à calculer une valeur de compensation temporelle entre la carte mère primaire et la carte mère de secours en adoptant une règle prédéfinie sur la base de la pluralité d'estampilles temporelles ; à corriger une déviation temporelle de la carte mère de secours par rapport à la carte mère primaire en fonction de la valeur de compensation temporelle. Dans la présente invention, une synchronisation temporelle est exécutée au moyen d'un logiciel et le problème dans l'état antérieur de la technique, selon lequel les coûts de la solution pour mettre en œuvre la synchronisation sont élevés, est résolu.
PCT/CN2015/092571 2015-05-22 2015-10-22 Procédé et dispositif de synchronisation temporelle entre une carte mère primaire et une carte mère de secours WO2016188026A1 (fr)

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CN201510269107.0 2015-05-22
CN201510269107.0A CN106301745A (zh) 2015-05-22 2015-05-22 主用主控板与备用主控板之间时间同步的方法及装置

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Publication number Priority date Publication date Assignee Title
CN112311621A (zh) * 2020-10-15 2021-02-02 新华三技术有限公司合肥分公司 通信检测方法及装置
CN113162813A (zh) * 2020-01-22 2021-07-23 烽火通信科技股份有限公司 一种ptp报文丢失检测分析方法和装置
CN113839816A (zh) * 2021-09-23 2021-12-24 新华三信息安全技术有限公司 一种配线装置及其故障切换方法
CN114598639A (zh) * 2022-01-28 2022-06-07 新华三技术有限公司合肥分公司 一种报文处理方法及装置
CN116436555A (zh) * 2023-06-09 2023-07-14 新华三技术有限公司 一种时间同步方法、装置及分布式网络设备

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106851817A (zh) * 2017-02-20 2017-06-13 成都物梦工场信息技术有限公司 一种基站之间的高精度时钟同步方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101425961A (zh) * 2007-10-31 2009-05-06 华为技术有限公司 实现链路状态数据库同步方法、路由器及线路板、主控板
CN101483540A (zh) * 2008-01-11 2009-07-15 上海博达数据通信有限公司 一种高端数据通信设备中的主备倒换方法
CN102098155A (zh) * 2011-03-18 2011-06-15 北京国智恒电力管理科技有限公司 基于ptp协议实现亚微秒级同步精度的方法
US20120275501A1 (en) * 2011-04-27 2012-11-01 Sergiu Rotenstein Pluggable synchronization clocks, networks, systems and methods related thereto
CN102781090A (zh) * 2012-06-28 2012-11-14 华为技术有限公司 一种多模基站及其实现方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101242419B1 (ko) * 2009-07-20 2013-03-12 한국전자통신연구원 병렬처리 기반의 시각 동기화 장치
CN102013931B (zh) * 2009-09-08 2015-04-01 中兴通讯股份有限公司 时间同步方法及系统、从属定时设备及主定时设备
JP5576747B2 (ja) * 2010-09-06 2014-08-20 株式会社日立製作所 通信システム及び時刻同期方法
CN103763056A (zh) * 2013-12-31 2014-04-30 电信科学技术第五研究所 时间同步高精度远程监控的方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101425961A (zh) * 2007-10-31 2009-05-06 华为技术有限公司 实现链路状态数据库同步方法、路由器及线路板、主控板
CN101483540A (zh) * 2008-01-11 2009-07-15 上海博达数据通信有限公司 一种高端数据通信设备中的主备倒换方法
CN102098155A (zh) * 2011-03-18 2011-06-15 北京国智恒电力管理科技有限公司 基于ptp协议实现亚微秒级同步精度的方法
US20120275501A1 (en) * 2011-04-27 2012-11-01 Sergiu Rotenstein Pluggable synchronization clocks, networks, systems and methods related thereto
CN102781090A (zh) * 2012-06-28 2012-11-14 华为技术有限公司 一种多模基站及其实现方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
CHEN, HUAJIN ET AL.: "New Mechanism of Realizing Time-Synchronization in LAN by Using CPU Time Stamp", JOURNAL OF COMPUTER APPLICATIONS, vol. 29, no. 11, 1 November 2009 (2009-11-01), ISSN: 1001-9081 *
CHU, YINGJUN ET AL.: "An Implementation Method of IEEE 1588 Time Synchronization Technology Based on Hardware Timestamping", MODERN TRANSMISSION, vol. 1, no. 1, 15 February 2011 (2011-02-15), ISSN: 1673-5137 *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113162813A (zh) * 2020-01-22 2021-07-23 烽火通信科技股份有限公司 一种ptp报文丢失检测分析方法和装置
CN113162813B (zh) * 2020-01-22 2022-06-03 烽火通信科技股份有限公司 一种ptp报文丢失检测分析方法和装置
CN112311621A (zh) * 2020-10-15 2021-02-02 新华三技术有限公司合肥分公司 通信检测方法及装置
CN112311621B (zh) * 2020-10-15 2022-05-24 新华三技术有限公司合肥分公司 通信检测方法及装置
CN113839816A (zh) * 2021-09-23 2021-12-24 新华三信息安全技术有限公司 一种配线装置及其故障切换方法
CN113839816B (zh) * 2021-09-23 2024-01-19 新华三信息安全技术有限公司 一种配线装置及其故障切换方法
CN114598639A (zh) * 2022-01-28 2022-06-07 新华三技术有限公司合肥分公司 一种报文处理方法及装置
CN114598639B (zh) * 2022-01-28 2023-12-26 新华三技术有限公司合肥分公司 一种报文处理方法及装置
CN116436555A (zh) * 2023-06-09 2023-07-14 新华三技术有限公司 一种时间同步方法、装置及分布式网络设备
CN116436555B (zh) * 2023-06-09 2023-08-18 新华三技术有限公司 一种时间同步方法、装置及分布式网络设备

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