WO2016188008A1 - 一种提高晶振长期稳定度的装置和方法 - Google Patents

一种提高晶振长期稳定度的装置和方法 Download PDF

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WO2016188008A1
WO2016188008A1 PCT/CN2015/091514 CN2015091514W WO2016188008A1 WO 2016188008 A1 WO2016188008 A1 WO 2016188008A1 CN 2015091514 W CN2015091514 W CN 2015091514W WO 2016188008 A1 WO2016188008 A1 WO 2016188008A1
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frequency
crystal oscillator
voltage
output
phase detector
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PCT/CN2015/091514
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English (en)
French (fr)
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吴成林
张泉
王崔州
杨晓东
吴洋
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成都西蒙电子技术有限公司
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Publication of WO2016188008A1 publication Critical patent/WO2016188008A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

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  • the invention relates to a device for improving the long-term stability of a crystal oscillator, and particularly relates to a device for improving the long-term stability of a crystal oscillator by using a microwave phase-locked loop technology.
  • crystal oscillators are indispensable components in various fields such as satellite navigation, communication, broadcasting, radar, precision guidance, electronic countermeasures, remote telemetry, etc., and the frequency accuracy of crystal oscillators is increasingly demanding. high.
  • the industry has designed a constant temperature crystal oscillator (OCXO) using temperature compensation technology, and its frequency stability has been greatly improved.
  • OXO constant temperature crystal oscillator
  • the main reasons include aging, external environmental changes, and voltage-controlled voltage imbalance.
  • the main reason for the aging of the crystal oscillator is the mass effect and the stress effect, which are unavoidable error terms, and the external environment change and the voltage-controlled voltage imbalance are also unavoidable. Therefore, after the crystal resonator is used for a period of time, its frequency accuracy is inevitably deteriorated.
  • the voltage offset of the crystal resonator can be adjusted to compensate for the frequency offset. .
  • crystal oscillators In order to achieve higher long-term frequency stability, crystal oscillators currently use the following technical methods:
  • the 1pps (Pulse Per Second) signal with high stability in the GPS or Beidou system is divided by the crystal oscillator to obtain a correction signal of 1 pps, and the correction signal is subjected to frequency discrimination, filtering, EFC (Electrical Frequency Control), etc., and then The obtained error signal voltage value is sent to the D/A converter to be converted into a voltage value, and the voltage value is sent to the crystal oscillator tuning end to correct the frequency offset of the crystal oscillator.
  • EFC Electronic Frequency Control
  • the calibration method of the voltage controlled crystal oscillator based on GPS and Beidou dual-mode timing is very effective for the special crystal oscillator calibration system, but the crystal oscillator applied to the test instrument such as the frequency counter and the pulse modulation domain analyzer needs to be calibrated. Time.
  • This method has limited integration and is not conducive to integration on a printed board with limited space.
  • the aging curve of the crystal oscillator is fitted, and a set of time-to-frequency arrays is generated according to the aging rate curve by the graphical analysis processing method, and the corresponding aging rate DAC array is calculated by the control system.
  • digital frequency stabilization of the crystal oscillator frequency is performed.
  • Digital frequency stabilization compensation is the fitting compensation of the aging curve of the crystal oscillator, and the aging curve of each crystal oscillator under the same process is also different.
  • the compensation method can only be approximated, and it is not suitable for accuracy. High demand areas of application.
  • the BVA quartz resonator (electrodeless resonator) is fabricated by a rigorous process. Since the BVA quartz resonator does not have the effect of stress aging of the electrode film, the surface loss is greatly reduced.
  • the BVA quartz resonator fabricated by SC cutting has a crystal frequency stability of 10-14/s and a daily frequency stability of 5 ⁇ 10-12/d. Its performance index is very close to that of the atomic clock.
  • the present invention adopts the following technical solutions.
  • the device for improving the long-term stability of a crystal oscillator in the invention comprises an oven controlled crystal oscillator, a frequency divider, a phase detector, a reference voltage source and a comparator;
  • the constant temperature crystal oscillator is connected to the frequency divider, and the frequency divider performs two frequency divisions with different frequency division ratios on an output frequency of the constant temperature crystal oscillator;
  • the input end of the phase detector is connected to the output end of the frequency divider, and the phase detector performs frequency discrimination on the first frequency-divided signal and the second frequency-divided signal output by the frequency divider;
  • the opposite input end and the non-inverting input end of the comparator are respectively connected to the output end of the phase detector and the reference voltage source, and the output end thereof is connected to the voltage control voltage end of the constant temperature crystal oscillator, the comparison Comparing the frequency discrimination voltage of the phase detector and the reference voltage provided by the reference voltage source, and outputting an error signal voltage to the voltage control voltage terminal of the constant temperature crystal oscillator to adjust an output frequency of the constant temperature crystal oscillator .
  • the apparatus further comprises a filter disposed between the output of the comparator and the voltage controlled voltage terminal of the oven controlled crystal oscillator.
  • the device further comprises a microprocessor, a switch, an AD/DA converter;
  • the microprocessor is connected to the output end of the filter through an AD circuit of the AD/DA converter, and is connected to an input end of the switch through a DA circuit of the AD/DA converter; the control end of the switch The microprocessor is connected, the other input thereof is connected to the output end of the filter, and the output end thereof is connected to the voltage control voltage end of the constant temperature crystal oscillator; so that the microprocessor periodically controls the switch Switch the phase-locked circuit to access and withdraw.
  • the phase discrimination interval of the phase detector always includes the first frequency division signal and the second frequency division signal.
  • the frequency of the number, and the dead zone of the phase detector is always smaller than the difference between the equivalent phase discrimination periods of the first frequency divided signal and the second frequency divided signal.
  • a method for improving the long-term stability of a crystal oscillator by using the device of the invention wherein the frequency divider performs two frequency divisions on the output frequency of the constant temperature crystal oscillator according to two different frequency division ratios set by the frequency divider, and outputs The first frequency-divided signal and the second frequency-divided signal are sent to the phase detector;
  • the phase detector outputs a corresponding frequency-dividing voltage to the comparator according to a frequency difference between the first frequency-divided signal and the second frequency-divided signal;
  • the comparator compares the non-inverting input terminal voltage input by the reference voltage source and the inverting input terminal voltage input by the phase detector, and outputs a corresponding error signal voltage to the voltage control voltage terminal of the constant temperature crystal oscillator;
  • the error signal voltage adjusts an output frequency of the oven controlled crystal oscillator and locks the stability of the oven controlled crystal oscillator to a reference voltage of the reference voltage source.
  • the error signal voltage is filtered between the output of the comparator and the voltage-controlled voltage terminal of the oven controlled crystal oscillator to reduce the error signal voltage output by the comparator. AC component.
  • the phase lock circuit is periodically switched on or removed to reduce the phase noise effect of the phase lock circuit on the oven controlled crystal oscillator.
  • the frequency division ratios of the frequency divider under the condition that the output frequency of the oven controlled crystal oscillator and its stability index and the dead zone of the phase detector are constant.
  • the range of ratios is determined.
  • the invention has the beneficial effects that the invention self-adjusts the frequency accuracy of the constant temperature crystal oscillator by the negative feedback function of the inter-frequency phase-locked circuit and its phase-locked loop, and locks the stability of the output frequency to the reference voltage source.
  • the long-term stability of the constant temperature crystal oscillator is greatly improved, and the structure is simple and the cost is low, which can meet the application requirements in many fields.
  • FIG. 1 is a schematic diagram of the apparatus for improving the long-term stability of a crystal oscillator of the present invention
  • Figure 2 is a schematic view of a first embodiment of the apparatus of the present invention
  • Figure 3 is a block diagram of a transfer function of the first embodiment of the apparatus of the present invention.
  • Figure 4 is a schematic view showing a second embodiment of the apparatus of the present invention.
  • Figure 5 is a waveform diagram of a frequency division signal in the present invention.
  • Figure 6 is a waveform diagram of the frequency-resolved voltage in the present invention.
  • Fig. 7 is a waveform diagram showing the error signal voltage in the present invention.
  • Constant temperature crystal oscillator 2 Frequency divider 3: Phase detector
  • FIG. 1 is a schematic diagram of a device for improving the long-term stability of a crystal oscillator according to the present invention, which comprises an oven controlled crystal oscillator 1, a frequency divider 2, a phase detector 3, a reference voltage source 4, and a comparator 5; an oven controlled crystal oscillator 1 and a frequency division
  • the input end of the device 2 is connected, the input end of the phase detector 3 is connected to the output end of the frequency divider 2, the phase detector 3 receives the frequency-divided signal transmitted by the frequency divider 2; the reverse input end of the comparator 5 and the same direction
  • the input end is respectively connected to the output end of the phase detector 3 and the reference voltage source 4, and the output end of the comparator 5 is connected to the voltage control voltage end of the constant temperature crystal oscillator 1.
  • the frequency divider 2 performs frequency division with different frequency division ratios on the output frequency of the constant temperature crystal oscillator 1, and outputs the first frequency-divided signal and the second frequency-divided signal to the
  • the phase detector 3 outputs a corresponding frequency-dividing voltage to the comparator 5 according to the frequency difference between the first frequency-divided signal and the second frequency-divided signal;
  • the comparator 5 compares the reference voltage of the reference voltage source 4 with the phase detector 3 outputting the frequency discrimination voltage and outputting the corresponding error signal voltage to the voltage control voltage terminal of the constant temperature crystal oscillator 1 to adjust the output frequency of the constant temperature crystal oscillator.
  • FIG. 2 is a schematic diagram of a first embodiment of the apparatus of the present invention.
  • a filter 6 is added to the basic structure of the apparatus of the present invention, and the filter 6 is disposed at the output of the comparator 5 and the voltage of the oven 1. Between the control voltage terminals, the error signal voltage outputted by the comparator 5 is filtered by the filter 6, which can reduce the AC component of the error signal voltage and help to improve the accuracy of the error signal voltage.
  • V ref is a reference voltage supplied from the reference voltage source 4
  • V d is a frequency-resolved voltage output from the phase detector 3
  • V e is a output of the comparator 5
  • the error signal voltage V t is the tuning voltage associated with the error signal voltage after filtering by the filter 6
  • K is the amplification gain of the comparator 5
  • F(S) is the transfer function of the filter 6
  • f out is the constant temperature crystal oscillator
  • the output frequency of 1 is ⁇ 0 , which is the output phase of the constant temperature crystal oscillator 1
  • ⁇ 1 and ⁇ 2 are the phases of the frequency-divided signals whose frequency division ratios of the frequency divider 2 are M and N, respectively.
  • V t (s) K*F(s)*V e (s) (2)
  • V e (s) V ref (s)-V d (s) (3)
  • K 0 is the gain factor of the constant temperature crystal oscillator
  • K d is the phase discriminator gain of the phase detector
  • the phase-locked loop of the inter-frequency phase-locked circuit of the present invention has a negative feedback effect, and at the same time, due to the negative feedback action of the phase-locked loop, the output frequency of the oven-controlled crystal oscillator 1 is only related to V ref , thereby achieving f out self-stability. the goal of.
  • the inter-frequency phase-locked circuit of the present invention When the components in the inter-frequency phase-locked circuit of the present invention are determined, that is, the values of K 0 , K d , and K are determined, and only the values of M and N need to be selected, the long-term stability of the oven crystal oscillator 1 can be provided. Therefore, the inter-frequency phase-locked circuit of the present invention has a simple structure, and the selection of suitable components according to needs can reduce the cost to a certain extent.
  • FIG. 4 is a schematic diagram of a second embodiment of the apparatus of the present invention. This embodiment adds a microprocessor 7, a switch 8, and an AD/DA converter 9 based on the first embodiment to implement timing access of the phase locked circuit. And removal.
  • the I/O port of the microprocessor 7 is connected to the data port of the AD/DA converter 9, and the I/O port of the D11 to D15 of the microprocessor 7 passes through the AD circuit and filter of the AD/DA converter 9.
  • the output terminals of 6 are connected, and the I/O ports of D21 to D25 of the microprocessor 7 are connected to one input terminal of the switch 8 through the DA circuit of the AD/DA converter 9; the control terminal of the switch 8 is connected to the microprocessor 7.
  • the other input end of the switch 8 is connected to the output end of the filter 6, and the output end of the switch 8 is connected to the voltage control voltage end of the constant temperature crystal oscillator 1 to enable the microprocessor 7 to periodically control the switch 8 to switch the phase lock circuit. In and out. Thereby, the phase noise effect of the inter-frequency phase locked circuit on the constant temperature crystal oscillator 1 is reduced.
  • the microprocessor 7 starts to time according to the set time, the phase lock circuit is in an access state, and the output end of the filter 6 is connected with the voltage control voltage end of the constant temperature crystal oscillator 1 to realize an error signal voltage to the constant temperature crystal oscillator.
  • the state switching causes the DA circuit of the AD/DA converter 9 to be connected to the voltage-controlled voltage terminal of the constant temperature crystal oscillator 1, that is, the phase-locked loop circuit is removed.
  • the microprocessor 7 in this embodiment can employ an ARM9 series microprocessor.
  • the phase detector 3 in the present invention can adopt the ADF4002, and the frequency divider 2 can be an integer frequency divider, a fractional frequency divider or a DDS (Direct Digital Frequency Synthesizer) device or the like.
  • the comparator 5 can employ an OP184.
  • Filter 6 can employ a second order low pass filter.
  • phase detector 3 will have a dead zone, that is, when the difference between the equivalent phase discrimination periods of the two input signals is smaller than the dead zone, the phase detector 3 will lose the output of the phase detector pulse, resulting in incompleteness.
  • the frequency response or phase difference information of the input signal is not limited to, but not limited to, but not limited to, but not limited to, but not limited to, but not limited to, but not limited to, but not limited to, but not limited to the phase detector 3 will lose the output of the phase detector pulse, resulting in incompleteness. The frequency response or phase difference information of the input signal.
  • the voltage V d is a fixed AC waveform that passes through the filter 6 to obtain a fixed tuning voltage V t .
  • the dead zone of the phase detector 3 should always be smaller than that of the first frequency-divided signal and the second frequency-divided signal. The difference between the equivalent phase detection periods. Thereby, the accuracy of the frequency discrimination voltage output from the phase detector 3 is ensured.
  • the present invention also provides a method for improving the long-term stability of the crystal oscillator by using the device of the present invention.
  • a method for improving the long-term stability of the crystal oscillator by using the device of the present invention For an embodiment of the present invention, reference may be made to the embodiment of the device of the present invention, and details are not described herein again.
  • the present invention provides a method for improving the long-term stability of the crystal oscillator by using the apparatus of the present invention:
  • the frequency divider 2 performs two frequency divisions on the output frequency of the constant temperature crystal oscillator 1 according to two different frequency division ratios set by the frequency divider 2, and outputs the first frequency division signal and the second frequency division signal to the phase detector 3 .
  • the phase detector 3 outputs a corresponding frequency-dividing voltage to the comparator according to the frequency difference between the first frequency-divided signal and the second frequency-divided signal. 5; comparing the non-inverting input terminal voltage input by the reference voltage source 4 and the inverting input terminal voltage input by the phase detector 3 through the comparator 5, and outputting the corresponding error signal voltage to the voltage control voltage of the constant temperature crystal oscillator 1.
  • the output frequency of the oven controlled crystal oscillator 1 is adjusted by the error signal voltage and the stability of the oven controlled crystal oscillator 1 is locked to the reference voltage of the reference voltage source 4.
  • the frequencies of the first frequency-divided signal and the second frequency-divided signal output by the frequency divider 2 are f 1 and f 2 , respectively . Since the phase detector 3 performs error output by comparing the rising edges of f1 and f2, the phase detector 3 is set to 1 at the rising edge of the first frequency-divided signal, and is raised at the second frequency-divided signal. At the edge, the phase detector output signal is set to 0, and finally the equivalent frequency of frequency f 0 is obtained .
  • V pp is the peak voltage of the voltage discriminator.
  • the phase detector 3 whether a pulse averaging method or a method using a sampling pulse, the output of the frequency discriminator phase detector 3 will be a voltage V d is a group of the sawtooth waveform of the present cycle.
  • the error signal voltage Ve is filtered between the output of the comparator 5 and the voltage controlled voltage terminal of the oven controlled crystal oscillator 1, and the error signal voltage Ve is tuned after passing through the filter 6.
  • a voltage V t wherein the tuning voltage V t is a smoother DC voltage obtained by filtering out the high frequency component and the error component of the error signal voltage V e , and the magnitude of the voltage is related to the V e period and the peak value, which is equivalent to an error signal The effect of the rms voltage of the voltage V e .
  • f 1 and f 2 are not strictly in a set proportional relationship, and there is a slight phase deviation, which causes a change in the period and peak value of the error signal voltage Ve , thereby passing
  • the output frequency of the V t controlled constant temperature crystal oscillator tends to be locked; when the phase lock circuit is locked, the system forms a negative feedback loop, and f 1 and f 2 strictly satisfy the set proportional relationship, and the output of the constant temperature crystal oscillator 1
  • the frequency is controlled by the stability of the error signal voltage V t , and the frequency corresponding to the output of the oven controlled crystal oscillator 1 is locked to the reference voltage V ref . Therefore, the reference voltage source 4 having a higher stability can be selected to ensure the constant temperature crystal oscillator. Long-term stability of 1.
  • the long-term stability of a precision reference voltage source is generally tens to hundreds of PPM/year. It is better to achieve several PPM/year.
  • a common reference voltage source of 50 PPM/year Take a common reference voltage source of 50 PPM/year as an example.
  • the reference voltage V ref is 2V
  • the constant temperature crystal oscillator 1 is within the tuning range of 12V, its frequency tuning range 2PPM
  • the long-term stability of the oven crystal oscillator 1 can be improved by selecting the reference voltage source 4 having a higher stability and selecting an appropriate loop parameter.
  • the microprocessor 7 controls the switching of the switch 8 periodically to realize the access or removal of the phase-locked loop.
  • the phase-locked loop is removed, Keeping the tuning voltage V t at the moment before the phase-locked loop is removed, the output frequency of the constant-temperature crystal oscillator 1 is kept stable for a short period of time, and the phase noise effect of the inter-frequency phase-locked circuit on the constant-temperature crystal oscillator 1 is reduced; At this time, the tuning voltage V t is generated correspondingly to adjust the output frequency of the constant temperature crystal oscillator 1.
  • two different frequency division signals are outputted by two different frequency division ratios set on the frequency divider 2, and the frequency division ratio of the two signals and the constant temperature crystal are set.
  • the output frequency and stability of the oscillator, the stability of the reference voltage source, and the dead zone of the phase detector are all related.
  • the division ratio of the first frequency-divided signal is M
  • the frequency division ratio of the second frequency-divided signal is N.
  • the M and N values are determined as follows:
  • the frequencies of the first frequency-divided signal and the second frequency-divided signal are f 1 and f 2 , respectively, and the corresponding periods are t 1 and t 2 .
  • the dead zone is set to 1 ps, then at
  • ⁇ f/(f out /N) is the frequency stability of the constant temperature crystal oscillator 1
  • the method for improving the long-term stability of the crystal according to the present invention the stability of the crystal oscillator 1 is locked in the reference voltage source 4 in the phase-locked circuit
  • the stability of the constant temperature crystal oscillator 1 should not be lower than the stability of the reference voltage 4, and the stability of the constant temperature crystal oscillator 1 is assumed to be 10 -8 in the present invention.
  • the minimum value of the division ratio N can be determined.
  • the selected constant temperature crystal oscillator 1 of the present invention has an output frequency f out of 100 MHz, and then N ⁇ 10 4 .
  • the frequency of the frequency discrimination signal f 0 at this time is:
  • the frequencies of the different first frequency-divided signals and the second frequency-divided signals input to the phase detector 3 are 10 kHz and 5 kHz, respectively.
  • the present invention determines the range of values for M and N under conditions that satisfy a particular output frequency, long-term stability of a particular requirement, and a particular phase detector deadband condition.

Abstract

一种提高晶振长期稳定度的装置和方法，所述装置包括恒温晶体振荡器（1）、分频器（2）、鉴相器（3）、基准电压源（4）和比较器（5），其中，恒温晶体振荡器（1）与分频器（2）连接，鉴相器（3）的输入端与分频器（2）的输出端连接，比较器（5）的反向输入端、同向输入端和输出端分别连接鉴相器（3）的输出端、基准电压源（4）和恒温晶体振荡器（1）的压控电压端；所述方法是通过鉴相器（3）对两个不同倍数的分频信号进行异频鉴频，再由比较器（5）将鉴相器（3）的鉴频电压与基准电压比较，产生误差信号电压并将误差信号电压作用于恒温晶体振荡器（1）的压控电压端进行反馈调节，从而完成对恒温晶体振荡器（1）的输出频率自动调节，使恒温晶体振荡器（1）输出频率保持在一个固定的频率，以达到提升频率长期稳定度的目的。

Description

一种提高晶振长期稳定度的装置和方法 技术领域
本发明涉及一种提高晶振长期稳定度的装置，特别设计一种应用了微波锁相环技术的提高晶振长期稳定度的装置。
背景技术
现代社会，在卫星导航、通讯、广播、雷达、精确制导、电子对抗、遥控遥测等各种领域，晶体振荡器都是必不可少的部件，而且对于晶体振荡器的频率准确度要求越来越高。
业界已经利用温度补偿技术设计了恒温晶体振荡器(OCXO)，其频率稳定度有了极大的改善。但是随着时间的推移，即使是恒温晶体振荡器，其频率准确度也会逐渐恶化，其主要原因包括老化、外界环境变化、压控电压的失调等。晶体振荡器老化的主要原因是质量效应和应力效应，是不可避免的误差项，而外界环境变化、压控电压失调，同样也是不可避免的。因此在晶体谐振器使用一段时间后，其频率准确度必然恶化。但不管是老化、外界环境变化、压控电压的失调中哪一种因素，或是共同作用造成的频率准确度恶化，都可以通过调整晶体谐振器的压控端电压来校准补偿其频率偏移。
目前晶体振荡器为了获得更高的长期频率稳定性，采用的技术方法主要有：
(1)基于GPS与北斗双模授时的压控晶体振荡器校准
利用GPS或北斗系统中稳定度较高的1pps(Pulse Per Second)信号与晶体振荡器分频后得到1pps的修正信号，对修正信号进行鉴频、滤波、EFC(Electrical Frequency Control)等处理，然后将得到的误差信号电压数值送入D/A转换器转换为电压值，将该电压值送入晶体振荡器调谐端，来修正晶体振荡器的频率偏移。
基于GPS与北斗双模授时的压控晶体振荡器的校准方法对于专门的晶体振荡器校准系统来说十分有效，但应用在频率计数器、脉冲调制域分析仪等测试仪器上的晶体振荡器需要校准时。该方法集成度有限，不利于集成到空间有限的印制板上。
(2)数字稳频补偿
通过对晶振工作时的输出频率进行长期测量，拟合出晶振的老化曲线，利用图形解析处理方法根据老化率曲线生成一组时间对频率值的数组，通过控制系统计算出对应的老化率DAC数组，从而对晶体振荡器的频率进行数字稳频补偿。
数字稳频补偿是对晶振的老化曲线进行的拟合补偿，而且相同工艺下的每只晶振的老化曲线也是不尽相同的，这种补偿的方法也只能是大致近似，不适用于准确度要求高的应用领域。
(3)BVA晶体振荡器
通过严密的工艺制作BVA石英谐振器(无电极式谐振器)，由于BVA石英谐振器不存在电极膜应力老化影响，其表面损耗大大地降低了。采用SC切制作的BVA石英谐振器，其晶振的频率稳定度达10-14/s、日频率稳定度达5×10-12/d，其性能指标非常接近原子钟的性能指标。
但由于BVA振荡器制作的工艺条件要求极其苛刻，其制作成本昂贵，其工艺流程复杂，不适合批量生产和广泛地使用。
因此存在开发一种结构简单、制作成本低廉且提高晶振输出频率长期稳定度的装置的需要。
发明内容
为提供一种结构简单、制作成本低廉且提高晶振输出频率长期稳定度的装置，本发明采用以下技术方案。
本发明中的提高晶振长期稳定度的装置，其包括恒温晶体振荡器、分频器、鉴相器、基准电压源和比较器；
所述恒温晶体振荡器与所述分频器连接，所述分频器对所述恒温晶体振荡器的输出频率进行两个具有不同分频比的分频；
所述鉴相器的输入端与所述分频器的输出端连接，所述鉴相器对由所述分频器输出的第一分频信号和第二分频信号进行鉴频；
所述比较器的反向输入端和同向输入端分别连接所述鉴相器的输出端和所述基准电压源，其输出端连接所述恒温晶体振荡器的压控电压端，所述比较器比较所述鉴相器的鉴频电压和所述基准电压源提供的基准电压而输出误差信号电压至所述恒温晶体振荡器的压控电压端，以调节所述恒温晶体振荡器的输出频率。
根据一种优选的实施方式，所述装置还包括滤波器，所述滤波器设置在所述比较器的输出端与所述恒温晶体振荡器的压控电压端之间。
根据一种优选的实施方式，所述装置还包括微处理器、开关、AD/DA转换器；
其中，所述微处理器通过AD/DA转换器的AD电路与所述滤波器的输出端连接，通过AD/DA转换器的DA电路与开关的一个输入端连接；所述开关的控制端与所述微处理器连接，其另一个输入端与所述滤波器的输出端连接，其输出端与所述恒温晶体振荡器的压控电压端连接；以使所述微处理器定时地控制开关切换锁相电路接入和撤出。
根据一种优选的实施方式，所述鉴相器的鉴频区间始终包括第一分频信号和第二分频信 号的频率，并且所述鉴相器的死区始终小于所述第一分频信号和第二分频信号的等效鉴相周期之差。
一种利用本发明所述装置提高晶振长期稳定度的方法，该方法为分频器按照其设置的两个不同的分频比，对恒温晶体振荡器的输出频率进行两个分频，并输出第一分频信号和第二分频信号至鉴相器；
所述鉴相器根据所述第一分频信号与第二分频信号的频差而输出相应的鉴频电压至比较器；
所述比较器比较由基准电压源输入的同相输入端电压和由所述鉴相器输入的反向输入端电压，并输出相应的误差信号电压至所述恒温晶体振荡器的压控电压端；
所述误差信号电压调节所述恒温晶体振荡器的输出频率并将所述恒温晶体振荡器的稳定度锁定在所述基准电压源的基准电压上。
根据一种优选的实施方式，在所述比较器的输出端与所述恒温晶体振荡器的压控电压端之间对误差信号电压进行滤波，以减小所述比较器输出的误差信号电压的交流分量。
根据一种优选的实施方式，将锁相电路定时地接入或撤除，以减少所述锁相电路对恒温晶体振荡器的相噪影响。
根据一种优选的实施方式，在所述恒温晶体振荡器的输出频率和其稳定度指标以及鉴相器的死区一定的条件下，所述分频器的两个不同分频比之间的比值范围是确定的。
本发明的有益效果在于：本发明通过异频锁相电路及其锁相环的负反馈作用完成对恒温晶体振荡器频率准确度的自我调节，并将其输出频率的稳定度锁定在基准电压源上，大大提高了恒温晶体振荡器的长期稳定度，并且结构简单，成本低廉，能够满足许多领域的应用需求。
附图说明
图1是本发明提高晶振长期稳定度装置的原理图；
图2是本发明装置第一实施例示意图；
图3是本发明装置第一实施例的传递函数框图；
图4是本发明装置第二实施例示意图；
图5是本发明中分频信号的波形示意图；
图6是本发明中鉴频电压的波形示意图；
图7是本发明中误差信号电压的波形示意图。
附图标记列表
1：恒温晶体振荡器  2：分频器  3：鉴相器
4：基准电压源      5：比较器  6：滤波器
7：微处理器        8：开关    9：AD/DA转换器
具体实施方式
下面结合附图进行详细说明。
图1是本发明提高晶振长期稳定度装置的原理图，其包括恒温晶体振荡器1、分频器2、鉴相器3、基准电压源4和比较器5；恒温晶体振荡器1与分频器2的输入端连接，鉴相器3的输入端与分频器2的输出端连接，鉴相器3接收分频器2传输的分频信号；比较器5的反向输入端和同向输入端分别连接鉴相器3的输出端和基准电压源4，比较器5的输出端连接恒温晶体振荡器1的压控电压端。
本发明的提高晶振长期稳定度装置的工作原理：分频器2对恒温晶体振荡器1输出频率进行具有不同分频比的分频，并输出第一分频信号和第二分频信号至鉴相器3；鉴相器3根据第一分频信号与第二分频信号的频率差而输出相应的鉴频电压至比较器5；比较器5比较基准电压源4的基准电压和鉴相器3输出的鉴频电压并输出相应的误差信号电压至恒温晶体振荡器1的压控电压端，以调节所述恒温晶体振荡器的输出频率。
图2是本发明装置第一实施例的原理图，本实施例在本发明装置的基础结构上增加滤波器6，将滤波器6设置在比较器5的输出端与恒温晶体振荡器1的压控电压端之间，通过滤波器6对比较器5输出的误差信号电压进行滤波，可减少误差信号电压的交流分量，有助于提高误差信号电压的准确度。
图3是本发明装置第一实施例的传递函数框图，其中，Vref为基准电压源4提供的基准电压，Vd为鉴相器3输出的鉴频电压，Ve为比较器5输出的误差信号电压，Vt为经滤波器6滤波后与误差信号电压相关的调谐电压，K为比较器5的放大增益，F(S)为滤波器6的传递函数，fout为恒温晶体振荡器1的输出频率，θ0为恒温晶体振荡器1的输出相位，θ1和θ2分别为分频器2输出的分频比为M和N的分频信号的相位。
根据经典锁相环的拉普拉斯变换理论，有如下关系。
θ0＝K0*Vt(s)/s       (1)
Vt(s)＝K*F(s)*Ve(s)       (2)
Ve(s)＝Vref(s)-Vd(s)   (3)
Vd(s)＝Kd*(θ1(s)-θ2(s))＝Kd*θ0(s)*(1/M-1/N)    (4)
其中，K0为恒温晶振的增益因子，Kd为鉴相器鉴频增益。
因此，在比较器5的输入端得到的开环传递函数G(s)为：
G(s)＝Vd(s)/Ve(s)＝[Kd*(1/M-1/N)*K0*K*F(s)]/s         (5)
根据上述等式对锁相电路的闭环传递函数进行定性分析，其中，当fout增大时，根据数学关系相位是频率的积分，则θ0增大；由于θ0增大，根据等式4，Vd增大；由于Vd增大，根据等式3，Ve减小；由于Ve减小，根据等式2，Vt减小；由于Vt减小，根据恒温晶体振荡器1的压控电压端电压与其输出频率的正相关性，fout减小。
同理，当fout减小时，经过闭环传递函数传递后的结果是fout增大。所以，本发明的异频锁相电路的锁相环具有负反馈作用，同时由于锁相环的负反馈作用，恒温晶体振荡器1的输出频率就只与Vref相关，从而达到fout自我稳定的目的。
当本发明的异频锁相电路中的元件确定时，即K0，Kd，K的值都确定，只需要选择M和N的值，即可提供恒温晶体振荡器1的长期稳定度。因此，本发明的异频锁相电路结构简单，根据需要选择合适的元件，可在一定程度上降低成本。
图4是本发明装置第二实施例的原理图，本实施例在第一实施例的基础上增加微处理器7、开关8、AD/DA转换器9，以实现锁相电路的定时接入和撤除。
其中，微处理器7的I/O端口与AD/DA转换器9的数据端口对应相连，微处理器7的D11～D15的I/O端口通过AD/DA转换器9的AD电路与滤波器6的输出端连接，微处理器7的D21～D25的I/O端口通过AD/DA转换器9的DA电路与开关8的一个输入端连接；开关8的控制端与微处理器7连接，开关8的另一个输入端与滤波器6的输出端连接，开关8的输出端与恒温晶体振荡器1的压控电压端连接；以使微处理器7定时地控制开关8切换锁相电路接入和撤出。从而降低异频锁相电路对恒温晶体振荡器1的相噪影响。
具体的，微处理器7开始按照设定时间计时，锁相电路为接入状态，滤波器6的输出端和恒温晶体振荡器1的压控电压端连接，实现误差信号电压对恒温晶体振荡器1的输出频率的调控。在自我调节完成后，微处理器7通过AD/DA转换器9的AD电路读取此次的调谐电压Vt并储存，再通过AD/DA转换器9的DA电路输出VO(VO＝Vt)来保持恒温晶体振荡器1的压控电压端处于校准后的状态，当微处理器7的达到设定时间时，微处理器7输出一 个控制信号至开关8的控制端，开关8状态切换，使AD/DA转换器9的DA电路与恒温晶体振荡器1的压控电压端连接，即将锁相环电路撤除。本实施例中的微处理器7可采用ARM9系列微处理器。
本发明中的鉴相器3可采用ADF4002，分频器2可以是整数分频器，也可以是小数分频器或者DDS(直接数字频率合成)器件等。比较器5可采用OP184。滤波器6可采用二阶低通滤波器。
其中，通常由于鉴相器3会存在死区，即当两个输入信号的等效鉴相周期之差小于死区时，鉴相器3将会丢失这部分鉴相脉冲的输出，导致不能完整地反应输入信号的频差或者相差信息。
如图5所示，在异频鉴相过程中，第一分频信号和第二分频信号的频率为f1和f2，且f1≠f2，f1＝A*fc，f2＝B*fc，fc为f1和f2的最大公因子频率，f0＝A*B*fc，T0＝1/A*B*fc，f0为等效鉴相频率，T0为等效鉴相周期。
本发明装置在异频锁定的过程会使f1*B＝f2*A等式成立，即f1和f2的等效鉴相周期相等且等于T0，鉴相器3输出的鉴相电压Vd是一个固定的交流波形，经过滤波器6后得到一个固定的调谐电压Vt。
若在锁定过程中，f1*B＝f2*A等式不成立，等效鉴相频率f0的交流波形会发生变化，调谐电压Vt的大小也相应地变化并调节恒温晶体振荡器1的输出频率大小，使得f1*B＝f2*A等式成立，完成异频锁定；而在鉴相时，由于第一分频信号和第二分频信号的等效鉴相周期T01和T02非常接近，会存在上升沿同时到达的情况而使鉴相器3在死区的时间范围内没有鉴相电压的输出，造成恒温晶体振荡器1的输出频率误差。
因此，为保证鉴相器3能反应第一分频信号和第二分频信号的频率差的微小变化，鉴相器3的死区应始终小于第一分频信号与第二分频信号的等效鉴相周期之差。从而保证鉴相器3输出的鉴频电压的准确度。
基于与本发明所述装置相同的发明构思，本发明还提供一种利用本发明装置提高晶振长期稳定度的方法，其实施例可参见本发明所述装置的实施例，此处不再赘述。
结合图1中本发明提高晶振长期稳定度装置的基本原理图，本发明提供一种利用本发明装置提高晶振长期稳定度的方法为：
通过分频器2按照其设置的两个不同的分频比，对恒温晶体振荡器1的输出频率进行两个分频，并输出第一分频信号和第二分频信号至鉴相器3。
由鉴相器3根据第一分频信号与第二分频信号的频差而输出相应的鉴频电压至比较器 5；再通过比较器5比较由基准电压源4输入的同相输入端电压和由鉴相器3输入的反向输入端电压，并输出相应的误差信号电压至恒温晶体振荡器1的压控电压端；通过误差信号电压来调节恒温晶体振荡器1的输出频率并将恒温晶体振荡器1的稳定度锁定在基准电压源4的基准电压上。
具体的，如图5，其中，分频器2输出的第一分频信号和第二分频信号的频率分别为f1和f2。由于鉴相器3是通过f1和f2的上升沿比对进行误差输出，鉴相器3在第一分频信号的上升沿时，鉴相器输出信号置1，在第二分频信号的上升沿时，鉴相器输出信号置0，最终得到等效鉴频频率f0。
如图6，其中，Um为鉴频电压的最低电压，Vpp为鉴频电压的峰值电压。鉴相器3无论采用脉冲平均的方法或者是脉冲取样的方法，鉴相器3输出的鉴频电压Vd将是一个呈现周期变化的一组锯齿波形。
如图7，其中，在比较器5通过比较鉴频电压Vd和基准电压Vref后，而相应地输出误差信号电压Ve，其过程为通过基准电压Vref将鉴频电压Vd的锯齿波形下移Um电压，而得到的误差信号电压Ve是以零电压为最低电压的周期性变化的锯齿波形，即Ve＝Vd-Vref＝Vd-Um；因此，误差信号电压Ve也是呈周期变化的一组锯齿波形。
结合本发明的第一实施例，在比较器5的输出端与恒温晶体振荡器1的压控电压端之间对误差信号电压Ve进行滤波，误差信号电压Ve经过滤波器6后得到调谐电压Vt，其中，调谐电压Vt为误差信号电压Ve滤除高频成分和误差分量后得到的更平滑的直流电压，该电压的大小与Ve周期和峰值相关的，相当于是误差信号电压Ve的有效值电压的作用。
进一步地，当锁相电路没有完全锁定时，f1和f2不是严格按照设定的比例关系，会存在微小的相位偏差，则会使误差信号电压Ve的周期和峰值产生变化，从而通过Vt控制恒温晶体振荡器的输出频率趋于锁定；而当锁相电路锁定后，系统就形成负反馈回路，f1和f2严格满足所设定的比例关系，恒温晶体振荡器1的输出频率受误差信号电压Vt稳定的控制，相当于恒温晶体振荡器1的输出的频率锁定在基准电压Vref上，因此，可选择具有较高稳定度的基准电压源4来保证恒温晶体振荡器1的长期稳定度。
精密的基准电压源的长期稳定度一般为几十至几百PPM/年，较好的能做到几个PPM/年，以50PPM/年的普通基准电压源为例，假设基准电压Vref为2V，其年老化波动电压为：2*50*10-6*103＝0.1V，其中103为比较器5的放大增益；恒温晶体振荡器1在12V的调谐范围内，其频率调谐范围为2PPM；由于基准电压Vref带来的恒温晶体振荡器1输出频率漂移为2*0.1/12＝0.02PPM/年，达到了10-8/年(10-11/天)量级的长期稳定度。
在本发明提高晶振长期稳定度的方法中，只要选择具有较高稳定度的基准电压源4以及选用合适的环路参数，便可提高恒温晶体振荡器1的长期稳定度。
结合本发明的第二实施例，本发明提高晶振长期稳定度的方法中，通过微处理器7定时地控制开关8的切换，实现锁相回路的接入或撤除，在撤除锁相回路时，保持撤除锁相回路前一刻的调谐电压Vt，使恒温晶体振荡器1的输出频率保持短期稳定，同时降低异频锁相电路对恒温晶体振荡器1的相噪影响；在接入锁相回路时，则重新相应的产生调谐电压Vt来调节恒温晶体振荡器1的输出频率。
在本发明提高晶振长期稳定度的方法中，是通过在分频器2上设置的两个不同的分频比而输出两个频率不一样的信号，设置两个信号的分频比与恒温晶体振荡器的输出频率及稳定度、基准电压源的稳定度，鉴相器的死区都有关，设第一分频信号的分频比为M，第二分频信号的分频比为N，M和N值的确定方法如下：
假设第一分频信号和第二分频信号的频率分别为f1和f2，对应周期为t1和t2，根据鉴相器3死区的定义，设死区为1ps，那么在|t1-t2|≤1ps时，鉴相器将没有反应而不能响应频差或相差变化。
由于最小的可检测频差是由鉴相器死区决定的，所以有：
Figure PCTCN2015091514-appb-000001
Δf＝f1*f2*1*10-12≈f1*f1*1*10-12    (7)
其中，1ps＝1*10-12s；f1＝fout/N，fout是恒温晶体振荡器1的输出频率，根据等式7：
Δf＝f12*10-12＝(fout/N)2*10-12    (8)
Δf/(fout/N)＝(fout/N)*10-12    (9)
其中Δf/(fout/N)为恒温晶体振荡器1的频率稳定度，根据本发明提高晶振长期稳定度的方法，在锁相电路中恒温晶体振荡器1的稳定度锁定在基准电压源4上，当基准电压源4的选型确定，恒温晶体振荡器1的稳定度应不低于基准电压4的稳定度，本发明中假设恒温晶体振荡器1要求达到的稳定度为10-8/年，根据等式9：
10-8＝(fout/N)*10-12    (10)
根据等式10可知，当恒温晶体振荡器1的输出频率fout确定时，分频比N的最小值是可以确定的。本发明选择的恒温晶体振荡器1输出频率fout为100MHz，则N≥104。
设恒温晶体振荡器1的输出频率fout变化1Hz时，此时鉴频信号f0的频率为：
(fout+1)*(1/N-1/M)＝fout*(1/N-1/M)+(1/N-1/M)   (11)
其中，fout*(1/N-1/M)为初始的鉴频频差，(1/N-1/M)为鉴相器3能够有鉴频输出的最小频差。设N＝104，即f1＝10KHz。根据等式(6)：
1/N-1/M≥10-4    (12)
设M＝X*N，则X-1≥1；即X≥2；取X的最小值，则M＝2*104。
即输入鉴相器3的异第一分频信号和第二分频信号的频率分别为10KHz和5KHz。因此，本发明在在满足特定输出频率、特定要求的长期稳定度和特定鉴相器死区条件下确定了M和N的取值范围。
需要注意的是，上述具体实施例是示例性的，本领域技术人员可以在本发明公开内容的启发下想出各种解决方案，而这些解决方案也都属于本发明的公开范围并落入本发明的保护范围之内。本领域技术人员应该明白，本发明说明书及其附图均为说明性而并非构成对权利要求的限制。本发明的保护范围由权利要求及其等同物限定。

Claims (8)

  1. 一种提高晶振长期稳定度的装置，其特征在于，所述装置包括恒温晶体振荡器(1)、分频器(2)、鉴相器(3)、基准电压源(4)和比较器(5)；
    所述恒温晶体振荡器(1)与所述分频器(2)连接，所述分频器(2)对所述恒温晶体振荡器(1)的输出频率进行两个具有不同分频比的分频；
    所述鉴相器(3)的输入端与所述分频器(2)的输出端连接，所述鉴相器(3)对由所述分频器(2)输出的第一分频信号和第二分频信号进行鉴频；
    所述比较器(5)的反向输入端和同向输入端分别连接所述鉴相器(3)的输出端和所述基准电压源(4)，其输出端连接所述恒温晶体振荡器(1)的压控电压端，所述比较器(5)比较所述鉴相器(3)的鉴频电压和所述基准电压源(4)提供的基准电压而输出误差信号电压至所述恒温晶体振荡器(1)的压控电压端，以调节所述恒温晶体振荡器(1)的输出频率。
  2. 根据权利要求1所述的提高晶振长期稳定度的装置，其特征在于，所述装置还包括滤波器(6)，所述滤波器(6)设置在所述比较器(5)的输出端与所述恒温晶体振荡器(1)的压控电压端之间。
  3. 根据权利要求2所述的提高晶振长期稳定度的装置，其特征在于，所述装置还包括微处理器(7)、开关(8)、AD/DA转换器(9)；
    其中，所述微处理器(7)通过AD/DA转换器(9)的AD电路与所述滤波器(6)的输出端连接，通过AD/DA转换器(9)的DA电路与开关(8)的一个输入端连接；所述开关(8)的控制端与所述微处理器(7)连接，其另一个输入端与所述滤波器(6)的输出端连接，其输出端与所述恒温晶体振荡器(1)的压控电压端连接；以使所述微处理器(7)定时地控制开关(8)切换锁相电路接入和撤出。
  4. 根据权利要求1所述的提高晶振长期稳定度的装置，其特征在于，所述鉴相器(3)的鉴频区间始终包括第一分频信号和第二分频信号的频率，并且所述鉴相器(3)的死区始终小于所述第一分频信号和第二分频信号的等效鉴相周期之差。
  5. 一种利用权利要求1所述装置提高晶振长期稳定度的方法，其特征在于，分频器(2)按照其设置的两个不同的分频比，对恒温晶体振荡器(1)的输出频率进行两个分频，并输出第一分频信号和第二分频信号至鉴相器(3)；
    所述鉴相器(3)根据所述第一分频信号与第二分频信号的频差而输出相 应的鉴频电压至比较器(5)；
    所述比较器(5)比较由基准电压源(4)输入的同相输入端电压和由所述鉴相器(3)输入的反向输入端电压，并输出相应的误差信号电压至所述恒温晶体振荡器(1)的压控电压端；
    所述误差信号电压调节所述恒温晶体振荡器(1)的输出频率并将所述恒温晶体振荡器(1)的稳定度锁定在所述基准电压源(4)的基准电压上。
  6. 根据权利要求5所述的提高晶振长期稳定度的方法，其特征在于，在所述比较器(5)的输出端与所述恒温晶体振荡器(1)的压控电压端之间对误差信号电压进行滤波，以减小所述误差信号电压的误差分量。
  7. 根据权利要求6所述的提高晶振长期稳定度的方法，其特征在于，将锁相电路定时地接入或撤除，以减少所述锁相电路对恒温晶体振荡器(1)的相位噪声影响。
  8. 根据权利要求5所述的提高晶振长期稳定度的方法，其特征在于，在所述恒温晶体振荡器(1)的输出频率和其稳定度指标以及鉴相器(3)的死区一定的条件下，所述分频器的两个不同分频比之间的比值范围是确定的。
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